1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // cs35l41-lib.c -- CS35L41 Common functions for HDA and ASoC Audio drivers 4 // 5 // Copyright 2017-2021 Cirrus Logic, Inc. 6 // 7 // Author: David Rhodes <david.rhodes@cirrus.com> 8 // Author: Lucas Tanure <lucas.tanure@cirrus.com> 9 10 #include <linux/dev_printk.h> 11 #include <linux/module.h> 12 #include <linux/regmap.h> 13 #include <linux/regulator/consumer.h> 14 #include <linux/slab.h> 15 #include <linux/firmware/cirrus/wmfw.h> 16 17 #include <sound/cs35l41.h> 18 19 static const struct reg_default cs35l41_reg[] = { 20 { CS35L41_PWR_CTRL1, 0x00000000 }, 21 { CS35L41_PWR_CTRL2, 0x00000000 }, 22 { CS35L41_PWR_CTRL3, 0x01000010 }, 23 { CS35L41_GPIO_PAD_CONTROL, 0x00000000 }, 24 { CS35L41_GLOBAL_CLK_CTRL, 0x00000003 }, 25 { CS35L41_TST_FS_MON0, 0x00020016 }, 26 { CS35L41_BSTCVRT_COEFF, 0x00002424 }, 27 { CS35L41_BSTCVRT_SLOPE_LBST, 0x00007500 }, 28 { CS35L41_BSTCVRT_PEAK_CUR, 0x0000004A }, 29 { CS35L41_SP_ENABLES, 0x00000000 }, 30 { CS35L41_SP_RATE_CTRL, 0x00000028 }, 31 { CS35L41_SP_FORMAT, 0x18180200 }, 32 { CS35L41_SP_HIZ_CTRL, 0x00000002 }, 33 { CS35L41_SP_FRAME_TX_SLOT, 0x03020100 }, 34 { CS35L41_SP_FRAME_RX_SLOT, 0x00000100 }, 35 { CS35L41_SP_TX_WL, 0x00000018 }, 36 { CS35L41_SP_RX_WL, 0x00000018 }, 37 { CS35L41_DAC_PCM1_SRC, 0x00000008 }, 38 { CS35L41_ASP_TX1_SRC, 0x00000018 }, 39 { CS35L41_ASP_TX2_SRC, 0x00000019 }, 40 { CS35L41_ASP_TX3_SRC, 0x00000000 }, 41 { CS35L41_ASP_TX4_SRC, 0x00000000 }, 42 { CS35L41_DSP1_RX1_SRC, 0x00000008 }, 43 { CS35L41_DSP1_RX2_SRC, 0x00000009 }, 44 { CS35L41_DSP1_RX3_SRC, 0x00000018 }, 45 { CS35L41_DSP1_RX4_SRC, 0x00000019 }, 46 { CS35L41_DSP1_RX5_SRC, 0x00000020 }, 47 { CS35L41_DSP1_RX6_SRC, 0x00000021 }, 48 { CS35L41_DSP1_RX7_SRC, 0x0000003A }, 49 { CS35L41_DSP1_RX8_SRC, 0x0000003B }, 50 { CS35L41_NGATE1_SRC, 0x00000008 }, 51 { CS35L41_NGATE2_SRC, 0x00000009 }, 52 { CS35L41_AMP_DIG_VOL_CTRL, 0x00008000 }, 53 { CS35L41_CLASSH_CFG, 0x000B0405 }, 54 { CS35L41_WKFET_CFG, 0x00000111 }, 55 { CS35L41_NG_CFG, 0x00000033 }, 56 { CS35L41_AMP_GAIN_CTRL, 0x00000000 }, 57 { CS35L41_IRQ1_MASK1, 0xFFFFFFFF }, 58 { CS35L41_IRQ1_MASK2, 0xFFFFFFFF }, 59 { CS35L41_IRQ1_MASK3, 0xFFFF87FF }, 60 { CS35L41_IRQ1_MASK4, 0xFEFFFFFF }, 61 { CS35L41_GPIO1_CTRL1, 0x81000001 }, 62 { CS35L41_GPIO2_CTRL1, 0x81000001 }, 63 { CS35L41_MIXER_NGATE_CFG, 0x00000000 }, 64 { CS35L41_MIXER_NGATE_CH1_CFG, 0x00000303 }, 65 { CS35L41_MIXER_NGATE_CH2_CFG, 0x00000303 }, 66 { CS35L41_DSP1_CCM_CORE_CTRL, 0x00000101 }, 67 }; 68 69 static bool cs35l41_readable_reg(struct device *dev, unsigned int reg) 70 { 71 switch (reg) { 72 case CS35L41_DEVID: 73 case CS35L41_REVID: 74 case CS35L41_FABID: 75 case CS35L41_RELID: 76 case CS35L41_OTPID: 77 case CS35L41_SFT_RESET: 78 case CS35L41_TEST_KEY_CTL: 79 case CS35L41_USER_KEY_CTL: 80 case CS35L41_OTP_CTRL0: 81 case CS35L41_OTP_CTRL3: 82 case CS35L41_OTP_CTRL4: 83 case CS35L41_OTP_CTRL5: 84 case CS35L41_OTP_CTRL6: 85 case CS35L41_OTP_CTRL7: 86 case CS35L41_OTP_CTRL8: 87 case CS35L41_PWR_CTRL1: 88 case CS35L41_PWR_CTRL2: 89 case CS35L41_PWR_CTRL3: 90 case CS35L41_CTRL_OVRRIDE: 91 case CS35L41_AMP_OUT_MUTE: 92 case CS35L41_PROTECT_REL_ERR_IGN: 93 case CS35L41_GPIO_PAD_CONTROL: 94 case CS35L41_JTAG_CONTROL: 95 case CS35L41_PWRMGT_CTL: 96 case CS35L41_WAKESRC_CTL: 97 case CS35L41_PWRMGT_STS: 98 case CS35L41_PLL_CLK_CTRL: 99 case CS35L41_DSP_CLK_CTRL: 100 case CS35L41_GLOBAL_CLK_CTRL: 101 case CS35L41_DATA_FS_SEL: 102 case CS35L41_TST_FS_MON0: 103 case CS35L41_MDSYNC_EN: 104 case CS35L41_MDSYNC_TX_ID: 105 case CS35L41_MDSYNC_PWR_CTRL: 106 case CS35L41_MDSYNC_DATA_TX: 107 case CS35L41_MDSYNC_TX_STATUS: 108 case CS35L41_MDSYNC_DATA_RX: 109 case CS35L41_MDSYNC_RX_STATUS: 110 case CS35L41_MDSYNC_ERR_STATUS: 111 case CS35L41_MDSYNC_SYNC_PTE2: 112 case CS35L41_MDSYNC_SYNC_PTE3: 113 case CS35L41_MDSYNC_SYNC_MSM_STATUS: 114 case CS35L41_BSTCVRT_VCTRL1: 115 case CS35L41_BSTCVRT_VCTRL2: 116 case CS35L41_BSTCVRT_PEAK_CUR: 117 case CS35L41_BSTCVRT_SFT_RAMP: 118 case CS35L41_BSTCVRT_COEFF: 119 case CS35L41_BSTCVRT_SLOPE_LBST: 120 case CS35L41_BSTCVRT_SW_FREQ: 121 case CS35L41_BSTCVRT_DCM_CTRL: 122 case CS35L41_BSTCVRT_DCM_MODE_FORCE: 123 case CS35L41_BSTCVRT_OVERVOLT_CTRL: 124 case CS35L41_VI_VOL_POL: 125 case CS35L41_DTEMP_WARN_THLD: 126 case CS35L41_DTEMP_CFG: 127 case CS35L41_DTEMP_EN: 128 case CS35L41_VPVBST_FS_SEL: 129 case CS35L41_SP_ENABLES: 130 case CS35L41_SP_RATE_CTRL: 131 case CS35L41_SP_FORMAT: 132 case CS35L41_SP_HIZ_CTRL: 133 case CS35L41_SP_FRAME_TX_SLOT: 134 case CS35L41_SP_FRAME_RX_SLOT: 135 case CS35L41_SP_TX_WL: 136 case CS35L41_SP_RX_WL: 137 case CS35L41_DAC_PCM1_SRC: 138 case CS35L41_ASP_TX1_SRC: 139 case CS35L41_ASP_TX2_SRC: 140 case CS35L41_ASP_TX3_SRC: 141 case CS35L41_ASP_TX4_SRC: 142 case CS35L41_DSP1_RX1_SRC: 143 case CS35L41_DSP1_RX2_SRC: 144 case CS35L41_DSP1_RX3_SRC: 145 case CS35L41_DSP1_RX4_SRC: 146 case CS35L41_DSP1_RX5_SRC: 147 case CS35L41_DSP1_RX6_SRC: 148 case CS35L41_DSP1_RX7_SRC: 149 case CS35L41_DSP1_RX8_SRC: 150 case CS35L41_NGATE1_SRC: 151 case CS35L41_NGATE2_SRC: 152 case CS35L41_AMP_DIG_VOL_CTRL: 153 case CS35L41_VPBR_CFG: 154 case CS35L41_VBBR_CFG: 155 case CS35L41_VPBR_STATUS: 156 case CS35L41_VBBR_STATUS: 157 case CS35L41_OVERTEMP_CFG: 158 case CS35L41_AMP_ERR_VOL: 159 case CS35L41_VOL_STATUS_TO_DSP: 160 case CS35L41_CLASSH_CFG: 161 case CS35L41_WKFET_CFG: 162 case CS35L41_NG_CFG: 163 case CS35L41_AMP_GAIN_CTRL: 164 case CS35L41_DAC_MSM_CFG: 165 case CS35L41_IRQ1_CFG: 166 case CS35L41_IRQ1_STATUS: 167 case CS35L41_IRQ1_STATUS1: 168 case CS35L41_IRQ1_STATUS2: 169 case CS35L41_IRQ1_STATUS3: 170 case CS35L41_IRQ1_STATUS4: 171 case CS35L41_IRQ1_RAW_STATUS1: 172 case CS35L41_IRQ1_RAW_STATUS2: 173 case CS35L41_IRQ1_RAW_STATUS3: 174 case CS35L41_IRQ1_RAW_STATUS4: 175 case CS35L41_IRQ1_MASK1: 176 case CS35L41_IRQ1_MASK2: 177 case CS35L41_IRQ1_MASK3: 178 case CS35L41_IRQ1_MASK4: 179 case CS35L41_IRQ1_FRC1: 180 case CS35L41_IRQ1_FRC2: 181 case CS35L41_IRQ1_FRC3: 182 case CS35L41_IRQ1_FRC4: 183 case CS35L41_IRQ1_EDGE1: 184 case CS35L41_IRQ1_EDGE4: 185 case CS35L41_IRQ1_POL1: 186 case CS35L41_IRQ1_POL2: 187 case CS35L41_IRQ1_POL3: 188 case CS35L41_IRQ1_POL4: 189 case CS35L41_IRQ1_DB3: 190 case CS35L41_IRQ2_CFG: 191 case CS35L41_IRQ2_STATUS: 192 case CS35L41_IRQ2_STATUS1: 193 case CS35L41_IRQ2_STATUS2: 194 case CS35L41_IRQ2_STATUS3: 195 case CS35L41_IRQ2_STATUS4: 196 case CS35L41_IRQ2_RAW_STATUS1: 197 case CS35L41_IRQ2_RAW_STATUS2: 198 case CS35L41_IRQ2_RAW_STATUS3: 199 case CS35L41_IRQ2_RAW_STATUS4: 200 case CS35L41_IRQ2_MASK1: 201 case CS35L41_IRQ2_MASK2: 202 case CS35L41_IRQ2_MASK3: 203 case CS35L41_IRQ2_MASK4: 204 case CS35L41_IRQ2_FRC1: 205 case CS35L41_IRQ2_FRC2: 206 case CS35L41_IRQ2_FRC3: 207 case CS35L41_IRQ2_FRC4: 208 case CS35L41_IRQ2_EDGE1: 209 case CS35L41_IRQ2_EDGE4: 210 case CS35L41_IRQ2_POL1: 211 case CS35L41_IRQ2_POL2: 212 case CS35L41_IRQ2_POL3: 213 case CS35L41_IRQ2_POL4: 214 case CS35L41_IRQ2_DB3: 215 case CS35L41_GPIO_STATUS1: 216 case CS35L41_GPIO1_CTRL1: 217 case CS35L41_GPIO2_CTRL1: 218 case CS35L41_MIXER_NGATE_CFG: 219 case CS35L41_MIXER_NGATE_CH1_CFG: 220 case CS35L41_MIXER_NGATE_CH2_CFG: 221 case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8: 222 case CS35L41_CLOCK_DETECT_1: 223 case CS35L41_DIE_STS1: 224 case CS35L41_DIE_STS2: 225 case CS35L41_TEMP_CAL1: 226 case CS35L41_TEMP_CAL2: 227 case CS35L41_DSP1_TIMESTAMP_COUNT: 228 case CS35L41_DSP1_SYS_ID: 229 case CS35L41_DSP1_SYS_VERSION: 230 case CS35L41_DSP1_SYS_CORE_ID: 231 case CS35L41_DSP1_SYS_AHB_ADDR: 232 case CS35L41_DSP1_SYS_XSRAM_SIZE: 233 case CS35L41_DSP1_SYS_YSRAM_SIZE: 234 case CS35L41_DSP1_SYS_PSRAM_SIZE: 235 case CS35L41_DSP1_SYS_PM_BOOT_SIZE: 236 case CS35L41_DSP1_SYS_FEATURES: 237 case CS35L41_DSP1_SYS_FIR_FILTERS: 238 case CS35L41_DSP1_SYS_LMS_FILTERS: 239 case CS35L41_DSP1_SYS_XM_BANK_SIZE: 240 case CS35L41_DSP1_SYS_YM_BANK_SIZE: 241 case CS35L41_DSP1_SYS_PM_BANK_SIZE: 242 case CS35L41_DSP1_RX1_RATE: 243 case CS35L41_DSP1_RX2_RATE: 244 case CS35L41_DSP1_RX3_RATE: 245 case CS35L41_DSP1_RX4_RATE: 246 case CS35L41_DSP1_RX5_RATE: 247 case CS35L41_DSP1_RX6_RATE: 248 case CS35L41_DSP1_RX7_RATE: 249 case CS35L41_DSP1_RX8_RATE: 250 case CS35L41_DSP1_TX1_RATE: 251 case CS35L41_DSP1_TX2_RATE: 252 case CS35L41_DSP1_TX3_RATE: 253 case CS35L41_DSP1_TX4_RATE: 254 case CS35L41_DSP1_TX5_RATE: 255 case CS35L41_DSP1_TX6_RATE: 256 case CS35L41_DSP1_TX7_RATE: 257 case CS35L41_DSP1_TX8_RATE: 258 case CS35L41_DSP1_SCRATCH1: 259 case CS35L41_DSP1_SCRATCH2: 260 case CS35L41_DSP1_SCRATCH3: 261 case CS35L41_DSP1_SCRATCH4: 262 case CS35L41_DSP1_CCM_CORE_CTRL: 263 case CS35L41_DSP1_CCM_CLK_OVERRIDE: 264 case CS35L41_DSP1_XM_MSTR_EN: 265 case CS35L41_DSP1_XM_CORE_PRI: 266 case CS35L41_DSP1_XM_AHB_PACK_PL_PRI: 267 case CS35L41_DSP1_XM_AHB_UP_PL_PRI: 268 case CS35L41_DSP1_XM_ACCEL_PL0_PRI: 269 case CS35L41_DSP1_XM_NPL0_PRI: 270 case CS35L41_DSP1_YM_MSTR_EN: 271 case CS35L41_DSP1_YM_CORE_PRI: 272 case CS35L41_DSP1_YM_AHB_PACK_PL_PRI: 273 case CS35L41_DSP1_YM_AHB_UP_PL_PRI: 274 case CS35L41_DSP1_YM_ACCEL_PL0_PRI: 275 case CS35L41_DSP1_YM_NPL0_PRI: 276 case CS35L41_DSP1_MPU_XM_ACCESS0: 277 case CS35L41_DSP1_MPU_YM_ACCESS0: 278 case CS35L41_DSP1_MPU_WNDW_ACCESS0: 279 case CS35L41_DSP1_MPU_XREG_ACCESS0: 280 case CS35L41_DSP1_MPU_YREG_ACCESS0: 281 case CS35L41_DSP1_MPU_XM_ACCESS1: 282 case CS35L41_DSP1_MPU_YM_ACCESS1: 283 case CS35L41_DSP1_MPU_WNDW_ACCESS1: 284 case CS35L41_DSP1_MPU_XREG_ACCESS1: 285 case CS35L41_DSP1_MPU_YREG_ACCESS1: 286 case CS35L41_DSP1_MPU_XM_ACCESS2: 287 case CS35L41_DSP1_MPU_YM_ACCESS2: 288 case CS35L41_DSP1_MPU_WNDW_ACCESS2: 289 case CS35L41_DSP1_MPU_XREG_ACCESS2: 290 case CS35L41_DSP1_MPU_YREG_ACCESS2: 291 case CS35L41_DSP1_MPU_XM_ACCESS3: 292 case CS35L41_DSP1_MPU_YM_ACCESS3: 293 case CS35L41_DSP1_MPU_WNDW_ACCESS3: 294 case CS35L41_DSP1_MPU_XREG_ACCESS3: 295 case CS35L41_DSP1_MPU_YREG_ACCESS3: 296 case CS35L41_DSP1_MPU_XM_VIO_ADDR: 297 case CS35L41_DSP1_MPU_XM_VIO_STATUS: 298 case CS35L41_DSP1_MPU_YM_VIO_ADDR: 299 case CS35L41_DSP1_MPU_YM_VIO_STATUS: 300 case CS35L41_DSP1_MPU_PM_VIO_ADDR: 301 case CS35L41_DSP1_MPU_PM_VIO_STATUS: 302 case CS35L41_DSP1_MPU_LOCK_CONFIG: 303 case CS35L41_DSP1_MPU_WDT_RST_CTRL: 304 case CS35L41_OTP_TRIM_1: 305 case CS35L41_OTP_TRIM_2: 306 case CS35L41_OTP_TRIM_3: 307 case CS35L41_OTP_TRIM_4: 308 case CS35L41_OTP_TRIM_5: 309 case CS35L41_OTP_TRIM_6: 310 case CS35L41_OTP_TRIM_7: 311 case CS35L41_OTP_TRIM_8: 312 case CS35L41_OTP_TRIM_9: 313 case CS35L41_OTP_TRIM_10: 314 case CS35L41_OTP_TRIM_11: 315 case CS35L41_OTP_TRIM_12: 316 case CS35L41_OTP_TRIM_13: 317 case CS35L41_OTP_TRIM_14: 318 case CS35L41_OTP_TRIM_15: 319 case CS35L41_OTP_TRIM_16: 320 case CS35L41_OTP_TRIM_17: 321 case CS35L41_OTP_TRIM_18: 322 case CS35L41_OTP_TRIM_19: 323 case CS35L41_OTP_TRIM_20: 324 case CS35L41_OTP_TRIM_21: 325 case CS35L41_OTP_TRIM_22: 326 case CS35L41_OTP_TRIM_23: 327 case CS35L41_OTP_TRIM_24: 328 case CS35L41_OTP_TRIM_25: 329 case CS35L41_OTP_TRIM_26: 330 case CS35L41_OTP_TRIM_27: 331 case CS35L41_OTP_TRIM_28: 332 case CS35L41_OTP_TRIM_29: 333 case CS35L41_OTP_TRIM_30: 334 case CS35L41_OTP_TRIM_31: 335 case CS35L41_OTP_TRIM_32: 336 case CS35L41_OTP_TRIM_33: 337 case CS35L41_OTP_TRIM_34: 338 case CS35L41_OTP_TRIM_35: 339 case CS35L41_OTP_TRIM_36: 340 case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31: 341 case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068: 342 case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046: 343 case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093: 344 case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532: 345 case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022: 346 case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045: 347 case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114: 348 /*test regs*/ 349 case CS35L41_PLL_OVR: 350 case CS35L41_BST_TEST_DUTY: 351 case CS35L41_DIGPWM_IOCTRL: 352 return true; 353 default: 354 return false; 355 } 356 } 357 358 static bool cs35l41_precious_reg(struct device *dev, unsigned int reg) 359 { 360 switch (reg) { 361 case CS35L41_TEST_KEY_CTL: 362 case CS35L41_USER_KEY_CTL: 363 case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31: 364 case CS35L41_TST_FS_MON0: 365 case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068: 366 case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532: 367 case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114: 368 return true; 369 default: 370 return false; 371 } 372 } 373 374 static bool cs35l41_volatile_reg(struct device *dev, unsigned int reg) 375 { 376 switch (reg) { 377 case CS35L41_DEVID: 378 case CS35L41_SFT_RESET: 379 case CS35L41_FABID: 380 case CS35L41_REVID: 381 case CS35L41_OTPID: 382 case CS35L41_TEST_KEY_CTL: 383 case CS35L41_USER_KEY_CTL: 384 case CS35L41_PWRMGT_CTL: 385 case CS35L41_WAKESRC_CTL: 386 case CS35L41_PWRMGT_STS: 387 case CS35L41_DTEMP_EN: 388 case CS35L41_IRQ1_STATUS: 389 case CS35L41_IRQ1_STATUS1: 390 case CS35L41_IRQ1_STATUS2: 391 case CS35L41_IRQ1_STATUS3: 392 case CS35L41_IRQ1_STATUS4: 393 case CS35L41_IRQ1_RAW_STATUS1: 394 case CS35L41_IRQ1_RAW_STATUS2: 395 case CS35L41_IRQ1_RAW_STATUS3: 396 case CS35L41_IRQ1_RAW_STATUS4: 397 case CS35L41_IRQ2_STATUS: 398 case CS35L41_IRQ2_STATUS1: 399 case CS35L41_IRQ2_STATUS2: 400 case CS35L41_IRQ2_STATUS3: 401 case CS35L41_IRQ2_STATUS4: 402 case CS35L41_IRQ2_RAW_STATUS1: 403 case CS35L41_IRQ2_RAW_STATUS2: 404 case CS35L41_IRQ2_RAW_STATUS3: 405 case CS35L41_IRQ2_RAW_STATUS4: 406 case CS35L41_GPIO_STATUS1: 407 case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8: 408 case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068: 409 case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046: 410 case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093: 411 case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532: 412 case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022: 413 case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045: 414 case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114: 415 case CS35L41_DSP1_SCRATCH1: 416 case CS35L41_DSP1_SCRATCH2: 417 case CS35L41_DSP1_SCRATCH3: 418 case CS35L41_DSP1_SCRATCH4: 419 case CS35L41_DSP1_CCM_CLK_OVERRIDE ... CS35L41_DSP1_WDT_STATUS: 420 case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31: 421 return true; 422 default: 423 return false; 424 } 425 } 426 427 static const struct cs35l41_otp_packed_element_t otp_map_1[] = { 428 /* addr shift size */ 429 { 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/ 430 { 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/ 431 { 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/ 432 { 0x00002090, 14, 4 }, /*TST_REF_TRIM*/ 433 { 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/ 434 { 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/ 435 { 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/ 436 { 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/ 437 { 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/ 438 { 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/ 439 { 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/ 440 { 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/ 441 { 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/ 442 { 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/ 443 { 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/ 444 { 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/ 445 { 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/ 446 { 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/ 447 { 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/ 448 { 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/ 449 { 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/ 450 { 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/ 451 { 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/ 452 { 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/ 453 { 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/ 454 { 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/ 455 { 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/ 456 { 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/ 457 { 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/ 458 { 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/ 459 { 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/ 460 { 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/ 461 { 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/ 462 { 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/ 463 { 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/ 464 { 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/ 465 { 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/ 466 { 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/ 467 { 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/ 468 { 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/ 469 { 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/ 470 { 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/ 471 { 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/ 472 { 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/ 473 { 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/ 474 { 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/ 475 { 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/ 476 { 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/ 477 { 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/ 478 { 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/ 479 { 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/ 480 { 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/ 481 { 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/ 482 { 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/ 483 { 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/ 484 { 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/ 485 { 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/ 486 { 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/ 487 { 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/ 488 { 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/ 489 { 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/ 490 { 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/ 491 { 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/ 492 { 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/ 493 { 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/ 494 { 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/ 495 { 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/ 496 { 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/ 497 { 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/ 498 { 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/ 499 { 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/ 500 { 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/ 501 { 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/ 502 { 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/ 503 { 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/ 504 { 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/ 505 { 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/ 506 { 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/ 507 { 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/ 508 { 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/ 509 { 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/ 510 { 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/ 511 { 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/ 512 { 0x00006E64, 0, 10 }, /*VOFF_INT1*/ 513 { 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/ 514 { 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/ 515 { 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/ 516 { 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/ 517 { 0x00007434, 17, 1 }, /*FORCE_CAL*/ 518 { 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/ 519 { 0x00007068, 0, 9 }, /*MODIX*/ 520 { 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/ 521 { 0x0000400C, 0, 7 }, /*VIMON_DLY*/ 522 { 0x00000000, 0, 1 }, /*extra bit*/ 523 { 0x00017040, 0, 8 }, /*X_COORDINATE*/ 524 { 0x00017040, 8, 8 }, /*Y_COORDINATE*/ 525 { 0x00017040, 16, 8 }, /*WAFER_ID*/ 526 { 0x00017040, 24, 8 }, /*DVS*/ 527 { 0x00017044, 0, 24 }, /*LOT_NUMBER*/ 528 }; 529 530 static const struct cs35l41_otp_packed_element_t otp_map_2[] = { 531 /* addr shift size */ 532 { 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/ 533 { 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/ 534 { 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/ 535 { 0x00002090, 14, 4 }, /*TST_REF_TRIM*/ 536 { 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/ 537 { 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/ 538 { 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/ 539 { 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/ 540 { 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/ 541 { 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/ 542 { 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/ 543 { 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/ 544 { 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/ 545 { 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/ 546 { 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/ 547 { 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/ 548 { 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/ 549 { 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/ 550 { 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/ 551 { 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/ 552 { 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/ 553 { 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/ 554 { 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/ 555 { 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/ 556 { 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/ 557 { 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/ 558 { 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/ 559 { 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/ 560 { 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/ 561 { 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/ 562 { 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/ 563 { 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/ 564 { 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/ 565 { 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/ 566 { 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/ 567 { 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/ 568 { 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/ 569 { 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/ 570 { 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/ 571 { 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/ 572 { 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/ 573 { 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/ 574 { 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/ 575 { 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/ 576 { 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/ 577 { 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/ 578 { 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/ 579 { 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/ 580 { 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/ 581 { 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/ 582 { 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/ 583 { 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/ 584 { 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/ 585 { 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/ 586 { 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/ 587 { 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/ 588 { 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/ 589 { 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/ 590 { 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/ 591 { 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/ 592 { 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/ 593 { 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/ 594 { 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/ 595 { 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/ 596 { 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/ 597 { 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/ 598 { 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/ 599 { 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/ 600 { 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/ 601 { 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/ 602 { 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/ 603 { 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/ 604 { 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/ 605 { 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/ 606 { 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/ 607 { 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/ 608 { 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/ 609 { 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/ 610 { 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/ 611 { 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/ 612 { 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/ 613 { 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/ 614 { 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/ 615 { 0x00006E64, 0, 10 }, /*VOFF_INT1*/ 616 { 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/ 617 { 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/ 618 { 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/ 619 { 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/ 620 { 0x00007434, 17, 1 }, /*FORCE_CAL*/ 621 { 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/ 622 { 0x00007068, 0, 9 }, /*MODIX*/ 623 { 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/ 624 { 0x0000400C, 0, 7 }, /*VIMON_DLY*/ 625 { 0x00004000, 11, 1 }, /*VMON_POL*/ 626 { 0x00017040, 0, 8 }, /*X_COORDINATE*/ 627 { 0x00017040, 8, 8 }, /*Y_COORDINATE*/ 628 { 0x00017040, 16, 8 }, /*WAFER_ID*/ 629 { 0x00017040, 24, 8 }, /*DVS*/ 630 { 0x00017044, 0, 24 }, /*LOT_NUMBER*/ 631 }; 632 633 static const struct reg_sequence cs35l41_reva0_errata_patch[] = { 634 { 0x00003854, 0x05180240 }, 635 { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 }, 636 { 0x00004310, 0x00000000 }, 637 { CS35L41_VPVBST_FS_SEL, 0x00000000 }, 638 { CS35L41_OTP_TRIM_30, 0x9091A1C8 }, 639 { 0x00003014, 0x0200EE0E }, 640 { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 }, 641 { 0x00000054, 0x00000004 }, 642 { CS35L41_IRQ1_DB3, 0x00000000 }, 643 { CS35L41_IRQ2_DB3, 0x00000000 }, 644 { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 }, 645 { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 }, 646 { CS35L41_PWR_CTRL2, 0x00000000 }, 647 { CS35L41_AMP_GAIN_CTRL, 0x00000000 }, 648 { CS35L41_ASP_TX3_SRC, 0x00000000 }, 649 { CS35L41_ASP_TX4_SRC, 0x00000000 }, 650 }; 651 652 static const struct reg_sequence cs35l41_revb0_errata_patch[] = { 653 { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 }, 654 { 0x00004310, 0x00000000 }, 655 { CS35L41_VPVBST_FS_SEL, 0x00000000 }, 656 { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 }, 657 { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 }, 658 { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 }, 659 { CS35L41_PWR_CTRL2, 0x00000000 }, 660 { CS35L41_AMP_GAIN_CTRL, 0x00000000 }, 661 { CS35L41_ASP_TX3_SRC, 0x00000000 }, 662 { CS35L41_ASP_TX4_SRC, 0x00000000 }, 663 }; 664 665 static const struct reg_sequence cs35l41_revb2_errata_patch[] = { 666 { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 }, 667 { 0x00004310, 0x00000000 }, 668 { CS35L41_VPVBST_FS_SEL, 0x00000000 }, 669 { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 }, 670 { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 }, 671 { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 }, 672 { CS35L41_PWR_CTRL2, 0x00000000 }, 673 { CS35L41_AMP_GAIN_CTRL, 0x00000000 }, 674 { CS35L41_ASP_TX3_SRC, 0x00000000 }, 675 { CS35L41_ASP_TX4_SRC, 0x00000000 }, 676 }; 677 678 static const struct reg_sequence cs35l41_fs_errata_patch[] = { 679 { CS35L41_DSP1_RX1_RATE, 0x00000001 }, 680 { CS35L41_DSP1_RX2_RATE, 0x00000001 }, 681 { CS35L41_DSP1_RX3_RATE, 0x00000001 }, 682 { CS35L41_DSP1_RX4_RATE, 0x00000001 }, 683 { CS35L41_DSP1_RX5_RATE, 0x00000001 }, 684 { CS35L41_DSP1_RX6_RATE, 0x00000001 }, 685 { CS35L41_DSP1_RX7_RATE, 0x00000001 }, 686 { CS35L41_DSP1_RX8_RATE, 0x00000001 }, 687 { CS35L41_DSP1_TX1_RATE, 0x00000001 }, 688 { CS35L41_DSP1_TX2_RATE, 0x00000001 }, 689 { CS35L41_DSP1_TX3_RATE, 0x00000001 }, 690 { CS35L41_DSP1_TX4_RATE, 0x00000001 }, 691 { CS35L41_DSP1_TX5_RATE, 0x00000001 }, 692 { CS35L41_DSP1_TX6_RATE, 0x00000001 }, 693 { CS35L41_DSP1_TX7_RATE, 0x00000001 }, 694 { CS35L41_DSP1_TX8_RATE, 0x00000001 }, 695 }; 696 697 static const struct cs35l41_otp_map_element_t cs35l41_otp_map_map[] = { 698 { 699 .id = 0x01, 700 .map = otp_map_1, 701 .num_elements = ARRAY_SIZE(otp_map_1), 702 .bit_offset = 16, 703 .word_offset = 2, 704 }, 705 { 706 .id = 0x02, 707 .map = otp_map_2, 708 .num_elements = ARRAY_SIZE(otp_map_2), 709 .bit_offset = 16, 710 .word_offset = 2, 711 }, 712 { 713 .id = 0x03, 714 .map = otp_map_2, 715 .num_elements = ARRAY_SIZE(otp_map_2), 716 .bit_offset = 16, 717 .word_offset = 2, 718 }, 719 { 720 .id = 0x06, 721 .map = otp_map_2, 722 .num_elements = ARRAY_SIZE(otp_map_2), 723 .bit_offset = 16, 724 .word_offset = 2, 725 }, 726 { 727 .id = 0x08, 728 .map = otp_map_1, 729 .num_elements = ARRAY_SIZE(otp_map_1), 730 .bit_offset = 16, 731 .word_offset = 2, 732 }, 733 }; 734 735 struct regmap_config cs35l41_regmap_i2c = { 736 .reg_bits = 32, 737 .val_bits = 32, 738 .reg_stride = CS35L41_REGSTRIDE, 739 .reg_format_endian = REGMAP_ENDIAN_BIG, 740 .val_format_endian = REGMAP_ENDIAN_BIG, 741 .max_register = CS35L41_LASTREG, 742 .reg_defaults = cs35l41_reg, 743 .num_reg_defaults = ARRAY_SIZE(cs35l41_reg), 744 .volatile_reg = cs35l41_volatile_reg, 745 .readable_reg = cs35l41_readable_reg, 746 .precious_reg = cs35l41_precious_reg, 747 .cache_type = REGCACHE_MAPLE, 748 }; 749 EXPORT_SYMBOL_GPL(cs35l41_regmap_i2c); 750 751 struct regmap_config cs35l41_regmap_spi = { 752 .reg_bits = 32, 753 .val_bits = 32, 754 .pad_bits = 16, 755 .reg_stride = CS35L41_REGSTRIDE, 756 .reg_format_endian = REGMAP_ENDIAN_BIG, 757 .val_format_endian = REGMAP_ENDIAN_BIG, 758 .max_register = CS35L41_LASTREG, 759 .reg_defaults = cs35l41_reg, 760 .num_reg_defaults = ARRAY_SIZE(cs35l41_reg), 761 .volatile_reg = cs35l41_volatile_reg, 762 .readable_reg = cs35l41_readable_reg, 763 .precious_reg = cs35l41_precious_reg, 764 .cache_type = REGCACHE_MAPLE, 765 }; 766 EXPORT_SYMBOL_GPL(cs35l41_regmap_spi); 767 768 static const struct cs35l41_otp_map_element_t *cs35l41_find_otp_map(u32 otp_id) 769 { 770 int i; 771 772 for (i = 0; i < ARRAY_SIZE(cs35l41_otp_map_map); i++) { 773 if (cs35l41_otp_map_map[i].id == otp_id) 774 return &cs35l41_otp_map_map[i]; 775 } 776 777 return NULL; 778 } 779 780 int cs35l41_test_key_unlock(struct device *dev, struct regmap *regmap) 781 { 782 static const struct reg_sequence unlock[] = { 783 { CS35L41_TEST_KEY_CTL, 0x00000055 }, 784 { CS35L41_TEST_KEY_CTL, 0x000000AA }, 785 }; 786 int ret; 787 788 ret = regmap_multi_reg_write(regmap, unlock, ARRAY_SIZE(unlock)); 789 if (ret) 790 dev_err(dev, "Failed to unlock test key: %d\n", ret); 791 792 return ret; 793 } 794 EXPORT_SYMBOL_GPL(cs35l41_test_key_unlock); 795 796 int cs35l41_test_key_lock(struct device *dev, struct regmap *regmap) 797 { 798 static const struct reg_sequence unlock[] = { 799 { CS35L41_TEST_KEY_CTL, 0x000000CC }, 800 { CS35L41_TEST_KEY_CTL, 0x00000033 }, 801 }; 802 int ret; 803 804 ret = regmap_multi_reg_write(regmap, unlock, ARRAY_SIZE(unlock)); 805 if (ret) 806 dev_err(dev, "Failed to lock test key: %d\n", ret); 807 808 return ret; 809 } 810 EXPORT_SYMBOL_GPL(cs35l41_test_key_lock); 811 812 /* Must be called with the TEST_KEY unlocked */ 813 int cs35l41_otp_unpack(struct device *dev, struct regmap *regmap) 814 { 815 const struct cs35l41_otp_map_element_t *otp_map_match; 816 const struct cs35l41_otp_packed_element_t *otp_map; 817 int bit_offset, word_offset, ret, i; 818 unsigned int bit_sum = 8; 819 u32 otp_val, otp_id_reg; 820 u32 *otp_mem; 821 822 otp_mem = kmalloc_array(CS35L41_OTP_SIZE_WORDS, sizeof(*otp_mem), GFP_KERNEL); 823 if (!otp_mem) 824 return -ENOMEM; 825 826 ret = regmap_read(regmap, CS35L41_OTPID, &otp_id_reg); 827 if (ret) { 828 dev_err(dev, "Read OTP ID failed: %d\n", ret); 829 goto err_otp_unpack; 830 } 831 832 otp_map_match = cs35l41_find_otp_map(otp_id_reg); 833 834 if (!otp_map_match) { 835 dev_err(dev, "OTP Map matching ID %d not found\n", otp_id_reg); 836 ret = -EINVAL; 837 goto err_otp_unpack; 838 } 839 840 ret = regmap_bulk_read(regmap, CS35L41_OTP_MEM0, otp_mem, CS35L41_OTP_SIZE_WORDS); 841 if (ret) { 842 dev_err(dev, "Read OTP Mem failed: %d\n", ret); 843 goto err_otp_unpack; 844 } 845 846 otp_map = otp_map_match->map; 847 848 bit_offset = otp_map_match->bit_offset; 849 word_offset = otp_map_match->word_offset; 850 851 for (i = 0; i < otp_map_match->num_elements; i++) { 852 dev_dbg(dev, "bitoffset= %d, word_offset=%d, bit_sum mod 32=%d, otp_map[i].size = %u\n", 853 bit_offset, word_offset, bit_sum % 32, otp_map[i].size); 854 if (bit_offset + otp_map[i].size - 1 >= 32) { 855 otp_val = (otp_mem[word_offset] & 856 GENMASK(31, bit_offset)) >> bit_offset; 857 otp_val |= (otp_mem[++word_offset] & 858 GENMASK(bit_offset + otp_map[i].size - 33, 0)) << 859 (32 - bit_offset); 860 bit_offset += otp_map[i].size - 32; 861 } else if (bit_offset + otp_map[i].size - 1 >= 0) { 862 otp_val = (otp_mem[word_offset] & 863 GENMASK(bit_offset + otp_map[i].size - 1, bit_offset) 864 ) >> bit_offset; 865 bit_offset += otp_map[i].size; 866 } else /* both bit_offset and otp_map[i].size are 0 */ 867 otp_val = 0; 868 869 bit_sum += otp_map[i].size; 870 871 if (bit_offset == 32) { 872 bit_offset = 0; 873 word_offset++; 874 } 875 876 if (otp_map[i].reg != 0) { 877 ret = regmap_update_bits(regmap, otp_map[i].reg, 878 GENMASK(otp_map[i].shift + otp_map[i].size - 1, 879 otp_map[i].shift), 880 otp_val << otp_map[i].shift); 881 if (ret < 0) { 882 dev_err(dev, "Write OTP val failed: %d\n", ret); 883 goto err_otp_unpack; 884 } 885 } 886 } 887 888 ret = 0; 889 890 err_otp_unpack: 891 kfree(otp_mem); 892 893 return ret; 894 } 895 EXPORT_SYMBOL_GPL(cs35l41_otp_unpack); 896 897 /* Must be called with the TEST_KEY unlocked */ 898 int cs35l41_register_errata_patch(struct device *dev, struct regmap *reg, unsigned int reg_revid) 899 { 900 char *rev; 901 int ret; 902 903 switch (reg_revid) { 904 case CS35L41_REVID_A0: 905 ret = regmap_register_patch(reg, cs35l41_reva0_errata_patch, 906 ARRAY_SIZE(cs35l41_reva0_errata_patch)); 907 rev = "A0"; 908 break; 909 case CS35L41_REVID_B0: 910 ret = regmap_register_patch(reg, cs35l41_revb0_errata_patch, 911 ARRAY_SIZE(cs35l41_revb0_errata_patch)); 912 rev = "B0"; 913 break; 914 case CS35L41_REVID_B2: 915 ret = regmap_register_patch(reg, cs35l41_revb2_errata_patch, 916 ARRAY_SIZE(cs35l41_revb2_errata_patch)); 917 rev = "B2"; 918 break; 919 default: 920 ret = -EINVAL; 921 rev = "XX"; 922 break; 923 } 924 925 if (ret) 926 dev_err(dev, "Failed to apply %s errata patch: %d\n", rev, ret); 927 928 ret = regmap_write(reg, CS35L41_DSP1_CCM_CORE_CTRL, 0); 929 if (ret < 0) 930 dev_err(dev, "Write CCM_CORE_CTRL failed: %d\n", ret); 931 932 return ret; 933 } 934 EXPORT_SYMBOL_GPL(cs35l41_register_errata_patch); 935 936 int cs35l41_set_channels(struct device *dev, struct regmap *reg, 937 unsigned int tx_num, unsigned int *tx_slot, 938 unsigned int rx_num, unsigned int *rx_slot) 939 { 940 unsigned int val, mask; 941 int i; 942 943 if (tx_num > 4 || rx_num > 2) 944 return -EINVAL; 945 946 val = 0; 947 mask = 0; 948 for (i = 0; i < rx_num; i++) { 949 dev_dbg(dev, "rx slot %d position = %d\n", i, rx_slot[i]); 950 val |= rx_slot[i] << (i * 8); 951 mask |= 0x3F << (i * 8); 952 } 953 regmap_update_bits(reg, CS35L41_SP_FRAME_RX_SLOT, mask, val); 954 955 val = 0; 956 mask = 0; 957 for (i = 0; i < tx_num; i++) { 958 dev_dbg(dev, "tx slot %d position = %d\n", i, tx_slot[i]); 959 val |= tx_slot[i] << (i * 8); 960 mask |= 0x3F << (i * 8); 961 } 962 regmap_update_bits(reg, CS35L41_SP_FRAME_TX_SLOT, mask, val); 963 964 return 0; 965 } 966 EXPORT_SYMBOL_GPL(cs35l41_set_channels); 967 968 static const unsigned char cs35l41_bst_k1_table[4][5] = { 969 { 0x24, 0x32, 0x32, 0x4F, 0x57 }, 970 { 0x24, 0x32, 0x32, 0x4F, 0x57 }, 971 { 0x40, 0x32, 0x32, 0x4F, 0x57 }, 972 { 0x40, 0x32, 0x32, 0x4F, 0x57 } 973 }; 974 975 static const unsigned char cs35l41_bst_k2_table[4][5] = { 976 { 0x24, 0x49, 0x66, 0xA3, 0xEA }, 977 { 0x24, 0x49, 0x66, 0xA3, 0xEA }, 978 { 0x48, 0x49, 0x66, 0xA3, 0xEA }, 979 { 0x48, 0x49, 0x66, 0xA3, 0xEA } 980 }; 981 982 static const unsigned char cs35l41_bst_slope_table[4] = { 983 0x75, 0x6B, 0x3B, 0x28 984 }; 985 986 static int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_ind, 987 int boost_cap, int boost_ipk) 988 { 989 unsigned char bst_lbst_val, bst_cbst_range, bst_ipk_scaled; 990 int ret; 991 992 switch (boost_ind) { 993 case 1000: /* 1.0 uH */ 994 bst_lbst_val = 0; 995 break; 996 case 1200: /* 1.2 uH */ 997 bst_lbst_val = 1; 998 break; 999 case 1500: /* 1.5 uH */ 1000 bst_lbst_val = 2; 1001 break; 1002 case 2200: /* 2.2 uH */ 1003 bst_lbst_val = 3; 1004 break; 1005 default: 1006 dev_err(dev, "Invalid boost inductor value: %d nH\n", boost_ind); 1007 return -EINVAL; 1008 } 1009 1010 switch (boost_cap) { 1011 case 0 ... 19: 1012 bst_cbst_range = 0; 1013 break; 1014 case 20 ... 50: 1015 bst_cbst_range = 1; 1016 break; 1017 case 51 ... 100: 1018 bst_cbst_range = 2; 1019 break; 1020 case 101 ... 200: 1021 bst_cbst_range = 3; 1022 break; 1023 default: 1024 if (boost_cap < 0) { 1025 dev_err(dev, "Invalid boost capacitor value: %d nH\n", boost_cap); 1026 return -EINVAL; 1027 } 1028 /* 201 uF and greater */ 1029 bst_cbst_range = 4; 1030 } 1031 1032 if (boost_ipk < 1600 || boost_ipk > 4500) { 1033 dev_err(dev, "Invalid boost inductor peak current: %d mA\n", boost_ipk); 1034 return -EINVAL; 1035 } 1036 1037 ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_COEFF, 1038 CS35L41_BST_K1_MASK | CS35L41_BST_K2_MASK, 1039 cs35l41_bst_k1_table[bst_lbst_val][bst_cbst_range] 1040 << CS35L41_BST_K1_SHIFT | 1041 cs35l41_bst_k2_table[bst_lbst_val][bst_cbst_range] 1042 << CS35L41_BST_K2_SHIFT); 1043 if (ret) { 1044 dev_err(dev, "Failed to write boost coefficients: %d\n", ret); 1045 return ret; 1046 } 1047 1048 ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_SLOPE_LBST, 1049 CS35L41_BST_SLOPE_MASK | CS35L41_BST_LBST_VAL_MASK, 1050 cs35l41_bst_slope_table[bst_lbst_val] 1051 << CS35L41_BST_SLOPE_SHIFT | 1052 bst_lbst_val << CS35L41_BST_LBST_VAL_SHIFT); 1053 if (ret) { 1054 dev_err(dev, "Failed to write boost slope/inductor value: %d\n", ret); 1055 return ret; 1056 } 1057 1058 bst_ipk_scaled = ((boost_ipk - 1600) / 50) + 0x10; 1059 1060 ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_PEAK_CUR, CS35L41_BST_IPK_MASK, 1061 bst_ipk_scaled << CS35L41_BST_IPK_SHIFT); 1062 if (ret) { 1063 dev_err(dev, "Failed to write boost inductor peak current: %d\n", ret); 1064 return ret; 1065 } 1066 1067 regmap_update_bits(regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK, 1068 CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT); 1069 1070 return 0; 1071 } 1072 1073 static const struct reg_sequence cs35l41_safe_to_reset[] = { 1074 { 0x00000040, 0x00000055 }, 1075 { 0x00000040, 0x000000AA }, 1076 { 0x0000393C, 0x000000C0, 6000}, 1077 { 0x0000393C, 0x00000000 }, 1078 { 0x00007414, 0x00C82222 }, 1079 { 0x0000742C, 0x00000000 }, 1080 { 0x00000040, 0x000000CC }, 1081 { 0x00000040, 0x00000033 }, 1082 }; 1083 1084 static const struct reg_sequence cs35l41_active_to_safe_start[] = { 1085 { 0x00000040, 0x00000055 }, 1086 { 0x00000040, 0x000000AA }, 1087 { 0x00007438, 0x00585941 }, 1088 { CS35L41_PWR_CTRL1, 0x00000000 }, 1089 { 0x0000742C, 0x00000009 }, 1090 }; 1091 1092 static const struct reg_sequence cs35l41_active_to_safe_end[] = { 1093 { 0x00007438, 0x00580941 }, 1094 { 0x00000040, 0x000000CC }, 1095 { 0x00000040, 0x00000033 }, 1096 }; 1097 1098 static const struct reg_sequence cs35l41_safe_to_active_start[] = { 1099 { 0x00000040, 0x00000055 }, 1100 { 0x00000040, 0x000000AA }, 1101 { 0x0000742C, 0x0000000F }, 1102 { 0x0000742C, 0x00000079 }, 1103 { 0x00007438, 0x00585941 }, 1104 { CS35L41_PWR_CTRL1, 0x00000001 }, // GLOBAL_EN = 1 1105 }; 1106 1107 static const struct reg_sequence cs35l41_safe_to_active_en_spk[] = { 1108 { 0x0000742C, 0x000000F9 }, 1109 { 0x00007438, 0x00580941 }, 1110 }; 1111 1112 static const struct reg_sequence cs35l41_reset_to_safe[] = { 1113 { 0x00000040, 0x00000055 }, 1114 { 0x00000040, 0x000000AA }, 1115 { 0x00007438, 0x00585941 }, 1116 { 0x00007414, 0x08C82222 }, 1117 { 0x0000742C, 0x00000009 }, 1118 { 0x00000040, 0x000000CC }, 1119 { 0x00000040, 0x00000033 }, 1120 }; 1121 1122 static const struct reg_sequence cs35l41_actv_seq[] = { 1123 /* SYNC_BST_CTL_RX_EN = 1; SYNC_BST_CTL_TX_EN = 1 */ 1124 {CS35L41_MDSYNC_EN, 0x00003000}, 1125 /* BST_CTL_SEL = MDSYNC */ 1126 {CS35L41_BSTCVRT_VCTRL2, 0x00000002}, 1127 }; 1128 1129 static const struct reg_sequence cs35l41_pass_seq[] = { 1130 /* SYNC_BST_CTL_RX_EN = 0; SYNC_BST_CTL_TX_EN = 1 */ 1131 {CS35L41_MDSYNC_EN, 0x00001000}, 1132 /* BST_EN = 0 */ 1133 {CS35L41_PWR_CTRL2, 0x00003300}, 1134 /* BST_CTL_SEL = MDSYNC */ 1135 {CS35L41_BSTCVRT_VCTRL2, 0x00000002}, 1136 }; 1137 1138 int cs35l41_init_boost(struct device *dev, struct regmap *regmap, 1139 struct cs35l41_hw_cfg *hw_cfg) 1140 { 1141 int ret; 1142 1143 switch (hw_cfg->bst_type) { 1144 case CS35L41_SHD_BOOST_ACTV: 1145 regmap_multi_reg_write(regmap, cs35l41_actv_seq, ARRAY_SIZE(cs35l41_actv_seq)); 1146 fallthrough; 1147 case CS35L41_INT_BOOST: 1148 ret = cs35l41_boost_config(dev, regmap, hw_cfg->bst_ind, 1149 hw_cfg->bst_cap, hw_cfg->bst_ipk); 1150 if (ret) 1151 dev_err(dev, "Error in Boost DT config: %d\n", ret); 1152 break; 1153 case CS35L41_EXT_BOOST: 1154 case CS35L41_EXT_BOOST_NO_VSPK_SWITCH: 1155 /* Only CLSA0100 doesn't use GPIO as VSPK switch, but even on that laptop we can 1156 * toggle GPIO1 as is not connected to anything. 1157 * There will be no other device without VSPK switch. 1158 */ 1159 regmap_write(regmap, CS35L41_GPIO1_CTRL1, 0x00000001); 1160 regmap_multi_reg_write(regmap, cs35l41_reset_to_safe, 1161 ARRAY_SIZE(cs35l41_reset_to_safe)); 1162 ret = regmap_update_bits(regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK, 1163 CS35L41_BST_DIS_FET_OFF << CS35L41_BST_EN_SHIFT); 1164 break; 1165 case CS35L41_SHD_BOOST_PASS: 1166 ret = regmap_multi_reg_write(regmap, cs35l41_pass_seq, 1167 ARRAY_SIZE(cs35l41_pass_seq)); 1168 break; 1169 default: 1170 dev_err(dev, "Boost type %d not supported\n", hw_cfg->bst_type); 1171 ret = -EINVAL; 1172 break; 1173 } 1174 1175 return ret; 1176 } 1177 EXPORT_SYMBOL_GPL(cs35l41_init_boost); 1178 1179 bool cs35l41_safe_reset(struct regmap *regmap, enum cs35l41_boost_type b_type) 1180 { 1181 switch (b_type) { 1182 /* There is only one laptop that doesn't have VSPK switch. */ 1183 case CS35L41_EXT_BOOST_NO_VSPK_SWITCH: 1184 return false; 1185 case CS35L41_EXT_BOOST: 1186 regmap_write(regmap, CS35L41_GPIO1_CTRL1, 0x00000001); 1187 regmap_multi_reg_write(regmap, cs35l41_safe_to_reset, 1188 ARRAY_SIZE(cs35l41_safe_to_reset)); 1189 return true; 1190 default: 1191 return true; 1192 } 1193 } 1194 EXPORT_SYMBOL_GPL(cs35l41_safe_reset); 1195 1196 /* 1197 * Enabling the CS35L41_SHD_BOOST_ACTV and CS35L41_SHD_BOOST_PASS shared boosts 1198 * does also require a call to cs35l41_mdsync_up(), but not before getting the 1199 * PLL Lock signal. 1200 * 1201 * PLL Lock seems to be triggered soon after snd_pcm_start() is executed and 1202 * SNDRV_PCM_TRIGGER_START command is processed, which happens (long) after the 1203 * SND_SOC_DAPM_PRE_PMU event handler is invoked as part of snd_pcm_prepare(). 1204 * 1205 * This event handler is where cs35l41_global_enable() is normally called from, 1206 * but waiting for PLL Lock here will time out. Increasing the wait duration 1207 * will not help, as the only consequence of it would be to add an unnecessary 1208 * delay in the invocation of snd_pcm_start(). 1209 * 1210 * Trying to move the wait in the SNDRV_PCM_TRIGGER_START callback is not a 1211 * solution either, as the trigger is executed in an IRQ-off atomic context. 1212 * 1213 * The current approach is to invoke cs35l41_mdsync_up() right after receiving 1214 * the PLL Lock interrupt, in the IRQ handler. 1215 */ 1216 int cs35l41_global_enable(struct device *dev, struct regmap *regmap, enum cs35l41_boost_type b_type, 1217 int enable, bool firmware_running) 1218 { 1219 int ret; 1220 unsigned int gpio1_func, pad_control, pwr_ctrl1, pwr_ctrl3, int_status, pup_pdn_mask; 1221 unsigned int pwr_ctl1_val; 1222 struct reg_sequence cs35l41_mdsync_down_seq[] = { 1223 {CS35L41_PWR_CTRL3, 0}, 1224 {CS35L41_GPIO_PAD_CONTROL, 0}, 1225 {CS35L41_PWR_CTRL1, 0, 3000}, 1226 }; 1227 1228 pup_pdn_mask = enable ? CS35L41_PUP_DONE_MASK : CS35L41_PDN_DONE_MASK; 1229 1230 ret = regmap_read(regmap, CS35L41_PWR_CTRL1, &pwr_ctl1_val); 1231 if (ret) 1232 return ret; 1233 1234 if ((pwr_ctl1_val & CS35L41_GLOBAL_EN_MASK) && enable) { 1235 dev_dbg(dev, "Cannot set Global Enable - already set.\n"); 1236 return 0; 1237 } else if (!(pwr_ctl1_val & CS35L41_GLOBAL_EN_MASK) && !enable) { 1238 dev_dbg(dev, "Cannot unset Global Enable - not set.\n"); 1239 return 0; 1240 } 1241 1242 switch (b_type) { 1243 case CS35L41_SHD_BOOST_ACTV: 1244 case CS35L41_SHD_BOOST_PASS: 1245 regmap_read(regmap, CS35L41_PWR_CTRL3, &pwr_ctrl3); 1246 regmap_read(regmap, CS35L41_GPIO_PAD_CONTROL, &pad_control); 1247 1248 pwr_ctrl3 &= ~CS35L41_SYNC_EN_MASK; 1249 pwr_ctrl1 = enable << CS35L41_GLOBAL_EN_SHIFT; 1250 1251 gpio1_func = enable ? CS35L41_GPIO1_MDSYNC : CS35L41_GPIO1_HIZ; 1252 gpio1_func <<= CS35L41_GPIO1_CTRL_SHIFT; 1253 1254 pad_control &= ~CS35L41_GPIO1_CTRL_MASK; 1255 pad_control |= gpio1_func & CS35L41_GPIO1_CTRL_MASK; 1256 1257 cs35l41_mdsync_down_seq[0].def = pwr_ctrl3; 1258 cs35l41_mdsync_down_seq[1].def = pad_control; 1259 cs35l41_mdsync_down_seq[2].def = pwr_ctrl1; 1260 1261 ret = regmap_multi_reg_write(regmap, cs35l41_mdsync_down_seq, 1262 ARRAY_SIZE(cs35l41_mdsync_down_seq)); 1263 /* Activation to be completed later via cs35l41_mdsync_up() */ 1264 if (ret || enable) 1265 return ret; 1266 1267 ret = regmap_read_poll_timeout(regmap, CS35L41_IRQ1_STATUS1, 1268 int_status, int_status & pup_pdn_mask, 1269 1000, 100000); 1270 if (ret) 1271 dev_err(dev, "Enable(%d) failed: %d\n", enable, ret); 1272 1273 /* Clear PUP/PDN status */ 1274 regmap_write(regmap, CS35L41_IRQ1_STATUS1, pup_pdn_mask); 1275 break; 1276 case CS35L41_INT_BOOST: 1277 ret = regmap_update_bits(regmap, CS35L41_PWR_CTRL1, CS35L41_GLOBAL_EN_MASK, 1278 enable << CS35L41_GLOBAL_EN_SHIFT); 1279 if (ret) { 1280 dev_err(dev, "CS35L41_PWR_CTRL1 set failed: %d\n", ret); 1281 return ret; 1282 } 1283 1284 ret = regmap_read_poll_timeout(regmap, CS35L41_IRQ1_STATUS1, 1285 int_status, int_status & pup_pdn_mask, 1286 1000, 100000); 1287 if (ret) 1288 dev_err(dev, "Enable(%d) failed: %d\n", enable, ret); 1289 1290 /* Clear PUP/PDN status */ 1291 regmap_write(regmap, CS35L41_IRQ1_STATUS1, pup_pdn_mask); 1292 break; 1293 case CS35L41_EXT_BOOST: 1294 case CS35L41_EXT_BOOST_NO_VSPK_SWITCH: 1295 if (enable) { 1296 /* Test Key is unlocked here */ 1297 ret = regmap_multi_reg_write(regmap, cs35l41_safe_to_active_start, 1298 ARRAY_SIZE(cs35l41_safe_to_active_start)); 1299 if (ret) 1300 return ret; 1301 1302 ret = regmap_read_poll_timeout(regmap, CS35L41_IRQ1_STATUS1, int_status, 1303 int_status & CS35L41_PUP_DONE_MASK, 1000, 100000); 1304 if (ret) { 1305 dev_err(dev, "Failed waiting for CS35L41_PUP_DONE_MASK: %d\n", ret); 1306 /* Lock the test key, it was unlocked during the multi_reg_write */ 1307 cs35l41_test_key_lock(dev, regmap); 1308 return ret; 1309 } 1310 regmap_write(regmap, CS35L41_IRQ1_STATUS1, CS35L41_PUP_DONE_MASK); 1311 1312 if (firmware_running) 1313 ret = cs35l41_set_cspl_mbox_cmd(dev, regmap, 1314 CSPL_MBOX_CMD_SPK_OUT_ENABLE); 1315 else 1316 ret = regmap_multi_reg_write(regmap, cs35l41_safe_to_active_en_spk, 1317 ARRAY_SIZE(cs35l41_safe_to_active_en_spk)); 1318 1319 /* Lock the test key, it was unlocked during the multi_reg_write */ 1320 cs35l41_test_key_lock(dev, regmap); 1321 } else { 1322 /* Test Key is unlocked here */ 1323 ret = regmap_multi_reg_write(regmap, cs35l41_active_to_safe_start, 1324 ARRAY_SIZE(cs35l41_active_to_safe_start)); 1325 if (ret) { 1326 /* Lock the test key, it was unlocked during the multi_reg_write */ 1327 cs35l41_test_key_lock(dev, regmap); 1328 return ret; 1329 } 1330 1331 ret = regmap_read_poll_timeout(regmap, CS35L41_IRQ1_STATUS1, int_status, 1332 int_status & CS35L41_PDN_DONE_MASK, 1000, 100000); 1333 if (ret) { 1334 dev_err(dev, "Failed waiting for CS35L41_PDN_DONE_MASK: %d\n", ret); 1335 /* Lock the test key, it was unlocked during the multi_reg_write */ 1336 cs35l41_test_key_lock(dev, regmap); 1337 return ret; 1338 } 1339 regmap_write(regmap, CS35L41_IRQ1_STATUS1, CS35L41_PDN_DONE_MASK); 1340 1341 /* Test Key is locked here */ 1342 ret = regmap_multi_reg_write(regmap, cs35l41_active_to_safe_end, 1343 ARRAY_SIZE(cs35l41_active_to_safe_end)); 1344 } 1345 break; 1346 default: 1347 ret = -EINVAL; 1348 break; 1349 } 1350 1351 return ret; 1352 } 1353 EXPORT_SYMBOL_GPL(cs35l41_global_enable); 1354 1355 /* 1356 * To be called after receiving the IRQ Lock interrupt, in order to complete 1357 * any shared boost activation initiated by cs35l41_global_enable(). 1358 */ 1359 int cs35l41_mdsync_up(struct regmap *regmap) 1360 { 1361 return regmap_update_bits(regmap, CS35L41_PWR_CTRL3, 1362 CS35L41_SYNC_EN_MASK, CS35L41_SYNC_EN_MASK); 1363 } 1364 EXPORT_SYMBOL_GPL(cs35l41_mdsync_up); 1365 1366 int cs35l41_gpio_config(struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg) 1367 { 1368 struct cs35l41_gpio_cfg *gpio1 = &hw_cfg->gpio1; 1369 struct cs35l41_gpio_cfg *gpio2 = &hw_cfg->gpio2; 1370 int irq_pol = IRQF_TRIGGER_NONE; 1371 1372 regmap_update_bits(regmap, CS35L41_GPIO1_CTRL1, 1373 CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK, 1374 gpio1->pol_inv << CS35L41_GPIO_POL_SHIFT | 1375 !gpio1->out_en << CS35L41_GPIO_DIR_SHIFT); 1376 1377 regmap_update_bits(regmap, CS35L41_GPIO2_CTRL1, 1378 CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK, 1379 gpio2->pol_inv << CS35L41_GPIO_POL_SHIFT | 1380 !gpio2->out_en << CS35L41_GPIO_DIR_SHIFT); 1381 1382 if (gpio1->valid) 1383 regmap_update_bits(regmap, CS35L41_GPIO_PAD_CONTROL, CS35L41_GPIO1_CTRL_MASK, 1384 gpio1->func << CS35L41_GPIO1_CTRL_SHIFT); 1385 1386 if (gpio2->valid) { 1387 regmap_update_bits(regmap, CS35L41_GPIO_PAD_CONTROL, CS35L41_GPIO2_CTRL_MASK, 1388 gpio2->func << CS35L41_GPIO2_CTRL_SHIFT); 1389 1390 switch (gpio2->func) { 1391 case CS35L41_GPIO2_INT_PUSH_PULL_LOW: 1392 case CS35L41_GPIO2_INT_OPEN_DRAIN: 1393 irq_pol = IRQF_TRIGGER_LOW; 1394 break; 1395 case CS35L41_GPIO2_INT_PUSH_PULL_HIGH: 1396 irq_pol = IRQF_TRIGGER_HIGH; 1397 break; 1398 default: 1399 break; 1400 } 1401 } 1402 1403 return irq_pol; 1404 } 1405 EXPORT_SYMBOL_GPL(cs35l41_gpio_config); 1406 1407 static const struct cs_dsp_region cs35l41_dsp1_regions[] = { 1408 { .type = WMFW_HALO_PM_PACKED, .base = CS35L41_DSP1_PMEM_0 }, 1409 { .type = WMFW_HALO_XM_PACKED, .base = CS35L41_DSP1_XMEM_PACK_0 }, 1410 { .type = WMFW_HALO_YM_PACKED, .base = CS35L41_DSP1_YMEM_PACK_0 }, 1411 {. type = WMFW_ADSP2_XM, .base = CS35L41_DSP1_XMEM_UNPACK24_0}, 1412 {. type = WMFW_ADSP2_YM, .base = CS35L41_DSP1_YMEM_UNPACK24_0}, 1413 }; 1414 1415 void cs35l41_configure_cs_dsp(struct device *dev, struct regmap *reg, struct cs_dsp *dsp) 1416 { 1417 dsp->num = 1; 1418 dsp->type = WMFW_HALO; 1419 dsp->rev = 0; 1420 dsp->dev = dev; 1421 dsp->regmap = reg; 1422 dsp->base = CS35L41_DSP1_CTRL_BASE; 1423 dsp->base_sysinfo = CS35L41_DSP1_SYS_ID; 1424 dsp->mem = cs35l41_dsp1_regions; 1425 dsp->num_mems = ARRAY_SIZE(cs35l41_dsp1_regions); 1426 dsp->lock_regions = 0xFFFFFFFF; 1427 } 1428 EXPORT_SYMBOL_GPL(cs35l41_configure_cs_dsp); 1429 1430 static bool cs35l41_check_cspl_mbox_sts(enum cs35l41_cspl_mbox_cmd cmd, 1431 enum cs35l41_cspl_mbox_status sts) 1432 { 1433 switch (cmd) { 1434 case CSPL_MBOX_CMD_NONE: 1435 case CSPL_MBOX_CMD_UNKNOWN_CMD: 1436 return true; 1437 case CSPL_MBOX_CMD_PAUSE: 1438 case CSPL_MBOX_CMD_OUT_OF_HIBERNATE: 1439 return (sts == CSPL_MBOX_STS_PAUSED); 1440 case CSPL_MBOX_CMD_RESUME: 1441 return (sts == CSPL_MBOX_STS_RUNNING); 1442 case CSPL_MBOX_CMD_REINIT: 1443 return (sts == CSPL_MBOX_STS_RUNNING); 1444 case CSPL_MBOX_CMD_STOP_PRE_REINIT: 1445 return (sts == CSPL_MBOX_STS_RDY_FOR_REINIT); 1446 case CSPL_MBOX_CMD_SPK_OUT_ENABLE: 1447 return (sts == CSPL_MBOX_STS_RUNNING); 1448 default: 1449 return false; 1450 } 1451 } 1452 1453 int cs35l41_set_cspl_mbox_cmd(struct device *dev, struct regmap *regmap, 1454 enum cs35l41_cspl_mbox_cmd cmd) 1455 { 1456 unsigned int sts = 0, i; 1457 int ret; 1458 1459 // Set mailbox cmd 1460 ret = regmap_write(regmap, CS35L41_DSP_VIRT1_MBOX_1, cmd); 1461 if (ret < 0) { 1462 if (cmd != CSPL_MBOX_CMD_OUT_OF_HIBERNATE) 1463 dev_err(dev, "Failed to write MBOX: %d\n", ret); 1464 return ret; 1465 } 1466 1467 // Read mailbox status and verify it is appropriate for the given cmd 1468 for (i = 0; i < 5; i++) { 1469 usleep_range(1000, 1100); 1470 1471 ret = regmap_read(regmap, CS35L41_DSP_MBOX_2, &sts); 1472 if (ret < 0) { 1473 dev_err(dev, "Failed to read MBOX STS: %d\n", ret); 1474 continue; 1475 } 1476 1477 if (sts == CSPL_MBOX_STS_ERROR || sts == CSPL_MBOX_STS_ERROR2) { 1478 dev_err(dev, "CSPL Error Detected\n"); 1479 return -EINVAL; 1480 } 1481 1482 if (!cs35l41_check_cspl_mbox_sts(cmd, sts)) 1483 dev_dbg(dev, "[%u] cmd %u returned invalid sts %u", i, cmd, sts); 1484 else 1485 return 0; 1486 } 1487 1488 if (cmd != CSPL_MBOX_CMD_OUT_OF_HIBERNATE) 1489 dev_err(dev, "Failed to set mailbox cmd %u (status %u)\n", cmd, sts); 1490 1491 return -ENOMSG; 1492 } 1493 EXPORT_SYMBOL_GPL(cs35l41_set_cspl_mbox_cmd); 1494 1495 int cs35l41_write_fs_errata(struct device *dev, struct regmap *regmap) 1496 { 1497 int ret; 1498 1499 ret = regmap_multi_reg_write(regmap, cs35l41_fs_errata_patch, 1500 ARRAY_SIZE(cs35l41_fs_errata_patch)); 1501 if (ret < 0) 1502 dev_err(dev, "Failed to write fs errata: %d\n", ret); 1503 1504 return ret; 1505 } 1506 EXPORT_SYMBOL_GPL(cs35l41_write_fs_errata); 1507 1508 int cs35l41_enter_hibernate(struct device *dev, struct regmap *regmap, 1509 enum cs35l41_boost_type b_type) 1510 { 1511 if (!cs35l41_safe_reset(regmap, b_type)) { 1512 dev_dbg(dev, "System does not support Suspend\n"); 1513 return -EINVAL; 1514 } 1515 1516 dev_dbg(dev, "Enter hibernate\n"); 1517 regmap_write(regmap, CS35L41_WAKESRC_CTL, 0x0088); 1518 regmap_write(regmap, CS35L41_WAKESRC_CTL, 0x0188); 1519 1520 // Don't wait for ACK since bus activity would wake the device 1521 regmap_write(regmap, CS35L41_DSP_VIRT1_MBOX_1, CSPL_MBOX_CMD_HIBERNATE); 1522 1523 return 0; 1524 } 1525 EXPORT_SYMBOL_GPL(cs35l41_enter_hibernate); 1526 1527 static void cs35l41_wait_for_pwrmgt_sts(struct device *dev, struct regmap *regmap) 1528 { 1529 const int pwrmgt_retries = 10; 1530 unsigned int sts; 1531 int i, ret; 1532 1533 for (i = 0; i < pwrmgt_retries; i++) { 1534 ret = regmap_read(regmap, CS35L41_PWRMGT_STS, &sts); 1535 if (ret) 1536 dev_err(dev, "Failed to read PWRMGT_STS: %d\n", ret); 1537 else if (!(sts & CS35L41_WR_PEND_STS_MASK)) 1538 return; 1539 1540 udelay(20); 1541 } 1542 1543 dev_err(dev, "Timed out reading PWRMGT_STS\n"); 1544 } 1545 1546 int cs35l41_exit_hibernate(struct device *dev, struct regmap *regmap) 1547 { 1548 const int wake_retries = 20; 1549 const int sleep_retries = 5; 1550 int ret, i, j; 1551 1552 for (i = 0; i < sleep_retries; i++) { 1553 dev_dbg(dev, "Exit hibernate\n"); 1554 1555 for (j = 0; j < wake_retries; j++) { 1556 ret = cs35l41_set_cspl_mbox_cmd(dev, regmap, 1557 CSPL_MBOX_CMD_OUT_OF_HIBERNATE); 1558 if (!ret) 1559 break; 1560 1561 usleep_range(100, 200); 1562 } 1563 1564 if (j < wake_retries) { 1565 dev_dbg(dev, "Wake success at cycle: %d\n", j); 1566 return 0; 1567 } 1568 1569 dev_err(dev, "Wake failed, re-enter hibernate: %d\n", ret); 1570 1571 cs35l41_wait_for_pwrmgt_sts(dev, regmap); 1572 regmap_write(regmap, CS35L41_WAKESRC_CTL, 0x0088); 1573 1574 cs35l41_wait_for_pwrmgt_sts(dev, regmap); 1575 regmap_write(regmap, CS35L41_WAKESRC_CTL, 0x0188); 1576 1577 cs35l41_wait_for_pwrmgt_sts(dev, regmap); 1578 regmap_write(regmap, CS35L41_PWRMGT_CTL, 0x3); 1579 } 1580 1581 dev_err(dev, "Timed out waking device\n"); 1582 1583 return -ETIMEDOUT; 1584 } 1585 EXPORT_SYMBOL_GPL(cs35l41_exit_hibernate); 1586 1587 MODULE_DESCRIPTION("CS35L41 library"); 1588 MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>"); 1589 MODULE_AUTHOR("Lucas Tanure, Cirrus Logic Inc, <tanureal@opensource.cirrus.com>"); 1590 MODULE_LICENSE("GPL"); 1591