1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v12_0.h" 34 #include "soc24.h" 35 #include "nvd.h" 36 37 #include "gc/gc_12_0_0_offset.h" 38 #include "gc/gc_12_0_0_sh_mask.h" 39 #include "soc24_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "clearstate_gfx12.h" 45 #include "v12_structs.h" 46 #include "gfx_v12_0.h" 47 #include "nbif_v6_3_1.h" 48 #include "mes_v12_0.h" 49 50 #define GFX12_NUM_GFX_RINGS 1 51 #define GFX12_MEC_HPD_SIZE 2048 52 53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 54 55 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 56 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 57 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin"); 59 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin"); 60 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin"); 61 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin"); 62 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); 63 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin"); 64 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin"); 65 66 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = { 67 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 78 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 79 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 80 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 81 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 82 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 83 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 84 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 85 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 86 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 87 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 88 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 89 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 90 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 91 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 97 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 98 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 99 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 100 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 101 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 102 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 103 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 104 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 105 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 106 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 107 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 108 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), 109 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 113 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 114 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 115 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 116 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 117 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), 118 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), 119 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), 120 121 /* cp header registers */ 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 126 /* SE status registers */ 127 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 128 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 129 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 130 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 131 }; 132 133 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = { 134 /* compute registers */ 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS) 174 }; 175 176 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 177 /* gfx queue registers */ 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 193 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 195 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 196 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ) 203 }; 204 205 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = { 206 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f), 207 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000), 208 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020) 209 }; 210 211 static const struct soc15_reg_golden golden_settings_gc_12_0[] = { 212 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000), 213 }; 214 215 #define DEFAULT_SH_MEM_CONFIG \ 216 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 217 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 218 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 219 220 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev); 221 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev); 222 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev); 223 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev); 224 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev); 225 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev); 226 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 227 struct amdgpu_cu_info *cu_info); 228 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev); 229 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 230 u32 sh_num, u32 instance, int xcc_id); 231 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 232 233 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 234 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 235 uint32_t val); 236 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 237 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 238 uint16_t pasid, uint32_t flush_type, 239 bool all_hub, uint8_t dst_sel); 240 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 241 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 242 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 243 bool enable); 244 245 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 246 uint64_t queue_mask) 247 { 248 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 249 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 250 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 251 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 252 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 253 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 254 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 255 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 256 amdgpu_ring_write(kiq_ring, 0); 257 } 258 259 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 260 struct amdgpu_ring *ring) 261 { 262 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 263 uint64_t wptr_addr = ring->wptr_gpu_addr; 264 uint32_t me = 0, eng_sel = 0; 265 266 switch (ring->funcs->type) { 267 case AMDGPU_RING_TYPE_COMPUTE: 268 me = 1; 269 eng_sel = 0; 270 break; 271 case AMDGPU_RING_TYPE_GFX: 272 me = 0; 273 eng_sel = 4; 274 break; 275 case AMDGPU_RING_TYPE_MES: 276 me = 2; 277 eng_sel = 5; 278 break; 279 default: 280 WARN_ON(1); 281 } 282 283 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 284 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 285 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 286 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 287 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 288 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 289 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 290 PACKET3_MAP_QUEUES_ME((me)) | 291 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 292 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 293 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 294 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 295 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 296 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 297 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 298 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 299 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 300 } 301 302 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 303 struct amdgpu_ring *ring, 304 enum amdgpu_unmap_queues_action action, 305 u64 gpu_addr, u64 seq) 306 { 307 struct amdgpu_device *adev = kiq_ring->adev; 308 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 309 310 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 311 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 312 return; 313 } 314 315 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 316 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 317 PACKET3_UNMAP_QUEUES_ACTION(action) | 318 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 319 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 320 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 321 amdgpu_ring_write(kiq_ring, 322 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 323 324 if (action == PREEMPT_QUEUES_NO_UNMAP) { 325 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 326 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 327 amdgpu_ring_write(kiq_ring, seq); 328 } else { 329 amdgpu_ring_write(kiq_ring, 0); 330 amdgpu_ring_write(kiq_ring, 0); 331 amdgpu_ring_write(kiq_ring, 0); 332 } 333 } 334 335 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 336 struct amdgpu_ring *ring, 337 u64 addr, u64 seq) 338 { 339 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 340 341 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 342 amdgpu_ring_write(kiq_ring, 343 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 344 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 345 PACKET3_QUERY_STATUS_COMMAND(2)); 346 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 347 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 348 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 349 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 350 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 351 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 352 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 353 } 354 355 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 356 uint16_t pasid, 357 uint32_t flush_type, 358 bool all_hub) 359 { 360 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 361 } 362 363 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = { 364 .kiq_set_resources = gfx_v12_0_kiq_set_resources, 365 .kiq_map_queues = gfx_v12_0_kiq_map_queues, 366 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues, 367 .kiq_query_status = gfx_v12_0_kiq_query_status, 368 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs, 369 .set_resources_size = 8, 370 .map_queues_size = 7, 371 .unmap_queues_size = 6, 372 .query_status_size = 7, 373 .invalidate_tlbs_size = 2, 374 }; 375 376 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 377 { 378 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; 379 } 380 381 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 382 int mem_space, int opt, uint32_t addr0, 383 uint32_t addr1, uint32_t ref, 384 uint32_t mask, uint32_t inv) 385 { 386 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 387 amdgpu_ring_write(ring, 388 /* memory (1) or register (0) */ 389 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 390 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 391 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 392 WAIT_REG_MEM_ENGINE(eng_sel))); 393 394 if (mem_space) 395 BUG_ON(addr0 & 0x3); /* Dword align */ 396 amdgpu_ring_write(ring, addr0); 397 amdgpu_ring_write(ring, addr1); 398 amdgpu_ring_write(ring, ref); 399 amdgpu_ring_write(ring, mask); 400 amdgpu_ring_write(ring, inv); /* poll interval */ 401 } 402 403 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring) 404 { 405 struct amdgpu_device *adev = ring->adev; 406 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 407 uint32_t tmp = 0; 408 unsigned i; 409 int r; 410 411 WREG32(scratch, 0xCAFEDEAD); 412 r = amdgpu_ring_alloc(ring, 5); 413 if (r) { 414 dev_err(adev->dev, 415 "amdgpu: cp failed to lock ring %d (%d).\n", 416 ring->idx, r); 417 return r; 418 } 419 420 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 421 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 422 } else { 423 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 424 amdgpu_ring_write(ring, scratch - 425 PACKET3_SET_UCONFIG_REG_START); 426 amdgpu_ring_write(ring, 0xDEADBEEF); 427 } 428 amdgpu_ring_commit(ring); 429 430 for (i = 0; i < adev->usec_timeout; i++) { 431 tmp = RREG32(scratch); 432 if (tmp == 0xDEADBEEF) 433 break; 434 if (amdgpu_emu_mode == 1) 435 msleep(1); 436 else 437 udelay(1); 438 } 439 440 if (i >= adev->usec_timeout) 441 r = -ETIMEDOUT; 442 return r; 443 } 444 445 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 446 { 447 struct amdgpu_device *adev = ring->adev; 448 struct amdgpu_ib ib; 449 struct dma_fence *f = NULL; 450 unsigned index; 451 uint64_t gpu_addr; 452 volatile uint32_t *cpu_ptr; 453 long r; 454 455 /* MES KIQ fw hasn't indirect buffer support for now */ 456 if (adev->enable_mes_kiq && 457 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 458 return 0; 459 460 memset(&ib, 0, sizeof(ib)); 461 462 if (ring->is_mes_queue) { 463 uint32_t padding, offset; 464 465 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 466 padding = amdgpu_mes_ctx_get_offs(ring, 467 AMDGPU_MES_CTX_PADDING_OFFS); 468 469 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 470 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 471 472 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 473 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 474 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 475 } else { 476 r = amdgpu_device_wb_get(adev, &index); 477 if (r) 478 return r; 479 480 gpu_addr = adev->wb.gpu_addr + (index * 4); 481 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 482 cpu_ptr = &adev->wb.wb[index]; 483 484 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 485 if (r) { 486 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); 487 goto err1; 488 } 489 } 490 491 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 492 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 493 ib.ptr[2] = lower_32_bits(gpu_addr); 494 ib.ptr[3] = upper_32_bits(gpu_addr); 495 ib.ptr[4] = 0xDEADBEEF; 496 ib.length_dw = 5; 497 498 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 499 if (r) 500 goto err2; 501 502 r = dma_fence_wait_timeout(f, false, timeout); 503 if (r == 0) { 504 r = -ETIMEDOUT; 505 goto err2; 506 } else if (r < 0) { 507 goto err2; 508 } 509 510 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 511 r = 0; 512 else 513 r = -EINVAL; 514 err2: 515 if (!ring->is_mes_queue) 516 amdgpu_ib_free(&ib, NULL); 517 dma_fence_put(f); 518 err1: 519 if (!ring->is_mes_queue) 520 amdgpu_device_wb_free(adev, index); 521 return r; 522 } 523 524 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev) 525 { 526 amdgpu_ucode_release(&adev->gfx.pfp_fw); 527 amdgpu_ucode_release(&adev->gfx.me_fw); 528 amdgpu_ucode_release(&adev->gfx.rlc_fw); 529 amdgpu_ucode_release(&adev->gfx.mec_fw); 530 531 kfree(adev->gfx.rlc.register_list_format); 532 } 533 534 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 535 { 536 const struct psp_firmware_header_v1_0 *toc_hdr; 537 int err = 0; 538 539 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 540 AMDGPU_UCODE_REQUIRED, 541 "amdgpu/%s_toc.bin", ucode_prefix); 542 if (err) 543 goto out; 544 545 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 546 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 547 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 548 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 549 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 550 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 551 return 0; 552 out: 553 amdgpu_ucode_release(&adev->psp.toc_fw); 554 return err; 555 } 556 557 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) 558 { 559 char ucode_prefix[15]; 560 int err; 561 const struct rlc_firmware_header_v2_0 *rlc_hdr; 562 uint16_t version_major; 563 uint16_t version_minor; 564 565 DRM_DEBUG("\n"); 566 567 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 568 569 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 570 AMDGPU_UCODE_REQUIRED, 571 "amdgpu/%s_pfp.bin", ucode_prefix); 572 if (err) 573 goto out; 574 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 575 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 576 577 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 578 AMDGPU_UCODE_REQUIRED, 579 "amdgpu/%s_me.bin", ucode_prefix); 580 if (err) 581 goto out; 582 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 583 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 584 585 if (!amdgpu_sriov_vf(adev)) { 586 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 587 AMDGPU_UCODE_REQUIRED, 588 "amdgpu/%s_rlc.bin", ucode_prefix); 589 if (err) 590 goto out; 591 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 592 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 593 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 594 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 595 if (err) 596 goto out; 597 } 598 599 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 600 AMDGPU_UCODE_REQUIRED, 601 "amdgpu/%s_mec.bin", ucode_prefix); 602 if (err) 603 goto out; 604 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 605 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 606 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 607 608 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 609 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix); 610 611 /* only one MEC for gfx 12 */ 612 adev->gfx.mec2_fw = NULL; 613 614 if (adev->gfx.imu.funcs) { 615 if (adev->gfx.imu.funcs->init_microcode) { 616 err = adev->gfx.imu.funcs->init_microcode(adev); 617 if (err) 618 dev_err(adev->dev, "Failed to load imu firmware!\n"); 619 } 620 } 621 622 out: 623 if (err) { 624 amdgpu_ucode_release(&adev->gfx.pfp_fw); 625 amdgpu_ucode_release(&adev->gfx.me_fw); 626 amdgpu_ucode_release(&adev->gfx.rlc_fw); 627 amdgpu_ucode_release(&adev->gfx.mec_fw); 628 } 629 630 return err; 631 } 632 633 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev) 634 { 635 u32 count = 0; 636 const struct cs_section_def *sect = NULL; 637 const struct cs_extent_def *ext = NULL; 638 639 count += 1; 640 641 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 642 if (sect->id == SECT_CONTEXT) { 643 for (ext = sect->section; ext->extent != NULL; ++ext) 644 count += 2 + ext->reg_count; 645 } else 646 return 0; 647 } 648 649 return count; 650 } 651 652 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, 653 volatile u32 *buffer) 654 { 655 u32 count = 0, clustercount = 0, i; 656 const struct cs_section_def *sect = NULL; 657 const struct cs_extent_def *ext = NULL; 658 659 if (adev->gfx.rlc.cs_data == NULL) 660 return; 661 if (buffer == NULL) 662 return; 663 664 count += 1; 665 666 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 667 if (sect->id == SECT_CONTEXT) { 668 for (ext = sect->section; ext->extent != NULL; ++ext) { 669 clustercount++; 670 buffer[count++] = ext->reg_count; 671 buffer[count++] = ext->reg_index; 672 673 for (i = 0; i < ext->reg_count; i++) 674 buffer[count++] = cpu_to_le32(ext->extent[i]); 675 } 676 } else 677 return; 678 } 679 680 buffer[0] = clustercount; 681 } 682 683 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev) 684 { 685 /* clear state block */ 686 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 687 &adev->gfx.rlc.clear_state_gpu_addr, 688 (void **)&adev->gfx.rlc.cs_ptr); 689 690 /* jump table block */ 691 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 692 &adev->gfx.rlc.cp_table_gpu_addr, 693 (void **)&adev->gfx.rlc.cp_table_ptr); 694 } 695 696 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 697 { 698 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 699 700 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 701 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 702 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 703 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 704 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 705 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 706 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 707 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 708 adev->gfx.rlc.rlcg_reg_access_supported = true; 709 } 710 711 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) 712 { 713 const struct cs_section_def *cs_data; 714 int r; 715 716 adev->gfx.rlc.cs_data = gfx12_cs_data; 717 718 cs_data = adev->gfx.rlc.cs_data; 719 720 if (cs_data) { 721 /* init clear state block */ 722 r = amdgpu_gfx_rlc_init_csb(adev); 723 if (r) 724 return r; 725 } 726 727 /* init spm vmid with 0xf */ 728 if (adev->gfx.rlc.funcs->update_spm_vmid) 729 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 730 731 return 0; 732 } 733 734 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev) 735 { 736 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 737 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 738 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 739 } 740 741 static void gfx_v12_0_me_init(struct amdgpu_device *adev) 742 { 743 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 744 745 amdgpu_gfx_graphics_queue_acquire(adev); 746 } 747 748 static int gfx_v12_0_mec_init(struct amdgpu_device *adev) 749 { 750 int r; 751 u32 *hpd; 752 size_t mec_hpd_size; 753 754 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 755 756 /* take ownership of the relevant compute queues */ 757 amdgpu_gfx_compute_queue_acquire(adev); 758 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE; 759 760 if (mec_hpd_size) { 761 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 762 AMDGPU_GEM_DOMAIN_GTT, 763 &adev->gfx.mec.hpd_eop_obj, 764 &adev->gfx.mec.hpd_eop_gpu_addr, 765 (void **)&hpd); 766 if (r) { 767 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 768 gfx_v12_0_mec_fini(adev); 769 return r; 770 } 771 772 memset(hpd, 0, mec_hpd_size); 773 774 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 775 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 776 } 777 778 return 0; 779 } 780 781 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 782 { 783 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 784 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 785 (address << SQ_IND_INDEX__INDEX__SHIFT)); 786 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 787 } 788 789 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 790 uint32_t thread, uint32_t regno, 791 uint32_t num, uint32_t *out) 792 { 793 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 794 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 795 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 796 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 797 (SQ_IND_INDEX__AUTO_INCR_MASK)); 798 while (num--) 799 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 800 } 801 802 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, 803 uint32_t xcc_id, 804 uint32_t simd, uint32_t wave, 805 uint32_t *dst, int *no_fields) 806 { 807 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 808 * field when performing a select_se_sh so it should be 809 * zero here */ 810 WARN_ON(simd != 0); 811 812 /* type 4 wave data */ 813 dst[(*no_fields)++] = 4; 814 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 815 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 816 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 817 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 818 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 819 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 820 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 821 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 822 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 823 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 824 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 825 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 826 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 827 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 828 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); 829 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 830 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); 831 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); 832 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); 833 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); 834 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 835 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 836 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); 837 } 838 839 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, 840 uint32_t xcc_id, uint32_t simd, 841 uint32_t wave, uint32_t start, 842 uint32_t size, uint32_t *dst) 843 { 844 WARN_ON(simd != 0); 845 846 wave_read_regs( 847 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 848 dst); 849 } 850 851 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev, 852 uint32_t xcc_id, uint32_t simd, 853 uint32_t wave, uint32_t thread, 854 uint32_t start, uint32_t size, 855 uint32_t *dst) 856 { 857 wave_read_regs( 858 adev, wave, thread, 859 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 860 } 861 862 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev, 863 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 864 { 865 soc24_grbm_select(adev, me, pipe, q, vm); 866 } 867 868 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { 869 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter, 870 .select_se_sh = &gfx_v12_0_select_se_sh, 871 .read_wave_data = &gfx_v12_0_read_wave_data, 872 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs, 873 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs, 874 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, 875 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, 876 }; 877 878 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) 879 { 880 881 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 882 case IP_VERSION(12, 0, 0): 883 case IP_VERSION(12, 0, 1): 884 adev->gfx.config.max_hw_contexts = 8; 885 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 886 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 887 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 888 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 889 break; 890 default: 891 BUG(); 892 break; 893 } 894 895 return 0; 896 } 897 898 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 899 int me, int pipe, int queue) 900 { 901 int r; 902 struct amdgpu_ring *ring; 903 unsigned int irq_type; 904 905 ring = &adev->gfx.gfx_ring[ring_id]; 906 907 ring->me = me; 908 ring->pipe = pipe; 909 ring->queue = queue; 910 911 ring->ring_obj = NULL; 912 ring->use_doorbell = true; 913 914 if (!ring_id) 915 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 916 else 917 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 918 ring->vm_hub = AMDGPU_GFXHUB(0); 919 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 920 921 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 922 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 923 AMDGPU_RING_PRIO_DEFAULT, NULL); 924 if (r) 925 return r; 926 return 0; 927 } 928 929 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 930 int mec, int pipe, int queue) 931 { 932 int r; 933 unsigned irq_type; 934 struct amdgpu_ring *ring; 935 unsigned int hw_prio; 936 937 ring = &adev->gfx.compute_ring[ring_id]; 938 939 /* mec0 is me1 */ 940 ring->me = mec + 1; 941 ring->pipe = pipe; 942 ring->queue = queue; 943 944 ring->ring_obj = NULL; 945 ring->use_doorbell = true; 946 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 947 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 948 + (ring_id * GFX12_MEC_HPD_SIZE); 949 ring->vm_hub = AMDGPU_GFXHUB(0); 950 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 951 952 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 953 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 954 + ring->pipe; 955 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 956 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 957 /* type-2 packets are deprecated on MEC, use type-3 instead */ 958 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 959 hw_prio, NULL); 960 if (r) 961 return r; 962 963 return 0; 964 } 965 966 static struct { 967 SOC24_FIRMWARE_ID id; 968 unsigned int offset; 969 unsigned int size; 970 unsigned int size_x16; 971 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 972 973 #define RLC_TOC_OFFSET_DWUNIT 8 974 #define RLC_SIZE_MULTIPLE 1024 975 #define RLC_TOC_UMF_SIZE_inM 23ULL 976 #define RLC_TOC_FORMAT_API 165ULL 977 978 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 979 { 980 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 981 982 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 983 rlc_autoload_info[ucode->id].id = ucode->id; 984 rlc_autoload_info[ucode->id].offset = 985 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 986 rlc_autoload_info[ucode->id].size = 987 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 988 ucode->size * 4; 989 ucode++; 990 } 991 } 992 993 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev) 994 { 995 uint32_t total_size = 0; 996 SOC24_FIRMWARE_ID id; 997 998 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 999 1000 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 1001 total_size += rlc_autoload_info[id].size; 1002 1003 /* In case the offset in rlc toc ucode is aligned */ 1004 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 1005 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 1006 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 1007 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 1008 total_size = RLC_TOC_UMF_SIZE_inM << 20; 1009 1010 return total_size; 1011 } 1012 1013 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1014 { 1015 int r; 1016 uint32_t total_size; 1017 1018 total_size = gfx_v12_0_calc_toc_total_size(adev); 1019 1020 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1021 AMDGPU_GEM_DOMAIN_VRAM, 1022 &adev->gfx.rlc.rlc_autoload_bo, 1023 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1024 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1025 1026 if (r) { 1027 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1028 return r; 1029 } 1030 1031 return 0; 1032 } 1033 1034 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1035 SOC24_FIRMWARE_ID id, 1036 const void *fw_data, 1037 uint32_t fw_size) 1038 { 1039 uint32_t toc_offset; 1040 uint32_t toc_fw_size; 1041 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1042 1043 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 1044 return; 1045 1046 toc_offset = rlc_autoload_info[id].offset; 1047 toc_fw_size = rlc_autoload_info[id].size; 1048 1049 if (fw_size == 0) 1050 fw_size = toc_fw_size; 1051 1052 if (fw_size > toc_fw_size) 1053 fw_size = toc_fw_size; 1054 1055 memcpy(ptr + toc_offset, fw_data, fw_size); 1056 1057 if (fw_size < toc_fw_size) 1058 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1059 } 1060 1061 static void 1062 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1063 { 1064 void *data; 1065 uint32_t size; 1066 uint32_t *toc_ptr; 1067 1068 data = adev->psp.toc.start_addr; 1069 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 1070 1071 toc_ptr = (uint32_t *)data + size / 4 - 2; 1072 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 1073 1074 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 1075 data, size); 1076 } 1077 1078 static void 1079 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1080 { 1081 const __le32 *fw_data; 1082 uint32_t fw_size; 1083 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1084 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1085 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 1086 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1087 uint16_t version_major, version_minor; 1088 1089 /* pfp ucode */ 1090 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1091 adev->gfx.pfp_fw->data; 1092 /* instruction */ 1093 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1094 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1095 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1096 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP, 1097 fw_data, fw_size); 1098 /* data */ 1099 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1100 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1101 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1102 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK, 1103 fw_data, fw_size); 1104 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK, 1105 fw_data, fw_size); 1106 /* me ucode */ 1107 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1108 adev->gfx.me_fw->data; 1109 /* instruction */ 1110 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1111 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1112 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1113 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME, 1114 fw_data, fw_size); 1115 /* data */ 1116 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1117 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1118 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1119 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK, 1120 fw_data, fw_size); 1121 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK, 1122 fw_data, fw_size); 1123 /* mec ucode */ 1124 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1125 adev->gfx.mec_fw->data; 1126 /* instruction */ 1127 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1128 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1129 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1130 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 1131 fw_data, fw_size); 1132 /* data */ 1133 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1134 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1135 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1136 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 1137 fw_data, fw_size); 1138 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1139 fw_data, fw_size); 1140 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1141 fw_data, fw_size); 1142 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1143 fw_data, fw_size); 1144 1145 /* rlc ucode */ 1146 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1147 adev->gfx.rlc_fw->data; 1148 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1149 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1150 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1151 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1152 fw_data, fw_size); 1153 1154 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1155 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1156 if (version_major == 2) { 1157 if (version_minor >= 1) { 1158 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1159 1160 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1161 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1162 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1163 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1164 fw_data, fw_size); 1165 1166 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1167 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1168 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1169 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1170 fw_data, fw_size); 1171 } 1172 if (version_minor >= 2) { 1173 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1174 1175 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1176 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1177 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1178 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1179 fw_data, fw_size); 1180 1181 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1182 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1183 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1184 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1185 fw_data, fw_size); 1186 } 1187 } 1188 } 1189 1190 static void 1191 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1192 { 1193 const __le32 *fw_data; 1194 uint32_t fw_size; 1195 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1196 1197 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1198 adev->sdma.instance[0].fw->data; 1199 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1200 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1201 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1202 1203 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1204 fw_data, fw_size); 1205 } 1206 1207 static void 1208 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1209 { 1210 const __le32 *fw_data; 1211 unsigned fw_size; 1212 const struct mes_firmware_header_v1_0 *mes_hdr; 1213 int pipe, ucode_id, data_id; 1214 1215 for (pipe = 0; pipe < 2; pipe++) { 1216 if (pipe == 0) { 1217 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1218 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1219 } else { 1220 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1221 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1222 } 1223 1224 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1225 adev->mes.fw[pipe]->data; 1226 1227 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1228 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1229 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1230 1231 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1232 1233 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1234 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1235 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1236 1237 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1238 } 1239 } 1240 1241 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1242 { 1243 uint32_t rlc_g_offset, rlc_g_size; 1244 uint64_t gpu_addr; 1245 uint32_t data; 1246 1247 /* RLC autoload sequence 2: copy ucode */ 1248 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1249 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1250 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev); 1251 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 1252 1253 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1254 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1255 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1256 1257 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1258 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1259 1260 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1261 1262 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 1263 /* RLC autoload sequence 3: load IMU fw */ 1264 if (adev->gfx.imu.funcs->load_microcode) 1265 adev->gfx.imu.funcs->load_microcode(adev); 1266 /* RLC autoload sequence 4 init IMU fw */ 1267 if (adev->gfx.imu.funcs->setup_imu) 1268 adev->gfx.imu.funcs->setup_imu(adev); 1269 if (adev->gfx.imu.funcs->start_imu) 1270 adev->gfx.imu.funcs->start_imu(adev); 1271 1272 /* RLC autoload sequence 5 disable gpa mode */ 1273 gfx_v12_0_disable_gpa_mode(adev); 1274 } else { 1275 /* unhalt rlc to start autoload without imu */ 1276 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1277 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1278 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1279 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data); 1280 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1281 } 1282 1283 return 0; 1284 } 1285 1286 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev) 1287 { 1288 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 1289 uint32_t *ptr; 1290 uint32_t inst; 1291 1292 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1293 if (!ptr) { 1294 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1295 adev->gfx.ip_dump_core = NULL; 1296 } else { 1297 adev->gfx.ip_dump_core = ptr; 1298 } 1299 1300 /* Allocate memory for compute queue registers for all the instances */ 1301 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 1302 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1303 adev->gfx.mec.num_queue_per_pipe; 1304 1305 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1306 if (!ptr) { 1307 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1308 adev->gfx.ip_dump_compute_queues = NULL; 1309 } else { 1310 adev->gfx.ip_dump_compute_queues = ptr; 1311 } 1312 1313 /* Allocate memory for gfx queue registers for all the instances */ 1314 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 1315 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1316 adev->gfx.me.num_queue_per_pipe; 1317 1318 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1319 if (!ptr) { 1320 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1321 adev->gfx.ip_dump_gfx_queues = NULL; 1322 } else { 1323 adev->gfx.ip_dump_gfx_queues = ptr; 1324 } 1325 } 1326 1327 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1328 { 1329 int i, j, k, r, ring_id = 0; 1330 unsigned num_compute_rings; 1331 int xcc_id = 0; 1332 struct amdgpu_device *adev = ip_block->adev; 1333 1334 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1335 1336 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1337 case IP_VERSION(12, 0, 0): 1338 case IP_VERSION(12, 0, 1): 1339 adev->gfx.me.num_me = 1; 1340 adev->gfx.me.num_pipe_per_me = 1; 1341 adev->gfx.me.num_queue_per_pipe = 1; 1342 adev->gfx.mec.num_mec = 2; 1343 adev->gfx.mec.num_pipe_per_mec = 2; 1344 adev->gfx.mec.num_queue_per_pipe = 4; 1345 break; 1346 default: 1347 adev->gfx.me.num_me = 1; 1348 adev->gfx.me.num_pipe_per_me = 1; 1349 adev->gfx.me.num_queue_per_pipe = 1; 1350 adev->gfx.mec.num_mec = 1; 1351 adev->gfx.mec.num_pipe_per_mec = 4; 1352 adev->gfx.mec.num_queue_per_pipe = 8; 1353 break; 1354 } 1355 1356 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1357 case IP_VERSION(12, 0, 0): 1358 case IP_VERSION(12, 0, 1): 1359 if (adev->gfx.me_fw_version >= 2480 && 1360 adev->gfx.pfp_fw_version >= 2530 && 1361 adev->gfx.mec_fw_version >= 2680 && 1362 adev->mes.fw_version[0] >= 100) 1363 adev->gfx.enable_cleaner_shader = true; 1364 break; 1365 default: 1366 adev->gfx.enable_cleaner_shader = false; 1367 break; 1368 } 1369 1370 /* recalculate compute rings to use based on hardware configuration */ 1371 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1372 adev->gfx.mec.num_queue_per_pipe) / 2; 1373 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1374 num_compute_rings); 1375 1376 /* EOP Event */ 1377 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1378 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1379 &adev->gfx.eop_irq); 1380 if (r) 1381 return r; 1382 1383 /* Bad opcode Event */ 1384 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1385 GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1386 &adev->gfx.bad_op_irq); 1387 if (r) 1388 return r; 1389 1390 /* Privileged reg */ 1391 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1392 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1393 &adev->gfx.priv_reg_irq); 1394 if (r) 1395 return r; 1396 1397 /* Privileged inst */ 1398 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1399 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1400 &adev->gfx.priv_inst_irq); 1401 if (r) 1402 return r; 1403 1404 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1405 1406 gfx_v12_0_me_init(adev); 1407 1408 r = gfx_v12_0_rlc_init(adev); 1409 if (r) { 1410 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1411 return r; 1412 } 1413 1414 r = gfx_v12_0_mec_init(adev); 1415 if (r) { 1416 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1417 return r; 1418 } 1419 1420 /* set up the gfx ring */ 1421 for (i = 0; i < adev->gfx.me.num_me; i++) { 1422 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1423 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1424 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1425 continue; 1426 1427 r = gfx_v12_0_gfx_ring_init(adev, ring_id, 1428 i, k, j); 1429 if (r) 1430 return r; 1431 ring_id++; 1432 } 1433 } 1434 } 1435 1436 ring_id = 0; 1437 /* set up the compute queues - allocate horizontally across pipes */ 1438 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1439 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1440 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1441 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1442 0, i, k, j)) 1443 continue; 1444 1445 r = gfx_v12_0_compute_ring_init(adev, ring_id, 1446 i, k, j); 1447 if (r) 1448 return r; 1449 1450 ring_id++; 1451 } 1452 } 1453 } 1454 1455 adev->gfx.gfx_supported_reset = 1456 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1457 adev->gfx.compute_supported_reset = 1458 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1459 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1460 case IP_VERSION(12, 0, 0): 1461 case IP_VERSION(12, 0, 1): 1462 if ((adev->gfx.me_fw_version >= 2660) && 1463 (adev->gfx.mec_fw_version >= 2920)) { 1464 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1465 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1466 } 1467 } 1468 1469 if (!adev->enable_mes_kiq) { 1470 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0); 1471 if (r) { 1472 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1473 return r; 1474 } 1475 1476 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1477 if (r) 1478 return r; 1479 } 1480 1481 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0); 1482 if (r) 1483 return r; 1484 1485 /* allocate visible FB for rlc auto-loading fw */ 1486 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1487 r = gfx_v12_0_rlc_autoload_buffer_init(adev); 1488 if (r) 1489 return r; 1490 } 1491 1492 r = gfx_v12_0_gpu_early_init(adev); 1493 if (r) 1494 return r; 1495 1496 gfx_v12_0_alloc_ip_dump(adev); 1497 1498 r = amdgpu_gfx_sysfs_init(adev); 1499 if (r) 1500 return r; 1501 1502 return 0; 1503 } 1504 1505 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev) 1506 { 1507 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1508 &adev->gfx.pfp.pfp_fw_gpu_addr, 1509 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1510 1511 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1512 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1513 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1514 } 1515 1516 static void gfx_v12_0_me_fini(struct amdgpu_device *adev) 1517 { 1518 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1519 &adev->gfx.me.me_fw_gpu_addr, 1520 (void **)&adev->gfx.me.me_fw_ptr); 1521 1522 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1523 &adev->gfx.me.me_fw_data_gpu_addr, 1524 (void **)&adev->gfx.me.me_fw_data_ptr); 1525 } 1526 1527 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1528 { 1529 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1530 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1531 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1532 } 1533 1534 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1535 { 1536 int i; 1537 struct amdgpu_device *adev = ip_block->adev; 1538 1539 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1540 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1541 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1542 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1543 1544 amdgpu_gfx_mqd_sw_fini(adev, 0); 1545 1546 if (!adev->enable_mes_kiq) { 1547 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1548 amdgpu_gfx_kiq_fini(adev, 0); 1549 } 1550 1551 gfx_v12_0_pfp_fini(adev); 1552 gfx_v12_0_me_fini(adev); 1553 gfx_v12_0_rlc_fini(adev); 1554 gfx_v12_0_mec_fini(adev); 1555 1556 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1557 gfx_v12_0_rlc_autoload_buffer_fini(adev); 1558 1559 gfx_v12_0_free_microcode(adev); 1560 1561 amdgpu_gfx_sysfs_fini(adev); 1562 1563 kfree(adev->gfx.ip_dump_core); 1564 kfree(adev->gfx.ip_dump_compute_queues); 1565 kfree(adev->gfx.ip_dump_gfx_queues); 1566 1567 return 0; 1568 } 1569 1570 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1571 u32 sh_num, u32 instance, int xcc_id) 1572 { 1573 u32 data; 1574 1575 if (instance == 0xffffffff) 1576 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1577 INSTANCE_BROADCAST_WRITES, 1); 1578 else 1579 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1580 instance); 1581 1582 if (se_num == 0xffffffff) 1583 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1584 1); 1585 else 1586 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1587 1588 if (sh_num == 0xffffffff) 1589 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1590 1); 1591 else 1592 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1593 1594 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1595 } 1596 1597 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1598 { 1599 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1600 1601 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE); 1602 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1603 GRBM_CC_GC_SA_UNIT_DISABLE, 1604 SA_DISABLE); 1605 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE); 1606 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1607 GRBM_GC_USER_SA_UNIT_DISABLE, 1608 SA_DISABLE); 1609 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1610 adev->gfx.config.max_shader_engines); 1611 1612 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1613 } 1614 1615 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1616 { 1617 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1618 u32 rb_mask; 1619 1620 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1621 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1622 CC_RB_BACKEND_DISABLE, 1623 BACKEND_DISABLE); 1624 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1625 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1626 GC_USER_RB_BACKEND_DISABLE, 1627 BACKEND_DISABLE); 1628 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1629 adev->gfx.config.max_shader_engines); 1630 1631 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1632 } 1633 1634 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev) 1635 { 1636 u32 rb_bitmap_per_sa; 1637 u32 rb_bitmap_width_per_sa; 1638 u32 max_sa; 1639 u32 active_sa_bitmap; 1640 u32 global_active_rb_bitmap; 1641 u32 active_rb_bitmap = 0; 1642 u32 i; 1643 1644 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1645 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev); 1646 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1647 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev); 1648 1649 /* generate active rb bitmap according to active sa bitmap */ 1650 max_sa = adev->gfx.config.max_shader_engines * 1651 adev->gfx.config.max_sh_per_se; 1652 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1653 adev->gfx.config.max_sh_per_se; 1654 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 1655 1656 for (i = 0; i < max_sa; i++) { 1657 if (active_sa_bitmap & (1 << i)) 1658 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 1659 } 1660 1661 active_rb_bitmap &= global_active_rb_bitmap; 1662 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1663 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1664 } 1665 1666 #define LDS_APP_BASE 0x1 1667 #define SCRATCH_APP_BASE 0x2 1668 1669 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev) 1670 { 1671 int i; 1672 uint32_t sh_mem_bases; 1673 uint32_t data; 1674 1675 /* 1676 * Configure apertures: 1677 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1678 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1679 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1680 */ 1681 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1682 SCRATCH_APP_BASE; 1683 1684 mutex_lock(&adev->srbm_mutex); 1685 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1686 soc24_grbm_select(adev, 0, 0, 0, i); 1687 /* CP and shaders */ 1688 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1689 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1690 1691 /* Enable trap for each kfd vmid. */ 1692 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1693 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1694 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1695 } 1696 soc24_grbm_select(adev, 0, 0, 0, 0); 1697 mutex_unlock(&adev->srbm_mutex); 1698 } 1699 1700 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev) 1701 { 1702 /* TODO: harvest feature to be added later. */ 1703 } 1704 1705 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev) 1706 { 1707 } 1708 1709 static void gfx_v12_0_constants_init(struct amdgpu_device *adev) 1710 { 1711 u32 tmp; 1712 int i; 1713 1714 if (!amdgpu_sriov_vf(adev)) 1715 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1716 1717 gfx_v12_0_setup_rb(adev); 1718 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info); 1719 gfx_v12_0_get_tcc_info(adev); 1720 adev->gfx.config.pa_sc_tile_steering_override = 0; 1721 1722 /* XXX SH_MEM regs */ 1723 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1724 mutex_lock(&adev->srbm_mutex); 1725 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1726 soc24_grbm_select(adev, 0, 0, 0, i); 1727 /* CP and shaders */ 1728 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1729 if (i != 0) { 1730 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1731 (adev->gmc.private_aperture_start >> 48)); 1732 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1733 (adev->gmc.shared_aperture_start >> 48)); 1734 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1735 } 1736 } 1737 soc24_grbm_select(adev, 0, 0, 0, 0); 1738 1739 mutex_unlock(&adev->srbm_mutex); 1740 1741 gfx_v12_0_init_compute_vmid(adev); 1742 } 1743 1744 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev, 1745 int me, int pipe) 1746 { 1747 if (me != 0) 1748 return 0; 1749 1750 switch (pipe) { 1751 case 0: 1752 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 1753 default: 1754 return 0; 1755 } 1756 } 1757 1758 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev, 1759 int me, int pipe) 1760 { 1761 /* 1762 * amdgpu controls only the first MEC. That's why this function only 1763 * handles the setting of interrupts for this specific MEC. All other 1764 * pipes' interrupts are set by amdkfd. 1765 */ 1766 if (me != 1) 1767 return 0; 1768 1769 switch (pipe) { 1770 case 0: 1771 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 1772 case 1: 1773 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 1774 default: 1775 return 0; 1776 } 1777 } 1778 1779 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1780 bool enable) 1781 { 1782 u32 tmp, cp_int_cntl_reg; 1783 int i, j; 1784 1785 if (amdgpu_sriov_vf(adev)) 1786 return; 1787 1788 for (i = 0; i < adev->gfx.me.num_me; i++) { 1789 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 1790 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 1791 1792 if (cp_int_cntl_reg) { 1793 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 1794 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1795 enable ? 1 : 0); 1796 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1797 enable ? 1 : 0); 1798 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1799 enable ? 1 : 0); 1800 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1801 enable ? 1 : 0); 1802 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 1803 } 1804 } 1805 } 1806 } 1807 1808 static int gfx_v12_0_init_csb(struct amdgpu_device *adev) 1809 { 1810 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1811 1812 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1813 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1814 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1815 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1816 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1817 1818 return 0; 1819 } 1820 1821 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev) 1822 { 1823 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1824 1825 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1826 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1827 } 1828 1829 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev) 1830 { 1831 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1832 udelay(50); 1833 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1834 udelay(50); 1835 } 1836 1837 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1838 bool enable) 1839 { 1840 uint32_t rlc_pg_cntl; 1841 1842 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1843 1844 if (!enable) { 1845 /* RLC_PG_CNTL[23] = 0 (default) 1846 * RLC will wait for handshake acks with SMU 1847 * GFXOFF will be enabled 1848 * RLC_PG_CNTL[23] = 1 1849 * RLC will not issue any message to SMU 1850 * hence no handshake between SMU & RLC 1851 * GFXOFF will be disabled 1852 */ 1853 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1854 } else 1855 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1856 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1857 } 1858 1859 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev) 1860 { 1861 /* TODO: enable rlc & smu handshake until smu 1862 * and gfxoff feature works as expected */ 1863 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1864 gfx_v12_0_rlc_smu_handshake_cntl(adev, false); 1865 1866 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1867 udelay(50); 1868 } 1869 1870 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev) 1871 { 1872 uint32_t tmp; 1873 1874 /* enable Save Restore Machine */ 1875 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1876 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1877 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1878 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1879 } 1880 1881 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev) 1882 { 1883 const struct rlc_firmware_header_v2_0 *hdr; 1884 const __le32 *fw_data; 1885 unsigned i, fw_size; 1886 1887 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1888 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1889 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1890 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1891 1892 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1893 RLCG_UCODE_LOADING_START_ADDRESS); 1894 1895 for (i = 0; i < fw_size; i++) 1896 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1897 le32_to_cpup(fw_data++)); 1898 1899 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1900 } 1901 1902 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1903 { 1904 const struct rlc_firmware_header_v2_2 *hdr; 1905 const __le32 *fw_data; 1906 unsigned i, fw_size; 1907 u32 tmp; 1908 1909 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1910 1911 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1912 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1913 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1914 1915 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 1916 1917 for (i = 0; i < fw_size; i++) { 1918 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1919 msleep(1); 1920 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 1921 le32_to_cpup(fw_data++)); 1922 } 1923 1924 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1925 1926 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1927 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 1928 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 1929 1930 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 1931 for (i = 0; i < fw_size; i++) { 1932 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1933 msleep(1); 1934 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 1935 le32_to_cpup(fw_data++)); 1936 } 1937 1938 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1939 1940 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 1941 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 1942 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 1943 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 1944 } 1945 1946 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev) 1947 { 1948 const struct rlc_firmware_header_v2_0 *hdr; 1949 uint16_t version_major; 1950 uint16_t version_minor; 1951 1952 if (!adev->gfx.rlc_fw) 1953 return -EINVAL; 1954 1955 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1956 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1957 1958 version_major = le16_to_cpu(hdr->header.header_version_major); 1959 version_minor = le16_to_cpu(hdr->header.header_version_minor); 1960 1961 if (version_major == 2) { 1962 gfx_v12_0_load_rlcg_microcode(adev); 1963 if (amdgpu_dpm == 1) { 1964 if (version_minor >= 2) 1965 gfx_v12_0_load_rlc_iram_dram_microcode(adev); 1966 } 1967 1968 return 0; 1969 } 1970 1971 return -EINVAL; 1972 } 1973 1974 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev) 1975 { 1976 int r; 1977 1978 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1979 gfx_v12_0_init_csb(adev); 1980 1981 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 1982 gfx_v12_0_rlc_enable_srm(adev); 1983 } else { 1984 if (amdgpu_sriov_vf(adev)) { 1985 gfx_v12_0_init_csb(adev); 1986 return 0; 1987 } 1988 1989 adev->gfx.rlc.funcs->stop(adev); 1990 1991 /* disable CG */ 1992 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 1993 1994 /* disable PG */ 1995 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 1996 1997 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1998 /* legacy rlc firmware loading */ 1999 r = gfx_v12_0_rlc_load_microcode(adev); 2000 if (r) 2001 return r; 2002 } 2003 2004 gfx_v12_0_init_csb(adev); 2005 2006 adev->gfx.rlc.funcs->start(adev); 2007 } 2008 2009 return 0; 2010 } 2011 2012 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev) 2013 { 2014 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2015 const struct gfx_firmware_header_v2_0 *me_hdr; 2016 const struct gfx_firmware_header_v2_0 *mec_hdr; 2017 uint32_t pipe_id, tmp; 2018 2019 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2020 adev->gfx.mec_fw->data; 2021 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2022 adev->gfx.me_fw->data; 2023 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2024 adev->gfx.pfp_fw->data; 2025 2026 /* config pfp program start addr */ 2027 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2028 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2029 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2030 (pfp_hdr->ucode_start_addr_hi << 30) | 2031 (pfp_hdr->ucode_start_addr_lo >> 2)); 2032 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2033 pfp_hdr->ucode_start_addr_hi >> 2); 2034 } 2035 soc24_grbm_select(adev, 0, 0, 0, 0); 2036 2037 /* reset pfp pipe */ 2038 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2039 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2040 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2041 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2042 2043 /* clear pfp pipe reset */ 2044 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2045 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2046 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2047 2048 /* config me program start addr */ 2049 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2050 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2051 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2052 (me_hdr->ucode_start_addr_hi << 30) | 2053 (me_hdr->ucode_start_addr_lo >> 2)); 2054 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2055 me_hdr->ucode_start_addr_hi>>2); 2056 } 2057 soc24_grbm_select(adev, 0, 0, 0, 0); 2058 2059 /* reset me pipe */ 2060 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2061 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2062 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2063 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2064 2065 /* clear me pipe reset */ 2066 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2067 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2068 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2069 2070 /* config mec program start addr */ 2071 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2072 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2073 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2074 mec_hdr->ucode_start_addr_lo >> 2 | 2075 mec_hdr->ucode_start_addr_hi << 30); 2076 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2077 mec_hdr->ucode_start_addr_hi >> 2); 2078 } 2079 soc24_grbm_select(adev, 0, 0, 0, 0); 2080 2081 /* reset mec pipe */ 2082 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2083 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2084 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2085 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2086 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2087 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2088 2089 /* clear mec pipe reset */ 2090 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2091 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2092 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2093 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2094 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2095 } 2096 2097 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev) 2098 { 2099 const struct gfx_firmware_header_v2_0 *cp_hdr; 2100 unsigned pipe_id, tmp; 2101 2102 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2103 adev->gfx.pfp_fw->data; 2104 mutex_lock(&adev->srbm_mutex); 2105 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2106 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2107 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2108 (cp_hdr->ucode_start_addr_hi << 30) | 2109 (cp_hdr->ucode_start_addr_lo >> 2)); 2110 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2111 cp_hdr->ucode_start_addr_hi>>2); 2112 2113 /* 2114 * Program CP_ME_CNTL to reset given PIPE to take 2115 * effect of CP_PFP_PRGRM_CNTR_START. 2116 */ 2117 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2118 if (pipe_id == 0) 2119 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2120 PFP_PIPE0_RESET, 1); 2121 else 2122 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2123 PFP_PIPE1_RESET, 1); 2124 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2125 2126 /* Clear pfp pipe0 reset bit. */ 2127 if (pipe_id == 0) 2128 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2129 PFP_PIPE0_RESET, 0); 2130 else 2131 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2132 PFP_PIPE1_RESET, 0); 2133 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2134 } 2135 soc24_grbm_select(adev, 0, 0, 0, 0); 2136 mutex_unlock(&adev->srbm_mutex); 2137 } 2138 2139 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev) 2140 { 2141 const struct gfx_firmware_header_v2_0 *cp_hdr; 2142 unsigned pipe_id, tmp; 2143 2144 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2145 adev->gfx.me_fw->data; 2146 mutex_lock(&adev->srbm_mutex); 2147 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2148 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2149 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2150 (cp_hdr->ucode_start_addr_hi << 30) | 2151 (cp_hdr->ucode_start_addr_lo >> 2) ); 2152 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2153 cp_hdr->ucode_start_addr_hi>>2); 2154 2155 /* 2156 * Program CP_ME_CNTL to reset given PIPE to take 2157 * effect of CP_ME_PRGRM_CNTR_START. 2158 */ 2159 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2160 if (pipe_id == 0) 2161 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2162 ME_PIPE0_RESET, 1); 2163 else 2164 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2165 ME_PIPE1_RESET, 1); 2166 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2167 2168 /* Clear pfp pipe0 reset bit. */ 2169 if (pipe_id == 0) 2170 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2171 ME_PIPE0_RESET, 0); 2172 else 2173 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2174 ME_PIPE1_RESET, 0); 2175 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2176 } 2177 soc24_grbm_select(adev, 0, 0, 0, 0); 2178 mutex_unlock(&adev->srbm_mutex); 2179 } 2180 2181 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev) 2182 { 2183 const struct gfx_firmware_header_v2_0 *cp_hdr; 2184 unsigned pipe_id; 2185 2186 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2187 adev->gfx.mec_fw->data; 2188 mutex_lock(&adev->srbm_mutex); 2189 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 2190 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2191 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2192 cp_hdr->ucode_start_addr_lo >> 2 | 2193 cp_hdr->ucode_start_addr_hi << 30); 2194 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2195 cp_hdr->ucode_start_addr_hi >> 2); 2196 } 2197 soc24_grbm_select(adev, 0, 0, 0, 0); 2198 mutex_unlock(&adev->srbm_mutex); 2199 } 2200 2201 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2202 { 2203 uint32_t cp_status; 2204 uint32_t bootload_status; 2205 int i; 2206 2207 for (i = 0; i < adev->usec_timeout; i++) { 2208 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2209 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2210 2211 if ((cp_status == 0) && 2212 (REG_GET_FIELD(bootload_status, 2213 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2214 break; 2215 } 2216 udelay(1); 2217 if (amdgpu_emu_mode) 2218 msleep(10); 2219 } 2220 2221 if (i >= adev->usec_timeout) { 2222 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2223 return -ETIMEDOUT; 2224 } 2225 2226 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2227 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2228 gfx_v12_0_set_me_ucode_start_addr(adev); 2229 gfx_v12_0_set_mec_ucode_start_addr(adev); 2230 } 2231 2232 return 0; 2233 } 2234 2235 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2236 { 2237 int i; 2238 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2239 2240 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2241 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2242 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2243 2244 for (i = 0; i < adev->usec_timeout; i++) { 2245 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2246 break; 2247 udelay(1); 2248 } 2249 2250 if (i >= adev->usec_timeout) 2251 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2252 2253 return 0; 2254 } 2255 2256 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2257 { 2258 int r; 2259 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2260 const __le32 *fw_ucode, *fw_data; 2261 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2262 uint32_t tmp; 2263 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2264 2265 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2266 adev->gfx.pfp_fw->data; 2267 2268 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2269 2270 /* instruction */ 2271 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2272 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2273 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2274 /* data */ 2275 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2276 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2277 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2278 2279 /* 64kb align */ 2280 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2281 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2282 &adev->gfx.pfp.pfp_fw_obj, 2283 &adev->gfx.pfp.pfp_fw_gpu_addr, 2284 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2285 if (r) { 2286 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2287 gfx_v12_0_pfp_fini(adev); 2288 return r; 2289 } 2290 2291 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2292 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2293 &adev->gfx.pfp.pfp_fw_data_obj, 2294 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2295 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2296 if (r) { 2297 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2298 gfx_v12_0_pfp_fini(adev); 2299 return r; 2300 } 2301 2302 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2303 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2304 2305 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2306 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2307 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2308 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2309 2310 if (amdgpu_emu_mode == 1) 2311 adev->hdp.funcs->flush_hdp(adev, NULL); 2312 2313 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2314 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2315 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2316 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2317 2318 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2319 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2320 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2321 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2322 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2323 2324 /* 2325 * Programming any of the CP_PFP_IC_BASE registers 2326 * forces invalidation of the ME L1 I$. Wait for the 2327 * invalidation complete 2328 */ 2329 for (i = 0; i < usec_timeout; i++) { 2330 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2331 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2332 INVALIDATE_CACHE_COMPLETE)) 2333 break; 2334 udelay(1); 2335 } 2336 2337 if (i >= usec_timeout) { 2338 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2339 return -EINVAL; 2340 } 2341 2342 /* Prime the L1 instruction caches */ 2343 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2344 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2345 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2346 /* Waiting for cache primed*/ 2347 for (i = 0; i < usec_timeout; i++) { 2348 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2349 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2350 ICACHE_PRIMED)) 2351 break; 2352 udelay(1); 2353 } 2354 2355 if (i >= usec_timeout) { 2356 dev_err(adev->dev, "failed to prime instruction cache\n"); 2357 return -EINVAL; 2358 } 2359 2360 mutex_lock(&adev->srbm_mutex); 2361 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2362 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2363 2364 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2365 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2366 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2367 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2368 } 2369 soc24_grbm_select(adev, 0, 0, 0, 0); 2370 mutex_unlock(&adev->srbm_mutex); 2371 2372 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2373 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2374 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2375 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2376 2377 /* Invalidate the data caches */ 2378 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2379 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2380 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2381 2382 for (i = 0; i < usec_timeout; i++) { 2383 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2384 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2385 INVALIDATE_DCACHE_COMPLETE)) 2386 break; 2387 udelay(1); 2388 } 2389 2390 if (i >= usec_timeout) { 2391 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2392 return -EINVAL; 2393 } 2394 2395 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2396 2397 return 0; 2398 } 2399 2400 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2401 { 2402 int r; 2403 const struct gfx_firmware_header_v2_0 *me_hdr; 2404 const __le32 *fw_ucode, *fw_data; 2405 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2406 uint32_t tmp; 2407 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2408 2409 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2410 adev->gfx.me_fw->data; 2411 2412 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2413 2414 /* instruction */ 2415 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2416 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2417 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2418 /* data */ 2419 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2420 le32_to_cpu(me_hdr->data_offset_bytes)); 2421 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2422 2423 /* 64kb align*/ 2424 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2425 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2426 &adev->gfx.me.me_fw_obj, 2427 &adev->gfx.me.me_fw_gpu_addr, 2428 (void **)&adev->gfx.me.me_fw_ptr); 2429 if (r) { 2430 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2431 gfx_v12_0_me_fini(adev); 2432 return r; 2433 } 2434 2435 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2436 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2437 &adev->gfx.me.me_fw_data_obj, 2438 &adev->gfx.me.me_fw_data_gpu_addr, 2439 (void **)&adev->gfx.me.me_fw_data_ptr); 2440 if (r) { 2441 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2442 gfx_v12_0_pfp_fini(adev); 2443 return r; 2444 } 2445 2446 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2447 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2448 2449 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2450 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2451 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2452 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2453 2454 if (amdgpu_emu_mode == 1) 2455 adev->hdp.funcs->flush_hdp(adev, NULL); 2456 2457 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2458 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2459 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2460 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2461 2462 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2463 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2464 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2465 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2466 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2467 2468 /* 2469 * Programming any of the CP_ME_IC_BASE registers 2470 * forces invalidation of the ME L1 I$. Wait for the 2471 * invalidation complete 2472 */ 2473 for (i = 0; i < usec_timeout; i++) { 2474 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2475 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2476 INVALIDATE_CACHE_COMPLETE)) 2477 break; 2478 udelay(1); 2479 } 2480 2481 if (i >= usec_timeout) { 2482 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2483 return -EINVAL; 2484 } 2485 2486 /* Prime the instruction caches */ 2487 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2488 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2489 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2490 2491 /* Waiting for instruction cache primed*/ 2492 for (i = 0; i < usec_timeout; i++) { 2493 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2494 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2495 ICACHE_PRIMED)) 2496 break; 2497 udelay(1); 2498 } 2499 2500 if (i >= usec_timeout) { 2501 dev_err(adev->dev, "failed to prime instruction cache\n"); 2502 return -EINVAL; 2503 } 2504 2505 mutex_lock(&adev->srbm_mutex); 2506 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2507 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2508 2509 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2510 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2511 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2512 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2513 } 2514 soc24_grbm_select(adev, 0, 0, 0, 0); 2515 mutex_unlock(&adev->srbm_mutex); 2516 2517 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2518 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2519 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2520 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2521 2522 /* Invalidate the data caches */ 2523 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2524 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2525 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2526 2527 for (i = 0; i < usec_timeout; i++) { 2528 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2529 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2530 INVALIDATE_DCACHE_COMPLETE)) 2531 break; 2532 udelay(1); 2533 } 2534 2535 if (i >= usec_timeout) { 2536 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2537 return -EINVAL; 2538 } 2539 2540 gfx_v12_0_set_me_ucode_start_addr(adev); 2541 2542 return 0; 2543 } 2544 2545 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2546 { 2547 int r; 2548 2549 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 2550 return -EINVAL; 2551 2552 gfx_v12_0_cp_gfx_enable(adev, false); 2553 2554 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev); 2555 if (r) { 2556 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2557 return r; 2558 } 2559 2560 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev); 2561 if (r) { 2562 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2563 return r; 2564 } 2565 2566 return 0; 2567 } 2568 2569 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev) 2570 { 2571 /* init the CP */ 2572 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 2573 adev->gfx.config.max_hw_contexts - 1); 2574 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 2575 2576 if (!amdgpu_async_gfx_ring) 2577 gfx_v12_0_cp_gfx_enable(adev, true); 2578 2579 return 0; 2580 } 2581 2582 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2583 CP_PIPE_ID pipe) 2584 { 2585 u32 tmp; 2586 2587 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 2588 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2589 2590 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 2591 } 2592 2593 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2594 struct amdgpu_ring *ring) 2595 { 2596 u32 tmp; 2597 2598 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2599 if (ring->use_doorbell) { 2600 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2601 DOORBELL_OFFSET, ring->doorbell_index); 2602 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2603 DOORBELL_EN, 1); 2604 } else { 2605 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2606 DOORBELL_EN, 0); 2607 } 2608 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 2609 2610 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2611 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2612 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 2613 2614 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2615 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2616 } 2617 2618 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev) 2619 { 2620 struct amdgpu_ring *ring; 2621 u32 tmp; 2622 u32 rb_bufsz; 2623 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2624 u32 i; 2625 2626 /* Set the write pointer delay */ 2627 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 2628 2629 /* set the RB to use vmid 0 */ 2630 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 2631 2632 /* Init gfx ring 0 for pipe 0 */ 2633 mutex_lock(&adev->srbm_mutex); 2634 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2635 2636 /* Set ring buffer size */ 2637 ring = &adev->gfx.gfx_ring[0]; 2638 rb_bufsz = order_base_2(ring->ring_size / 8); 2639 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2640 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2641 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2642 2643 /* Initialize the ring buffer's write pointers */ 2644 ring->wptr = 0; 2645 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2646 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2647 2648 /* set the wb address whether it's enabled or not */ 2649 rptr_addr = ring->rptr_gpu_addr; 2650 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2651 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2652 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2653 2654 wptr_gpu_addr = ring->wptr_gpu_addr; 2655 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 2656 lower_32_bits(wptr_gpu_addr)); 2657 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 2658 upper_32_bits(wptr_gpu_addr)); 2659 2660 mdelay(1); 2661 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2662 2663 rb_addr = ring->gpu_addr >> 8; 2664 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 2665 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2666 2667 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 2668 2669 gfx_v12_0_cp_gfx_set_doorbell(adev, ring); 2670 mutex_unlock(&adev->srbm_mutex); 2671 2672 /* Switch to pipe 0 */ 2673 mutex_lock(&adev->srbm_mutex); 2674 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2675 mutex_unlock(&adev->srbm_mutex); 2676 2677 /* start the ring */ 2678 gfx_v12_0_cp_gfx_start(adev); 2679 2680 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2681 ring = &adev->gfx.gfx_ring[i]; 2682 ring->sched.ready = true; 2683 } 2684 2685 return 0; 2686 } 2687 2688 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2689 { 2690 u32 data; 2691 2692 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2693 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2694 enable ? 0 : 1); 2695 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2696 enable ? 0 : 1); 2697 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2698 enable ? 0 : 1); 2699 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2700 enable ? 0 : 1); 2701 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2702 enable ? 0 : 1); 2703 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2704 enable ? 1 : 0); 2705 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2706 enable ? 1 : 0); 2707 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2708 enable ? 1 : 0); 2709 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2710 enable ? 1 : 0); 2711 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2712 enable ? 0 : 1); 2713 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 2714 2715 adev->gfx.kiq[0].ring.sched.ready = enable; 2716 2717 udelay(50); 2718 } 2719 2720 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 2721 { 2722 const struct gfx_firmware_header_v2_0 *mec_hdr; 2723 const __le32 *fw_ucode, *fw_data; 2724 u32 tmp, fw_ucode_size, fw_data_size; 2725 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 2726 u32 *fw_ucode_ptr, *fw_data_ptr; 2727 int r; 2728 2729 if (!adev->gfx.mec_fw) 2730 return -EINVAL; 2731 2732 gfx_v12_0_cp_compute_enable(adev, false); 2733 2734 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2735 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2736 2737 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2738 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2739 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2740 2741 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2742 le32_to_cpu(mec_hdr->data_offset_bytes)); 2743 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2744 2745 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2746 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2747 &adev->gfx.mec.mec_fw_obj, 2748 &adev->gfx.mec.mec_fw_gpu_addr, 2749 (void **)&fw_ucode_ptr); 2750 if (r) { 2751 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2752 gfx_v12_0_mec_fini(adev); 2753 return r; 2754 } 2755 2756 r = amdgpu_bo_create_reserved(adev, 2757 ALIGN(fw_data_size, 64 * 1024) * 2758 adev->gfx.mec.num_pipe_per_mec, 2759 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2760 &adev->gfx.mec.mec_fw_data_obj, 2761 &adev->gfx.mec.mec_fw_data_gpu_addr, 2762 (void **)&fw_data_ptr); 2763 if (r) { 2764 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2765 gfx_v12_0_mec_fini(adev); 2766 return r; 2767 } 2768 2769 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2770 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2771 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); 2772 } 2773 2774 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2775 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2776 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2777 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2778 2779 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2780 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2781 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2782 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2783 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2784 2785 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2786 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2787 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2788 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2789 2790 mutex_lock(&adev->srbm_mutex); 2791 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2792 soc24_grbm_select(adev, 1, i, 0, 0); 2793 2794 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, 2795 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2796 i * ALIGN(fw_data_size, 64 * 1024))); 2797 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2798 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2799 i * ALIGN(fw_data_size, 64 * 1024))); 2800 2801 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2802 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2803 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2804 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2805 } 2806 mutex_unlock(&adev->srbm_mutex); 2807 soc24_grbm_select(adev, 0, 0, 0, 0); 2808 2809 /* Trigger an invalidation of the L1 instruction caches */ 2810 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2811 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2812 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2813 2814 /* Wait for invalidation complete */ 2815 for (i = 0; i < usec_timeout; i++) { 2816 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2817 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2818 INVALIDATE_DCACHE_COMPLETE)) 2819 break; 2820 udelay(1); 2821 } 2822 2823 if (i >= usec_timeout) { 2824 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2825 return -EINVAL; 2826 } 2827 2828 /* Trigger an invalidation of the L1 instruction caches */ 2829 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2830 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2831 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2832 2833 /* Wait for invalidation complete */ 2834 for (i = 0; i < usec_timeout; i++) { 2835 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2836 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2837 INVALIDATE_CACHE_COMPLETE)) 2838 break; 2839 udelay(1); 2840 } 2841 2842 if (i >= usec_timeout) { 2843 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2844 return -EINVAL; 2845 } 2846 2847 gfx_v12_0_set_mec_ucode_start_addr(adev); 2848 2849 return 0; 2850 } 2851 2852 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring) 2853 { 2854 uint32_t tmp; 2855 struct amdgpu_device *adev = ring->adev; 2856 2857 /* tell RLC which is KIQ queue */ 2858 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 2859 tmp &= 0xffffff00; 2860 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2861 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 2862 } 2863 2864 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev) 2865 { 2866 /* set graphics engine doorbell range */ 2867 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 2868 (adev->doorbell_index.gfx_ring0 * 2) << 2); 2869 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2870 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 2871 2872 /* set compute engine doorbell range */ 2873 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 2874 (adev->doorbell_index.kiq * 2) << 2); 2875 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 2876 (adev->doorbell_index.userqueue_end * 2) << 2); 2877 } 2878 2879 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 2880 struct amdgpu_mqd_prop *prop) 2881 { 2882 struct v12_gfx_mqd *mqd = m; 2883 uint64_t hqd_gpu_addr, wb_gpu_addr; 2884 uint32_t tmp; 2885 uint32_t rb_bufsz; 2886 2887 /* set up gfx hqd wptr */ 2888 mqd->cp_gfx_hqd_wptr = 0; 2889 mqd->cp_gfx_hqd_wptr_hi = 0; 2890 2891 /* set the pointer to the MQD */ 2892 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 2893 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2894 2895 /* set up mqd control */ 2896 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 2897 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2898 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2899 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2900 mqd->cp_gfx_mqd_control = tmp; 2901 2902 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2903 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 2904 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2905 mqd->cp_gfx_hqd_vmid = 0; 2906 2907 /* set up default queue priority level 2908 * 0x0 = low priority, 0x1 = high priority */ 2909 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 2910 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 2911 mqd->cp_gfx_hqd_queue_priority = tmp; 2912 2913 /* set up time quantum */ 2914 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 2915 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 2916 mqd->cp_gfx_hqd_quantum = tmp; 2917 2918 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 2919 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 2920 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 2921 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 2922 2923 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 2924 wb_gpu_addr = prop->rptr_gpu_addr; 2925 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 2926 mqd->cp_gfx_hqd_rptr_addr_hi = 2927 upper_32_bits(wb_gpu_addr) & 0xffff; 2928 2929 /* set up rb_wptr_poll addr */ 2930 wb_gpu_addr = prop->wptr_gpu_addr; 2931 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2932 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2933 2934 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 2935 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 2936 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 2937 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 2938 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 2939 #ifdef __BIG_ENDIAN 2940 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 2941 #endif 2942 mqd->cp_gfx_hqd_cntl = tmp; 2943 2944 /* set up cp_doorbell_control */ 2945 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2946 if (prop->use_doorbell) { 2947 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2948 DOORBELL_OFFSET, prop->doorbell_index); 2949 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2950 DOORBELL_EN, 1); 2951 } else 2952 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2953 DOORBELL_EN, 0); 2954 mqd->cp_rb_doorbell_control = tmp; 2955 2956 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2957 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 2958 2959 /* active the queue */ 2960 mqd->cp_gfx_hqd_active = 1; 2961 2962 return 0; 2963 } 2964 2965 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 2966 { 2967 struct amdgpu_device *adev = ring->adev; 2968 struct v12_gfx_mqd *mqd = ring->mqd_ptr; 2969 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 2970 2971 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 2972 memset((void *)mqd, 0, sizeof(*mqd)); 2973 mutex_lock(&adev->srbm_mutex); 2974 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2975 amdgpu_ring_init_mqd(ring); 2976 soc24_grbm_select(adev, 0, 0, 0, 0); 2977 mutex_unlock(&adev->srbm_mutex); 2978 if (adev->gfx.me.mqd_backup[mqd_idx]) 2979 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 2980 } else { 2981 /* restore mqd with the backup copy */ 2982 if (adev->gfx.me.mqd_backup[mqd_idx]) 2983 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 2984 /* reset the ring */ 2985 ring->wptr = 0; 2986 *ring->wptr_cpu_addr = 0; 2987 amdgpu_ring_clear_ring(ring); 2988 } 2989 2990 return 0; 2991 } 2992 2993 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 2994 { 2995 int r, i; 2996 struct amdgpu_ring *ring; 2997 2998 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2999 ring = &adev->gfx.gfx_ring[i]; 3000 3001 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3002 if (unlikely(r != 0)) 3003 goto done; 3004 3005 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3006 if (!r) { 3007 r = gfx_v12_0_kgq_init_queue(ring, false); 3008 amdgpu_bo_kunmap(ring->mqd_obj); 3009 ring->mqd_ptr = NULL; 3010 } 3011 amdgpu_bo_unreserve(ring->mqd_obj); 3012 if (r) 3013 goto done; 3014 } 3015 3016 r = amdgpu_gfx_enable_kgq(adev, 0); 3017 if (r) 3018 goto done; 3019 3020 r = gfx_v12_0_cp_gfx_start(adev); 3021 if (r) 3022 goto done; 3023 3024 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3025 ring = &adev->gfx.gfx_ring[i]; 3026 ring->sched.ready = true; 3027 } 3028 done: 3029 return r; 3030 } 3031 3032 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3033 struct amdgpu_mqd_prop *prop) 3034 { 3035 struct v12_compute_mqd *mqd = m; 3036 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3037 uint32_t tmp; 3038 3039 mqd->header = 0xC0310800; 3040 mqd->compute_pipelinestat_enable = 0x00000001; 3041 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3042 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3043 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3044 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3045 mqd->compute_misc_reserved = 0x00000007; 3046 3047 eop_base_addr = prop->eop_gpu_addr >> 8; 3048 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3049 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3050 3051 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3052 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 3053 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3054 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 3055 3056 mqd->cp_hqd_eop_control = tmp; 3057 3058 /* enable doorbell? */ 3059 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3060 3061 if (prop->use_doorbell) { 3062 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3063 DOORBELL_OFFSET, prop->doorbell_index); 3064 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3065 DOORBELL_EN, 1); 3066 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3067 DOORBELL_SOURCE, 0); 3068 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3069 DOORBELL_HIT, 0); 3070 } else { 3071 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3072 DOORBELL_EN, 0); 3073 } 3074 3075 mqd->cp_hqd_pq_doorbell_control = tmp; 3076 3077 /* disable the queue if it's active */ 3078 mqd->cp_hqd_dequeue_request = 0; 3079 mqd->cp_hqd_pq_rptr = 0; 3080 mqd->cp_hqd_pq_wptr_lo = 0; 3081 mqd->cp_hqd_pq_wptr_hi = 0; 3082 3083 /* set the pointer to the MQD */ 3084 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3085 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3086 3087 /* set MQD vmid to 0 */ 3088 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 3089 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3090 mqd->cp_mqd_control = tmp; 3091 3092 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3093 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3094 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3095 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3096 3097 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3098 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 3099 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3100 (order_base_2(prop->queue_size / 4) - 1)); 3101 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3102 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3103 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3104 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3105 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3106 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3107 mqd->cp_hqd_pq_control = tmp; 3108 3109 /* set the wb address whether it's enabled or not */ 3110 wb_gpu_addr = prop->rptr_gpu_addr; 3111 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3112 mqd->cp_hqd_pq_rptr_report_addr_hi = 3113 upper_32_bits(wb_gpu_addr) & 0xffff; 3114 3115 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3116 wb_gpu_addr = prop->wptr_gpu_addr; 3117 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3118 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3119 3120 tmp = 0; 3121 /* enable the doorbell if requested */ 3122 if (prop->use_doorbell) { 3123 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3124 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3125 DOORBELL_OFFSET, prop->doorbell_index); 3126 3127 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3128 DOORBELL_EN, 1); 3129 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3130 DOORBELL_SOURCE, 0); 3131 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3132 DOORBELL_HIT, 0); 3133 } 3134 3135 mqd->cp_hqd_pq_doorbell_control = tmp; 3136 3137 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3138 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 3139 3140 /* set the vmid for the queue */ 3141 mqd->cp_hqd_vmid = 0; 3142 3143 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 3144 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3145 mqd->cp_hqd_persistent_state = tmp; 3146 3147 /* set MIN_IB_AVAIL_SIZE */ 3148 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 3149 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3150 mqd->cp_hqd_ib_control = tmp; 3151 3152 /* set static priority for a compute queue/ring */ 3153 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3154 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3155 3156 mqd->cp_hqd_active = prop->hqd_active; 3157 3158 return 0; 3159 } 3160 3161 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring) 3162 { 3163 struct amdgpu_device *adev = ring->adev; 3164 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3165 int j; 3166 3167 /* inactivate the queue */ 3168 if (amdgpu_sriov_vf(adev)) 3169 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3170 3171 /* disable wptr polling */ 3172 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3173 3174 /* write the EOP addr */ 3175 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3176 mqd->cp_hqd_eop_base_addr_lo); 3177 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3178 mqd->cp_hqd_eop_base_addr_hi); 3179 3180 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3181 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3182 mqd->cp_hqd_eop_control); 3183 3184 /* enable doorbell? */ 3185 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3186 mqd->cp_hqd_pq_doorbell_control); 3187 3188 /* disable the queue if it's active */ 3189 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3190 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3191 for (j = 0; j < adev->usec_timeout; j++) { 3192 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3193 break; 3194 udelay(1); 3195 } 3196 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3197 mqd->cp_hqd_dequeue_request); 3198 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3199 mqd->cp_hqd_pq_rptr); 3200 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3201 mqd->cp_hqd_pq_wptr_lo); 3202 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3203 mqd->cp_hqd_pq_wptr_hi); 3204 } 3205 3206 /* set the pointer to the MQD */ 3207 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3208 mqd->cp_mqd_base_addr_lo); 3209 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3210 mqd->cp_mqd_base_addr_hi); 3211 3212 /* set MQD vmid to 0 */ 3213 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3214 mqd->cp_mqd_control); 3215 3216 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3217 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3218 mqd->cp_hqd_pq_base_lo); 3219 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3220 mqd->cp_hqd_pq_base_hi); 3221 3222 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3223 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3224 mqd->cp_hqd_pq_control); 3225 3226 /* set the wb address whether it's enabled or not */ 3227 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3228 mqd->cp_hqd_pq_rptr_report_addr_lo); 3229 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3230 mqd->cp_hqd_pq_rptr_report_addr_hi); 3231 3232 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3233 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3234 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3235 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3236 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3237 3238 /* enable the doorbell if requested */ 3239 if (ring->use_doorbell) { 3240 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3241 (adev->doorbell_index.kiq * 2) << 2); 3242 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3243 (adev->doorbell_index.userqueue_end * 2) << 2); 3244 } 3245 3246 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3247 mqd->cp_hqd_pq_doorbell_control); 3248 3249 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3250 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3251 mqd->cp_hqd_pq_wptr_lo); 3252 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3253 mqd->cp_hqd_pq_wptr_hi); 3254 3255 /* set the vmid for the queue */ 3256 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3257 3258 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3259 mqd->cp_hqd_persistent_state); 3260 3261 /* activate the queue */ 3262 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3263 mqd->cp_hqd_active); 3264 3265 if (ring->use_doorbell) 3266 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3267 3268 return 0; 3269 } 3270 3271 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring) 3272 { 3273 struct amdgpu_device *adev = ring->adev; 3274 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3275 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3276 3277 gfx_v12_0_kiq_setting(ring); 3278 3279 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3280 /* reset MQD to a clean status */ 3281 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3282 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3283 3284 /* reset ring buffer */ 3285 ring->wptr = 0; 3286 amdgpu_ring_clear_ring(ring); 3287 3288 mutex_lock(&adev->srbm_mutex); 3289 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3290 gfx_v12_0_kiq_init_register(ring); 3291 soc24_grbm_select(adev, 0, 0, 0, 0); 3292 mutex_unlock(&adev->srbm_mutex); 3293 } else { 3294 memset((void *)mqd, 0, sizeof(*mqd)); 3295 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3296 amdgpu_ring_clear_ring(ring); 3297 mutex_lock(&adev->srbm_mutex); 3298 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3299 amdgpu_ring_init_mqd(ring); 3300 gfx_v12_0_kiq_init_register(ring); 3301 soc24_grbm_select(adev, 0, 0, 0, 0); 3302 mutex_unlock(&adev->srbm_mutex); 3303 3304 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3305 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3306 } 3307 3308 return 0; 3309 } 3310 3311 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) 3312 { 3313 struct amdgpu_device *adev = ring->adev; 3314 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3315 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3316 3317 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3318 memset((void *)mqd, 0, sizeof(*mqd)); 3319 mutex_lock(&adev->srbm_mutex); 3320 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3321 amdgpu_ring_init_mqd(ring); 3322 soc24_grbm_select(adev, 0, 0, 0, 0); 3323 mutex_unlock(&adev->srbm_mutex); 3324 3325 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3326 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3327 } else { 3328 /* restore MQD to a clean status */ 3329 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3330 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3331 /* reset ring buffer */ 3332 ring->wptr = 0; 3333 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3334 amdgpu_ring_clear_ring(ring); 3335 } 3336 3337 return 0; 3338 } 3339 3340 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev) 3341 { 3342 struct amdgpu_ring *ring; 3343 int r; 3344 3345 ring = &adev->gfx.kiq[0].ring; 3346 3347 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3348 if (unlikely(r != 0)) 3349 return r; 3350 3351 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3352 if (unlikely(r != 0)) { 3353 amdgpu_bo_unreserve(ring->mqd_obj); 3354 return r; 3355 } 3356 3357 gfx_v12_0_kiq_init_queue(ring); 3358 amdgpu_bo_kunmap(ring->mqd_obj); 3359 ring->mqd_ptr = NULL; 3360 amdgpu_bo_unreserve(ring->mqd_obj); 3361 ring->sched.ready = true; 3362 return 0; 3363 } 3364 3365 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev) 3366 { 3367 struct amdgpu_ring *ring = NULL; 3368 int r = 0, i; 3369 3370 if (!amdgpu_async_gfx_ring) 3371 gfx_v12_0_cp_compute_enable(adev, true); 3372 3373 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3374 ring = &adev->gfx.compute_ring[i]; 3375 3376 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3377 if (unlikely(r != 0)) 3378 goto done; 3379 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3380 if (!r) { 3381 r = gfx_v12_0_kcq_init_queue(ring, false); 3382 amdgpu_bo_kunmap(ring->mqd_obj); 3383 ring->mqd_ptr = NULL; 3384 } 3385 amdgpu_bo_unreserve(ring->mqd_obj); 3386 if (r) 3387 goto done; 3388 } 3389 3390 r = amdgpu_gfx_enable_kcq(adev, 0); 3391 done: 3392 return r; 3393 } 3394 3395 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev) 3396 { 3397 int r, i; 3398 struct amdgpu_ring *ring; 3399 3400 if (!(adev->flags & AMD_IS_APU)) 3401 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3402 3403 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3404 /* legacy firmware loading */ 3405 r = gfx_v12_0_cp_gfx_load_microcode(adev); 3406 if (r) 3407 return r; 3408 3409 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev); 3410 if (r) 3411 return r; 3412 } 3413 3414 gfx_v12_0_cp_set_doorbell_range(adev); 3415 3416 if (amdgpu_async_gfx_ring) { 3417 gfx_v12_0_cp_compute_enable(adev, true); 3418 gfx_v12_0_cp_gfx_enable(adev, true); 3419 } 3420 3421 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 3422 r = amdgpu_mes_kiq_hw_init(adev); 3423 else 3424 r = gfx_v12_0_kiq_resume(adev); 3425 if (r) 3426 return r; 3427 3428 r = gfx_v12_0_kcq_resume(adev); 3429 if (r) 3430 return r; 3431 3432 if (!amdgpu_async_gfx_ring) { 3433 r = gfx_v12_0_cp_gfx_resume(adev); 3434 if (r) 3435 return r; 3436 } else { 3437 r = gfx_v12_0_cp_async_gfx_ring_resume(adev); 3438 if (r) 3439 return r; 3440 } 3441 3442 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3443 ring = &adev->gfx.gfx_ring[i]; 3444 r = amdgpu_ring_test_helper(ring); 3445 if (r) 3446 return r; 3447 } 3448 3449 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3450 ring = &adev->gfx.compute_ring[i]; 3451 r = amdgpu_ring_test_helper(ring); 3452 if (r) 3453 return r; 3454 } 3455 3456 return 0; 3457 } 3458 3459 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable) 3460 { 3461 gfx_v12_0_cp_gfx_enable(adev, enable); 3462 gfx_v12_0_cp_compute_enable(adev, enable); 3463 } 3464 3465 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) 3466 { 3467 int r; 3468 bool value; 3469 3470 r = adev->gfxhub.funcs->gart_enable(adev); 3471 if (r) 3472 return r; 3473 3474 adev->hdp.funcs->flush_hdp(adev, NULL); 3475 3476 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 3477 false : true; 3478 3479 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 3480 /* TODO investigate why this and the hdp flush above is needed, 3481 * are we missing a flush somewhere else? */ 3482 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 3483 3484 return 0; 3485 } 3486 3487 static int get_gb_addr_config(struct amdgpu_device *adev) 3488 { 3489 u32 gb_addr_config; 3490 3491 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 3492 if (gb_addr_config == 0) 3493 return -EINVAL; 3494 3495 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3496 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 3497 3498 adev->gfx.config.gb_addr_config = gb_addr_config; 3499 3500 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 3501 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3502 GB_ADDR_CONFIG, NUM_PIPES); 3503 3504 adev->gfx.config.max_tile_pipes = 3505 adev->gfx.config.gb_addr_config_fields.num_pipes; 3506 3507 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 3508 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3509 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 3510 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 3511 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3512 GB_ADDR_CONFIG, NUM_RB_PER_SE); 3513 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 3514 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3515 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 3516 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 3517 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3518 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 3519 3520 return 0; 3521 } 3522 3523 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 3524 { 3525 uint32_t data; 3526 3527 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 3528 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 3529 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 3530 3531 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 3532 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 3533 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 3534 } 3535 3536 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) 3537 { 3538 if (amdgpu_sriov_vf(adev)) 3539 return; 3540 3541 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3542 case IP_VERSION(12, 0, 0): 3543 case IP_VERSION(12, 0, 1): 3544 soc15_program_register_sequence(adev, 3545 golden_settings_gc_12_0, 3546 (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); 3547 3548 if (adev->rev_id == 0) 3549 soc15_program_register_sequence(adev, 3550 golden_settings_gc_12_0_rev0, 3551 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0)); 3552 break; 3553 default: 3554 break; 3555 } 3556 } 3557 3558 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 3559 { 3560 int r; 3561 struct amdgpu_device *adev = ip_block->adev; 3562 3563 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3564 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3565 /* RLC autoload sequence 1: Program rlc ram */ 3566 if (adev->gfx.imu.funcs->program_rlc_ram) 3567 adev->gfx.imu.funcs->program_rlc_ram(adev); 3568 } 3569 /* rlc autoload firmware */ 3570 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev); 3571 if (r) 3572 return r; 3573 } else { 3574 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3575 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3576 if (adev->gfx.imu.funcs->load_microcode) 3577 adev->gfx.imu.funcs->load_microcode(adev); 3578 if (adev->gfx.imu.funcs->setup_imu) 3579 adev->gfx.imu.funcs->setup_imu(adev); 3580 if (adev->gfx.imu.funcs->start_imu) 3581 adev->gfx.imu.funcs->start_imu(adev); 3582 } 3583 3584 /* disable gpa mode in backdoor loading */ 3585 gfx_v12_0_disable_gpa_mode(adev); 3586 } 3587 } 3588 3589 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 3590 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3591 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev); 3592 if (r) { 3593 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 3594 return r; 3595 } 3596 } 3597 3598 if (!amdgpu_emu_mode) 3599 gfx_v12_0_init_golden_registers(adev); 3600 3601 adev->gfx.is_poweron = true; 3602 3603 if (get_gb_addr_config(adev)) 3604 DRM_WARN("Invalid gb_addr_config !\n"); 3605 3606 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 3607 gfx_v12_0_config_gfx_rs64(adev); 3608 3609 r = gfx_v12_0_gfxhub_enable(adev); 3610 if (r) 3611 return r; 3612 3613 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT || 3614 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) && 3615 (amdgpu_dpm == 1)) { 3616 /** 3617 * For gfx 12, rlc firmware loading relies on smu firmware is 3618 * loaded firstly, so in direct type, it has to load smc ucode 3619 * here before rlc. 3620 */ 3621 r = amdgpu_pm_load_smu_firmware(adev, NULL); 3622 if (r) 3623 return r; 3624 } 3625 3626 gfx_v12_0_constants_init(adev); 3627 3628 if (adev->nbio.funcs->gc_doorbell_init) 3629 adev->nbio.funcs->gc_doorbell_init(adev); 3630 3631 r = gfx_v12_0_rlc_resume(adev); 3632 if (r) 3633 return r; 3634 3635 /* 3636 * init golden registers and rlc resume may override some registers, 3637 * reconfig them here 3638 */ 3639 gfx_v12_0_tcp_harvest(adev); 3640 3641 r = gfx_v12_0_cp_resume(adev); 3642 if (r) 3643 return r; 3644 3645 return r; 3646 } 3647 3648 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 3649 { 3650 struct amdgpu_device *adev = ip_block->adev; 3651 uint32_t tmp; 3652 3653 cancel_delayed_work_sync(&adev->gfx.idle_work); 3654 3655 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3656 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3657 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3658 3659 if (!adev->no_hw_access) { 3660 if (amdgpu_async_gfx_ring) { 3661 if (amdgpu_gfx_disable_kgq(adev, 0)) 3662 DRM_ERROR("KGQ disable failed\n"); 3663 } 3664 3665 if (amdgpu_gfx_disable_kcq(adev, 0)) 3666 DRM_ERROR("KCQ disable failed\n"); 3667 3668 amdgpu_mes_kiq_hw_fini(adev); 3669 } 3670 3671 if (amdgpu_sriov_vf(adev)) { 3672 gfx_v12_0_cp_gfx_enable(adev, false); 3673 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 3674 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3675 tmp &= 0xffffff00; 3676 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3677 3678 return 0; 3679 } 3680 gfx_v12_0_cp_enable(adev, false); 3681 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3682 3683 adev->gfxhub.funcs->gart_disable(adev); 3684 3685 adev->gfx.is_poweron = false; 3686 3687 return 0; 3688 } 3689 3690 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) 3691 { 3692 return gfx_v12_0_hw_fini(ip_block); 3693 } 3694 3695 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) 3696 { 3697 return gfx_v12_0_hw_init(ip_block); 3698 } 3699 3700 static bool gfx_v12_0_is_idle(void *handle) 3701 { 3702 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3703 3704 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 3705 GRBM_STATUS, GUI_ACTIVE)) 3706 return false; 3707 else 3708 return true; 3709 } 3710 3711 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3712 { 3713 unsigned i; 3714 u32 tmp; 3715 struct amdgpu_device *adev = ip_block->adev; 3716 3717 for (i = 0; i < adev->usec_timeout; i++) { 3718 /* read MC_STATUS */ 3719 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 3720 GRBM_STATUS__GUI_ACTIVE_MASK; 3721 3722 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3723 return 0; 3724 udelay(1); 3725 } 3726 return -ETIMEDOUT; 3727 } 3728 3729 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3730 { 3731 uint64_t clock = 0; 3732 3733 if (adev->smuio.funcs && 3734 adev->smuio.funcs->get_gpu_clock_counter) 3735 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 3736 else 3737 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 3738 3739 return clock; 3740 } 3741 3742 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) 3743 { 3744 struct amdgpu_device *adev = ip_block->adev; 3745 3746 adev->gfx.funcs = &gfx_v12_0_gfx_funcs; 3747 3748 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS; 3749 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3750 AMDGPU_MAX_COMPUTE_RINGS); 3751 3752 gfx_v12_0_set_kiq_pm4_funcs(adev); 3753 gfx_v12_0_set_ring_funcs(adev); 3754 gfx_v12_0_set_irq_funcs(adev); 3755 gfx_v12_0_set_rlc_funcs(adev); 3756 gfx_v12_0_set_mqd_funcs(adev); 3757 gfx_v12_0_set_imu_funcs(adev); 3758 3759 gfx_v12_0_init_rlcg_reg_access_ctrl(adev); 3760 3761 return gfx_v12_0_init_microcode(adev); 3762 } 3763 3764 static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block) 3765 { 3766 struct amdgpu_device *adev = ip_block->adev; 3767 int r; 3768 3769 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3770 if (r) 3771 return r; 3772 3773 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3774 if (r) 3775 return r; 3776 3777 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 3778 if (r) 3779 return r; 3780 3781 return 0; 3782 } 3783 3784 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev) 3785 { 3786 uint32_t rlc_cntl; 3787 3788 /* if RLC is not enabled, do nothing */ 3789 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 3790 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3791 } 3792 3793 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, 3794 int xcc_id) 3795 { 3796 uint32_t data; 3797 unsigned i; 3798 3799 data = RLC_SAFE_MODE__CMD_MASK; 3800 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3801 3802 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 3803 3804 /* wait for RLC_SAFE_MODE */ 3805 for (i = 0; i < adev->usec_timeout; i++) { 3806 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 3807 RLC_SAFE_MODE, CMD)) 3808 break; 3809 udelay(1); 3810 } 3811 } 3812 3813 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, 3814 int xcc_id) 3815 { 3816 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 3817 } 3818 3819 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 3820 bool enable) 3821 { 3822 uint32_t def, data; 3823 3824 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 3825 return; 3826 3827 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3828 3829 if (enable) 3830 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3831 else 3832 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3833 3834 if (def != data) 3835 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3836 } 3837 3838 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, 3839 struct amdgpu_ring *ring, 3840 unsigned vmid) 3841 { 3842 u32 reg, data; 3843 3844 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3845 if (amdgpu_sriov_is_pp_one_vf(adev)) 3846 data = RREG32_NO_KIQ(reg); 3847 else 3848 data = RREG32(reg); 3849 3850 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 3851 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 3852 3853 if (amdgpu_sriov_is_pp_one_vf(adev)) 3854 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 3855 else 3856 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 3857 3858 if (ring 3859 && amdgpu_sriov_is_pp_one_vf(adev) 3860 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 3861 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 3862 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3863 amdgpu_ring_emit_wreg(ring, reg, data); 3864 } 3865 } 3866 3867 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = { 3868 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled, 3869 .set_safe_mode = gfx_v12_0_set_safe_mode, 3870 .unset_safe_mode = gfx_v12_0_unset_safe_mode, 3871 .init = gfx_v12_0_rlc_init, 3872 .get_csb_size = gfx_v12_0_get_csb_size, 3873 .get_csb_buffer = gfx_v12_0_get_csb_buffer, 3874 .resume = gfx_v12_0_rlc_resume, 3875 .stop = gfx_v12_0_rlc_stop, 3876 .reset = gfx_v12_0_rlc_reset, 3877 .start = gfx_v12_0_rlc_start, 3878 .update_spm_vmid = gfx_v12_0_update_spm_vmid, 3879 }; 3880 3881 #if 0 3882 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 3883 { 3884 /* TODO */ 3885 } 3886 3887 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 3888 { 3889 /* TODO */ 3890 } 3891 #endif 3892 3893 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3894 enum amd_powergating_state state) 3895 { 3896 struct amdgpu_device *adev = ip_block->adev; 3897 bool enable = (state == AMD_PG_STATE_GATE); 3898 3899 if (amdgpu_sriov_vf(adev)) 3900 return 0; 3901 3902 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3903 case IP_VERSION(12, 0, 0): 3904 case IP_VERSION(12, 0, 1): 3905 amdgpu_gfx_off_ctrl(adev, enable); 3906 break; 3907 default: 3908 break; 3909 } 3910 3911 return 0; 3912 } 3913 3914 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 3915 bool enable) 3916 { 3917 uint32_t def, data; 3918 3919 if (!(adev->cg_flags & 3920 (AMD_CG_SUPPORT_GFX_CGCG | 3921 AMD_CG_SUPPORT_GFX_CGLS | 3922 AMD_CG_SUPPORT_GFX_3D_CGCG | 3923 AMD_CG_SUPPORT_GFX_3D_CGLS))) 3924 return; 3925 3926 if (enable) { 3927 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3928 3929 /* unset CGCG override */ 3930 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3931 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 3932 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3933 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3934 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 3935 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3936 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3937 3938 /* update CGCG override bits */ 3939 if (def != data) 3940 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3941 3942 /* enable cgcg FSM(0x0000363F) */ 3943 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 3944 3945 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 3946 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 3947 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3948 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3949 } 3950 3951 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 3952 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 3953 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3954 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3955 } 3956 3957 if (def != data) 3958 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 3959 3960 /* Program RLC_CGCG_CGLS_CTRL_3D */ 3961 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 3962 3963 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 3964 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 3965 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3966 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 3967 } 3968 3969 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 3970 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 3971 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3972 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 3973 } 3974 3975 if (def != data) 3976 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 3977 3978 /* set IDLE_POLL_COUNT(0x00900100) */ 3979 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 3980 3981 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 3982 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3983 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3984 3985 if (def != data) 3986 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 3987 3988 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 3989 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 3990 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 3991 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 3992 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 3993 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 3994 3995 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 3996 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 3997 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 3998 3999 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4000 if (adev->sdma.num_instances > 1) { 4001 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4002 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4003 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4004 } 4005 } else { 4006 /* Program RLC_CGCG_CGLS_CTRL */ 4007 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4008 4009 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4010 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4011 4012 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4013 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4014 4015 if (def != data) 4016 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4017 4018 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4019 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4020 4021 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4022 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4023 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4024 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4025 4026 if (def != data) 4027 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4028 } 4029 } 4030 4031 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4032 bool enable) 4033 { 4034 uint32_t data, def; 4035 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4036 return; 4037 4038 /* It is disabled by HW by default */ 4039 if (enable) { 4040 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4041 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4042 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4043 4044 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4045 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4046 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4047 4048 if (def != data) 4049 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4050 } 4051 } else { 4052 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4053 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4054 4055 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4056 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4057 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4058 4059 if (def != data) 4060 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4061 } 4062 } 4063 } 4064 4065 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev, 4066 bool enable) 4067 { 4068 uint32_t def, data; 4069 4070 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4071 return; 4072 4073 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4074 4075 if (enable) 4076 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4077 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 4078 else 4079 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4080 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 4081 4082 if (def != data) 4083 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4084 } 4085 4086 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev, 4087 bool enable) 4088 { 4089 uint32_t def, data; 4090 4091 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4092 return; 4093 4094 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4095 4096 if (enable) 4097 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4098 else 4099 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4100 4101 if (def != data) 4102 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4103 } 4104 4105 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4106 bool enable) 4107 { 4108 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4109 4110 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable); 4111 4112 gfx_v12_0_update_medium_grain_clock_gating(adev, enable); 4113 4114 gfx_v12_0_update_repeater_fgcg(adev, enable); 4115 4116 gfx_v12_0_update_sram_fgcg(adev, enable); 4117 4118 gfx_v12_0_update_perf_clk(adev, enable); 4119 4120 if (adev->cg_flags & 4121 (AMD_CG_SUPPORT_GFX_MGCG | 4122 AMD_CG_SUPPORT_GFX_CGLS | 4123 AMD_CG_SUPPORT_GFX_CGCG | 4124 AMD_CG_SUPPORT_GFX_3D_CGCG | 4125 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4126 gfx_v12_0_enable_gui_idle_interrupt(adev, enable); 4127 4128 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4129 4130 return 0; 4131 } 4132 4133 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4134 enum amd_clockgating_state state) 4135 { 4136 struct amdgpu_device *adev = ip_block->adev; 4137 4138 if (amdgpu_sriov_vf(adev)) 4139 return 0; 4140 4141 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4142 case IP_VERSION(12, 0, 0): 4143 case IP_VERSION(12, 0, 1): 4144 gfx_v12_0_update_gfx_clock_gating(adev, 4145 state == AMD_CG_STATE_GATE); 4146 break; 4147 default: 4148 break; 4149 } 4150 4151 return 0; 4152 } 4153 4154 static void gfx_v12_0_get_clockgating_state(void *handle, u64 *flags) 4155 { 4156 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4157 int data; 4158 4159 /* AMD_CG_SUPPORT_GFX_MGCG */ 4160 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4161 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4162 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4163 4164 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 4165 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 4166 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 4167 4168 /* AMD_CG_SUPPORT_GFX_FGCG */ 4169 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 4170 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 4171 4172 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 4173 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 4174 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 4175 4176 /* AMD_CG_SUPPORT_GFX_CGCG */ 4177 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4178 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4179 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4180 4181 /* AMD_CG_SUPPORT_GFX_CGLS */ 4182 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4183 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4184 4185 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4186 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4187 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4188 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4189 4190 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4191 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4192 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4193 } 4194 4195 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4196 { 4197 /* gfx12 is 32bit rptr*/ 4198 return *(uint32_t *)ring->rptr_cpu_addr; 4199 } 4200 4201 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4202 { 4203 struct amdgpu_device *adev = ring->adev; 4204 u64 wptr; 4205 4206 /* XXX check if swapping is necessary on BE */ 4207 if (ring->use_doorbell) { 4208 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4209 } else { 4210 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 4211 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 4212 } 4213 4214 return wptr; 4215 } 4216 4217 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4218 { 4219 struct amdgpu_device *adev = ring->adev; 4220 uint32_t *wptr_saved; 4221 uint32_t *is_queue_unmap; 4222 uint64_t aggregated_db_index; 4223 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 4224 uint64_t wptr_tmp; 4225 4226 if (ring->is_mes_queue) { 4227 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 4228 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 4229 sizeof(uint32_t)); 4230 aggregated_db_index = 4231 amdgpu_mes_get_aggregated_doorbell_index(adev, 4232 ring->hw_prio); 4233 4234 wptr_tmp = ring->wptr & ring->buf_mask; 4235 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 4236 *wptr_saved = wptr_tmp; 4237 /* assume doorbell always being used by mes mapped queue */ 4238 if (*is_queue_unmap) { 4239 WDOORBELL64(aggregated_db_index, wptr_tmp); 4240 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4241 } else { 4242 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4243 4244 if (*is_queue_unmap) 4245 WDOORBELL64(aggregated_db_index, wptr_tmp); 4246 } 4247 } else { 4248 if (ring->use_doorbell) { 4249 /* XXX check if swapping is necessary on BE */ 4250 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4251 ring->wptr); 4252 WDOORBELL64(ring->doorbell_index, ring->wptr); 4253 } else { 4254 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 4255 lower_32_bits(ring->wptr)); 4256 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 4257 upper_32_bits(ring->wptr)); 4258 } 4259 } 4260 } 4261 4262 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4263 { 4264 /* gfx12 hardware is 32bit rptr */ 4265 return *(uint32_t *)ring->rptr_cpu_addr; 4266 } 4267 4268 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4269 { 4270 u64 wptr; 4271 4272 /* XXX check if swapping is necessary on BE */ 4273 if (ring->use_doorbell) 4274 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4275 else 4276 BUG(); 4277 return wptr; 4278 } 4279 4280 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4281 { 4282 struct amdgpu_device *adev = ring->adev; 4283 uint32_t *wptr_saved; 4284 uint32_t *is_queue_unmap; 4285 uint64_t aggregated_db_index; 4286 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 4287 uint64_t wptr_tmp; 4288 4289 if (ring->is_mes_queue) { 4290 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 4291 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 4292 sizeof(uint32_t)); 4293 aggregated_db_index = 4294 amdgpu_mes_get_aggregated_doorbell_index(adev, 4295 ring->hw_prio); 4296 4297 wptr_tmp = ring->wptr & ring->buf_mask; 4298 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 4299 *wptr_saved = wptr_tmp; 4300 /* assume doorbell always used by mes mapped queue */ 4301 if (*is_queue_unmap) { 4302 WDOORBELL64(aggregated_db_index, wptr_tmp); 4303 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4304 } else { 4305 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4306 4307 if (*is_queue_unmap) 4308 WDOORBELL64(aggregated_db_index, wptr_tmp); 4309 } 4310 } else { 4311 /* XXX check if swapping is necessary on BE */ 4312 if (ring->use_doorbell) { 4313 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4314 ring->wptr); 4315 WDOORBELL64(ring->doorbell_index, ring->wptr); 4316 } else { 4317 BUG(); /* only DOORBELL method supported on gfx12 now */ 4318 } 4319 } 4320 } 4321 4322 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4323 { 4324 struct amdgpu_device *adev = ring->adev; 4325 u32 ref_and_mask, reg_mem_engine; 4326 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 4327 4328 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4329 switch (ring->me) { 4330 case 1: 4331 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4332 break; 4333 case 2: 4334 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4335 break; 4336 default: 4337 return; 4338 } 4339 reg_mem_engine = 0; 4340 } else { 4341 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4342 reg_mem_engine = 1; /* pfp */ 4343 } 4344 4345 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4346 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4347 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4348 ref_and_mask, ref_and_mask, 0x20); 4349 } 4350 4351 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4352 struct amdgpu_job *job, 4353 struct amdgpu_ib *ib, 4354 uint32_t flags) 4355 { 4356 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4357 u32 header, control = 0; 4358 4359 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 4360 4361 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4362 4363 control |= ib->length_dw | (vmid << 24); 4364 4365 if (ring->is_mes_queue) 4366 /* inherit vmid from mqd */ 4367 control |= 0x400000; 4368 4369 amdgpu_ring_write(ring, header); 4370 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4371 amdgpu_ring_write(ring, 4372 #ifdef __BIG_ENDIAN 4373 (2 << 0) | 4374 #endif 4375 lower_32_bits(ib->gpu_addr)); 4376 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4377 amdgpu_ring_write(ring, control); 4378 } 4379 4380 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4381 struct amdgpu_job *job, 4382 struct amdgpu_ib *ib, 4383 uint32_t flags) 4384 { 4385 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4386 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4387 4388 if (ring->is_mes_queue) 4389 /* inherit vmid from mqd */ 4390 control |= 0x40000000; 4391 4392 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4393 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4394 amdgpu_ring_write(ring, 4395 #ifdef __BIG_ENDIAN 4396 (2 << 0) | 4397 #endif 4398 lower_32_bits(ib->gpu_addr)); 4399 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4400 amdgpu_ring_write(ring, control); 4401 } 4402 4403 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4404 u64 seq, unsigned flags) 4405 { 4406 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4407 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4408 4409 /* RELEASE_MEM - flush caches, send int */ 4410 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4411 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4412 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4413 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4414 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4415 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4416 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4417 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4418 4419 /* 4420 * the address should be Qword aligned if 64bit write, Dword 4421 * aligned if only send 32bit data low (discard data high) 4422 */ 4423 if (write64bit) 4424 BUG_ON(addr & 0x7); 4425 else 4426 BUG_ON(addr & 0x3); 4427 amdgpu_ring_write(ring, lower_32_bits(addr)); 4428 amdgpu_ring_write(ring, upper_32_bits(addr)); 4429 amdgpu_ring_write(ring, lower_32_bits(seq)); 4430 amdgpu_ring_write(ring, upper_32_bits(seq)); 4431 amdgpu_ring_write(ring, ring->is_mes_queue ? 4432 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 4433 } 4434 4435 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4436 { 4437 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4438 uint32_t seq = ring->fence_drv.sync_seq; 4439 uint64_t addr = ring->fence_drv.gpu_addr; 4440 4441 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4442 upper_32_bits(addr), seq, 0xffffffff, 4); 4443 } 4444 4445 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 4446 uint16_t pasid, uint32_t flush_type, 4447 bool all_hub, uint8_t dst_sel) 4448 { 4449 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 4450 amdgpu_ring_write(ring, 4451 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 4452 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 4453 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 4454 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 4455 } 4456 4457 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4458 unsigned vmid, uint64_t pd_addr) 4459 { 4460 if (ring->is_mes_queue) 4461 gfx_v12_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 4462 else 4463 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4464 4465 /* compute doesn't have PFP */ 4466 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4467 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4468 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4469 amdgpu_ring_write(ring, 0x0); 4470 } 4471 } 4472 4473 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4474 u64 seq, unsigned int flags) 4475 { 4476 struct amdgpu_device *adev = ring->adev; 4477 4478 /* we only allocate 32bit for each seq wb address */ 4479 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4480 4481 /* write fence seq to the "addr" */ 4482 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4483 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4484 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4485 amdgpu_ring_write(ring, lower_32_bits(addr)); 4486 amdgpu_ring_write(ring, upper_32_bits(addr)); 4487 amdgpu_ring_write(ring, lower_32_bits(seq)); 4488 4489 if (flags & AMDGPU_FENCE_FLAG_INT) { 4490 /* set register to trigger INT */ 4491 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4492 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4493 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4494 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 4495 amdgpu_ring_write(ring, 0); 4496 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4497 } 4498 } 4499 4500 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 4501 uint32_t flags) 4502 { 4503 uint32_t dw2 = 0; 4504 4505 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4506 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4507 /* set load_global_config & load_global_uconfig */ 4508 dw2 |= 0x8001; 4509 /* set load_cs_sh_regs */ 4510 dw2 |= 0x01000000; 4511 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4512 dw2 |= 0x10002; 4513 } 4514 4515 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4516 amdgpu_ring_write(ring, dw2); 4517 amdgpu_ring_write(ring, 0); 4518 } 4519 4520 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 4521 uint64_t addr) 4522 { 4523 unsigned ret; 4524 4525 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4526 amdgpu_ring_write(ring, lower_32_bits(addr)); 4527 amdgpu_ring_write(ring, upper_32_bits(addr)); 4528 /* discard following DWs if *cond_exec_gpu_addr==0 */ 4529 amdgpu_ring_write(ring, 0); 4530 ret = ring->wptr & ring->buf_mask; 4531 /* patch dummy value later */ 4532 amdgpu_ring_write(ring, 0); 4533 4534 return ret; 4535 } 4536 4537 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring) 4538 { 4539 int i, r = 0; 4540 struct amdgpu_device *adev = ring->adev; 4541 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 4542 struct amdgpu_ring *kiq_ring = &kiq->ring; 4543 unsigned long flags; 4544 4545 if (adev->enable_mes) 4546 return -EINVAL; 4547 4548 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4549 return -EINVAL; 4550 4551 spin_lock_irqsave(&kiq->ring_lock, flags); 4552 4553 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 4554 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4555 return -ENOMEM; 4556 } 4557 4558 /* assert preemption condition */ 4559 amdgpu_ring_set_preempt_cond_exec(ring, false); 4560 4561 /* assert IB preemption, emit the trailing fence */ 4562 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4563 ring->trail_fence_gpu_addr, 4564 ++ring->trail_seq); 4565 amdgpu_ring_commit(kiq_ring); 4566 4567 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4568 4569 /* poll the trailing fence */ 4570 for (i = 0; i < adev->usec_timeout; i++) { 4571 if (ring->trail_seq == 4572 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4573 break; 4574 udelay(1); 4575 } 4576 4577 if (i >= adev->usec_timeout) { 4578 r = -EINVAL; 4579 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4580 } 4581 4582 /* deassert preemption condition */ 4583 amdgpu_ring_set_preempt_cond_exec(ring, true); 4584 return r; 4585 } 4586 4587 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, 4588 bool start, 4589 bool secure) 4590 { 4591 uint32_t v = secure ? FRAME_TMZ : 0; 4592 4593 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4594 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 4595 } 4596 4597 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 4598 uint32_t reg_val_offs) 4599 { 4600 struct amdgpu_device *adev = ring->adev; 4601 4602 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4603 amdgpu_ring_write(ring, 0 | /* src: register*/ 4604 (5 << 8) | /* dst: memory */ 4605 (1 << 20)); /* write confirm */ 4606 amdgpu_ring_write(ring, reg); 4607 amdgpu_ring_write(ring, 0); 4608 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4609 reg_val_offs * 4)); 4610 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4611 reg_val_offs * 4)); 4612 } 4613 4614 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, 4615 uint32_t reg, 4616 uint32_t val) 4617 { 4618 uint32_t cmd = 0; 4619 4620 switch (ring->funcs->type) { 4621 case AMDGPU_RING_TYPE_GFX: 4622 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4623 break; 4624 case AMDGPU_RING_TYPE_KIQ: 4625 cmd = (1 << 16); /* no inc addr */ 4626 break; 4627 default: 4628 cmd = WR_CONFIRM; 4629 break; 4630 } 4631 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4632 amdgpu_ring_write(ring, cmd); 4633 amdgpu_ring_write(ring, reg); 4634 amdgpu_ring_write(ring, 0); 4635 amdgpu_ring_write(ring, val); 4636 } 4637 4638 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4639 uint32_t val, uint32_t mask) 4640 { 4641 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4642 } 4643 4644 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4645 uint32_t reg0, uint32_t reg1, 4646 uint32_t ref, uint32_t mask) 4647 { 4648 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4649 4650 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4651 ref, mask, 0x20); 4652 } 4653 4654 static void gfx_v12_0_ring_soft_recovery(struct amdgpu_ring *ring, 4655 unsigned vmid) 4656 { 4657 struct amdgpu_device *adev = ring->adev; 4658 uint32_t value = 0; 4659 4660 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 4661 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 4662 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 4663 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 4664 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4665 WREG32_SOC15(GC, 0, regSQ_CMD, value); 4666 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4667 } 4668 4669 static void 4670 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4671 uint32_t me, uint32_t pipe, 4672 enum amdgpu_interrupt_state state) 4673 { 4674 uint32_t cp_int_cntl, cp_int_cntl_reg; 4675 4676 if (!me) { 4677 switch (pipe) { 4678 case 0: 4679 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 4680 break; 4681 default: 4682 DRM_DEBUG("invalid pipe %d\n", pipe); 4683 return; 4684 } 4685 } else { 4686 DRM_DEBUG("invalid me %d\n", me); 4687 return; 4688 } 4689 4690 switch (state) { 4691 case AMDGPU_IRQ_STATE_DISABLE: 4692 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4693 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4694 TIME_STAMP_INT_ENABLE, 0); 4695 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4696 GENERIC0_INT_ENABLE, 0); 4697 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4698 break; 4699 case AMDGPU_IRQ_STATE_ENABLE: 4700 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4701 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4702 TIME_STAMP_INT_ENABLE, 1); 4703 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4704 GENERIC0_INT_ENABLE, 1); 4705 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4706 break; 4707 default: 4708 break; 4709 } 4710 } 4711 4712 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4713 int me, int pipe, 4714 enum amdgpu_interrupt_state state) 4715 { 4716 u32 mec_int_cntl, mec_int_cntl_reg; 4717 4718 /* 4719 * amdgpu controls only the first MEC. That's why this function only 4720 * handles the setting of interrupts for this specific MEC. All other 4721 * pipes' interrupts are set by amdkfd. 4722 */ 4723 4724 if (me == 1) { 4725 switch (pipe) { 4726 case 0: 4727 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 4728 break; 4729 case 1: 4730 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 4731 break; 4732 default: 4733 DRM_DEBUG("invalid pipe %d\n", pipe); 4734 return; 4735 } 4736 } else { 4737 DRM_DEBUG("invalid me %d\n", me); 4738 return; 4739 } 4740 4741 switch (state) { 4742 case AMDGPU_IRQ_STATE_DISABLE: 4743 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4744 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4745 TIME_STAMP_INT_ENABLE, 0); 4746 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4747 GENERIC0_INT_ENABLE, 0); 4748 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4749 break; 4750 case AMDGPU_IRQ_STATE_ENABLE: 4751 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4752 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4753 TIME_STAMP_INT_ENABLE, 1); 4754 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4755 GENERIC0_INT_ENABLE, 1); 4756 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4757 break; 4758 default: 4759 break; 4760 } 4761 } 4762 4763 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4764 struct amdgpu_irq_src *src, 4765 unsigned type, 4766 enum amdgpu_interrupt_state state) 4767 { 4768 switch (type) { 4769 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4770 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4771 break; 4772 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4773 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4774 break; 4775 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4776 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4777 break; 4778 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4779 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4780 break; 4781 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4782 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4783 break; 4784 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4785 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4786 break; 4787 default: 4788 break; 4789 } 4790 return 0; 4791 } 4792 4793 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, 4794 struct amdgpu_irq_src *source, 4795 struct amdgpu_iv_entry *entry) 4796 { 4797 int i; 4798 u8 me_id, pipe_id, queue_id; 4799 struct amdgpu_ring *ring; 4800 uint32_t mes_queue_id = entry->src_data[0]; 4801 4802 DRM_DEBUG("IH: CP EOP\n"); 4803 4804 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 4805 struct amdgpu_mes_queue *queue; 4806 4807 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 4808 4809 spin_lock(&adev->mes.queue_id_lock); 4810 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 4811 if (queue) { 4812 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 4813 amdgpu_fence_process(queue->ring); 4814 } 4815 spin_unlock(&adev->mes.queue_id_lock); 4816 } else { 4817 me_id = (entry->ring_id & 0x0c) >> 2; 4818 pipe_id = (entry->ring_id & 0x03) >> 0; 4819 queue_id = (entry->ring_id & 0x70) >> 4; 4820 4821 switch (me_id) { 4822 case 0: 4823 if (pipe_id == 0) 4824 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4825 else 4826 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4827 break; 4828 case 1: 4829 case 2: 4830 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4831 ring = &adev->gfx.compute_ring[i]; 4832 /* Per-queue interrupt is supported for MEC starting from VI. 4833 * The interrupt can only be enabled/disabled per pipe instead 4834 * of per queue. 4835 */ 4836 if ((ring->me == me_id) && 4837 (ring->pipe == pipe_id) && 4838 (ring->queue == queue_id)) 4839 amdgpu_fence_process(ring); 4840 } 4841 break; 4842 } 4843 } 4844 4845 return 0; 4846 } 4847 4848 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4849 struct amdgpu_irq_src *source, 4850 unsigned int type, 4851 enum amdgpu_interrupt_state state) 4852 { 4853 u32 cp_int_cntl_reg, cp_int_cntl; 4854 int i, j; 4855 4856 switch (state) { 4857 case AMDGPU_IRQ_STATE_DISABLE: 4858 case AMDGPU_IRQ_STATE_ENABLE: 4859 for (i = 0; i < adev->gfx.me.num_me; i++) { 4860 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4861 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4862 4863 if (cp_int_cntl_reg) { 4864 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4865 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4866 PRIV_REG_INT_ENABLE, 4867 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4868 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4869 } 4870 } 4871 } 4872 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4873 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4874 /* MECs start at 1 */ 4875 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4876 4877 if (cp_int_cntl_reg) { 4878 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4879 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4880 PRIV_REG_INT_ENABLE, 4881 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4882 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4883 } 4884 } 4885 } 4886 break; 4887 default: 4888 break; 4889 } 4890 4891 return 0; 4892 } 4893 4894 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev, 4895 struct amdgpu_irq_src *source, 4896 unsigned type, 4897 enum amdgpu_interrupt_state state) 4898 { 4899 u32 cp_int_cntl_reg, cp_int_cntl; 4900 int i, j; 4901 4902 switch (state) { 4903 case AMDGPU_IRQ_STATE_DISABLE: 4904 case AMDGPU_IRQ_STATE_ENABLE: 4905 for (i = 0; i < adev->gfx.me.num_me; i++) { 4906 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4907 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4908 4909 if (cp_int_cntl_reg) { 4910 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4911 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4912 OPCODE_ERROR_INT_ENABLE, 4913 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4914 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4915 } 4916 } 4917 } 4918 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4919 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4920 /* MECs start at 1 */ 4921 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4922 4923 if (cp_int_cntl_reg) { 4924 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4925 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4926 OPCODE_ERROR_INT_ENABLE, 4927 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4928 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4929 } 4930 } 4931 } 4932 break; 4933 default: 4934 break; 4935 } 4936 return 0; 4937 } 4938 4939 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4940 struct amdgpu_irq_src *source, 4941 unsigned int type, 4942 enum amdgpu_interrupt_state state) 4943 { 4944 u32 cp_int_cntl_reg, cp_int_cntl; 4945 int i, j; 4946 4947 switch (state) { 4948 case AMDGPU_IRQ_STATE_DISABLE: 4949 case AMDGPU_IRQ_STATE_ENABLE: 4950 for (i = 0; i < adev->gfx.me.num_me; i++) { 4951 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4952 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4953 4954 if (cp_int_cntl_reg) { 4955 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4956 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4957 PRIV_INSTR_INT_ENABLE, 4958 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4959 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4960 } 4961 } 4962 } 4963 break; 4964 default: 4965 break; 4966 } 4967 4968 return 0; 4969 } 4970 4971 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 4972 struct amdgpu_iv_entry *entry) 4973 { 4974 u8 me_id, pipe_id, queue_id; 4975 struct amdgpu_ring *ring; 4976 int i; 4977 4978 me_id = (entry->ring_id & 0x0c) >> 2; 4979 pipe_id = (entry->ring_id & 0x03) >> 0; 4980 queue_id = (entry->ring_id & 0x70) >> 4; 4981 4982 switch (me_id) { 4983 case 0: 4984 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4985 ring = &adev->gfx.gfx_ring[i]; 4986 if (ring->me == me_id && ring->pipe == pipe_id && 4987 ring->queue == queue_id) 4988 drm_sched_fault(&ring->sched); 4989 } 4990 break; 4991 case 1: 4992 case 2: 4993 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4994 ring = &adev->gfx.compute_ring[i]; 4995 if (ring->me == me_id && ring->pipe == pipe_id && 4996 ring->queue == queue_id) 4997 drm_sched_fault(&ring->sched); 4998 } 4999 break; 5000 default: 5001 BUG(); 5002 break; 5003 } 5004 } 5005 5006 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, 5007 struct amdgpu_irq_src *source, 5008 struct amdgpu_iv_entry *entry) 5009 { 5010 DRM_ERROR("Illegal register access in command stream\n"); 5011 gfx_v12_0_handle_priv_fault(adev, entry); 5012 return 0; 5013 } 5014 5015 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev, 5016 struct amdgpu_irq_src *source, 5017 struct amdgpu_iv_entry *entry) 5018 { 5019 DRM_ERROR("Illegal opcode in command stream \n"); 5020 gfx_v12_0_handle_priv_fault(adev, entry); 5021 return 0; 5022 } 5023 5024 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev, 5025 struct amdgpu_irq_src *source, 5026 struct amdgpu_iv_entry *entry) 5027 { 5028 DRM_ERROR("Illegal instruction in command stream\n"); 5029 gfx_v12_0_handle_priv_fault(adev, entry); 5030 return 0; 5031 } 5032 5033 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring) 5034 { 5035 const unsigned int gcr_cntl = 5036 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 5037 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 5038 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 5039 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 5040 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 5041 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 5042 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 5043 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 5044 5045 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 5046 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 5047 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 5048 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 5049 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 5050 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 5051 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 5052 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 5053 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 5054 } 5055 5056 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 5057 { 5058 /* Header itself is a NOP packet */ 5059 if (num_nop == 1) { 5060 amdgpu_ring_write(ring, ring->funcs->nop); 5061 return; 5062 } 5063 5064 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 5065 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 5066 5067 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 5068 amdgpu_ring_insert_nop(ring, num_nop - 1); 5069 } 5070 5071 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 5072 { 5073 /* Emit the cleaner shader */ 5074 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 5075 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 5076 } 5077 5078 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 5079 { 5080 struct amdgpu_device *adev = ip_block->adev; 5081 uint32_t i, j, k, reg, index = 0; 5082 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5083 5084 if (!adev->gfx.ip_dump_core) 5085 return; 5086 5087 for (i = 0; i < reg_count; i++) 5088 drm_printf(p, "%-50s \t 0x%08x\n", 5089 gc_reg_list_12_0[i].reg_name, 5090 adev->gfx.ip_dump_core[i]); 5091 5092 /* print compute queue registers for all instances */ 5093 if (!adev->gfx.ip_dump_compute_queues) 5094 return; 5095 5096 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5097 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 5098 adev->gfx.mec.num_mec, 5099 adev->gfx.mec.num_pipe_per_mec, 5100 adev->gfx.mec.num_queue_per_pipe); 5101 5102 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5103 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5104 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5105 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 5106 for (reg = 0; reg < reg_count; reg++) { 5107 drm_printf(p, "%-50s \t 0x%08x\n", 5108 gc_cp_reg_list_12[reg].reg_name, 5109 adev->gfx.ip_dump_compute_queues[index + reg]); 5110 } 5111 index += reg_count; 5112 } 5113 } 5114 } 5115 5116 /* print gfx queue registers for all instances */ 5117 if (!adev->gfx.ip_dump_gfx_queues) 5118 return; 5119 5120 index = 0; 5121 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5122 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 5123 adev->gfx.me.num_me, 5124 adev->gfx.me.num_pipe_per_me, 5125 adev->gfx.me.num_queue_per_pipe); 5126 5127 for (i = 0; i < adev->gfx.me.num_me; i++) { 5128 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5129 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5130 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 5131 for (reg = 0; reg < reg_count; reg++) { 5132 drm_printf(p, "%-50s \t 0x%08x\n", 5133 gc_gfx_queue_reg_list_12[reg].reg_name, 5134 adev->gfx.ip_dump_gfx_queues[index + reg]); 5135 } 5136 index += reg_count; 5137 } 5138 } 5139 } 5140 } 5141 5142 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block) 5143 { 5144 struct amdgpu_device *adev = ip_block->adev; 5145 uint32_t i, j, k, reg, index = 0; 5146 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5147 5148 if (!adev->gfx.ip_dump_core) 5149 return; 5150 5151 amdgpu_gfx_off_ctrl(adev, false); 5152 for (i = 0; i < reg_count; i++) 5153 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i])); 5154 amdgpu_gfx_off_ctrl(adev, true); 5155 5156 /* dump compute queue registers for all instances */ 5157 if (!adev->gfx.ip_dump_compute_queues) 5158 return; 5159 5160 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5161 amdgpu_gfx_off_ctrl(adev, false); 5162 mutex_lock(&adev->srbm_mutex); 5163 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5164 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5165 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5166 /* ME0 is for GFX so start from 1 for CP */ 5167 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 5168 for (reg = 0; reg < reg_count; reg++) { 5169 adev->gfx.ip_dump_compute_queues[index + reg] = 5170 RREG32(SOC15_REG_ENTRY_OFFSET( 5171 gc_cp_reg_list_12[reg])); 5172 } 5173 index += reg_count; 5174 } 5175 } 5176 } 5177 soc24_grbm_select(adev, 0, 0, 0, 0); 5178 mutex_unlock(&adev->srbm_mutex); 5179 amdgpu_gfx_off_ctrl(adev, true); 5180 5181 /* dump gfx queue registers for all instances */ 5182 if (!adev->gfx.ip_dump_gfx_queues) 5183 return; 5184 5185 index = 0; 5186 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5187 amdgpu_gfx_off_ctrl(adev, false); 5188 mutex_lock(&adev->srbm_mutex); 5189 for (i = 0; i < adev->gfx.me.num_me; i++) { 5190 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5191 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5192 soc24_grbm_select(adev, i, j, k, 0); 5193 5194 for (reg = 0; reg < reg_count; reg++) { 5195 adev->gfx.ip_dump_gfx_queues[index + reg] = 5196 RREG32(SOC15_REG_ENTRY_OFFSET( 5197 gc_gfx_queue_reg_list_12[reg])); 5198 } 5199 index += reg_count; 5200 } 5201 } 5202 } 5203 soc24_grbm_select(adev, 0, 0, 0, 0); 5204 mutex_unlock(&adev->srbm_mutex); 5205 amdgpu_gfx_off_ctrl(adev, true); 5206 } 5207 5208 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) 5209 { 5210 struct amdgpu_device *adev = ring->adev; 5211 int r; 5212 5213 if (amdgpu_sriov_vf(adev)) 5214 return -EINVAL; 5215 5216 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); 5217 if (r) { 5218 dev_err(adev->dev, "reset via MES failed %d\n", r); 5219 return r; 5220 } 5221 5222 r = amdgpu_bo_reserve(ring->mqd_obj, false); 5223 if (unlikely(r != 0)) { 5224 dev_err(adev->dev, "fail to resv mqd_obj\n"); 5225 return r; 5226 } 5227 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 5228 if (!r) { 5229 r = gfx_v12_0_kgq_init_queue(ring, true); 5230 amdgpu_bo_kunmap(ring->mqd_obj); 5231 ring->mqd_ptr = NULL; 5232 } 5233 amdgpu_bo_unreserve(ring->mqd_obj); 5234 if (r) { 5235 DRM_ERROR("fail to unresv mqd_obj\n"); 5236 return r; 5237 } 5238 5239 r = amdgpu_mes_map_legacy_queue(adev, ring); 5240 if (r) { 5241 dev_err(adev->dev, "failed to remap kgq\n"); 5242 return r; 5243 } 5244 5245 return amdgpu_ring_test_ring(ring); 5246 } 5247 5248 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) 5249 { 5250 struct amdgpu_device *adev = ring->adev; 5251 int r; 5252 5253 if (amdgpu_sriov_vf(adev)) 5254 return -EINVAL; 5255 5256 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); 5257 if (r) { 5258 dev_err(adev->dev, "reset via MMIO failed %d\n", r); 5259 return r; 5260 } 5261 5262 r = amdgpu_bo_reserve(ring->mqd_obj, false); 5263 if (unlikely(r != 0)) { 5264 DRM_ERROR("fail to resv mqd_obj\n"); 5265 return r; 5266 } 5267 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 5268 if (!r) { 5269 r = gfx_v12_0_kcq_init_queue(ring, true); 5270 amdgpu_bo_kunmap(ring->mqd_obj); 5271 ring->mqd_ptr = NULL; 5272 } 5273 amdgpu_bo_unreserve(ring->mqd_obj); 5274 if (r) { 5275 DRM_ERROR("fail to unresv mqd_obj\n"); 5276 return r; 5277 } 5278 r = amdgpu_mes_map_legacy_queue(adev, ring); 5279 if (r) { 5280 dev_err(adev->dev, "failed to remap kcq\n"); 5281 return r; 5282 } 5283 5284 return amdgpu_ring_test_ring(ring); 5285 } 5286 5287 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring) 5288 { 5289 amdgpu_gfx_profile_ring_begin_use(ring); 5290 5291 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 5292 } 5293 5294 static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring) 5295 { 5296 amdgpu_gfx_profile_ring_end_use(ring); 5297 5298 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 5299 } 5300 5301 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { 5302 .name = "gfx_v12_0", 5303 .early_init = gfx_v12_0_early_init, 5304 .late_init = gfx_v12_0_late_init, 5305 .sw_init = gfx_v12_0_sw_init, 5306 .sw_fini = gfx_v12_0_sw_fini, 5307 .hw_init = gfx_v12_0_hw_init, 5308 .hw_fini = gfx_v12_0_hw_fini, 5309 .suspend = gfx_v12_0_suspend, 5310 .resume = gfx_v12_0_resume, 5311 .is_idle = gfx_v12_0_is_idle, 5312 .wait_for_idle = gfx_v12_0_wait_for_idle, 5313 .set_clockgating_state = gfx_v12_0_set_clockgating_state, 5314 .set_powergating_state = gfx_v12_0_set_powergating_state, 5315 .get_clockgating_state = gfx_v12_0_get_clockgating_state, 5316 .dump_ip_state = gfx_v12_ip_dump, 5317 .print_ip_state = gfx_v12_ip_print, 5318 }; 5319 5320 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { 5321 .type = AMDGPU_RING_TYPE_GFX, 5322 .align_mask = 0xff, 5323 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5324 .support_64bit_ptrs = true, 5325 .secure_submission_supported = true, 5326 .get_rptr = gfx_v12_0_ring_get_rptr_gfx, 5327 .get_wptr = gfx_v12_0_ring_get_wptr_gfx, 5328 .set_wptr = gfx_v12_0_ring_set_wptr_gfx, 5329 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5330 5 + /* COND_EXEC */ 5331 7 + /* PIPELINE_SYNC */ 5332 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5333 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5334 2 + /* VM_FLUSH */ 5335 8 + /* FENCE for VM_FLUSH */ 5336 5 + /* COND_EXEC */ 5337 7 + /* HDP_flush */ 5338 4 + /* VGT_flush */ 5339 31 + /* DE_META */ 5340 3 + /* CNTX_CTRL */ 5341 5 + /* HDP_INVL */ 5342 8 + 8 + /* FENCE x2 */ 5343 8 + /* gfx_v12_0_emit_mem_sync */ 5344 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5345 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */ 5346 .emit_ib = gfx_v12_0_ring_emit_ib_gfx, 5347 .emit_fence = gfx_v12_0_ring_emit_fence, 5348 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5349 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5350 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5351 .test_ring = gfx_v12_0_ring_test_ring, 5352 .test_ib = gfx_v12_0_ring_test_ib, 5353 .insert_nop = gfx_v12_ring_insert_nop, 5354 .pad_ib = amdgpu_ring_generic_pad_ib, 5355 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, 5356 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, 5357 .preempt_ib = gfx_v12_0_ring_preempt_ib, 5358 .emit_frame_cntl = gfx_v12_0_ring_emit_frame_cntl, 5359 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5360 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5361 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5362 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5363 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5364 .reset = gfx_v12_0_reset_kgq, 5365 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5366 .begin_use = gfx_v12_0_ring_begin_use, 5367 .end_use = gfx_v12_0_ring_end_use, 5368 }; 5369 5370 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { 5371 .type = AMDGPU_RING_TYPE_COMPUTE, 5372 .align_mask = 0xff, 5373 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5374 .support_64bit_ptrs = true, 5375 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5376 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5377 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5378 .emit_frame_size = 5379 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5380 5 + /* hdp invalidate */ 5381 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5382 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5383 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5384 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5385 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */ 5386 8 + /* gfx_v12_0_emit_mem_sync */ 5387 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5388 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5389 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5390 .emit_fence = gfx_v12_0_ring_emit_fence, 5391 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5392 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5393 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5394 .test_ring = gfx_v12_0_ring_test_ring, 5395 .test_ib = gfx_v12_0_ring_test_ib, 5396 .insert_nop = gfx_v12_ring_insert_nop, 5397 .pad_ib = amdgpu_ring_generic_pad_ib, 5398 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5399 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5400 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5401 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5402 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5403 .reset = gfx_v12_0_reset_kcq, 5404 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5405 .begin_use = gfx_v12_0_ring_begin_use, 5406 .end_use = gfx_v12_0_ring_end_use, 5407 }; 5408 5409 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { 5410 .type = AMDGPU_RING_TYPE_KIQ, 5411 .align_mask = 0xff, 5412 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5413 .support_64bit_ptrs = true, 5414 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5415 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5416 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5417 .emit_frame_size = 5418 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5419 5 + /*hdp invalidate */ 5420 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5421 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5422 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5423 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5424 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5425 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5426 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5427 .emit_fence = gfx_v12_0_ring_emit_fence_kiq, 5428 .test_ring = gfx_v12_0_ring_test_ring, 5429 .test_ib = gfx_v12_0_ring_test_ib, 5430 .insert_nop = amdgpu_ring_insert_nop, 5431 .pad_ib = amdgpu_ring_generic_pad_ib, 5432 .emit_rreg = gfx_v12_0_ring_emit_rreg, 5433 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5434 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5435 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5436 }; 5437 5438 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev) 5439 { 5440 int i; 5441 5442 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq; 5443 5444 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5445 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx; 5446 5447 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5448 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute; 5449 } 5450 5451 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = { 5452 .set = gfx_v12_0_set_eop_interrupt_state, 5453 .process = gfx_v12_0_eop_irq, 5454 }; 5455 5456 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = { 5457 .set = gfx_v12_0_set_priv_reg_fault_state, 5458 .process = gfx_v12_0_priv_reg_irq, 5459 }; 5460 5461 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = { 5462 .set = gfx_v12_0_set_bad_op_fault_state, 5463 .process = gfx_v12_0_bad_op_irq, 5464 }; 5465 5466 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = { 5467 .set = gfx_v12_0_set_priv_inst_fault_state, 5468 .process = gfx_v12_0_priv_inst_irq, 5469 }; 5470 5471 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev) 5472 { 5473 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5474 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs; 5475 5476 adev->gfx.priv_reg_irq.num_types = 1; 5477 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs; 5478 5479 adev->gfx.bad_op_irq.num_types = 1; 5480 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs; 5481 5482 adev->gfx.priv_inst_irq.num_types = 1; 5483 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs; 5484 } 5485 5486 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev) 5487 { 5488 if (adev->flags & AMD_IS_APU) 5489 adev->gfx.imu.mode = MISSION_MODE; 5490 else 5491 adev->gfx.imu.mode = DEBUG_MODE; 5492 5493 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 5494 } 5495 5496 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev) 5497 { 5498 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs; 5499 } 5500 5501 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev) 5502 { 5503 /* set gfx eng mqd */ 5504 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 5505 sizeof(struct v12_gfx_mqd); 5506 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 5507 gfx_v12_0_gfx_mqd_init; 5508 /* set compute eng mqd */ 5509 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 5510 sizeof(struct v12_compute_mqd); 5511 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 5512 gfx_v12_0_compute_mqd_init; 5513 } 5514 5515 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5516 u32 bitmap) 5517 { 5518 u32 data; 5519 5520 if (!bitmap) 5521 return; 5522 5523 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5524 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5525 5526 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 5527 } 5528 5529 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5530 { 5531 u32 data, wgp_bitmask; 5532 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 5533 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 5534 5535 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5536 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5537 5538 wgp_bitmask = 5539 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5540 5541 return (~data) & wgp_bitmask; 5542 } 5543 5544 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5545 { 5546 u32 wgp_idx, wgp_active_bitmap; 5547 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5548 5549 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev); 5550 cu_active_bitmap = 0; 5551 5552 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5553 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5554 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5555 if (wgp_active_bitmap & (1 << wgp_idx)) 5556 cu_active_bitmap |= cu_bitmap_per_wgp; 5557 } 5558 5559 return cu_active_bitmap; 5560 } 5561 5562 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 5563 struct amdgpu_cu_info *cu_info) 5564 { 5565 int i, j, k, counter, active_cu_number = 0; 5566 u32 mask, bitmap; 5567 unsigned disable_masks[8 * 2]; 5568 5569 if (!adev || !cu_info) 5570 return -EINVAL; 5571 5572 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 5573 5574 mutex_lock(&adev->grbm_idx_mutex); 5575 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5576 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5577 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5578 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 5579 continue; 5580 mask = 1; 5581 counter = 0; 5582 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5583 if (i < 8 && j < 2) 5584 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh( 5585 adev, disable_masks[i * 2 + j]); 5586 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev); 5587 5588 /** 5589 * GFX12 could support more than 4 SEs, while the bitmap 5590 * in cu_info struct is 4x4 and ioctl interface struct 5591 * drm_amdgpu_info_device should keep stable. 5592 * So we use last two columns of bitmap to store cu mask for 5593 * SEs 4 to 7, the layout of the bitmap is as below: 5594 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 5595 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 5596 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 5597 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 5598 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 5599 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 5600 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 5601 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 5602 */ 5603 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 5604 5605 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5606 if (bitmap & mask) 5607 counter++; 5608 5609 mask <<= 1; 5610 } 5611 active_cu_number += counter; 5612 } 5613 } 5614 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5615 mutex_unlock(&adev->grbm_idx_mutex); 5616 5617 cu_info->number = active_cu_number; 5618 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5619 5620 return 0; 5621 } 5622 5623 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = { 5624 .type = AMD_IP_BLOCK_TYPE_GFX, 5625 .major = 12, 5626 .minor = 0, 5627 .rev = 0, 5628 .funcs = &gfx_v12_0_ip_funcs, 5629 }; 5630