1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #ifndef __MSM_DRV_H__ 9 #define __MSM_DRV_H__ 10 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/cpufreq.h> 14 #include <linux/devfreq.h> 15 #include <linux/module.h> 16 #include <linux/component.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/slab.h> 21 #include <linux/list.h> 22 #include <linux/iommu.h> 23 #include <linux/types.h> 24 #include <linux/of_graph.h> 25 #include <linux/of_device.h> 26 #include <linux/sizes.h> 27 #include <linux/kthread.h> 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/display/drm_dsc.h> 33 #include <drm/msm_drm.h> 34 #include <drm/drm_gem.h> 35 36 #ifdef CONFIG_FAULT_INJECTION 37 extern struct fault_attr fail_gem_alloc; 38 extern struct fault_attr fail_gem_iova; 39 #else 40 # define should_fail(attr, size) 0 41 #endif 42 43 struct msm_kms; 44 struct msm_gpu; 45 struct msm_mmu; 46 struct msm_mdss; 47 struct msm_rd_state; 48 struct msm_perf_state; 49 struct msm_gem_submit; 50 struct msm_fence_context; 51 struct msm_gem_address_space; 52 struct msm_gem_vma; 53 struct msm_disp_state; 54 55 #define MAX_CRTCS 8 56 #define MAX_BRIDGES 8 57 58 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 59 60 enum msm_dp_controller { 61 MSM_DP_CONTROLLER_0, 62 MSM_DP_CONTROLLER_1, 63 MSM_DP_CONTROLLER_2, 64 MSM_DP_CONTROLLER_3, 65 MSM_DP_CONTROLLER_COUNT, 66 }; 67 68 enum msm_dsi_controller { 69 MSM_DSI_CONTROLLER_0, 70 MSM_DSI_CONTROLLER_1, 71 MSM_DSI_CONTROLLER_COUNT, 72 }; 73 74 #define MSM_GPU_MAX_RINGS 4 75 #define MAX_H_TILES_PER_DISPLAY 2 76 77 /** 78 * enum msm_event_wait - type of HW events to wait for 79 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW 80 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel 81 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters) 82 */ 83 enum msm_event_wait { 84 MSM_ENC_COMMIT_DONE = 0, 85 MSM_ENC_TX_COMPLETE, 86 MSM_ENC_VBLANK, 87 }; 88 89 /** 90 * struct msm_display_topology - defines a display topology pipeline 91 * @num_lm: number of layer mixers used 92 * @num_intf: number of interfaces the panel is mounted on 93 * @num_dspp: number of dspp blocks used 94 * @num_dsc: number of Display Stream Compression (DSC) blocks used 95 */ 96 struct msm_display_topology { 97 u32 num_lm; 98 u32 num_intf; 99 u32 num_dspp; 100 u32 num_dsc; 101 }; 102 103 /* Commit/Event thread specific structure */ 104 struct msm_drm_thread { 105 struct drm_device *dev; 106 struct kthread_worker *worker; 107 }; 108 109 struct msm_drm_private { 110 111 struct drm_device *dev; 112 113 struct msm_kms *kms; 114 int (*kms_init)(struct drm_device *dev); 115 116 /* subordinate devices, if present: */ 117 struct platform_device *gpu_pdev; 118 119 /* possibly this should be in the kms component, but it is 120 * shared by both mdp4 and mdp5.. 121 */ 122 struct hdmi *hdmi; 123 124 /* DSI is shared by mdp4 and mdp5 */ 125 struct msm_dsi *dsi[MSM_DSI_CONTROLLER_COUNT]; 126 127 struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT]; 128 129 /* when we have more than one 'msm_gpu' these need to be an array: */ 130 struct msm_gpu *gpu; 131 132 /* gpu is only set on open(), but we need this info earlier */ 133 bool is_a2xx; 134 bool has_cached_coherent; 135 136 struct msm_rd_state *rd; /* debugfs to dump all submits */ 137 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 138 struct msm_perf_state *perf; 139 140 /** 141 * List of all GEM objects (mainly for debugfs, protected by obj_lock 142 * (acquire before per GEM object lock) 143 */ 144 struct list_head objects; 145 struct mutex obj_lock; 146 147 /** 148 * lru: 149 * 150 * The various LRU's that a GEM object is in at various stages of 151 * it's lifetime. Objects start out in the unbacked LRU. When 152 * pinned (for scannout or permanently mapped GPU buffers, like 153 * ringbuffer, memptr, fw, etc) it moves to the pinned LRU. When 154 * unpinned, it moves into willneed or dontneed LRU depending on 155 * madvise state. When backing pages are evicted (willneed) or 156 * purged (dontneed) it moves back into the unbacked LRU. 157 * 158 * The dontneed LRU is considered by the shrinker for objects 159 * that are candidate for purging, and the willneed LRU is 160 * considered for objects that could be evicted. 161 */ 162 struct { 163 /** 164 * unbacked: 165 * 166 * The LRU for GEM objects without backing pages allocated. 167 * This mostly exists so that objects are always is one 168 * LRU. 169 */ 170 struct drm_gem_lru unbacked; 171 172 /** 173 * pinned: 174 * 175 * The LRU for pinned GEM objects 176 */ 177 struct drm_gem_lru pinned; 178 179 /** 180 * willneed: 181 * 182 * The LRU for unpinned GEM objects which are in madvise 183 * WILLNEED state (ie. can be evicted) 184 */ 185 struct drm_gem_lru willneed; 186 187 /** 188 * dontneed: 189 * 190 * The LRU for unpinned GEM objects which are in madvise 191 * DONTNEED state (ie. can be purged) 192 */ 193 struct drm_gem_lru dontneed; 194 195 /** 196 * lock: 197 * 198 * Protects manipulation of all of the LRUs. 199 */ 200 struct mutex lock; 201 } lru; 202 203 struct workqueue_struct *wq; 204 205 unsigned int num_crtcs; 206 207 struct msm_drm_thread event_thread[MAX_CRTCS]; 208 209 /* VRAM carveout, used when no IOMMU: */ 210 struct { 211 unsigned long size; 212 dma_addr_t paddr; 213 /* NOTE: mm managed at the page level, size is in # of pages 214 * and position mm_node->start is in # of pages: 215 */ 216 struct drm_mm mm; 217 spinlock_t lock; /* Protects drm_mm node allocation/removal */ 218 } vram; 219 220 struct notifier_block vmap_notifier; 221 struct shrinker *shrinker; 222 223 struct drm_atomic_state *pm_state; 224 225 /** 226 * hangcheck_period: For hang detection, in ms 227 * 228 * Note that in practice, a submit/job will get at least two hangcheck 229 * periods, due to checking for progress being implemented as simply 230 * "have the CP position registers changed since last time?" 231 */ 232 unsigned int hangcheck_period; 233 234 /** gpu_devfreq_config: Devfreq tuning config for the GPU. */ 235 struct devfreq_simple_ondemand_data gpu_devfreq_config; 236 237 /** 238 * gpu_clamp_to_idle: Enable clamping to idle freq when inactive 239 */ 240 bool gpu_clamp_to_idle; 241 242 /** 243 * disable_err_irq: 244 * 245 * Disable handling of GPU hw error interrupts, to force fallback to 246 * sw hangcheck timer. Written (via debugfs) by igt tests to test 247 * the sw hangcheck mechanism. 248 */ 249 bool disable_err_irq; 250 }; 251 252 struct msm_format { 253 uint32_t pixel_format; 254 }; 255 256 struct msm_pending_timer; 257 258 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer, 259 struct msm_kms *kms, int crtc_idx); 260 void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer); 261 void msm_atomic_commit_tail(struct drm_atomic_state *state); 262 int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); 263 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); 264 void msm_atomic_state_clear(struct drm_atomic_state *state); 265 void msm_atomic_state_free(struct drm_atomic_state *state); 266 267 int msm_crtc_enable_vblank(struct drm_crtc *crtc); 268 void msm_crtc_disable_vblank(struct drm_crtc *crtc); 269 270 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 271 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 272 273 struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev); 274 bool msm_use_mmu(struct drm_device *dev); 275 276 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 277 struct drm_file *file); 278 279 #ifdef CONFIG_DEBUG_FS 280 unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan); 281 #endif 282 283 int msm_gem_shrinker_init(struct drm_device *dev); 284 void msm_gem_shrinker_cleanup(struct drm_device *dev); 285 286 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 287 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map); 288 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map); 289 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 290 struct dma_buf_attachment *attach, struct sg_table *sg); 291 int msm_gem_prime_pin(struct drm_gem_object *obj); 292 void msm_gem_prime_unpin(struct drm_gem_object *obj); 293 294 int msm_framebuffer_prepare(struct drm_framebuffer *fb, 295 struct msm_gem_address_space *aspace, bool needs_dirtyfb); 296 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, 297 struct msm_gem_address_space *aspace, bool needed_dirtyfb); 298 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, 299 struct msm_gem_address_space *aspace, int plane); 300 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 301 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 302 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 303 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 304 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 305 int w, int h, int p, uint32_t format); 306 307 #ifdef CONFIG_DRM_FBDEV_EMULATION 308 void msm_fbdev_setup(struct drm_device *dev); 309 #else 310 static inline void msm_fbdev_setup(struct drm_device *dev) 311 { 312 } 313 #endif 314 315 struct hdmi; 316 #ifdef CONFIG_DRM_MSM_HDMI 317 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 318 struct drm_encoder *encoder); 319 void __init msm_hdmi_register(void); 320 void __exit msm_hdmi_unregister(void); 321 #else 322 static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 323 struct drm_encoder *encoder) 324 { 325 return -EINVAL; 326 } 327 static inline void __init msm_hdmi_register(void) {} 328 static inline void __exit msm_hdmi_unregister(void) {} 329 #endif 330 331 struct msm_dsi; 332 #ifdef CONFIG_DRM_MSM_DSI 333 int dsi_dev_attach(struct platform_device *pdev); 334 void dsi_dev_detach(struct platform_device *pdev); 335 void __init msm_dsi_register(void); 336 void __exit msm_dsi_unregister(void); 337 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 338 struct drm_encoder *encoder); 339 void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi); 340 bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi); 341 bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi); 342 bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi); 343 bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi); 344 struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi); 345 #else 346 static inline void __init msm_dsi_register(void) 347 { 348 } 349 static inline void __exit msm_dsi_unregister(void) 350 { 351 } 352 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 353 struct drm_device *dev, 354 struct drm_encoder *encoder) 355 { 356 return -EINVAL; 357 } 358 static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) 359 { 360 } 361 static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi) 362 { 363 return false; 364 } 365 static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi) 366 { 367 return false; 368 } 369 static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi) 370 { 371 return false; 372 } 373 static inline bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi) 374 { 375 return false; 376 } 377 378 static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi) 379 { 380 return NULL; 381 } 382 #endif 383 384 #ifdef CONFIG_DRM_MSM_DP 385 int __init msm_dp_register(void); 386 void __exit msm_dp_unregister(void); 387 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, 388 struct drm_encoder *encoder); 389 void msm_dp_irq_postinstall(struct msm_dp *dp_display); 390 void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display); 391 392 void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor); 393 bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); 394 395 #else 396 static inline int __init msm_dp_register(void) 397 { 398 return -EINVAL; 399 } 400 static inline void __exit msm_dp_unregister(void) 401 { 402 } 403 static inline int msm_dp_modeset_init(struct msm_dp *dp_display, 404 struct drm_device *dev, 405 struct drm_encoder *encoder) 406 { 407 return -EINVAL; 408 } 409 410 static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display) 411 { 412 } 413 414 static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) 415 { 416 } 417 418 static inline void msm_dp_debugfs_init(struct msm_dp *dp_display, 419 struct drm_minor *minor) 420 { 421 } 422 423 static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display) 424 { 425 return false; 426 } 427 428 #endif 429 430 #ifdef CONFIG_DRM_MSM_MDP4 431 void msm_mdp4_register(void); 432 void msm_mdp4_unregister(void); 433 #else 434 static inline void msm_mdp4_register(void) {} 435 static inline void msm_mdp4_unregister(void) {} 436 #endif 437 438 #ifdef CONFIG_DRM_MSM_MDP5 439 void msm_mdp_register(void); 440 void msm_mdp_unregister(void); 441 #else 442 static inline void msm_mdp_register(void) {} 443 static inline void msm_mdp_unregister(void) {} 444 #endif 445 446 #ifdef CONFIG_DRM_MSM_DPU 447 void msm_dpu_register(void); 448 void msm_dpu_unregister(void); 449 #else 450 static inline void msm_dpu_register(void) {} 451 static inline void msm_dpu_unregister(void) {} 452 #endif 453 454 #ifdef CONFIG_DRM_MSM_MDSS 455 void msm_mdss_register(void); 456 void msm_mdss_unregister(void); 457 #else 458 static inline void msm_mdss_register(void) {} 459 static inline void msm_mdss_unregister(void) {} 460 #endif 461 462 #ifdef CONFIG_DEBUG_FS 463 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 464 int msm_debugfs_late_init(struct drm_device *dev); 465 int msm_rd_debugfs_init(struct drm_minor *minor); 466 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 467 __printf(3, 4) 468 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 469 const char *fmt, ...); 470 int msm_perf_debugfs_init(struct drm_minor *minor); 471 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); 472 #else 473 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 474 __printf(3, 4) 475 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, 476 struct msm_gem_submit *submit, 477 const char *fmt, ...) {} 478 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 479 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} 480 #endif 481 482 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 483 484 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 485 const char *name); 486 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name); 487 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, 488 phys_addr_t *size); 489 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name); 490 491 struct icc_path *msm_icc_get(struct device *dev, const char *name); 492 493 #define msm_writel(data, addr) writel((data), (addr)) 494 #define msm_readl(addr) readl((addr)) 495 496 static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or) 497 { 498 u32 val = msm_readl(addr); 499 500 val &= ~mask; 501 msm_writel(val | or, addr); 502 } 503 504 /** 505 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work 506 * 507 * @timer: hrtimer to control when the kthread work is triggered 508 * @work: the kthread work 509 * @worker: the kthread worker the work will be scheduled on 510 */ 511 struct msm_hrtimer_work { 512 struct hrtimer timer; 513 struct kthread_work work; 514 struct kthread_worker *worker; 515 }; 516 517 void msm_hrtimer_queue_work(struct msm_hrtimer_work *work, 518 ktime_t wakeup_time, 519 enum hrtimer_mode mode); 520 void msm_hrtimer_work_init(struct msm_hrtimer_work *work, 521 struct kthread_worker *worker, 522 kthread_work_func_t fn, 523 clockid_t clock_id, 524 enum hrtimer_mode mode); 525 526 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 527 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 528 529 static inline int align_pitch(int width, int bpp) 530 { 531 int bytespp = (bpp + 7) / 8; 532 /* adreno needs pitch aligned to 32 pixels: */ 533 return bytespp * ALIGN(width, 32); 534 } 535 536 /* for the generated headers: */ 537 #define INVALID_IDX(idx) ({BUG(); 0;}) 538 #define fui(x) ({BUG(); 0;}) 539 #define _mesa_float_to_half(x) ({BUG(); 0;}) 540 541 542 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 543 544 /* for conditionally setting boolean flag(s): */ 545 #define COND(bool, val) ((bool) ? (val) : 0) 546 547 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 548 { 549 ktime_t now = ktime_get(); 550 s64 remaining_jiffies; 551 552 if (ktime_compare(*timeout, now) < 0) { 553 remaining_jiffies = 0; 554 } else { 555 ktime_t rem = ktime_sub(*timeout, now); 556 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ); 557 } 558 559 return clamp(remaining_jiffies, 1LL, (s64)INT_MAX); 560 } 561 562 /* Driver helpers */ 563 564 extern const struct component_master_ops msm_drm_ops; 565 566 int msm_kms_pm_prepare(struct device *dev); 567 void msm_kms_pm_complete(struct device *dev); 568 569 int msm_drv_probe(struct device *dev, 570 int (*kms_init)(struct drm_device *dev), 571 struct msm_kms *kms); 572 void msm_kms_shutdown(struct platform_device *pdev); 573 574 575 #endif /* __MSM_DRV_H__ */ 576