1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * OMAP2/3 Clock Management (CM) register definitions 4 * 5 * Copyright (C) 2007-2009 Texas Instruments, Inc. 6 * Copyright (C) 2007-2010 Nokia Corporation 7 * Paul Walmsley 8 * 9 * The CM hardware modules on the OMAP2/3 are quite similar to each 10 * other. The CM modules/instances on OMAP4 are quite different, so 11 * they are handled in a separate file. 12 */ 13 #ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H 14 #define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H 15 16 #include "cm.h" 17 18 /* 19 * Module specific CM register offsets from CM_BASE + domain offset 20 * Use cm_{read,write}_mod_reg() with these registers. 21 * These register offsets generally appear in more than one PRCM submodule. 22 */ 23 24 /* Common between OMAP2 and OMAP3 */ 25 26 #define CM_FCLKEN 0x0000 27 #define CM_FCLKEN1 CM_FCLKEN 28 #define CM_CLKEN CM_FCLKEN 29 #define CM_ICLKEN 0x0010 30 #define CM_ICLKEN1 CM_ICLKEN 31 #define CM_ICLKEN2 0x0014 32 #define CM_ICLKEN3 0x0018 33 #define CM_IDLEST 0x0020 34 #define CM_IDLEST1 CM_IDLEST 35 #define CM_IDLEST2 0x0024 36 #define OMAP2430_CM_IDLEST3 0x0028 37 #define CM_AUTOIDLE 0x0030 38 #define CM_AUTOIDLE1 CM_AUTOIDLE 39 #define CM_AUTOIDLE2 0x0034 40 #define CM_AUTOIDLE3 0x0038 41 #define CM_CLKSEL 0x0040 42 #define CM_CLKSEL1 CM_CLKSEL 43 #define CM_CLKSEL2 0x0044 44 #define OMAP2_CM_CLKSTCTRL 0x0048 45 46 #ifndef __ASSEMBLER__ 47 48 #include <linux/io.h> 49 50 static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx) 51 { 52 return readl_relaxed(cm_base.va + module + idx); 53 } 54 55 static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx) 56 { 57 writel_relaxed(val, cm_base.va + module + idx); 58 } 59 60 /* Read-modify-write a register in a CM module. Caller must lock */ 61 static inline u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, 62 s16 idx) 63 { 64 u32 v; 65 66 v = omap2_cm_read_mod_reg(module, idx); 67 v &= ~mask; 68 v |= bits; 69 omap2_cm_write_mod_reg(v, module, idx); 70 71 return v; 72 } 73 74 /* Read a CM register, AND it, and shift the result down to bit 0 */ 75 static inline u32 omap2_cm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) 76 { 77 u32 v; 78 79 v = omap2_cm_read_mod_reg(domain, idx); 80 v &= mask; 81 v >>= __ffs(mask); 82 83 return v; 84 } 85 86 static inline u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) 87 { 88 return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx); 89 } 90 91 static inline u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) 92 { 93 return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx); 94 } 95 96 #endif 97 98 /* CM register bits shared between 24XX and 3430 */ 99 100 /* CM_CLKSEL_GFX */ 101 #define OMAP_CLKSEL_GFX_SHIFT 0 102 #define OMAP_CLKSEL_GFX_MASK (0x7 << 0) 103 #define OMAP_CLKSEL_GFX_WIDTH 3 104 105 /* CM_ICLKEN_GFX */ 106 #define OMAP_EN_GFX_SHIFT 0 107 #define OMAP_EN_GFX_MASK (1 << 0) 108 109 /* CM_IDLEST_GFX */ 110 #define OMAP_ST_GFX_MASK (1 << 0) 111 112 #endif 113