1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: DesignWare based PCIe controller on Rockchip SoCs 8 9maintainers: 10 - Shawn Lin <shawn.lin@rock-chips.com> 11 - Simon Xue <xxm@rock-chips.com> 12 - Heiko Stuebner <heiko@sntech.de> 13 14description: |+ 15 RK3568 SoC PCIe host controller is based on the Synopsys DesignWare 16 PCIe IP and thus inherits all the common properties defined in 17 snps,dw-pcie.yaml. 18 19allOf: 20 - $ref: /schemas/pci/snps,dw-pcie.yaml# 21 22properties: 23 compatible: 24 oneOf: 25 - const: rockchip,rk3568-pcie 26 - items: 27 - enum: 28 - rockchip,rk3588-pcie 29 - const: rockchip,rk3568-pcie 30 31 reg: 32 items: 33 - description: Data Bus Interface (DBI) registers 34 - description: Rockchip designed configuration registers 35 - description: Config registers 36 37 reg-names: 38 items: 39 - const: dbi 40 - const: apb 41 - const: config 42 43 clocks: 44 minItems: 5 45 items: 46 - description: AHB clock for PCIe master 47 - description: AHB clock for PCIe slave 48 - description: AHB clock for PCIe dbi 49 - description: APB clock for PCIe 50 - description: Auxiliary clock for PCIe 51 - description: PIPE clock 52 53 clock-names: 54 minItems: 5 55 items: 56 - const: aclk_mst 57 - const: aclk_slv 58 - const: aclk_dbi 59 - const: pclk 60 - const: aux 61 - const: pipe 62 63 interrupts: 64 items: 65 - description: 66 Combined system interrupt, which is used to signal the following 67 interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme, 68 hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi, 69 edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app 70 - description: 71 Combined PM interrupt, which is used to signal the following 72 interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2, 73 linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2, 74 linkst_out_l0s, pm_dstate_update 75 - description: 76 Combined message interrupt, which is used to signal the following 77 interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi, 78 pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active 79 - description: 80 Combined legacy interrupt, which is used to signal the following 81 interrupts - inta, intb, intc, intd 82 - description: 83 Combined error interrupt, which is used to signal the following 84 interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, 85 tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, 86 nf_err_rx, f_err_rx, radm_qoverflow 87 88 interrupt-names: 89 items: 90 - const: sys 91 - const: pmc 92 - const: msg 93 - const: legacy 94 - const: err 95 96 legacy-interrupt-controller: 97 description: Interrupt controller node for handling legacy PCI interrupts. 98 type: object 99 additionalProperties: false 100 properties: 101 "#address-cells": 102 const: 0 103 104 "#interrupt-cells": 105 const: 1 106 107 interrupt-controller: true 108 109 interrupts: 110 items: 111 - description: combined legacy interrupt 112 required: 113 - "#address-cells" 114 - "#interrupt-cells" 115 - interrupt-controller 116 - interrupts 117 118 msi-map: true 119 120 num-lanes: true 121 122 phys: 123 maxItems: 1 124 125 phy-names: 126 const: pcie-phy 127 128 power-domains: 129 maxItems: 1 130 131 ranges: 132 minItems: 2 133 maxItems: 3 134 135 resets: 136 minItems: 1 137 maxItems: 2 138 139 reset-names: 140 oneOf: 141 - const: pipe 142 - items: 143 - const: pwr 144 - const: pipe 145 146 vpcie3v3-supply: true 147 148required: 149 - compatible 150 - reg 151 - reg-names 152 - clocks 153 - clock-names 154 - msi-map 155 - num-lanes 156 - phys 157 - phy-names 158 - power-domains 159 - resets 160 - reset-names 161 162unevaluatedProperties: false 163 164examples: 165 - | 166 #include <dt-bindings/interrupt-controller/arm-gic.h> 167 168 bus { 169 #address-cells = <2>; 170 #size-cells = <2>; 171 172 pcie3x2: pcie@fe280000 { 173 compatible = "rockchip,rk3568-pcie"; 174 reg = <0x3 0xc0800000 0x0 0x390000>, 175 <0x0 0xfe280000 0x0 0x10000>, 176 <0x3 0x80000000 0x0 0x100000>; 177 reg-names = "dbi", "apb", "config"; 178 bus-range = <0x20 0x2f>; 179 clocks = <&cru 143>, <&cru 144>, 180 <&cru 145>, <&cru 146>, 181 <&cru 147>; 182 clock-names = "aclk_mst", "aclk_slv", 183 "aclk_dbi", "pclk", 184 "aux"; 185 device_type = "pci"; 186 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 191 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 192 linux,pci-domain = <2>; 193 max-link-speed = <2>; 194 msi-map = <0x2000 &its 0x2000 0x1000>; 195 num-lanes = <2>; 196 phys = <&pcie30phy>; 197 phy-names = "pcie-phy"; 198 power-domains = <&power 15>; 199 ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>, 200 <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>; 201 resets = <&cru 193>; 202 reset-names = "pipe"; 203 #address-cells = <3>; 204 #size-cells = <2>; 205 206 legacy-interrupt-controller { 207 interrupt-controller; 208 #address-cells = <0>; 209 #interrupt-cells = <1>; 210 interrupt-parent = <&gic>; 211 interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 212 }; 213 }; 214 }; 215... 216