1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Generic Pin Controller with a Single Register for One or More Pins 8 9maintainers: 10 - Tony Lindgren <tony@atomide.com> 11 12description: 13 Some pin controller devices use a single register for one or more pins. The 14 range of pin control registers can vary from one to many for each controller 15 instance. Some SoCs from Altera, Broadcom, HiSilicon, Ralink, and TI have this 16 kind of pin controller instances. 17 18properties: 19 compatible: 20 oneOf: 21 - enum: 22 - pinctrl-single 23 - pinconf-single 24 - items: 25 - enum: 26 - ti,am437-padconf 27 - ti,am654-padconf 28 - ti,dra7-padconf 29 - ti,omap2420-padconf 30 - ti,omap2430-padconf 31 - ti,omap3-padconf 32 - ti,omap4-padconf 33 - ti,omap5-padconf 34 - const: pinctrl-single 35 36 reg: 37 maxItems: 1 38 39 interrupt-controller: true 40 41 '#interrupt-cells': 42 const: 1 43 44 '#address-cells': 45 const: 1 46 47 '#size-cells': 48 const: 0 49 50 '#pinctrl-cells': 51 description: 52 Number of cells. Usually 2, consisting of register offset, pin configuration 53 value, and pinmux mode. Some controllers may use 1 for just offset and value. 54 enum: [ 1, 2 ] 55 56 pinctrl-single,bit-per-mux: 57 description: Optional flag to indicate register controls more than one pin 58 type: boolean 59 60 pinctrl-single,function-mask: 61 description: Mask of the allowed register bits 62 $ref: /schemas/types.yaml#/definitions/uint32 63 64 pinctrl-single,function-off: 65 description: Optional function off mode for disabled state 66 $ref: /schemas/types.yaml#/definitions/uint32 67 68 pinctrl-single,register-width: 69 description: Width of pin specific bits in the register 70 $ref: /schemas/types.yaml#/definitions/uint32 71 enum: [ 8, 16, 32 ] 72 73 pinctrl-single,gpio-range: 74 description: Optional list of pin base, nr pins & gpio function 75 $ref: /schemas/types.yaml#/definitions/phandle-array 76 items: 77 - items: 78 - description: phandle of a gpio-range node 79 - description: pin base 80 - description: number of pins 81 - description: gpio function 82 83 '#gpio-range-cells': 84 description: No longer needed, may exist in older files for gpio-ranges 85 deprecated: true 86 const: 3 87 88 gpio-range: 89 description: Optional node for gpio range cells 90 type: object 91 additionalProperties: false 92 properties: 93 '#pinctrl-single,gpio-range-cells': 94 description: Number of gpio range cells 95 const: 3 96 $ref: /schemas/types.yaml#/definitions/uint32 97 98patternProperties: 99 '-pins(-[0-9]+)?$|-pin$': 100 description: 101 Pin group node name using naming ending in -pins followed by an optional 102 instance number 103 type: object 104 additionalProperties: false 105 106 properties: 107 pinctrl-single,pins: 108 description: 109 Array of pins as described in pinmux-node.yaml for pinctrl-pin-array 110 $ref: /schemas/types.yaml#/definitions/uint32-array 111 112 pinctrl-single,bits: 113 description: Register bit configuration for pinctrl-single,bit-per-mux 114 $ref: /schemas/types.yaml#/definitions/uint32-array 115 items: 116 - description: register offset 117 - description: value 118 - description: pin bitmask in the register 119 120 pinctrl-single,bias-pullup: 121 description: Optional bias pull up configuration 122 $ref: /schemas/types.yaml#/definitions/uint32-array 123 items: 124 - description: input 125 - description: enabled pull up bits 126 - description: disabled pull up bits 127 - description: bias pull up mask 128 129 pinctrl-single,bias-pulldown: 130 description: Optional bias pull down configuration 131 $ref: /schemas/types.yaml#/definitions/uint32-array 132 items: 133 - description: input 134 - description: enabled pull down bits 135 - description: disabled pull down bits 136 - description: bias pull down mask 137 138 pinctrl-single,drive-strength: 139 description: Optional drive strength configuration 140 $ref: /schemas/types.yaml#/definitions/uint32-array 141 items: 142 - description: drive strength current 143 - description: drive strength mask 144 145 pinctrl-single,input-schmitt: 146 description: Optional input schmitt configuration 147 $ref: /schemas/types.yaml#/definitions/uint32-array 148 items: 149 - description: input 150 - description: enable bits 151 - description: disable bits 152 - description: input schmitt mask 153 154 pinctrl-single,low-power-mode: 155 description: Optional low power mode configuration 156 $ref: /schemas/types.yaml#/definitions/uint32-array 157 items: 158 - description: low power mode value 159 - description: low power mode mask 160 161 pinctrl-single,slew-rate: 162 description: Optional slew rate configuration 163 $ref: /schemas/types.yaml#/definitions/uint32-array 164 items: 165 - description: slew rate 166 - description: slew rate mask 167 168allOf: 169 - $ref: pinctrl.yaml# 170 171required: 172 - compatible 173 - reg 174 - pinctrl-single,register-width 175 176additionalProperties: false 177 178examples: 179 - | 180 soc { 181 #address-cells = <1>; 182 #size-cells = <1>; 183 184 pinmux@4a100040 { 185 compatible = "pinctrl-single"; 186 reg = <0x4a100040 0x0196>; 187 #address-cells = <1>; 188 #size-cells = <0>; 189 #pinctrl-cells = <2>; 190 #interrupt-cells = <1>; 191 interrupt-controller; 192 pinctrl-single,register-width = <16>; 193 pinctrl-single,function-mask = <0xffff>; 194 pinctrl-single,gpio-range = <&range 0 3 0>; 195 range: gpio-range { 196 #pinctrl-single,gpio-range-cells = <3>; 197 }; 198 199 uart2-pins { 200 pinctrl-single,pins = 201 <0xd8 0x118>, 202 <0xda 0>, 203 <0xdc 0x118>, 204 <0xde 0>; 205 }; 206 }; 207 }; 208