1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2022 ROHM Semiconductors 4 * 5 * ROHM/KIONIX accelerometer driver 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/interrupt.h> 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/mutex.h> 14 #include <linux/property.h> 15 #include <linux/regmap.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/slab.h> 18 #include <linux/string_choices.h> 19 #include <linux/units.h> 20 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 #include <linux/iio/trigger.h> 24 #include <linux/iio/trigger_consumer.h> 25 #include <linux/iio/triggered_buffer.h> 26 27 #include "kionix-kx022a.h" 28 29 /* 30 * The KX022A has FIFO which can store 43 samples of HiRes data from 2 31 * channels. This equals to 43 (samples) * 3 (channels) * 2 (bytes/sample) to 32 * 258 bytes of sample data. The quirk to know is that the amount of bytes in 33 * the FIFO is advertised via 8 bit register (max value 255). The thing to note 34 * is that full 258 bytes of data is indicated using the max value 255. 35 */ 36 #define KX022A_FIFO_LENGTH 43 37 #define KX022A_FIFO_FULL_VALUE 255 38 #define KX022A_SOFT_RESET_WAIT_TIME_US (5 * USEC_PER_MSEC) 39 #define KX022A_SOFT_RESET_TOTAL_WAIT_TIME_US (500 * USEC_PER_MSEC) 40 41 /* 3 axis, 2 bytes of data for each of the axis */ 42 #define KX022A_FIFO_SAMPLES_SIZE_BYTES 6 43 #define KX022A_FIFO_MAX_BYTES \ 44 (KX022A_FIFO_LENGTH * KX022A_FIFO_SAMPLES_SIZE_BYTES) 45 46 enum { 47 KX022A_STATE_SAMPLE, 48 KX022A_STATE_FIFO, 49 }; 50 51 /* kx022a Regmap configs */ 52 static const struct regmap_range kx022a_volatile_ranges[] = { 53 { 54 .range_min = KX022A_REG_XHP_L, 55 .range_max = KX022A_REG_COTR, 56 }, { 57 .range_min = KX022A_REG_TSCP, 58 .range_max = KX022A_REG_INT_REL, 59 }, { 60 /* The reset bit will be cleared by sensor */ 61 .range_min = KX022A_REG_CNTL2, 62 .range_max = KX022A_REG_CNTL2, 63 }, { 64 .range_min = KX022A_REG_BUF_STATUS_1, 65 .range_max = KX022A_REG_BUF_READ, 66 }, 67 }; 68 69 static const struct regmap_access_table kx022a_volatile_regs = { 70 .yes_ranges = &kx022a_volatile_ranges[0], 71 .n_yes_ranges = ARRAY_SIZE(kx022a_volatile_ranges), 72 }; 73 74 static const struct regmap_range kx022a_precious_ranges[] = { 75 { 76 .range_min = KX022A_REG_INT_REL, 77 .range_max = KX022A_REG_INT_REL, 78 }, 79 }; 80 81 static const struct regmap_access_table kx022a_precious_regs = { 82 .yes_ranges = &kx022a_precious_ranges[0], 83 .n_yes_ranges = ARRAY_SIZE(kx022a_precious_ranges), 84 }; 85 86 /* 87 * The HW does not set WHO_AM_I reg as read-only but we don't want to write it 88 * so we still include it in the read-only ranges. 89 */ 90 static const struct regmap_range kx022a_read_only_ranges[] = { 91 { 92 .range_min = KX022A_REG_XHP_L, 93 .range_max = KX022A_REG_INT_REL, 94 }, { 95 .range_min = KX022A_REG_BUF_STATUS_1, 96 .range_max = KX022A_REG_BUF_STATUS_2, 97 }, { 98 .range_min = KX022A_REG_BUF_READ, 99 .range_max = KX022A_REG_BUF_READ, 100 }, 101 }; 102 103 static const struct regmap_access_table kx022a_ro_regs = { 104 .no_ranges = &kx022a_read_only_ranges[0], 105 .n_no_ranges = ARRAY_SIZE(kx022a_read_only_ranges), 106 }; 107 108 static const struct regmap_range kx022a_write_only_ranges[] = { 109 { 110 .range_min = KX022A_REG_BTS_WUF_TH, 111 .range_max = KX022A_REG_BTS_WUF_TH, 112 }, { 113 .range_min = KX022A_REG_MAN_WAKE, 114 .range_max = KX022A_REG_MAN_WAKE, 115 }, { 116 .range_min = KX022A_REG_SELF_TEST, 117 .range_max = KX022A_REG_SELF_TEST, 118 }, { 119 .range_min = KX022A_REG_BUF_CLEAR, 120 .range_max = KX022A_REG_BUF_CLEAR, 121 }, 122 }; 123 124 static const struct regmap_access_table kx022a_wo_regs = { 125 .no_ranges = &kx022a_write_only_ranges[0], 126 .n_no_ranges = ARRAY_SIZE(kx022a_write_only_ranges), 127 }; 128 129 static const struct regmap_range kx022a_noinc_read_ranges[] = { 130 { 131 .range_min = KX022A_REG_BUF_READ, 132 .range_max = KX022A_REG_BUF_READ, 133 }, 134 }; 135 136 static const struct regmap_access_table kx022a_nir_regs = { 137 .yes_ranges = &kx022a_noinc_read_ranges[0], 138 .n_yes_ranges = ARRAY_SIZE(kx022a_noinc_read_ranges), 139 }; 140 141 static const struct regmap_config kx022a_regmap_config = { 142 .reg_bits = 8, 143 .val_bits = 8, 144 .volatile_table = &kx022a_volatile_regs, 145 .rd_table = &kx022a_wo_regs, 146 .wr_table = &kx022a_ro_regs, 147 .rd_noinc_table = &kx022a_nir_regs, 148 .precious_table = &kx022a_precious_regs, 149 .max_register = KX022A_MAX_REGISTER, 150 .cache_type = REGCACHE_RBTREE, 151 }; 152 153 /* Regmap configs kx132 */ 154 static const struct regmap_range kx132_volatile_ranges[] = { 155 { 156 .range_min = KX132_REG_XADP_L, 157 .range_max = KX132_REG_COTR, 158 }, { 159 .range_min = KX132_REG_TSCP, 160 .range_max = KX132_REG_INT_REL, 161 }, { 162 /* The reset bit will be cleared by sensor */ 163 .range_min = KX132_REG_CNTL2, 164 .range_max = KX132_REG_CNTL2, 165 }, { 166 .range_min = KX132_REG_CNTL5, 167 .range_max = KX132_REG_CNTL5, 168 }, { 169 .range_min = KX132_REG_BUF_STATUS_1, 170 .range_max = KX132_REG_BUF_READ, 171 }, 172 }; 173 174 static const struct regmap_access_table kx132_volatile_regs = { 175 .yes_ranges = &kx132_volatile_ranges[0], 176 .n_yes_ranges = ARRAY_SIZE(kx132_volatile_ranges), 177 }; 178 179 static const struct regmap_range kx132_precious_ranges[] = { 180 { 181 .range_min = KX132_REG_INT_REL, 182 .range_max = KX132_REG_INT_REL, 183 }, 184 }; 185 186 static const struct regmap_access_table kx132_precious_regs = { 187 .yes_ranges = &kx132_precious_ranges[0], 188 .n_yes_ranges = ARRAY_SIZE(kx132_precious_ranges), 189 }; 190 191 static const struct regmap_range kx132_read_only_ranges[] = { 192 { 193 .range_min = KX132_REG_XADP_L, 194 .range_max = KX132_REG_INT_REL, 195 }, { 196 .range_min = KX132_REG_BUF_STATUS_1, 197 .range_max = KX132_REG_BUF_STATUS_2, 198 }, { 199 .range_min = KX132_REG_BUF_READ, 200 .range_max = KX132_REG_BUF_READ, 201 }, { 202 /* Kionix reserved registers: should not be written */ 203 .range_min = 0x28, 204 .range_max = 0x28, 205 }, { 206 .range_min = 0x35, 207 .range_max = 0x36, 208 }, { 209 .range_min = 0x3c, 210 .range_max = 0x48, 211 }, { 212 .range_min = 0x4e, 213 .range_max = 0x5c, 214 }, { 215 .range_min = 0x77, 216 .range_max = 0x7f, 217 }, 218 }; 219 220 static const struct regmap_access_table kx132_ro_regs = { 221 .no_ranges = &kx132_read_only_ranges[0], 222 .n_no_ranges = ARRAY_SIZE(kx132_read_only_ranges), 223 }; 224 225 static const struct regmap_range kx132_write_only_ranges[] = { 226 { 227 .range_min = KX132_REG_SELF_TEST, 228 .range_max = KX132_REG_SELF_TEST, 229 }, { 230 .range_min = KX132_REG_BUF_CLEAR, 231 .range_max = KX132_REG_BUF_CLEAR, 232 }, 233 }; 234 235 static const struct regmap_access_table kx132_wo_regs = { 236 .no_ranges = &kx132_write_only_ranges[0], 237 .n_no_ranges = ARRAY_SIZE(kx132_write_only_ranges), 238 }; 239 240 static const struct regmap_range kx132_noinc_read_ranges[] = { 241 { 242 .range_min = KX132_REG_BUF_READ, 243 .range_max = KX132_REG_BUF_READ, 244 }, 245 }; 246 247 static const struct regmap_access_table kx132_nir_regs = { 248 .yes_ranges = &kx132_noinc_read_ranges[0], 249 .n_yes_ranges = ARRAY_SIZE(kx132_noinc_read_ranges), 250 }; 251 252 static const struct regmap_config kx132_regmap_config = { 253 .reg_bits = 8, 254 .val_bits = 8, 255 .volatile_table = &kx132_volatile_regs, 256 .rd_table = &kx132_wo_regs, 257 .wr_table = &kx132_ro_regs, 258 .rd_noinc_table = &kx132_nir_regs, 259 .precious_table = &kx132_precious_regs, 260 .max_register = KX132_MAX_REGISTER, 261 .cache_type = REGCACHE_RBTREE, 262 }; 263 264 struct kx022a_data { 265 struct regmap *regmap; 266 const struct kx022a_chip_info *chip_info; 267 struct iio_trigger *trig; 268 struct device *dev; 269 struct iio_mount_matrix orientation; 270 int64_t timestamp, old_timestamp; 271 272 int irq; 273 int inc_reg; 274 int ien_reg; 275 276 unsigned int state; 277 unsigned int odr_ns; 278 279 bool trigger_enabled; 280 /* 281 * Prevent toggling the sensor stby/active state (PC1 bit) in the 282 * middle of a configuration, or when the fifo is enabled. Also, 283 * protect the data stored/retrieved from this structure from 284 * concurrent accesses. 285 */ 286 struct mutex mutex; 287 u8 watermark; 288 289 __le16 *fifo_buffer; 290 291 /* 3 x 16bit accel data + timestamp */ 292 __le16 buffer[8] __aligned(IIO_DMA_MINALIGN); 293 struct { 294 __le16 channels[3]; 295 s64 ts __aligned(8); 296 } scan; 297 }; 298 299 static const struct iio_mount_matrix * 300 kx022a_get_mount_matrix(const struct iio_dev *idev, 301 const struct iio_chan_spec *chan) 302 { 303 struct kx022a_data *data = iio_priv(idev); 304 305 return &data->orientation; 306 } 307 308 enum { 309 AXIS_X, 310 AXIS_Y, 311 AXIS_Z, 312 AXIS_MAX 313 }; 314 315 static const unsigned long kx022a_scan_masks[] = { 316 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 0 317 }; 318 319 static const struct iio_chan_spec_ext_info kx022a_ext_info[] = { 320 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, kx022a_get_mount_matrix), 321 { } 322 }; 323 324 #define KX022A_ACCEL_CHAN(axis, reg, index) \ 325 { \ 326 .type = IIO_ACCEL, \ 327 .modified = 1, \ 328 .channel2 = IIO_MOD_##axis, \ 329 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 330 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 331 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 332 .info_mask_shared_by_type_available = \ 333 BIT(IIO_CHAN_INFO_SCALE) | \ 334 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 335 .ext_info = kx022a_ext_info, \ 336 .address = reg, \ 337 .scan_index = index, \ 338 .scan_type = { \ 339 .sign = 's', \ 340 .realbits = 16, \ 341 .storagebits = 16, \ 342 .endianness = IIO_LE, \ 343 }, \ 344 } 345 346 static const struct iio_chan_spec kx022a_channels[] = { 347 KX022A_ACCEL_CHAN(X, KX022A_REG_XOUT_L, 0), 348 KX022A_ACCEL_CHAN(Y, KX022A_REG_YOUT_L, 1), 349 KX022A_ACCEL_CHAN(Z, KX022A_REG_ZOUT_L, 2), 350 IIO_CHAN_SOFT_TIMESTAMP(3), 351 }; 352 353 static const struct iio_chan_spec kx132_channels[] = { 354 KX022A_ACCEL_CHAN(X, KX132_REG_XOUT_L, 0), 355 KX022A_ACCEL_CHAN(Y, KX132_REG_YOUT_L, 1), 356 KX022A_ACCEL_CHAN(Z, KX132_REG_ZOUT_L, 2), 357 IIO_CHAN_SOFT_TIMESTAMP(3), 358 }; 359 360 /* 361 * The sensor HW can support ODR up to 1600 Hz, which is beyond what most of the 362 * Linux CPUs can handle without dropping samples. Also, the low power mode is 363 * not available for higher sample rates. Thus, the driver only supports 200 Hz 364 * and slower ODRs. The slowest is 0.78 Hz. 365 */ 366 static const int kx022a_accel_samp_freq_table[][2] = { 367 { 0, 780000 }, 368 { 1, 563000 }, 369 { 3, 125000 }, 370 { 6, 250000 }, 371 { 12, 500000 }, 372 { 25, 0 }, 373 { 50, 0 }, 374 { 100, 0 }, 375 { 200, 0 }, 376 }; 377 378 static const unsigned int kx022a_odrs[] = { 379 1282051282, 380 639795266, 381 320 * MEGA, 382 160 * MEGA, 383 80 * MEGA, 384 40 * MEGA, 385 20 * MEGA, 386 10 * MEGA, 387 5 * MEGA, 388 }; 389 390 /* 391 * range is typically +-2G/4G/8G/16G, distributed over the amount of bits. 392 * The scale table can be calculated using 393 * (range / 2^bits) * g = (range / 2^bits) * 9.80665 m/s^2 394 * => KX022A uses 16 bit (HiRes mode - assume the low 8 bits are zeroed 395 * in low-power mode(?) ) 396 * => +/-2G => 4 / 2^16 * 9,80665 * 10^6 (to scale to micro) 397 * => +/-2G - 598.550415 398 * +/-4G - 1197.10083 399 * +/-8G - 2394.20166 400 * +/-16G - 4788.40332 401 */ 402 static const int kx022a_scale_table[][2] = { 403 { 598, 550415 }, 404 { 1197, 100830 }, 405 { 2394, 201660 }, 406 { 4788, 403320 }, 407 }; 408 409 static int kx022a_read_avail(struct iio_dev *indio_dev, 410 struct iio_chan_spec const *chan, 411 const int **vals, int *type, int *length, 412 long mask) 413 { 414 switch (mask) { 415 case IIO_CHAN_INFO_SAMP_FREQ: 416 *vals = (const int *)kx022a_accel_samp_freq_table; 417 *length = ARRAY_SIZE(kx022a_accel_samp_freq_table) * 418 ARRAY_SIZE(kx022a_accel_samp_freq_table[0]); 419 *type = IIO_VAL_INT_PLUS_MICRO; 420 return IIO_AVAIL_LIST; 421 case IIO_CHAN_INFO_SCALE: 422 *vals = (const int *)kx022a_scale_table; 423 *length = ARRAY_SIZE(kx022a_scale_table) * 424 ARRAY_SIZE(kx022a_scale_table[0]); 425 *type = IIO_VAL_INT_PLUS_MICRO; 426 return IIO_AVAIL_LIST; 427 default: 428 return -EINVAL; 429 } 430 } 431 432 #define KX022A_DEFAULT_PERIOD_NS (20 * NSEC_PER_MSEC) 433 434 static void kx022a_reg2freq(unsigned int val, int *val1, int *val2) 435 { 436 *val1 = kx022a_accel_samp_freq_table[val & KX022A_MASK_ODR][0]; 437 *val2 = kx022a_accel_samp_freq_table[val & KX022A_MASK_ODR][1]; 438 } 439 440 static void kx022a_reg2scale(unsigned int val, unsigned int *val1, 441 unsigned int *val2) 442 { 443 val &= KX022A_MASK_GSEL; 444 val >>= KX022A_GSEL_SHIFT; 445 446 *val1 = kx022a_scale_table[val][0]; 447 *val2 = kx022a_scale_table[val][1]; 448 } 449 450 static int kx022a_turn_on_off_unlocked(struct kx022a_data *data, bool on) 451 { 452 int ret; 453 454 if (on) 455 ret = regmap_set_bits(data->regmap, data->chip_info->cntl, 456 KX022A_MASK_PC1); 457 else 458 ret = regmap_clear_bits(data->regmap, data->chip_info->cntl, 459 KX022A_MASK_PC1); 460 if (ret) 461 dev_err(data->dev, "Turn %s fail %d\n", str_on_off(on), ret); 462 463 return ret; 464 } 465 466 static int kx022a_turn_off_lock(struct kx022a_data *data) 467 { 468 int ret; 469 470 mutex_lock(&data->mutex); 471 ret = kx022a_turn_on_off_unlocked(data, false); 472 if (ret) 473 mutex_unlock(&data->mutex); 474 475 return ret; 476 } 477 478 static int kx022a_turn_on_unlock(struct kx022a_data *data) 479 { 480 int ret; 481 482 ret = kx022a_turn_on_off_unlocked(data, true); 483 mutex_unlock(&data->mutex); 484 485 return ret; 486 } 487 488 static int kx022a_write_raw(struct iio_dev *idev, 489 struct iio_chan_spec const *chan, 490 int val, int val2, long mask) 491 { 492 struct kx022a_data *data = iio_priv(idev); 493 int ret, n; 494 495 /* 496 * We should not allow changing scale or frequency when FIFO is running 497 * as it will mess the timestamp/scale for samples existing in the 498 * buffer. If this turns out to be an issue we can later change logic 499 * to internally flush the fifo before reconfiguring so the samples in 500 * fifo keep matching the freq/scale settings. (Such setup could cause 501 * issues if users trust the watermark to be reached within known 502 * time-limit). 503 */ 504 ret = iio_device_claim_direct_mode(idev); 505 if (ret) 506 return ret; 507 508 switch (mask) { 509 case IIO_CHAN_INFO_SAMP_FREQ: 510 n = ARRAY_SIZE(kx022a_accel_samp_freq_table); 511 512 while (n--) 513 if (val == kx022a_accel_samp_freq_table[n][0] && 514 val2 == kx022a_accel_samp_freq_table[n][1]) 515 break; 516 if (n < 0) { 517 ret = -EINVAL; 518 goto unlock_out; 519 } 520 ret = kx022a_turn_off_lock(data); 521 if (ret) 522 break; 523 524 ret = regmap_update_bits(data->regmap, 525 data->chip_info->odcntl, 526 KX022A_MASK_ODR, n); 527 data->odr_ns = kx022a_odrs[n]; 528 kx022a_turn_on_unlock(data); 529 break; 530 case IIO_CHAN_INFO_SCALE: 531 n = ARRAY_SIZE(kx022a_scale_table); 532 533 while (n-- > 0) 534 if (val == kx022a_scale_table[n][0] && 535 val2 == kx022a_scale_table[n][1]) 536 break; 537 if (n < 0) { 538 ret = -EINVAL; 539 goto unlock_out; 540 } 541 542 ret = kx022a_turn_off_lock(data); 543 if (ret) 544 break; 545 546 ret = regmap_update_bits(data->regmap, data->chip_info->cntl, 547 KX022A_MASK_GSEL, 548 n << KX022A_GSEL_SHIFT); 549 kx022a_turn_on_unlock(data); 550 break; 551 default: 552 ret = -EINVAL; 553 break; 554 } 555 556 unlock_out: 557 iio_device_release_direct_mode(idev); 558 559 return ret; 560 } 561 562 static int kx022a_fifo_set_wmi(struct kx022a_data *data) 563 { 564 u8 threshold; 565 566 threshold = data->watermark; 567 568 return regmap_update_bits(data->regmap, data->chip_info->buf_cntl1, 569 KX022A_MASK_WM_TH, threshold); 570 } 571 572 static int kx022a_get_axis(struct kx022a_data *data, 573 struct iio_chan_spec const *chan, 574 int *val) 575 { 576 int ret; 577 578 ret = regmap_bulk_read(data->regmap, chan->address, &data->buffer[0], 579 sizeof(__le16)); 580 if (ret) 581 return ret; 582 583 *val = le16_to_cpu(data->buffer[0]); 584 585 return IIO_VAL_INT; 586 } 587 588 static int kx022a_read_raw(struct iio_dev *idev, 589 struct iio_chan_spec const *chan, 590 int *val, int *val2, long mask) 591 { 592 struct kx022a_data *data = iio_priv(idev); 593 unsigned int regval; 594 int ret; 595 596 switch (mask) { 597 case IIO_CHAN_INFO_RAW: 598 ret = iio_device_claim_direct_mode(idev); 599 if (ret) 600 return ret; 601 602 mutex_lock(&data->mutex); 603 ret = kx022a_get_axis(data, chan, val); 604 mutex_unlock(&data->mutex); 605 606 iio_device_release_direct_mode(idev); 607 608 return ret; 609 610 case IIO_CHAN_INFO_SAMP_FREQ: 611 ret = regmap_read(data->regmap, data->chip_info->odcntl, ®val); 612 if (ret) 613 return ret; 614 615 if ((regval & KX022A_MASK_ODR) > 616 ARRAY_SIZE(kx022a_accel_samp_freq_table)) { 617 dev_err(data->dev, "Invalid ODR\n"); 618 return -EINVAL; 619 } 620 621 kx022a_reg2freq(regval, val, val2); 622 623 return IIO_VAL_INT_PLUS_MICRO; 624 625 case IIO_CHAN_INFO_SCALE: 626 ret = regmap_read(data->regmap, data->chip_info->cntl, ®val); 627 if (ret < 0) 628 return ret; 629 630 kx022a_reg2scale(regval, val, val2); 631 632 return IIO_VAL_INT_PLUS_MICRO; 633 } 634 635 return -EINVAL; 636 }; 637 638 static int kx022a_set_watermark(struct iio_dev *idev, unsigned int val) 639 { 640 struct kx022a_data *data = iio_priv(idev); 641 642 val = min(data->chip_info->fifo_length, val); 643 644 mutex_lock(&data->mutex); 645 data->watermark = val; 646 mutex_unlock(&data->mutex); 647 648 return 0; 649 } 650 651 static ssize_t hwfifo_enabled_show(struct device *dev, 652 struct device_attribute *attr, 653 char *buf) 654 { 655 struct iio_dev *idev = dev_to_iio_dev(dev); 656 struct kx022a_data *data = iio_priv(idev); 657 bool state; 658 659 mutex_lock(&data->mutex); 660 state = data->state; 661 mutex_unlock(&data->mutex); 662 663 return sysfs_emit(buf, "%d\n", state); 664 } 665 666 static ssize_t hwfifo_watermark_show(struct device *dev, 667 struct device_attribute *attr, 668 char *buf) 669 { 670 struct iio_dev *idev = dev_to_iio_dev(dev); 671 struct kx022a_data *data = iio_priv(idev); 672 int wm; 673 674 mutex_lock(&data->mutex); 675 wm = data->watermark; 676 mutex_unlock(&data->mutex); 677 678 return sysfs_emit(buf, "%d\n", wm); 679 } 680 681 static IIO_DEVICE_ATTR_RO(hwfifo_enabled, 0); 682 static IIO_DEVICE_ATTR_RO(hwfifo_watermark, 0); 683 684 static const struct iio_dev_attr *kx022a_fifo_attributes[] = { 685 &iio_dev_attr_hwfifo_watermark, 686 &iio_dev_attr_hwfifo_enabled, 687 NULL 688 }; 689 690 static int kx022a_drop_fifo_contents(struct kx022a_data *data) 691 { 692 /* 693 * We must clear the old time-stamp to avoid computing the timestamps 694 * based on samples acquired when buffer was last enabled. 695 * 696 * We don't need to protect the timestamp as long as we are only 697 * called from fifo-disable where we can guarantee the sensor is not 698 * triggering interrupts and where the mutex is locked to prevent the 699 * user-space access. 700 */ 701 data->timestamp = 0; 702 703 return regmap_write(data->regmap, data->chip_info->buf_clear, 0x0); 704 } 705 706 static int kx022a_get_fifo_bytes_available(struct kx022a_data *data) 707 { 708 int ret, fifo_bytes; 709 710 ret = regmap_read(data->regmap, KX022A_REG_BUF_STATUS_1, &fifo_bytes); 711 if (ret) { 712 dev_err(data->dev, "Error reading buffer status\n"); 713 return ret; 714 } 715 716 if (fifo_bytes == KX022A_FIFO_FULL_VALUE) 717 return KX022A_FIFO_MAX_BYTES; 718 719 return fifo_bytes; 720 } 721 722 static int kx132_get_fifo_bytes_available(struct kx022a_data *data) 723 { 724 __le16 buf_status; 725 int ret, fifo_bytes; 726 727 ret = regmap_bulk_read(data->regmap, data->chip_info->buf_status1, 728 &buf_status, sizeof(buf_status)); 729 if (ret) { 730 dev_err(data->dev, "Error reading buffer status\n"); 731 return ret; 732 } 733 734 fifo_bytes = le16_to_cpu(buf_status); 735 fifo_bytes &= data->chip_info->buf_smp_lvl_mask; 736 fifo_bytes = min((unsigned int)fifo_bytes, data->chip_info->fifo_length * 737 KX022A_FIFO_SAMPLES_SIZE_BYTES); 738 739 return fifo_bytes; 740 } 741 742 static int __kx022a_fifo_flush(struct iio_dev *idev, unsigned int samples, 743 bool irq) 744 { 745 struct kx022a_data *data = iio_priv(idev); 746 uint64_t sample_period; 747 int count, fifo_bytes; 748 bool renable = false; 749 int64_t tstamp; 750 int ret, i; 751 752 fifo_bytes = data->chip_info->get_fifo_bytes_available(data); 753 754 if (fifo_bytes % KX022A_FIFO_SAMPLES_SIZE_BYTES) 755 dev_warn(data->dev, "Bad FIFO alignment. Data may be corrupt\n"); 756 757 count = fifo_bytes / KX022A_FIFO_SAMPLES_SIZE_BYTES; 758 if (!count) 759 return 0; 760 761 /* 762 * If we are being called from IRQ handler we know the stored timestamp 763 * is fairly accurate for the last stored sample. Otherwise, if we are 764 * called as a result of a read operation from userspace and hence 765 * before the watermark interrupt was triggered, take a timestamp 766 * now. We can fall anywhere in between two samples so the error in this 767 * case is at most one sample period. 768 */ 769 if (!irq) { 770 /* 771 * We need to have the IRQ disabled or we risk of messing-up 772 * the timestamps. If we are ran from IRQ, then the 773 * IRQF_ONESHOT has us covered - but if we are ran by the 774 * user-space read we need to disable the IRQ to be on a safe 775 * side. We do this usng synchronous disable so that if the 776 * IRQ thread is being ran on other CPU we wait for it to be 777 * finished. 778 */ 779 disable_irq(data->irq); 780 renable = true; 781 782 data->old_timestamp = data->timestamp; 783 data->timestamp = iio_get_time_ns(idev); 784 } 785 786 /* 787 * Approximate timestamps for each of the sample based on the sampling 788 * frequency, timestamp for last sample and number of samples. 789 * 790 * We'd better not use the current bandwidth settings to compute the 791 * sample period. The real sample rate varies with the device and 792 * small variation adds when we store a large number of samples. 793 * 794 * To avoid this issue we compute the actual sample period ourselves 795 * based on the timestamp delta between the last two flush operations. 796 */ 797 if (data->old_timestamp) { 798 sample_period = data->timestamp - data->old_timestamp; 799 do_div(sample_period, count); 800 } else { 801 sample_period = data->odr_ns; 802 } 803 tstamp = data->timestamp - (count - 1) * sample_period; 804 805 if (samples && count > samples) { 806 /* 807 * Here we leave some old samples to the buffer. We need to 808 * adjust the timestamp to match the first sample in the buffer 809 * or we will miscalculate the sample_period at next round. 810 */ 811 data->timestamp -= (count - samples) * sample_period; 812 count = samples; 813 } 814 815 fifo_bytes = count * KX022A_FIFO_SAMPLES_SIZE_BYTES; 816 ret = regmap_noinc_read(data->regmap, data->chip_info->buf_read, 817 data->fifo_buffer, fifo_bytes); 818 if (ret) 819 goto renable_out; 820 821 for (i = 0; i < count; i++) { 822 __le16 *sam = &data->fifo_buffer[i * 3]; 823 __le16 *chs; 824 int bit; 825 826 chs = &data->scan.channels[0]; 827 for_each_set_bit(bit, idev->active_scan_mask, AXIS_MAX) 828 chs[bit] = sam[bit]; 829 830 iio_push_to_buffers_with_timestamp(idev, &data->scan, tstamp); 831 832 tstamp += sample_period; 833 } 834 835 ret = count; 836 837 renable_out: 838 if (renable) 839 enable_irq(data->irq); 840 841 return ret; 842 } 843 844 static int kx022a_fifo_flush(struct iio_dev *idev, unsigned int samples) 845 { 846 struct kx022a_data *data = iio_priv(idev); 847 int ret; 848 849 mutex_lock(&data->mutex); 850 ret = __kx022a_fifo_flush(idev, samples, false); 851 mutex_unlock(&data->mutex); 852 853 return ret; 854 } 855 856 static const struct iio_info kx022a_info = { 857 .read_raw = &kx022a_read_raw, 858 .write_raw = &kx022a_write_raw, 859 .read_avail = &kx022a_read_avail, 860 861 .validate_trigger = iio_validate_own_trigger, 862 .hwfifo_set_watermark = kx022a_set_watermark, 863 .hwfifo_flush_to_buffer = kx022a_fifo_flush, 864 }; 865 866 static int kx022a_set_drdy_irq(struct kx022a_data *data, bool en) 867 { 868 if (en) 869 return regmap_set_bits(data->regmap, data->chip_info->cntl, 870 KX022A_MASK_DRDY); 871 872 return regmap_clear_bits(data->regmap, data->chip_info->cntl, 873 KX022A_MASK_DRDY); 874 } 875 876 static int kx022a_prepare_irq_pin(struct kx022a_data *data) 877 { 878 /* Enable IRQ1 pin. Set polarity to active low */ 879 int mask = KX022A_MASK_IEN | KX022A_MASK_IPOL | 880 KX022A_MASK_ITYP; 881 int val = KX022A_MASK_IEN | KX022A_IPOL_LOW | 882 KX022A_ITYP_LEVEL; 883 int ret; 884 885 ret = regmap_update_bits(data->regmap, data->inc_reg, mask, val); 886 if (ret) 887 return ret; 888 889 /* We enable WMI to IRQ pin only at buffer_enable */ 890 mask = KX022A_MASK_INS2_DRDY; 891 892 return regmap_set_bits(data->regmap, data->ien_reg, mask); 893 } 894 895 static int kx022a_fifo_disable(struct kx022a_data *data) 896 { 897 int ret = 0; 898 899 ret = kx022a_turn_off_lock(data); 900 if (ret) 901 return ret; 902 903 ret = regmap_clear_bits(data->regmap, data->ien_reg, KX022A_MASK_WMI); 904 if (ret) 905 goto unlock_out; 906 907 ret = regmap_clear_bits(data->regmap, data->chip_info->buf_cntl2, 908 KX022A_MASK_BUF_EN); 909 if (ret) 910 goto unlock_out; 911 912 data->state &= ~KX022A_STATE_FIFO; 913 914 kx022a_drop_fifo_contents(data); 915 916 kfree(data->fifo_buffer); 917 918 return kx022a_turn_on_unlock(data); 919 920 unlock_out: 921 mutex_unlock(&data->mutex); 922 923 return ret; 924 } 925 926 static int kx022a_buffer_predisable(struct iio_dev *idev) 927 { 928 struct kx022a_data *data = iio_priv(idev); 929 930 if (iio_device_get_current_mode(idev) == INDIO_BUFFER_TRIGGERED) 931 return 0; 932 933 return kx022a_fifo_disable(data); 934 } 935 936 static int kx022a_fifo_enable(struct kx022a_data *data) 937 { 938 int ret; 939 940 data->fifo_buffer = kmalloc_array(data->chip_info->fifo_length, 941 KX022A_FIFO_SAMPLES_SIZE_BYTES, 942 GFP_KERNEL); 943 if (!data->fifo_buffer) 944 return -ENOMEM; 945 946 ret = kx022a_turn_off_lock(data); 947 if (ret) 948 return ret; 949 950 /* Update watermark to HW */ 951 ret = kx022a_fifo_set_wmi(data); 952 if (ret) 953 goto unlock_out; 954 955 /* Enable buffer */ 956 ret = regmap_set_bits(data->regmap, data->chip_info->buf_cntl2, 957 KX022A_MASK_BUF_EN); 958 if (ret) 959 goto unlock_out; 960 961 data->state |= KX022A_STATE_FIFO; 962 ret = regmap_set_bits(data->regmap, data->ien_reg, 963 KX022A_MASK_WMI); 964 if (ret) 965 goto unlock_out; 966 967 return kx022a_turn_on_unlock(data); 968 969 unlock_out: 970 mutex_unlock(&data->mutex); 971 972 return ret; 973 } 974 975 static int kx022a_buffer_postenable(struct iio_dev *idev) 976 { 977 struct kx022a_data *data = iio_priv(idev); 978 979 /* 980 * If we use data-ready trigger, then the IRQ masks should be handled by 981 * trigger enable and the hardware buffer is not used but we just update 982 * results to the IIO fifo when data-ready triggers. 983 */ 984 if (iio_device_get_current_mode(idev) == INDIO_BUFFER_TRIGGERED) 985 return 0; 986 987 return kx022a_fifo_enable(data); 988 } 989 990 static const struct iio_buffer_setup_ops kx022a_buffer_ops = { 991 .postenable = kx022a_buffer_postenable, 992 .predisable = kx022a_buffer_predisable, 993 }; 994 995 static irqreturn_t kx022a_trigger_handler(int irq, void *p) 996 { 997 struct iio_poll_func *pf = p; 998 struct iio_dev *idev = pf->indio_dev; 999 struct kx022a_data *data = iio_priv(idev); 1000 int ret; 1001 1002 ret = regmap_bulk_read(data->regmap, data->chip_info->xout_l, data->buffer, 1003 KX022A_FIFO_SAMPLES_SIZE_BYTES); 1004 if (ret < 0) 1005 goto err_read; 1006 1007 iio_push_to_buffers_with_timestamp(idev, data->buffer, data->timestamp); 1008 err_read: 1009 iio_trigger_notify_done(idev->trig); 1010 1011 return IRQ_HANDLED; 1012 } 1013 1014 /* Get timestamps and wake the thread if we need to read data */ 1015 static irqreturn_t kx022a_irq_handler(int irq, void *private) 1016 { 1017 struct iio_dev *idev = private; 1018 struct kx022a_data *data = iio_priv(idev); 1019 1020 data->old_timestamp = data->timestamp; 1021 data->timestamp = iio_get_time_ns(idev); 1022 1023 if (data->state & KX022A_STATE_FIFO || data->trigger_enabled) 1024 return IRQ_WAKE_THREAD; 1025 1026 return IRQ_NONE; 1027 } 1028 1029 /* 1030 * WMI and data-ready IRQs are acked when results are read. If we add 1031 * TILT/WAKE or other IRQs - then we may need to implement the acking 1032 * (which is racy). 1033 */ 1034 static irqreturn_t kx022a_irq_thread_handler(int irq, void *private) 1035 { 1036 struct iio_dev *idev = private; 1037 struct kx022a_data *data = iio_priv(idev); 1038 irqreturn_t ret = IRQ_NONE; 1039 1040 mutex_lock(&data->mutex); 1041 1042 if (data->trigger_enabled) { 1043 iio_trigger_poll_nested(data->trig); 1044 ret = IRQ_HANDLED; 1045 } 1046 1047 if (data->state & KX022A_STATE_FIFO) { 1048 int ok; 1049 1050 ok = __kx022a_fifo_flush(idev, data->chip_info->fifo_length, true); 1051 if (ok > 0) 1052 ret = IRQ_HANDLED; 1053 } 1054 1055 mutex_unlock(&data->mutex); 1056 1057 return ret; 1058 } 1059 1060 static int kx022a_trigger_set_state(struct iio_trigger *trig, 1061 bool state) 1062 { 1063 struct kx022a_data *data = iio_trigger_get_drvdata(trig); 1064 int ret = 0; 1065 1066 mutex_lock(&data->mutex); 1067 1068 if (data->trigger_enabled == state) 1069 goto unlock_out; 1070 1071 if (data->state & KX022A_STATE_FIFO) { 1072 dev_warn(data->dev, "Can't set trigger when FIFO enabled\n"); 1073 ret = -EBUSY; 1074 goto unlock_out; 1075 } 1076 1077 ret = kx022a_turn_on_off_unlocked(data, false); 1078 if (ret) 1079 goto unlock_out; 1080 1081 data->trigger_enabled = state; 1082 ret = kx022a_set_drdy_irq(data, state); 1083 if (ret) 1084 goto unlock_out; 1085 1086 ret = kx022a_turn_on_off_unlocked(data, true); 1087 1088 unlock_out: 1089 mutex_unlock(&data->mutex); 1090 1091 return ret; 1092 } 1093 1094 static const struct iio_trigger_ops kx022a_trigger_ops = { 1095 .set_trigger_state = kx022a_trigger_set_state, 1096 }; 1097 1098 static int kx022a_chip_init(struct kx022a_data *data) 1099 { 1100 int ret, val; 1101 1102 /* Reset the senor */ 1103 ret = regmap_write(data->regmap, data->chip_info->cntl2, KX022A_MASK_SRST); 1104 if (ret) 1105 return ret; 1106 1107 /* 1108 * I've seen I2C read failures if we poll too fast after the sensor 1109 * reset. Slight delay gives I2C block the time to recover. 1110 */ 1111 msleep(1); 1112 1113 ret = regmap_read_poll_timeout(data->regmap, data->chip_info->cntl2, val, 1114 !(val & KX022A_MASK_SRST), 1115 KX022A_SOFT_RESET_WAIT_TIME_US, 1116 KX022A_SOFT_RESET_TOTAL_WAIT_TIME_US); 1117 if (ret) { 1118 dev_err(data->dev, "Sensor reset %s\n", 1119 val & KX022A_MASK_SRST ? "timeout" : "fail#"); 1120 return ret; 1121 } 1122 1123 ret = regmap_reinit_cache(data->regmap, data->chip_info->regmap_config); 1124 if (ret) { 1125 dev_err(data->dev, "Failed to reinit reg cache\n"); 1126 return ret; 1127 } 1128 1129 /* set data res 16bit */ 1130 ret = regmap_set_bits(data->regmap, data->chip_info->buf_cntl2, 1131 KX022A_MASK_BRES16); 1132 if (ret) { 1133 dev_err(data->dev, "Failed to set data resolution\n"); 1134 return ret; 1135 } 1136 1137 return kx022a_prepare_irq_pin(data); 1138 } 1139 1140 const struct kx022a_chip_info kx022a_chip_info = { 1141 .name = "kx022-accel", 1142 .regmap_config = &kx022a_regmap_config, 1143 .channels = kx022a_channels, 1144 .num_channels = ARRAY_SIZE(kx022a_channels), 1145 .fifo_length = KX022A_FIFO_LENGTH, 1146 .who = KX022A_REG_WHO, 1147 .id = KX022A_ID, 1148 .cntl = KX022A_REG_CNTL, 1149 .cntl2 = KX022A_REG_CNTL2, 1150 .odcntl = KX022A_REG_ODCNTL, 1151 .buf_cntl1 = KX022A_REG_BUF_CNTL1, 1152 .buf_cntl2 = KX022A_REG_BUF_CNTL2, 1153 .buf_clear = KX022A_REG_BUF_CLEAR, 1154 .buf_status1 = KX022A_REG_BUF_STATUS_1, 1155 .buf_read = KX022A_REG_BUF_READ, 1156 .inc1 = KX022A_REG_INC1, 1157 .inc4 = KX022A_REG_INC4, 1158 .inc5 = KX022A_REG_INC5, 1159 .inc6 = KX022A_REG_INC6, 1160 .xout_l = KX022A_REG_XOUT_L, 1161 .get_fifo_bytes_available = kx022a_get_fifo_bytes_available, 1162 }; 1163 EXPORT_SYMBOL_NS_GPL(kx022a_chip_info, IIO_KX022A); 1164 1165 const struct kx022a_chip_info kx132_chip_info = { 1166 .name = "kx132-1211", 1167 .regmap_config = &kx132_regmap_config, 1168 .channels = kx132_channels, 1169 .num_channels = ARRAY_SIZE(kx132_channels), 1170 .fifo_length = KX132_FIFO_LENGTH, 1171 .who = KX132_REG_WHO, 1172 .id = KX132_ID, 1173 .cntl = KX132_REG_CNTL, 1174 .cntl2 = KX132_REG_CNTL2, 1175 .odcntl = KX132_REG_ODCNTL, 1176 .buf_cntl1 = KX132_REG_BUF_CNTL1, 1177 .buf_cntl2 = KX132_REG_BUF_CNTL2, 1178 .buf_clear = KX132_REG_BUF_CLEAR, 1179 .buf_status1 = KX132_REG_BUF_STATUS_1, 1180 .buf_smp_lvl_mask = KX132_MASK_BUF_SMP_LVL, 1181 .buf_read = KX132_REG_BUF_READ, 1182 .inc1 = KX132_REG_INC1, 1183 .inc4 = KX132_REG_INC4, 1184 .inc5 = KX132_REG_INC5, 1185 .inc6 = KX132_REG_INC6, 1186 .xout_l = KX132_REG_XOUT_L, 1187 .get_fifo_bytes_available = kx132_get_fifo_bytes_available, 1188 }; 1189 EXPORT_SYMBOL_NS_GPL(kx132_chip_info, IIO_KX022A); 1190 1191 /* 1192 * Despite the naming, KX132ACR-LBZ is not similar to KX132-1211 but it is 1193 * exact subset of KX022A. KX132ACR-LBZ is meant to be used for industrial 1194 * applications and the tap/double tap, free fall and tilt engines were 1195 * removed. Rest of the registers and functionalities (excluding the ID 1196 * register) are exact match to what is found in KX022. 1197 */ 1198 const struct kx022a_chip_info kx132acr_chip_info = { 1199 .name = "kx132acr-lbz", 1200 .regmap_config = &kx022a_regmap_config, 1201 .channels = kx022a_channels, 1202 .num_channels = ARRAY_SIZE(kx022a_channels), 1203 .fifo_length = KX022A_FIFO_LENGTH, 1204 .who = KX022A_REG_WHO, 1205 .id = KX132ACR_LBZ_ID, 1206 .cntl = KX022A_REG_CNTL, 1207 .cntl2 = KX022A_REG_CNTL2, 1208 .odcntl = KX022A_REG_ODCNTL, 1209 .buf_cntl1 = KX022A_REG_BUF_CNTL1, 1210 .buf_cntl2 = KX022A_REG_BUF_CNTL2, 1211 .buf_clear = KX022A_REG_BUF_CLEAR, 1212 .buf_status1 = KX022A_REG_BUF_STATUS_1, 1213 .buf_read = KX022A_REG_BUF_READ, 1214 .inc1 = KX022A_REG_INC1, 1215 .inc4 = KX022A_REG_INC4, 1216 .inc5 = KX022A_REG_INC5, 1217 .inc6 = KX022A_REG_INC6, 1218 .xout_l = KX022A_REG_XOUT_L, 1219 .get_fifo_bytes_available = kx022a_get_fifo_bytes_available, 1220 }; 1221 EXPORT_SYMBOL_NS_GPL(kx132acr_chip_info, IIO_KX022A); 1222 1223 int kx022a_probe_internal(struct device *dev, const struct kx022a_chip_info *chip_info) 1224 { 1225 static const char * const regulator_names[] = {"io-vdd", "vdd"}; 1226 struct iio_trigger *indio_trig; 1227 struct fwnode_handle *fwnode; 1228 struct kx022a_data *data; 1229 struct regmap *regmap; 1230 unsigned int chip_id; 1231 struct iio_dev *idev; 1232 int ret, irq; 1233 char *name; 1234 1235 regmap = dev_get_regmap(dev, NULL); 1236 if (!regmap) { 1237 dev_err(dev, "no regmap\n"); 1238 return -EINVAL; 1239 } 1240 1241 fwnode = dev_fwnode(dev); 1242 if (!fwnode) 1243 return -ENODEV; 1244 1245 idev = devm_iio_device_alloc(dev, sizeof(*data)); 1246 if (!idev) 1247 return -ENOMEM; 1248 1249 data = iio_priv(idev); 1250 data->chip_info = chip_info; 1251 1252 /* 1253 * VDD is the analog and digital domain voltage supply and 1254 * IO_VDD is the digital I/O voltage supply. 1255 */ 1256 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulator_names), 1257 regulator_names); 1258 if (ret && ret != -ENODEV) 1259 return dev_err_probe(dev, ret, "failed to enable regulator\n"); 1260 1261 ret = regmap_read(regmap, chip_info->who, &chip_id); 1262 if (ret) 1263 return dev_err_probe(dev, ret, "Failed to access sensor\n"); 1264 1265 if (chip_id != chip_info->id) 1266 dev_warn(dev, "unknown device 0x%x\n", chip_id); 1267 1268 irq = fwnode_irq_get_byname(fwnode, "INT1"); 1269 if (irq > 0) { 1270 data->inc_reg = chip_info->inc1; 1271 data->ien_reg = chip_info->inc4; 1272 } else { 1273 irq = fwnode_irq_get_byname(fwnode, "INT2"); 1274 if (irq < 0) 1275 return dev_err_probe(dev, irq, "No suitable IRQ\n"); 1276 1277 data->inc_reg = chip_info->inc5; 1278 data->ien_reg = chip_info->inc6; 1279 } 1280 1281 data->regmap = regmap; 1282 data->dev = dev; 1283 data->irq = irq; 1284 data->odr_ns = KX022A_DEFAULT_PERIOD_NS; 1285 mutex_init(&data->mutex); 1286 1287 idev->channels = chip_info->channels; 1288 idev->num_channels = chip_info->num_channels; 1289 idev->name = chip_info->name; 1290 idev->info = &kx022a_info; 1291 idev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; 1292 idev->available_scan_masks = kx022a_scan_masks; 1293 1294 /* Read the mounting matrix, if present */ 1295 ret = iio_read_mount_matrix(dev, &data->orientation); 1296 if (ret) 1297 return ret; 1298 1299 /* The sensor must be turned off for configuration */ 1300 ret = kx022a_turn_off_lock(data); 1301 if (ret) 1302 return ret; 1303 1304 ret = kx022a_chip_init(data); 1305 if (ret) { 1306 mutex_unlock(&data->mutex); 1307 return ret; 1308 } 1309 1310 ret = kx022a_turn_on_unlock(data); 1311 if (ret) 1312 return ret; 1313 1314 ret = devm_iio_triggered_buffer_setup_ext(dev, idev, 1315 &iio_pollfunc_store_time, 1316 kx022a_trigger_handler, 1317 IIO_BUFFER_DIRECTION_IN, 1318 &kx022a_buffer_ops, 1319 kx022a_fifo_attributes); 1320 1321 if (ret) 1322 return dev_err_probe(data->dev, ret, 1323 "iio_triggered_buffer_setup_ext FAIL\n"); 1324 indio_trig = devm_iio_trigger_alloc(dev, "%sdata-rdy-dev%d", idev->name, 1325 iio_device_id(idev)); 1326 if (!indio_trig) 1327 return -ENOMEM; 1328 1329 data->trig = indio_trig; 1330 1331 indio_trig->ops = &kx022a_trigger_ops; 1332 iio_trigger_set_drvdata(indio_trig, data); 1333 1334 /* 1335 * No need to check for NULL. request_threaded_irq() defaults to 1336 * dev_name() should the alloc fail. 1337 */ 1338 name = devm_kasprintf(data->dev, GFP_KERNEL, "%s-kx022a", 1339 dev_name(data->dev)); 1340 1341 ret = devm_request_threaded_irq(data->dev, irq, kx022a_irq_handler, 1342 &kx022a_irq_thread_handler, 1343 IRQF_ONESHOT, name, idev); 1344 if (ret) 1345 return dev_err_probe(data->dev, ret, "Could not request IRQ\n"); 1346 1347 ret = devm_iio_trigger_register(dev, indio_trig); 1348 if (ret) 1349 return dev_err_probe(data->dev, ret, 1350 "Trigger registration failed\n"); 1351 1352 ret = devm_iio_device_register(data->dev, idev); 1353 if (ret < 0) 1354 return dev_err_probe(dev, ret, 1355 "Unable to register iio device\n"); 1356 1357 return ret; 1358 } 1359 EXPORT_SYMBOL_NS_GPL(kx022a_probe_internal, IIO_KX022A); 1360 1361 MODULE_DESCRIPTION("ROHM/Kionix KX022A accelerometer driver"); 1362 MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); 1363 MODULE_LICENSE("GPL"); 1364