1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell Octeon EP (EndPoint) Ethernet Driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef _OCTEP_TX_H_ 9 #define _OCTEP_TX_H_ 10 11 #define IQ_SEND_OK 0 12 #define IQ_SEND_STOP 1 13 #define IQ_SEND_FAILED -1 14 15 #define TX_BUFTYPE_NONE 0 16 #define TX_BUFTYPE_NET 1 17 #define TX_BUFTYPE_NET_SG 2 18 #define NUM_TX_BUFTYPES 3 19 20 /* Hardware format for Scatter/Gather list 21 * 22 * 63 48|47 32|31 16|15 0 23 * ----------------------------------------- 24 * | Len 0 | Len 1 | Len 2 | Len 3 | 25 * ----------------------------------------- 26 * | Ptr 0 | 27 * ----------------------------------------- 28 * | Ptr 1 | 29 * ----------------------------------------- 30 * | Ptr 2 | 31 * ----------------------------------------- 32 * | Ptr 3 | 33 * ----------------------------------------- 34 */ 35 struct octep_tx_sglist_desc { 36 u16 len[4]; 37 dma_addr_t dma_ptr[4]; 38 }; 39 static_assert(sizeof(struct octep_tx_sglist_desc) == 40); 40 41 /* Each Scatter/Gather entry sent to hardwar hold four pointers. 42 * So, number of entries required is (MAX_SKB_FRAGS + 1)/4, where '+1' 43 * is for main skb which also goes as a gather buffer to Octeon hardware. 44 * To allocate sufficient SGLIST entries for a packet with max fragments, 45 * align by adding 3 before calcuating max SGLIST entries per packet. 46 */ 47 #define OCTEP_SGLIST_ENTRIES_PER_PKT ((MAX_SKB_FRAGS + 1 + 3) / 4) 48 #define OCTEP_SGLIST_SIZE_PER_PKT \ 49 (OCTEP_SGLIST_ENTRIES_PER_PKT * sizeof(struct octep_tx_sglist_desc)) 50 51 struct octep_tx_buffer { 52 struct sk_buff *skb; 53 dma_addr_t dma; 54 struct octep_tx_sglist_desc *sglist; 55 dma_addr_t sglist_dma; 56 u8 gather; 57 }; 58 59 #define OCTEP_IQ_TXBUFF_INFO_SIZE (sizeof(struct octep_tx_buffer)) 60 61 /* Hardware interface Tx statistics */ 62 struct octep_iface_tx_stats { 63 /* Packets dropped due to excessive collisions */ 64 u64 xscol; 65 66 /* Packets dropped due to excessive deferral */ 67 u64 xsdef; 68 69 /* Packets sent that experienced multiple collisions before successful 70 * transmission 71 */ 72 u64 mcol; 73 74 /* Packets sent that experienced a single collision before successful 75 * transmission 76 */ 77 u64 scol; 78 79 /* Total octets sent on the interface */ 80 u64 octs; 81 82 /* Total frames sent on the interface */ 83 u64 pkts; 84 85 /* Packets sent with an octet count < 64 */ 86 u64 hist_lt64; 87 88 /* Packets sent with an octet count == 64 */ 89 u64 hist_eq64; 90 91 /* Packets sent with an octet count of 65–127 */ 92 u64 hist_65to127; 93 94 /* Packets sent with an octet count of 128–255 */ 95 u64 hist_128to255; 96 97 /* Packets sent with an octet count of 256–511 */ 98 u64 hist_256to511; 99 100 /* Packets sent with an octet count of 512–1023 */ 101 u64 hist_512to1023; 102 103 /* Packets sent with an octet count of 1024-1518 */ 104 u64 hist_1024to1518; 105 106 /* Packets sent with an octet count of > 1518 */ 107 u64 hist_gt1518; 108 109 /* Packets sent to a broadcast DMAC */ 110 u64 bcst; 111 112 /* Packets sent to the multicast DMAC */ 113 u64 mcst; 114 115 /* Packets sent that experienced a transmit underflow and were 116 * truncated 117 */ 118 u64 undflw; 119 120 /* Control/PAUSE packets sent */ 121 u64 ctl; 122 }; 123 124 /* Input Queue statistics. Each input queue has four stats fields. */ 125 struct octep_iq_stats { 126 /* Instructions posted to this queue. */ 127 u64 instr_posted; 128 129 /* Instructions copied by hardware for processing. */ 130 u64 instr_completed; 131 132 /* Instructions that could not be processed. */ 133 u64 instr_dropped; 134 135 /* Bytes sent through this queue. */ 136 u64 bytes_sent; 137 138 /* Gather entries sent through this queue. */ 139 u64 sgentry_sent; 140 141 /* Number of transmit failures due to TX_BUSY */ 142 u64 tx_busy; 143 144 /* Number of times the queue is restarted */ 145 u64 restart_cnt; 146 }; 147 148 /* The instruction (input) queue. 149 * The input queue is used to post raw (instruction) mode data or packet 150 * data to Octeon device from the host. Each input queue (up to 4) for 151 * a Octeon device has one such structure to represent it. 152 */ 153 struct octep_iq { 154 u32 q_no; 155 156 struct octep_device *octep_dev; 157 struct net_device *netdev; 158 struct device *dev; 159 struct netdev_queue *netdev_q; 160 161 /* Index in input ring where driver should write the next packet */ 162 u16 host_write_index; 163 164 /* Index in input ring where Octeon is expected to read next packet */ 165 u16 octep_read_index; 166 167 /* This index aids in finding the window in the queue where Octeon 168 * has read the commands. 169 */ 170 u16 flush_index; 171 172 /* Statistics for this input queue. */ 173 struct octep_iq_stats stats; 174 175 /* This field keeps track of the instructions pending in this queue. */ 176 atomic_t instr_pending; 177 178 /* Pointer to the Virtual Base addr of the input ring. */ 179 struct octep_tx_desc_hw *desc_ring; 180 181 /* DMA mapped base address of the input descriptor ring. */ 182 dma_addr_t desc_ring_dma; 183 184 /* Info of Tx buffers pending completion. */ 185 struct octep_tx_buffer *buff_info; 186 187 /* Base pointer to Scatter/Gather lists for all ring descriptors. */ 188 struct octep_tx_sglist_desc *sglist; 189 190 /* DMA mapped addr of Scatter Gather Lists */ 191 dma_addr_t sglist_dma; 192 193 /* Octeon doorbell register for the ring. */ 194 u8 __iomem *doorbell_reg; 195 196 /* Octeon instruction count register for this ring. */ 197 u8 __iomem *inst_cnt_reg; 198 199 /* interrupt level register for this ring */ 200 u8 __iomem *intr_lvl_reg; 201 202 /* Maximum no. of instructions in this queue. */ 203 u32 max_count; 204 u32 ring_size_mask; 205 206 u32 pkt_in_done; 207 u32 pkts_processed; 208 209 u32 status; 210 211 /* Number of instructions pending to be posted to Octeon. */ 212 u32 fill_cnt; 213 214 /* The max. number of instructions that can be held pending by the 215 * driver before ringing doorbell. 216 */ 217 u32 fill_threshold; 218 }; 219 220 /* Hardware Tx Instruction Header */ 221 struct octep_instr_hdr { 222 /* Data Len */ 223 u64 tlen:16; 224 225 /* Reserved */ 226 u64 rsvd:20; 227 228 /* PKIND for SDP */ 229 u64 pkind:6; 230 231 /* Front Data size */ 232 u64 fsz:6; 233 234 /* No. of entries in gather list */ 235 u64 gsz:14; 236 237 /* Gather indicator 1=gather*/ 238 u64 gather:1; 239 240 /* Reserved3 */ 241 u64 reserved3:1; 242 }; 243 static_assert(sizeof(struct octep_instr_hdr) == 8); 244 245 /* Hardware Tx completion response header */ 246 struct octep_instr_resp_hdr { 247 /* Request ID */ 248 u64 rid:16; 249 250 /* PCIe port to use for response */ 251 u64 pcie_port:3; 252 253 /* Scatter indicator 1=scatter */ 254 u64 scatter:1; 255 256 /* Size of Expected result OR no. of entries in scatter list */ 257 u64 rlenssz:14; 258 259 /* Desired destination port for result */ 260 u64 dport:6; 261 262 /* Opcode Specific parameters */ 263 u64 param:8; 264 265 /* Opcode for the return packet */ 266 u64 opcode:16; 267 }; 268 static_assert(sizeof(struct octep_instr_hdr) == 8); 269 270 /* 64-byte Tx instruction format. 271 * Format of instruction for a 64-byte mode input queue. 272 * 273 * only first 16-bytes (dptr and ih) are mandatory; rest are optional 274 * and filled by the driver based on firmware/hardware capabilities. 275 * These optional headers together called Front Data and its size is 276 * described by ih->fsz. 277 */ 278 struct octep_tx_desc_hw { 279 /* Pointer where the input data is available. */ 280 u64 dptr; 281 282 /* Instruction Header. */ 283 union { 284 struct octep_instr_hdr ih; 285 u64 ih64; 286 }; 287 288 /* Pointer where the response for a RAW mode packet will be written 289 * by Octeon. 290 */ 291 u64 rptr; 292 293 /* Input Instruction Response Header. */ 294 struct octep_instr_resp_hdr irh; 295 296 /* Additional headers available in a 64-byte instruction. */ 297 u64 exhdr[4]; 298 }; 299 static_assert(sizeof(struct octep_tx_desc_hw) == 64); 300 301 #define OCTEP_IQ_DESC_SIZE (sizeof(struct octep_tx_desc_hw)) 302 #endif /* _OCTEP_TX_H_ */ 303