1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/msi.h> 8 #include <linux/pci.h> 9 #include <linux/firmware.h> 10 #include <linux/of.h> 11 #include <linux/of_address.h> 12 #include <linux/ioport.h> 13 14 #include "core.h" 15 #include "debug.h" 16 #include "mhi.h" 17 #include "pci.h" 18 #include "pcic.h" 19 20 #define MHI_TIMEOUT_DEFAULT_MS 20000 21 #define RDDM_DUMP_SIZE 0x420000 22 23 static struct mhi_channel_config ath11k_mhi_channels_qca6390[] = { 24 { 25 .num = 0, 26 .name = "LOOPBACK", 27 .num_elements = 32, 28 .event_ring = 0, 29 .dir = DMA_TO_DEVICE, 30 .ee_mask = 0x4, 31 .pollcfg = 0, 32 .doorbell = MHI_DB_BRST_DISABLE, 33 .lpm_notify = false, 34 .offload_channel = false, 35 .doorbell_mode_switch = false, 36 .auto_queue = false, 37 }, 38 { 39 .num = 1, 40 .name = "LOOPBACK", 41 .num_elements = 32, 42 .event_ring = 0, 43 .dir = DMA_FROM_DEVICE, 44 .ee_mask = 0x4, 45 .pollcfg = 0, 46 .doorbell = MHI_DB_BRST_DISABLE, 47 .lpm_notify = false, 48 .offload_channel = false, 49 .doorbell_mode_switch = false, 50 .auto_queue = false, 51 }, 52 { 53 .num = 20, 54 .name = "IPCR", 55 .num_elements = 64, 56 .event_ring = 1, 57 .dir = DMA_TO_DEVICE, 58 .ee_mask = 0x4, 59 .pollcfg = 0, 60 .doorbell = MHI_DB_BRST_DISABLE, 61 .lpm_notify = false, 62 .offload_channel = false, 63 .doorbell_mode_switch = false, 64 .auto_queue = false, 65 }, 66 { 67 .num = 21, 68 .name = "IPCR", 69 .num_elements = 64, 70 .event_ring = 1, 71 .dir = DMA_FROM_DEVICE, 72 .ee_mask = 0x4, 73 .pollcfg = 0, 74 .doorbell = MHI_DB_BRST_DISABLE, 75 .lpm_notify = false, 76 .offload_channel = false, 77 .doorbell_mode_switch = false, 78 .auto_queue = true, 79 }, 80 }; 81 82 static struct mhi_event_config ath11k_mhi_events_qca6390[] = { 83 { 84 .num_elements = 32, 85 .irq_moderation_ms = 0, 86 .irq = 1, 87 .mode = MHI_DB_BRST_DISABLE, 88 .data_type = MHI_ER_CTRL, 89 .hardware_event = false, 90 .client_managed = false, 91 .offload_channel = false, 92 }, 93 { 94 .num_elements = 256, 95 .irq_moderation_ms = 1, 96 .irq = 2, 97 .mode = MHI_DB_BRST_DISABLE, 98 .priority = 1, 99 .hardware_event = false, 100 .client_managed = false, 101 .offload_channel = false, 102 }, 103 }; 104 105 static struct mhi_controller_config ath11k_mhi_config_qca6390 = { 106 .max_channels = 128, 107 .timeout_ms = 2000, 108 .use_bounce_buf = false, 109 .buf_len = 0, 110 .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qca6390), 111 .ch_cfg = ath11k_mhi_channels_qca6390, 112 .num_events = ARRAY_SIZE(ath11k_mhi_events_qca6390), 113 .event_cfg = ath11k_mhi_events_qca6390, 114 }; 115 116 static struct mhi_channel_config ath11k_mhi_channels_qcn9074[] = { 117 { 118 .num = 0, 119 .name = "LOOPBACK", 120 .num_elements = 32, 121 .event_ring = 1, 122 .dir = DMA_TO_DEVICE, 123 .ee_mask = 0x14, 124 .pollcfg = 0, 125 .doorbell = MHI_DB_BRST_DISABLE, 126 .lpm_notify = false, 127 .offload_channel = false, 128 .doorbell_mode_switch = false, 129 .auto_queue = false, 130 }, 131 { 132 .num = 1, 133 .name = "LOOPBACK", 134 .num_elements = 32, 135 .event_ring = 1, 136 .dir = DMA_FROM_DEVICE, 137 .ee_mask = 0x14, 138 .pollcfg = 0, 139 .doorbell = MHI_DB_BRST_DISABLE, 140 .lpm_notify = false, 141 .offload_channel = false, 142 .doorbell_mode_switch = false, 143 .auto_queue = false, 144 }, 145 { 146 .num = 20, 147 .name = "IPCR", 148 .num_elements = 32, 149 .event_ring = 1, 150 .dir = DMA_TO_DEVICE, 151 .ee_mask = 0x14, 152 .pollcfg = 0, 153 .doorbell = MHI_DB_BRST_DISABLE, 154 .lpm_notify = false, 155 .offload_channel = false, 156 .doorbell_mode_switch = false, 157 .auto_queue = false, 158 }, 159 { 160 .num = 21, 161 .name = "IPCR", 162 .num_elements = 32, 163 .event_ring = 1, 164 .dir = DMA_FROM_DEVICE, 165 .ee_mask = 0x14, 166 .pollcfg = 0, 167 .doorbell = MHI_DB_BRST_DISABLE, 168 .lpm_notify = false, 169 .offload_channel = false, 170 .doorbell_mode_switch = false, 171 .auto_queue = true, 172 }, 173 }; 174 175 static struct mhi_event_config ath11k_mhi_events_qcn9074[] = { 176 { 177 .num_elements = 32, 178 .irq_moderation_ms = 0, 179 .irq = 1, 180 .data_type = MHI_ER_CTRL, 181 .mode = MHI_DB_BRST_DISABLE, 182 .hardware_event = false, 183 .client_managed = false, 184 .offload_channel = false, 185 }, 186 { 187 .num_elements = 256, 188 .irq_moderation_ms = 1, 189 .irq = 2, 190 .mode = MHI_DB_BRST_DISABLE, 191 .priority = 1, 192 .hardware_event = false, 193 .client_managed = false, 194 .offload_channel = false, 195 }, 196 }; 197 198 static struct mhi_controller_config ath11k_mhi_config_qcn9074 = { 199 .max_channels = 30, 200 .timeout_ms = 10000, 201 .use_bounce_buf = false, 202 .buf_len = 0, 203 .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qcn9074), 204 .ch_cfg = ath11k_mhi_channels_qcn9074, 205 .num_events = ARRAY_SIZE(ath11k_mhi_events_qcn9074), 206 .event_cfg = ath11k_mhi_events_qcn9074, 207 }; 208 209 void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab) 210 { 211 u32 val; 212 213 val = ath11k_pcic_read32(ab, MHISTATUS); 214 215 ath11k_dbg(ab, ATH11K_DBG_PCI, "mhistatus 0x%x\n", val); 216 217 /* Observed on QCA6390 that after SOC_GLOBAL_RESET, MHISTATUS 218 * has SYSERR bit set and thus need to set MHICTRL_RESET 219 * to clear SYSERR. 220 */ 221 ath11k_pcic_write32(ab, MHICTRL, MHICTRL_RESET_MASK); 222 223 mdelay(10); 224 } 225 226 static void ath11k_mhi_reset_txvecdb(struct ath11k_base *ab) 227 { 228 ath11k_pcic_write32(ab, PCIE_TXVECDB, 0); 229 } 230 231 static void ath11k_mhi_reset_txvecstatus(struct ath11k_base *ab) 232 { 233 ath11k_pcic_write32(ab, PCIE_TXVECSTATUS, 0); 234 } 235 236 static void ath11k_mhi_reset_rxvecdb(struct ath11k_base *ab) 237 { 238 ath11k_pcic_write32(ab, PCIE_RXVECDB, 0); 239 } 240 241 static void ath11k_mhi_reset_rxvecstatus(struct ath11k_base *ab) 242 { 243 ath11k_pcic_write32(ab, PCIE_RXVECSTATUS, 0); 244 } 245 246 void ath11k_mhi_clear_vector(struct ath11k_base *ab) 247 { 248 ath11k_mhi_reset_txvecdb(ab); 249 ath11k_mhi_reset_txvecstatus(ab); 250 ath11k_mhi_reset_rxvecdb(ab); 251 ath11k_mhi_reset_rxvecstatus(ab); 252 } 253 254 static int ath11k_mhi_get_msi(struct ath11k_pci *ab_pci) 255 { 256 struct ath11k_base *ab = ab_pci->ab; 257 u32 user_base_data, base_vector; 258 int ret, num_vectors, i; 259 int *irq; 260 unsigned int msi_data; 261 262 ret = ath11k_pcic_get_user_msi_assignment(ab, "MHI", &num_vectors, 263 &user_base_data, &base_vector); 264 if (ret) 265 return ret; 266 267 ath11k_dbg(ab, ATH11K_DBG_PCI, "num_vectors %d base_vector %d\n", 268 num_vectors, base_vector); 269 270 irq = kcalloc(num_vectors, sizeof(int), GFP_KERNEL); 271 if (!irq) 272 return -ENOMEM; 273 274 for (i = 0; i < num_vectors; i++) { 275 msi_data = base_vector; 276 277 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags)) 278 msi_data += i; 279 280 irq[i] = ath11k_pci_get_msi_irq(ab, msi_data); 281 } 282 283 ab_pci->mhi_ctrl->irq = irq; 284 ab_pci->mhi_ctrl->nr_irqs = num_vectors; 285 286 return 0; 287 } 288 289 static int ath11k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl) 290 { 291 return 0; 292 } 293 294 static void ath11k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl) 295 { 296 } 297 298 static char *ath11k_mhi_op_callback_to_str(enum mhi_callback reason) 299 { 300 switch (reason) { 301 case MHI_CB_IDLE: 302 return "MHI_CB_IDLE"; 303 case MHI_CB_PENDING_DATA: 304 return "MHI_CB_PENDING_DATA"; 305 case MHI_CB_LPM_ENTER: 306 return "MHI_CB_LPM_ENTER"; 307 case MHI_CB_LPM_EXIT: 308 return "MHI_CB_LPM_EXIT"; 309 case MHI_CB_EE_RDDM: 310 return "MHI_CB_EE_RDDM"; 311 case MHI_CB_EE_MISSION_MODE: 312 return "MHI_CB_EE_MISSION_MODE"; 313 case MHI_CB_SYS_ERROR: 314 return "MHI_CB_SYS_ERROR"; 315 case MHI_CB_FATAL_ERROR: 316 return "MHI_CB_FATAL_ERROR"; 317 case MHI_CB_BW_REQ: 318 return "MHI_CB_BW_REQ"; 319 default: 320 return "UNKNOWN"; 321 } 322 }; 323 324 static void ath11k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl, 325 enum mhi_callback cb) 326 { 327 struct ath11k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev); 328 329 ath11k_dbg(ab, ATH11K_DBG_BOOT, "notify status reason %s\n", 330 ath11k_mhi_op_callback_to_str(cb)); 331 332 switch (cb) { 333 case MHI_CB_SYS_ERROR: 334 ath11k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n"); 335 break; 336 case MHI_CB_EE_RDDM: 337 ath11k_warn(ab, "firmware crashed: MHI_CB_EE_RDDM\n"); 338 if (!(test_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags))) 339 queue_work(ab->workqueue_aux, &ab->reset_work); 340 break; 341 default: 342 break; 343 } 344 } 345 346 static int ath11k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl, 347 void __iomem *addr, 348 u32 *out) 349 { 350 *out = readl(addr); 351 352 return 0; 353 } 354 355 static void ath11k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl, 356 void __iomem *addr, 357 u32 val) 358 { 359 writel(val, addr); 360 } 361 362 static int ath11k_mhi_read_addr_from_dt(struct mhi_controller *mhi_ctrl) 363 { 364 struct device_node *np; 365 struct resource res; 366 int ret; 367 368 np = of_find_node_by_type(NULL, "memory"); 369 if (!np) 370 return -ENOENT; 371 372 ret = of_address_to_resource(np, 0, &res); 373 of_node_put(np); 374 if (ret) 375 return ret; 376 377 mhi_ctrl->iova_start = res.start + 0x1000000; 378 mhi_ctrl->iova_stop = res.end; 379 380 return 0; 381 } 382 383 int ath11k_mhi_register(struct ath11k_pci *ab_pci) 384 { 385 struct ath11k_base *ab = ab_pci->ab; 386 struct mhi_controller *mhi_ctrl; 387 struct mhi_controller_config *ath11k_mhi_config; 388 int ret; 389 390 mhi_ctrl = mhi_alloc_controller(); 391 if (!mhi_ctrl) 392 return -ENOMEM; 393 394 ab_pci->mhi_ctrl = mhi_ctrl; 395 mhi_ctrl->cntrl_dev = ab->dev; 396 mhi_ctrl->regs = ab->mem; 397 mhi_ctrl->reg_len = ab->mem_len; 398 399 if (ab->fw.amss_data && ab->fw.amss_len > 0) { 400 /* use MHI firmware file from firmware-N.bin */ 401 mhi_ctrl->fw_data = ab->fw.amss_data; 402 mhi_ctrl->fw_sz = ab->fw.amss_len; 403 } else { 404 /* use the old separate mhi.bin MHI firmware file */ 405 ath11k_core_create_firmware_path(ab, ATH11K_AMSS_FILE, 406 ab_pci->amss_path, 407 sizeof(ab_pci->amss_path)); 408 mhi_ctrl->fw_image = ab_pci->amss_path; 409 } 410 411 ret = ath11k_mhi_get_msi(ab_pci); 412 if (ret) { 413 ath11k_err(ab, "failed to get msi for mhi\n"); 414 goto free_controller; 415 } 416 417 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags)) 418 mhi_ctrl->irq_flags = IRQF_SHARED | IRQF_NOBALANCING; 419 420 if (test_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags)) { 421 ret = ath11k_mhi_read_addr_from_dt(mhi_ctrl); 422 if (ret < 0) 423 goto free_controller; 424 } else { 425 mhi_ctrl->iova_start = 0; 426 mhi_ctrl->iova_stop = 0xFFFFFFFF; 427 } 428 429 mhi_ctrl->rddm_size = RDDM_DUMP_SIZE; 430 mhi_ctrl->sbl_size = SZ_512K; 431 mhi_ctrl->seg_len = SZ_512K; 432 mhi_ctrl->fbc_download = true; 433 mhi_ctrl->runtime_get = ath11k_mhi_op_runtime_get; 434 mhi_ctrl->runtime_put = ath11k_mhi_op_runtime_put; 435 mhi_ctrl->status_cb = ath11k_mhi_op_status_cb; 436 mhi_ctrl->read_reg = ath11k_mhi_op_read_reg; 437 mhi_ctrl->write_reg = ath11k_mhi_op_write_reg; 438 439 switch (ab->hw_rev) { 440 case ATH11K_HW_QCN9074_HW10: 441 ath11k_mhi_config = &ath11k_mhi_config_qcn9074; 442 break; 443 case ATH11K_HW_QCA6390_HW20: 444 case ATH11K_HW_WCN6855_HW20: 445 case ATH11K_HW_WCN6855_HW21: 446 ath11k_mhi_config = &ath11k_mhi_config_qca6390; 447 break; 448 default: 449 ath11k_err(ab, "failed assign mhi_config for unknown hw rev %d\n", 450 ab->hw_rev); 451 ret = -EINVAL; 452 goto free_controller; 453 } 454 455 ret = mhi_register_controller(mhi_ctrl, ath11k_mhi_config); 456 if (ret) { 457 ath11k_err(ab, "failed to register to mhi bus, err = %d\n", ret); 458 goto free_controller; 459 } 460 461 return 0; 462 463 free_controller: 464 mhi_free_controller(mhi_ctrl); 465 ab_pci->mhi_ctrl = NULL; 466 return ret; 467 } 468 469 void ath11k_mhi_unregister(struct ath11k_pci *ab_pci) 470 { 471 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl; 472 473 mhi_unregister_controller(mhi_ctrl); 474 kfree(mhi_ctrl->irq); 475 mhi_free_controller(mhi_ctrl); 476 } 477 478 int ath11k_mhi_start(struct ath11k_pci *ab_pci) 479 { 480 struct ath11k_base *ab = ab_pci->ab; 481 int ret; 482 483 ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS; 484 485 ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl); 486 if (ret) { 487 ath11k_warn(ab, "failed to prepare mhi: %d", ret); 488 return ret; 489 } 490 491 ret = mhi_sync_power_up(ab_pci->mhi_ctrl); 492 if (ret) { 493 ath11k_warn(ab, "failed to power up mhi: %d", ret); 494 return ret; 495 } 496 497 return 0; 498 } 499 500 void ath11k_mhi_stop(struct ath11k_pci *ab_pci) 501 { 502 mhi_power_down(ab_pci->mhi_ctrl, true); 503 mhi_unprepare_after_power_down(ab_pci->mhi_ctrl); 504 } 505 506 int ath11k_mhi_suspend(struct ath11k_pci *ab_pci) 507 { 508 struct ath11k_base *ab = ab_pci->ab; 509 int ret; 510 511 ret = mhi_pm_suspend(ab_pci->mhi_ctrl); 512 if (ret) { 513 ath11k_warn(ab, "failed to suspend mhi: %d", ret); 514 return ret; 515 } 516 517 return 0; 518 } 519 520 int ath11k_mhi_resume(struct ath11k_pci *ab_pci) 521 { 522 struct ath11k_base *ab = ab_pci->ab; 523 int ret; 524 525 /* Do force MHI resume as some devices like QCA6390, WCN6855 526 * are not in M3 state but they are functional. So just ignore 527 * the MHI state while resuming. 528 */ 529 ret = mhi_pm_resume_force(ab_pci->mhi_ctrl); 530 if (ret) { 531 ath11k_warn(ab, "failed to resume mhi: %d", ret); 532 return ret; 533 } 534 535 return 0; 536 } 537