| 8535df5d | 18-Dec-2025 |
Uwe Kleine-König <u.kleine-koenig@baylibre.com> |
bus: mhi: host: Use bus callbacks for .probe() and .remove()
These are nearly identical to the driver callbacks, the only relevant difference is that the bus remove method returns void (instead of a
bus: mhi: host: Use bus callbacks for .probe() and .remove()
These are nearly identical to the driver callbacks, the only relevant difference is that the bus remove method returns void (instead of an int where the value is ignored).
The objective is to get rid of users of struct device_driver callbacks .probe(), and .remove() to eventually remove these.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Link: https://patch.msgid.link/e8032b3c2a8953a4a2b84dfa79a260c35f1d71b7.1766090211.git.ukleinek@kernel.org
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| 4a9ba211 | 18-Dec-2025 |
Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> |
bus: mhi: host: Drop the auto_queue support
Now that the only user of the 'auto_queue' feature, (QRTR) has been converted to manage the buffers on its own, drop the code related to it.
Signed-off-b
bus: mhi: host: Drop the auto_queue support
Now that the only user of the 'auto_queue' feature, (QRTR) has been converted to manage the buffers on its own, drop the code related to it.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Reviewed-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Link: https://patch.msgid.link/20251218-qrtr-fix-v2-2-c7499bfcfbe0@oss.qualcomm.com
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| 51731792 | 18-Dec-2025 |
Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> |
net: qrtr: Drop the MHI auto_queue feature for IPCR DL channels
MHI stack offers the 'auto_queue' feature, which allows the MHI stack to auto queue the buffers for the RX path (DL channel). Though t
net: qrtr: Drop the MHI auto_queue feature for IPCR DL channels
MHI stack offers the 'auto_queue' feature, which allows the MHI stack to auto queue the buffers for the RX path (DL channel). Though this feature simplifies the client driver design, it introduces race between the client drivers and the MHI stack. For instance, with auto_queue, the 'dl_callback' for the DL channel may get called before the client driver is fully probed. This means, by the time the dl_callback gets called, the client driver's structures might not be initialized, leading to NULL ptr dereference.
Currently, the drivers have to workaround this issue by initializing the internal structures before calling mhi_prepare_for_transfer_autoqueue(). But even so, there is a chance that the client driver's internal code path may call the MHI queue APIs before mhi_prepare_for_transfer_autoqueue() is called, leading to similar NULL ptr dereference. This issue has been reported on the Qcom X1E80100 CRD machines affecting boot.
So to properly fix all these races, drop the MHI 'auto_queue' feature altogether and let the client driver (QRTR) manage the RX buffers manually. In the QRTR driver, queue the RX buffers based on the ring length during probe and recycle the buffers in 'dl_callback' once they are consumed. This also warrants removing the setting of 'auto_queue' flag from controller drivers.
Currently, this 'auto_queue' feature is only enabled for IPCR DL channel. So only the QRTR client driver requires the modification.
Fixes: 227fee5fc99e ("bus: mhi: core: Add an API for auto queueing buffers for DL channel") Fixes: 68a838b84eff ("net: qrtr: start MHI channel after endpoit creation") Reported-by: Johan Hovold <johan@kernel.org> Closes: https://lore.kernel.org/linux-arm-msm/ZyTtVdkCCES0lkl4@hovoldconsulting.com Suggested-by: Chris Lew <quic_clew@quicinc.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Reviewed-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Acked-by: Jeff Johnson <jjohnson@kernel.org> # drivers/net/wireless/ath/... Acked-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Acked-by: Paolo Abeni <pabeni@redhat.com> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20251218-qrtr-fix-v2-1-c7499bfcfbe0@oss.qualcomm.com
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| ac35e04f | 19-Nov-2025 |
Slark Xiao <slark_xiao@163.com> |
bus: mhi: host: pci_generic: Add Foxconn T99W760 modem
T99W760 modem is based on Qualcomm SDX35 chipset. It uses the same channel configurations of Foxconn SDX61 modem. Hence, add support for it by
bus: mhi: host: pci_generic: Add Foxconn T99W760 modem
T99W760 modem is based on Qualcomm SDX35 chipset. It uses the same channel configurations of Foxconn SDX61 modem. Hence, add support for it by reusing the 'modem_foxconn_sdx61_config' config structure.
The EDL firmware for this modem has been pushed to linux-firmware.
Signed-off-by: Slark Xiao <slark_xiao@163.com> [mani: reworded description] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Link: https://patch.msgid.link/20251119105615.48295-2-slark_xiao@163.com
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| 54c67740 | 12-Sep-2025 |
Vivek Pernamitta <quic_vpernami@quicinc.com> |
bus: mhi: host: pci_generic: Set DMA mask for VFs
VFs in devices like QDU100 are capable of accessing host memory up to 40 bits, compared to 32 bits used by PFs and other non-SR-IOV capable MHI devi
bus: mhi: host: pci_generic: Set DMA mask for VFs
VFs in devices like QDU100 are capable of accessing host memory up to 40 bits, compared to 32 bits used by PFs and other non-SR-IOV capable MHI devices.
To support this, configure `dma_mask` independently for PFs and VFs, by introducing a new 'vf_dma_data_width' member in 'mhi_pci_dev_info' struct and set it to 40 for QDU100.
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com> [mani: reworded subject and description] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Link: https://patch.msgid.link/20250912-uevent_vdev_next-20250911-v4-6-fa2f6ccd301b@quicinc.com
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| aa1a0e93 | 12-Sep-2025 |
Vivek Pernamitta <quic_vpernami@quicinc.com> |
bus: mhi: core: Improve mhi_sync_power_up handling for SYS_ERR state
Allow mhi_sync_power_up to handle SYS_ERR during power-up, reboot, or recovery. This is to avoid premature exit when MHI_PM_IN_ER
bus: mhi: core: Improve mhi_sync_power_up handling for SYS_ERR state
Allow mhi_sync_power_up to handle SYS_ERR during power-up, reboot, or recovery. This is to avoid premature exit when MHI_PM_IN_ERROR_STATE is observed during above mentioned system states.
To achieve this, treat SYS_ERR as a valid state and let its handler process the error and queue the next transition to Mission Mode instead of aborting early.
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com> [mani: reworded description] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Link: https://patch.msgid.link/20250912-uevent_vdev_next-20250911-v4-5-fa2f6ccd301b@quicinc.com
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| 12543f44 | 12-Sep-2025 |
Vivek Pernamitta <quic_vpernami@quicinc.com> |
bus: mhi: host: pci_generic: Reset QDU100 while the MHI driver is removed
So, When the MHI driver is removed from the host side, it is essential to ensure a clean and stable recovery of the device.
bus: mhi: host: pci_generic: Reset QDU100 while the MHI driver is removed
So, When the MHI driver is removed from the host side, it is essential to ensure a clean and stable recovery of the device. This commit introduces the following steps to achieve that:
1. Disable SR-IOV for any SR-IOV-enabled devices on the Physical Function. 2. Perform a SOC_RESET on the PF to fully reset the device.
Disabling SR-IOV ensures all Virtual Functions (VFs) are properly shutdown, preventing issues during the reset process. The SOC_RESET guarantees that the PF is restored to a known good state.
If soc_reset is not performed device at driver remove, device will be stuck in mission mode state and subsequent driver insert/power_up will not proceed further.
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com> [mani: reworded subject] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Link: https://patch.msgid.link/20250912-uevent_vdev_next-20250911-v4-4-fa2f6ccd301b@quicinc.com
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| fd6e0509 | 12-Sep-2025 |
Vivek Pernamitta <quic_vpernami@quicinc.com> |
bus: mhi: host: pci_generic: Add SRIOV support
pci_sriov_configure_simple() will enable or disable SR-IOV for devices that don't require any specific PF setup before enabling SR-IOV.
Signed-off-by:
bus: mhi: host: pci_generic: Add SRIOV support
pci_sriov_configure_simple() will enable or disable SR-IOV for devices that don't require any specific PF setup before enabling SR-IOV.
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Reviewed-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Link: https://patch.msgid.link/20250912-uevent_vdev_next-20250911-v4-3-fa2f6ccd301b@quicinc.com
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| b4d01c5b | 12-Sep-2025 |
Vivek Pernamitta <quic_vpernami@quicinc.com> |
bus: mhi: host: pci_generic: Read SUBSYSTEM_VENDOR_ID for VF's to check status
In SR-IOV enabled devices, reading the VF DEVICE/VENDOR ID register returns `FFFFh`, as specified in section 3.4.1.1 of
bus: mhi: host: pci_generic: Read SUBSYSTEM_VENDOR_ID for VF's to check status
In SR-IOV enabled devices, reading the VF DEVICE/VENDOR ID register returns `FFFFh`, as specified in section 3.4.1.1 of the PCIe SR-IOV spec. To accurately determine device activity, read the PCIe VENDOR_ID of the Physical Function (PF) instead. Health check monitoring for Virtual Functions (VFs) has been disabled, since VFs are not physical functions and lack direct hardware control. This change prevents unnecessary CPU cycles from being consumed by VF health checks, which are both unintended and non-functional.
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Reviewed-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Link: https://patch.msgid.link/20250912-uevent_vdev_next-20250911-v4-2-fa2f6ccd301b@quicinc.com
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| a9e3d5a6 | 12-Sep-2025 |
Vivek Pernamitta <quic_vpernami@quicinc.com> |
bus: mhi: host: Add support for separate controller configurations for VF and PF
Implement support for separate controller configurations for both Virtual Functions (VF) and Physical Functions (PF).
bus: mhi: host: Add support for separate controller configurations for VF and PF
Implement support for separate controller configurations for both Virtual Functions (VF) and Physical Functions (PF).
This enhancement allows for more flexible and efficient management of resources. The PF takes on a supervisory role and will have bootup information such as SAHARA, DIAG, and NDB (for file system sync data, etc.). VFs can handle resources associated with the main data movement of the Function are available to the SI (system image) as per PCIe SRIOV spec (rev 0.9 1.Architectural overview)
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com> Reviewed-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Link: https://patch.msgid.link/20250912-uevent_vdev_next-20250911-v4-1-fa2f6ccd301b@quicinc.com
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| d5411ed6 | 12-Sep-2025 |
Vivek Pernamitta <quic_vpernami@quicinc.com> |
bus: mhi: host: Notify EE change via uevent
Notify the MHI device's Execution Environment (EE) state via uevent, enabling applications to receive real-time updates and take appropriate actions based
bus: mhi: host: Notify EE change via uevent
Notify the MHI device's Execution Environment (EE) state via uevent, enabling applications to receive real-time updates and take appropriate actions based on the current state of MHI.
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com> [mani: Reworded subject, removed error print, fixed indentation] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Link: https://patch.msgid.link/20250912-b4-uevent_vdev_next-20250911-v2-1-89440407bf7e@quicinc.com
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| d0856a6d | 05-Sep-2025 |
Adam Xue <zxue@semtech.com> |
bus: mhi: host: Do not use uninitialized 'dev' pointer in mhi_init_irq_setup()
In mhi_init_irq_setup, the device pointer used for dev_err() was not initialized. Use the pointer from mhi_cntrl instea
bus: mhi: host: Do not use uninitialized 'dev' pointer in mhi_init_irq_setup()
In mhi_init_irq_setup, the device pointer used for dev_err() was not initialized. Use the pointer from mhi_cntrl instead.
Fixes: b0fc0167f254 ("bus: mhi: core: Allow shared IRQ for event rings") Fixes: 3000f85b8f47 ("bus: mhi: core: Add support for basic PM operations") Signed-off-by: Adam Xue <zxue@semtech.com> [mani: reworded subject/description and CCed stable] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Reviewed-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20250905174118.38512-1-zxue@semtech.com
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| 00559ba3 | 16-Jul-2025 |
Daniele Palmas <dnlplm@gmail.com> |
bus: mhi: host: pci_generic: Add Telit FN990B40 modem support
Add SDX72 based modem Telit FN990B40, reusing FN920C04 configuration.
01:00.0 Unassigned class [ff00]: Qualcomm Device 0309 Sub
bus: mhi: host: pci_generic: Add Telit FN990B40 modem support
Add SDX72 based modem Telit FN990B40, reusing FN920C04 configuration.
01:00.0 Unassigned class [ff00]: Qualcomm Device 0309 Subsystem: Device 1c5d:201a
Signed-off-by: Daniele Palmas <dnlplm@gmail.com> [mani: added sdx72 in the comment to identify the chipset] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20250716091836.999364-1-dnlplm@gmail.com
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| 5bd398e2 | 14-Jul-2025 |
Youssef Samir <quic_yabdulra@quicinc.com> |
bus: mhi: host: Detect events pointing to unexpected TREs
When a remote device sends a completion event to the host, it contains a pointer to the consumed TRE. The host uses this pointer to process
bus: mhi: host: Detect events pointing to unexpected TREs
When a remote device sends a completion event to the host, it contains a pointer to the consumed TRE. The host uses this pointer to process all of the TREs between it and the host's local copy of the ring's read pointer. This works when processing completion for chained transactions, but can lead to nasty results if the device sends an event for a single-element transaction with a read pointer that is multiple elements ahead of the host's read pointer.
For instance, if the host accesses an event ring while the device is updating it, the pointer inside of the event might still point to an old TRE. If the host uses the channel's xfer_cb() to directly free the buffer pointed to by the TRE, the buffer will be double-freed.
This behavior was observed on an ep that used upstream EP stack without 'commit 6f18d174b73d ("bus: mhi: ep: Update read pointer only after buffer is written")'. Where the device updated the events ring pointer before updating the event contents, so it left a window where the host was able to access the stale data the event pointed to, before the device had the chance to update them. The usual pattern was that the host received an event pointing to a TRE that is not immediately after the last processed one, so it got treated as if it was a chained transaction, processing all of the TREs in between the two read pointers.
This commit aims to harden the host by ensuring transactions where the event points to a TRE that isn't local_rp + 1 are chained.
Fixes: 1d3173a3bae7 ("bus: mhi: core: Add support for processing events from client device") Signed-off-by: Youssef Samir <quic_yabdulra@quicinc.com> [mani: added stable tag and reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20250714163039.3438985-1-quic_yabdulra@quicinc.com
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| 0d63055e | 28-May-2025 |
Slark Xiao <slark_xiao@163.com> |
bus: mhi: host: pci_generic: Add Foxconn T99W696 modem
T99W696 modem is based on Qualcomm SDX61 chipset, which is an economic version compared to the baseline SDX62/SDX65 chipsets. Add support for i
bus: mhi: host: pci_generic: Add Foxconn T99W696 modem
T99W696 modem is based on Qualcomm SDX61 chipset, which is an economic version compared to the baseline SDX62/SDX65 chipsets. Add support for it by introducing a new 'mhi_channel_config'. Since this modem supports the NMEA channel, a new config is needed.
Signed-off-by: Slark Xiao <slark_xiao@163.com> [mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20250528092232.16111-1-slark_xiao@163.com
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| e99f55e4 | 23-Jun-2025 |
Yumeng Fang <fang.yumeng@zte.com.cn> |
bus: mhi: host: Use str_true_false() helper
Remove hard-coded strings by using the str_true_false() helper.
Signed-off-by: Yumeng Fang <fang.yumeng@zte.com.cn> Signed-off-by: Manivannan Sadhasivam
bus: mhi: host: Use str_true_false() helper
Remove hard-coded strings by using the str_true_false() helper.
Signed-off-by: Yumeng Fang <fang.yumeng@zte.com.cn> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20250623202814633ukJqUDLU7BRlLLhvWkbD7@zte.com.cn
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| b484fa61 | 28-May-2025 |
Adam Xue <zxue@semtech.com> |
bus: mhi: host: pci_generic: Add support for EM929x and set MRU to 32768 for better performance.
Add MHI controller config for EM929x. It uses the same configuration as EM919x. Also set the MRU to 3
bus: mhi: host: pci_generic: Add support for EM929x and set MRU to 32768 for better performance.
Add MHI controller config for EM929x. It uses the same configuration as EM919x. Also set the MRU to 32768 to improve downlink throughput.
02:00.0 Unassigned class [ff00]: Qualcomm Technologies, Inc Device 0308 Subsystem: Device 18d7:0301
Signed-off-by: Adam Xue <zxue@semtech.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20250528175943.12739-1-zxue@semtech.com
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| f471578e | 19-May-2025 |
Alexander Wilhelm <alexander.wilhelm@westermo.com> |
bus: mhi: host: Fix endianness of BHI vector table
On big endian platform like PowerPC, the MHI bus (which is little endian) does not start properly. The following example shows the error messages b
bus: mhi: host: Fix endianness of BHI vector table
On big endian platform like PowerPC, the MHI bus (which is little endian) does not start properly. The following example shows the error messages by using QCN9274 WLAN device with ath12k driver:
ath12k_pci 0001:01:00.0: BAR 0: assigned [mem 0xc00000000-0xc001fffff 64bit] ath12k_pci 0001:01:00.0: MSI vectors: 1 ath12k_pci 0001:01:00.0: Hardware name: qcn9274 hw2.0 ath12k_pci 0001:01:00.0: failed to set mhi state: POWER_ON(2) ath12k_pci 0001:01:00.0: failed to start mhi: -110 ath12k_pci 0001:01:00.0: failed to power up :-110 ath12k_pci 0001:01:00.0: failed to create soc core: -110 ath12k_pci 0001:01:00.0: failed to init core: -110 ath12k_pci: probe of 0001:01:00.0 failed with error -110
The issue seems to be with the incorrect DMA address/size used for transferring the firmware image over BHI. So fix it by converting the DMA address and size of the BHI vector table to little endian format before sending them to the device.
Fixes: 6cd330ae76ff ("bus: mhi: core: Add support for ringing channel/event ring doorbells") Signed-off-by: Alexander Wilhelm <alexander.wilhelm@westermo.com> [mani: added stable tag and reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Reviewed-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20250519145837.958153-1-alexander.wilhelm@westermo.com
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| 0494cf97 | 25-Apr-2025 |
Vivek Pernamitta <quic_vpernami@quicinc.com> |
bus: mhi: host: pci_generic: Disable runtime PM for QDU100
The QDU100 device does not support the MHI M3 state, necessitating the disabling of runtime PM for this device. It is essential to disable
bus: mhi: host: pci_generic: Disable runtime PM for QDU100
The QDU100 device does not support the MHI M3 state, necessitating the disabling of runtime PM for this device. It is essential to disable runtime PM if the device does not support M3 state.
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com> [mani: Fixed the kdoc comment for no_m3] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Link: https://patch.msgid.link/20250425-vdev_next-20250411_pm_disable-v4-1-d4870a73ebf9@quicinc.com
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