1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2024 Intel Corporation 4 */ 5 6 #ifndef _XE_PCODE_REGS_H_ 7 #define _XE_PCODE_REGS_H_ 8 9 #include "regs/xe_reg_defs.h" 10 11 /* 12 * This file contains addresses of PCODE registers visible through GT MMIO space. 13 */ 14 15 #define PVC_GT0_PACKAGE_ENERGY_STATUS XE_REG(0x281004) 16 #define PVC_GT0_PACKAGE_RAPL_LIMIT XE_REG(0x281008) 17 #define PVC_GT0_PACKAGE_POWER_SKU_UNIT XE_REG(0x281068) 18 #define PVC_GT0_PLATFORM_ENERGY_STATUS XE_REG(0x28106c) 19 #define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080) 20 21 #define BMG_FAN_1_SPEED XE_REG(0x138140) 22 #define BMG_FAN_2_SPEED XE_REG(0x138170) 23 #define BMG_FAN_3_SPEED XE_REG(0x1381a0) 24 #define BMG_VRAM_TEMPERATURE_N(n) XE_REG(0x138260 + ((n) * (sizeof(u32)))) 25 #define BMG_VRAM_TEMPERATURE XE_REG(0x1382c0) 26 #define TEMP_MASK_VRAM_N REG_GENMASK(30, 8) 27 #define TEMP_SIGN_MASK REG_BIT(31) 28 #define BMG_PACKAGE_TEMPERATURE XE_REG(0x138434) 29 30 #endif /* _XE_PCODE_REGS_H_ */ 31