1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2015-2018 Etnaviv Project
4 */
5
6 #include <linux/clk.h>
7 #include <linux/component.h>
8 #include <linux/delay.h>
9 #include <linux/dma-fence.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/reset.h>
17 #include <linux/thermal.h>
18
19 #include <drm/drm_print.h>
20
21 #include "etnaviv_cmdbuf.h"
22 #include "etnaviv_dump.h"
23 #include "etnaviv_flop_reset.h"
24 #include "etnaviv_gpu.h"
25 #include "etnaviv_gem.h"
26 #include "etnaviv_mmu.h"
27 #include "etnaviv_perfmon.h"
28 #include "etnaviv_sched.h"
29 #include "common.xml.h"
30 #include "state.xml.h"
31 #include "state_hi.xml.h"
32 #include "cmdstream.xml.h"
33
34 static const struct platform_device_id gpu_ids[] = {
35 { .name = "etnaviv-gpu,2d" },
36 { },
37 };
38
39 /*
40 * Driver functions:
41 */
42
etnaviv_gpu_get_param(struct etnaviv_gpu * gpu,u32 param,u64 * value)43 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
44 {
45 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
46
47 switch (param) {
48 case ETNAVIV_PARAM_GPU_MODEL:
49 *value = gpu->identity.model;
50 break;
51
52 case ETNAVIV_PARAM_GPU_REVISION:
53 *value = gpu->identity.revision;
54 break;
55
56 case ETNAVIV_PARAM_GPU_FEATURES_0:
57 *value = gpu->identity.features;
58 break;
59
60 case ETNAVIV_PARAM_GPU_FEATURES_1:
61 *value = gpu->identity.minor_features0;
62 break;
63
64 case ETNAVIV_PARAM_GPU_FEATURES_2:
65 *value = gpu->identity.minor_features1;
66 break;
67
68 case ETNAVIV_PARAM_GPU_FEATURES_3:
69 *value = gpu->identity.minor_features2;
70 break;
71
72 case ETNAVIV_PARAM_GPU_FEATURES_4:
73 *value = gpu->identity.minor_features3;
74 break;
75
76 case ETNAVIV_PARAM_GPU_FEATURES_5:
77 *value = gpu->identity.minor_features4;
78 break;
79
80 case ETNAVIV_PARAM_GPU_FEATURES_6:
81 *value = gpu->identity.minor_features5;
82 break;
83
84 case ETNAVIV_PARAM_GPU_FEATURES_7:
85 *value = gpu->identity.minor_features6;
86 break;
87
88 case ETNAVIV_PARAM_GPU_FEATURES_8:
89 *value = gpu->identity.minor_features7;
90 break;
91
92 case ETNAVIV_PARAM_GPU_FEATURES_9:
93 *value = gpu->identity.minor_features8;
94 break;
95
96 case ETNAVIV_PARAM_GPU_FEATURES_10:
97 *value = gpu->identity.minor_features9;
98 break;
99
100 case ETNAVIV_PARAM_GPU_FEATURES_11:
101 *value = gpu->identity.minor_features10;
102 break;
103
104 case ETNAVIV_PARAM_GPU_FEATURES_12:
105 *value = gpu->identity.minor_features11;
106 break;
107
108 case ETNAVIV_PARAM_GPU_STREAM_COUNT:
109 *value = gpu->identity.stream_count;
110 break;
111
112 case ETNAVIV_PARAM_GPU_REGISTER_MAX:
113 *value = gpu->identity.register_max;
114 break;
115
116 case ETNAVIV_PARAM_GPU_THREAD_COUNT:
117 *value = gpu->identity.thread_count;
118 break;
119
120 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
121 *value = gpu->identity.vertex_cache_size;
122 break;
123
124 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
125 *value = gpu->identity.shader_core_count;
126 break;
127
128 case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
129 *value = gpu->identity.pixel_pipes;
130 break;
131
132 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
133 *value = gpu->identity.vertex_output_buffer_size;
134 break;
135
136 case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
137 *value = gpu->identity.buffer_size;
138 break;
139
140 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
141 *value = gpu->identity.instruction_count;
142 break;
143
144 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
145 *value = gpu->identity.num_constants;
146 break;
147
148 case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
149 *value = gpu->identity.varyings_count;
150 break;
151
152 case ETNAVIV_PARAM_SOFTPIN_START_ADDR:
153 if (priv->mmu_global->version == ETNAVIV_IOMMU_V2)
154 *value = ETNAVIV_SOFTPIN_START_ADDRESS;
155 else
156 *value = ~0ULL;
157 break;
158
159 case ETNAVIV_PARAM_GPU_PRODUCT_ID:
160 *value = gpu->identity.product_id;
161 break;
162
163 case ETNAVIV_PARAM_GPU_CUSTOMER_ID:
164 *value = gpu->identity.customer_id;
165 break;
166
167 case ETNAVIV_PARAM_GPU_ECO_ID:
168 *value = gpu->identity.eco_id;
169 break;
170
171 default:
172 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
173 return -EINVAL;
174 }
175
176 return 0;
177 }
178
etnaviv_gpu_reset_deassert(struct etnaviv_gpu * gpu)179 static int etnaviv_gpu_reset_deassert(struct etnaviv_gpu *gpu)
180 {
181 int ret;
182
183 /*
184 * 32 core clock cycles (slowest clock) required before deassertion
185 * 1 microsecond might match all implementations without computation
186 */
187 usleep_range(1, 2);
188
189 ret = reset_control_deassert(gpu->rst);
190 if (ret)
191 return ret;
192
193 /*
194 * 128 core clock cycles (slowest clock) required before any activity on AHB
195 * 1 microsecond might match all implementations without computation
196 */
197 usleep_range(1, 2);
198
199 return 0;
200 }
201
etnaviv_is_model_rev(struct etnaviv_gpu * gpu,u32 model,u32 revision)202 static inline bool etnaviv_is_model_rev(struct etnaviv_gpu *gpu, u32 model, u32 revision)
203 {
204 return gpu->identity.model == model &&
205 gpu->identity.revision == revision;
206 }
207
208 #define etnaviv_field(val, field) \
209 (((val) & field##__MASK) >> field##__SHIFT)
210
etnaviv_hw_specs(struct etnaviv_gpu * gpu)211 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
212 {
213 if (gpu->identity.minor_features0 &
214 chipMinorFeatures0_MORE_MINOR_FEATURES) {
215 u32 specs[4];
216 unsigned int streams;
217
218 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
219 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
220 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
221 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
222
223 gpu->identity.stream_count = etnaviv_field(specs[0],
224 VIVS_HI_CHIP_SPECS_STREAM_COUNT);
225 gpu->identity.register_max = etnaviv_field(specs[0],
226 VIVS_HI_CHIP_SPECS_REGISTER_MAX);
227 gpu->identity.thread_count = etnaviv_field(specs[0],
228 VIVS_HI_CHIP_SPECS_THREAD_COUNT);
229 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
230 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
231 gpu->identity.shader_core_count = etnaviv_field(specs[0],
232 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
233 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
234 VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
235 gpu->identity.vertex_output_buffer_size =
236 etnaviv_field(specs[0],
237 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
238
239 gpu->identity.buffer_size = etnaviv_field(specs[1],
240 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
241 gpu->identity.instruction_count = etnaviv_field(specs[1],
242 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
243 gpu->identity.num_constants = etnaviv_field(specs[1],
244 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
245
246 gpu->identity.varyings_count = etnaviv_field(specs[2],
247 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
248
249 /* This overrides the value from older register if non-zero */
250 streams = etnaviv_field(specs[3],
251 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
252 if (streams)
253 gpu->identity.stream_count = streams;
254 }
255
256 /* Fill in the stream count if not specified */
257 if (gpu->identity.stream_count == 0) {
258 if (gpu->identity.model >= 0x1000)
259 gpu->identity.stream_count = 4;
260 else
261 gpu->identity.stream_count = 1;
262 }
263
264 /* Convert the register max value */
265 if (gpu->identity.register_max)
266 gpu->identity.register_max = 1 << gpu->identity.register_max;
267 else if (gpu->identity.model == chipModel_GC400)
268 gpu->identity.register_max = 32;
269 else
270 gpu->identity.register_max = 64;
271
272 /* Convert thread count */
273 if (gpu->identity.thread_count)
274 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
275 else if (gpu->identity.model == chipModel_GC400)
276 gpu->identity.thread_count = 64;
277 else if (gpu->identity.model == chipModel_GC500 ||
278 gpu->identity.model == chipModel_GC530)
279 gpu->identity.thread_count = 128;
280 else
281 gpu->identity.thread_count = 256;
282
283 if (gpu->identity.vertex_cache_size == 0)
284 gpu->identity.vertex_cache_size = 8;
285
286 if (gpu->identity.shader_core_count == 0) {
287 if (gpu->identity.model >= 0x1000)
288 gpu->identity.shader_core_count = 2;
289 else
290 gpu->identity.shader_core_count = 1;
291 }
292
293 if (gpu->identity.pixel_pipes == 0)
294 gpu->identity.pixel_pipes = 1;
295
296 /* Convert virtex buffer size */
297 if (gpu->identity.vertex_output_buffer_size) {
298 gpu->identity.vertex_output_buffer_size =
299 1 << gpu->identity.vertex_output_buffer_size;
300 } else if (gpu->identity.model == chipModel_GC400) {
301 if (gpu->identity.revision < 0x4000)
302 gpu->identity.vertex_output_buffer_size = 512;
303 else if (gpu->identity.revision < 0x4200)
304 gpu->identity.vertex_output_buffer_size = 256;
305 else
306 gpu->identity.vertex_output_buffer_size = 128;
307 } else {
308 gpu->identity.vertex_output_buffer_size = 512;
309 }
310
311 switch (gpu->identity.instruction_count) {
312 case 0:
313 if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
314 gpu->identity.model == chipModel_GC880)
315 gpu->identity.instruction_count = 512;
316 else
317 gpu->identity.instruction_count = 256;
318 break;
319
320 case 1:
321 gpu->identity.instruction_count = 1024;
322 break;
323
324 case 2:
325 gpu->identity.instruction_count = 2048;
326 break;
327
328 default:
329 gpu->identity.instruction_count = 256;
330 break;
331 }
332
333 if (gpu->identity.num_constants == 0)
334 gpu->identity.num_constants = 168;
335
336 if (gpu->identity.varyings_count == 0) {
337 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
338 gpu->identity.varyings_count = 12;
339 else
340 gpu->identity.varyings_count = 8;
341 }
342
343 /*
344 * For some cores, two varyings are consumed for position, so the
345 * maximum varying count needs to be reduced by one.
346 */
347 if (etnaviv_is_model_rev(gpu, 0x5000, 0x5434) ||
348 etnaviv_is_model_rev(gpu, 0x4000, 0x5222) ||
349 etnaviv_is_model_rev(gpu, 0x4000, 0x5245) ||
350 etnaviv_is_model_rev(gpu, 0x4000, 0x5208) ||
351 etnaviv_is_model_rev(gpu, 0x3000, 0x5435) ||
352 etnaviv_is_model_rev(gpu, 0x2200, 0x5244) ||
353 etnaviv_is_model_rev(gpu, 0x2100, 0x5108) ||
354 etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
355 etnaviv_is_model_rev(gpu, 0x1500, 0x5246) ||
356 etnaviv_is_model_rev(gpu, 0x880, 0x5107) ||
357 etnaviv_is_model_rev(gpu, 0x880, 0x5106))
358 gpu->identity.varyings_count -= 1;
359 }
360
etnaviv_hw_identify(struct etnaviv_gpu * gpu)361 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
362 {
363 u32 chipIdentity;
364
365 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
366
367 /* Special case for older graphic cores. */
368 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
369 gpu->identity.model = chipModel_GC500;
370 gpu->identity.revision = etnaviv_field(chipIdentity,
371 VIVS_HI_CHIP_IDENTITY_REVISION);
372 } else {
373 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
374
375 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
376 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
377 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID);
378
379 /*
380 * Reading these two registers on GC600 rev 0x19 result in a
381 * unhandled fault: external abort on non-linefetch
382 */
383 if (!etnaviv_is_model_rev(gpu, 0x600, 0x19)) {
384 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);
385 gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);
386 }
387
388 /*
389 * !!!! HACK ALERT !!!!
390 * Because people change device IDs without letting software
391 * know about it - here is the hack to make it all look the
392 * same. Only for GC400 family.
393 */
394 if ((gpu->identity.model & 0xff00) == 0x0400 &&
395 gpu->identity.model != chipModel_GC420) {
396 gpu->identity.model = gpu->identity.model & 0x0400;
397 }
398
399 /* Another special case */
400 if (etnaviv_is_model_rev(gpu, 0x300, 0x2201)) {
401 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
402
403 if (chipDate == 0x20080814 && chipTime == 0x12051100) {
404 /*
405 * This IP has an ECO; put the correct
406 * revision in it.
407 */
408 gpu->identity.revision = 0x1051;
409 }
410 }
411
412 /*
413 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
414 * reality it's just a re-branded GC3000. We can identify this
415 * core by the upper half of the revision register being all 1.
416 * Fix model/rev here, so all other places can refer to this
417 * core by its real identity.
418 */
419 if (etnaviv_is_model_rev(gpu, 0x2000, 0xffff5450)) {
420 gpu->identity.model = chipModel_GC3000;
421 gpu->identity.revision &= 0xffff;
422 }
423
424 if (etnaviv_is_model_rev(gpu, 0x1000, 0x5037) && (chipDate == 0x20120617))
425 gpu->identity.eco_id = 1;
426
427 if (etnaviv_is_model_rev(gpu, 0x320, 0x5303) && (chipDate == 0x20140511))
428 gpu->identity.eco_id = 1;
429 }
430
431 dev_info(gpu->dev, "model: GC%x, revision: %x\n",
432 gpu->identity.model, gpu->identity.revision);
433
434 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
435 /*
436 * If there is a match in the HWDB, we aren't interested in the
437 * remaining register values, as they might be wrong.
438 */
439 if (etnaviv_fill_identity_from_hwdb(gpu))
440 return;
441
442 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
443
444 /* Disable fast clear on GC700. */
445 if (gpu->identity.model == chipModel_GC700)
446 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
447
448 /* These models/revisions don't have the 2D pipe bit */
449 if ((gpu->identity.model == chipModel_GC500 &&
450 gpu->identity.revision <= 2) ||
451 gpu->identity.model == chipModel_GC300)
452 gpu->identity.features |= chipFeatures_PIPE_2D;
453
454 if ((gpu->identity.model == chipModel_GC500 &&
455 gpu->identity.revision < 2) ||
456 (gpu->identity.model == chipModel_GC300 &&
457 gpu->identity.revision < 0x2000)) {
458
459 /*
460 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
461 * registers.
462 */
463 gpu->identity.minor_features0 = 0;
464 gpu->identity.minor_features1 = 0;
465 gpu->identity.minor_features2 = 0;
466 gpu->identity.minor_features3 = 0;
467 gpu->identity.minor_features4 = 0;
468 gpu->identity.minor_features5 = 0;
469 } else
470 gpu->identity.minor_features0 =
471 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
472
473 if (gpu->identity.minor_features0 &
474 chipMinorFeatures0_MORE_MINOR_FEATURES) {
475 gpu->identity.minor_features1 =
476 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
477 gpu->identity.minor_features2 =
478 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
479 gpu->identity.minor_features3 =
480 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
481 gpu->identity.minor_features4 =
482 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
483 gpu->identity.minor_features5 =
484 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
485 }
486
487 /* GC600/300 idle register reports zero bits where modules aren't present */
488 if (gpu->identity.model == chipModel_GC600 ||
489 gpu->identity.model == chipModel_GC300)
490 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
491 VIVS_HI_IDLE_STATE_RA |
492 VIVS_HI_IDLE_STATE_SE |
493 VIVS_HI_IDLE_STATE_PA |
494 VIVS_HI_IDLE_STATE_SH |
495 VIVS_HI_IDLE_STATE_PE |
496 VIVS_HI_IDLE_STATE_DE |
497 VIVS_HI_IDLE_STATE_FE;
498
499 etnaviv_hw_specs(gpu);
500 }
501
etnaviv_gpu_load_clock(struct etnaviv_gpu * gpu,u32 clock)502 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
503 {
504 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
505 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
506 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
507 }
508
etnaviv_gpu_update_clock(struct etnaviv_gpu * gpu)509 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
510 {
511 if (gpu->identity.minor_features2 &
512 chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
513 clk_set_rate(gpu->clk_core,
514 gpu->base_rate_core >> gpu->freq_scale);
515 clk_set_rate(gpu->clk_shader,
516 gpu->base_rate_shader >> gpu->freq_scale);
517 } else {
518 unsigned int fscale = 1 << (6 - gpu->freq_scale);
519 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
520
521 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
522 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
523 etnaviv_gpu_load_clock(gpu, clock);
524 }
525
526 /*
527 * Choose number of wait cycles to target a ~30us (1/32768) max latency
528 * until new work is picked up by the FE when it polls in the idle loop.
529 * If the GPU base frequency is unknown use 200 wait cycles.
530 */
531 gpu->fe_waitcycles = clamp(gpu->base_rate_core >> (15 - gpu->freq_scale),
532 200UL, 0xffffUL);
533 }
534
etnaviv_hw_reset(struct etnaviv_gpu * gpu)535 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
536 {
537 u32 control, idle;
538 unsigned long timeout;
539 bool failed = true;
540
541 /* We hope that the GPU resets in under one second */
542 timeout = jiffies + msecs_to_jiffies(1000);
543
544 while (time_is_after_jiffies(timeout)) {
545 unsigned int fscale = 1 << (6 - gpu->freq_scale);
546 u32 pulse_eater = 0x01590880;
547
548 /* disable clock gating */
549 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, 0x0);
550
551 /* disable pulse eater */
552 pulse_eater |= BIT(17);
553 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
554 pulse_eater |= BIT(0);
555 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
556
557 /* enable clock */
558 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
559 etnaviv_gpu_load_clock(gpu, control);
560
561 /* isolate the GPU. */
562 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
563 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
564
565 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
566 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
567 VIVS_MMUv2_AHB_CONTROL_RESET);
568 } else {
569 /* set soft reset. */
570 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
571 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
572 }
573
574 /* wait for reset. */
575 usleep_range(10, 20);
576
577 /* reset soft reset bit. */
578 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
579 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
580
581 /* reset GPU isolation. */
582 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
583 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
584
585 /* read idle register. */
586 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
587
588 /* try resetting again if FE is not idle */
589 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
590 dev_dbg(gpu->dev, "FE is not idle\n");
591 continue;
592 }
593
594 /* read reset register. */
595 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
596
597 /* is the GPU idle? */
598 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
599 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
600 dev_dbg(gpu->dev, "GPU is not idle\n");
601 continue;
602 }
603
604 /* enable debug register access */
605 control &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
606 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
607
608 failed = false;
609 break;
610 }
611
612 if (failed) {
613 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
614 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
615
616 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
617 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
618 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
619 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
620
621 return -EBUSY;
622 }
623
624 /* We rely on the GPU running, so program the clock */
625 etnaviv_gpu_update_clock(gpu);
626
627 gpu->state = ETNA_GPU_STATE_RESET;
628 gpu->exec_state = -1;
629 if (gpu->mmu_context)
630 etnaviv_iommu_context_put(gpu->mmu_context);
631 gpu->mmu_context = NULL;
632
633 return 0;
634 }
635
etnaviv_gpu_enable_mlcg(struct etnaviv_gpu * gpu)636 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
637 {
638 u32 pmc, ppc;
639
640 /* enable clock gating */
641 ppc = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
642 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
643
644 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
645 if (gpu->identity.revision == 0x4301 ||
646 gpu->identity.revision == 0x4302)
647 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
648
649 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, ppc);
650
651 pmc = gpu_read_power(gpu, VIVS_PM_MODULE_CONTROLS);
652
653 /* Disable PA clock gating for GC400+ without bugfix except for GC420 */
654 if (gpu->identity.model >= chipModel_GC400 &&
655 gpu->identity.model != chipModel_GC420 &&
656 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
657 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
658
659 /*
660 * Disable PE clock gating on revs < 5.0.0.0 when HZ is
661 * present without a bug fix.
662 */
663 if (gpu->identity.revision < 0x5000 &&
664 gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
665 !(gpu->identity.minor_features1 &
666 chipMinorFeatures1_DISABLE_PE_GATING))
667 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
668
669 if (gpu->identity.revision < 0x5422)
670 pmc |= BIT(15); /* Unknown bit */
671
672 /* Disable TX clock gating on affected core revisions. */
673 if (etnaviv_is_model_rev(gpu, 0x4000, 0x5222) ||
674 etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
675 etnaviv_is_model_rev(gpu, 0x7000, 0x6202) ||
676 etnaviv_is_model_rev(gpu, 0x7000, 0x6203))
677 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
678
679 /* Disable SE and RA clock gating on affected core revisions. */
680 if (etnaviv_is_model_rev(gpu, 0x7000, 0x6202))
681 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |
682 VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA;
683
684 /* Disable SH_EU clock gating on affected core revisions. */
685 if (etnaviv_is_model_rev(gpu, 0x8000, 0x7200) ||
686 etnaviv_is_model_rev(gpu, 0x8000, 0x8002) ||
687 etnaviv_is_model_rev(gpu, 0x9200, 0x6304))
688 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH_EU;
689
690 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
691 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
692
693 gpu_write_power(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
694 }
695
etnaviv_gpu_start_fe(struct etnaviv_gpu * gpu,u32 address,u16 prefetch)696 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
697 {
698 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
699 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
700 VIVS_FE_COMMAND_CONTROL_ENABLE |
701 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
702
703 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
704 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
705 VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
706 VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
707 }
708 }
709
etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu * gpu,struct etnaviv_iommu_context * context)710 static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu,
711 struct etnaviv_iommu_context *context)
712 {
713 u16 prefetch;
714 u32 address;
715
716 WARN_ON(gpu->state != ETNA_GPU_STATE_INITIALIZED);
717
718 /* setup the MMU */
719 etnaviv_iommu_restore(gpu, context);
720
721 /* Start command processor */
722 prefetch = etnaviv_buffer_init(gpu);
723 address = etnaviv_cmdbuf_get_va(&gpu->buffer,
724 &gpu->mmu_context->cmdbuf_mapping);
725
726 etnaviv_gpu_start_fe(gpu, address, prefetch);
727
728 gpu->state = ETNA_GPU_STATE_RUNNING;
729 }
730
etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu * gpu)731 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
732 {
733 /*
734 * Base value for VIVS_PM_PULSE_EATER register on models where it
735 * cannot be read, extracted from vivante kernel driver.
736 */
737 u32 pulse_eater = 0x01590880;
738
739 if (etnaviv_is_model_rev(gpu, 0x4000, 0x5208) ||
740 etnaviv_is_model_rev(gpu, 0x4000, 0x5222)) {
741 pulse_eater |= BIT(23);
742
743 }
744
745 if (etnaviv_is_model_rev(gpu, 0x1000, 0x5039) ||
746 etnaviv_is_model_rev(gpu, 0x1000, 0x5040)) {
747 pulse_eater &= ~BIT(16);
748 pulse_eater |= BIT(17);
749 }
750
751 if ((gpu->identity.revision > 0x5420) &&
752 (gpu->identity.features & chipFeatures_PIPE_3D))
753 {
754 /* Performance fix: disable internal DFS */
755 pulse_eater = gpu_read_power(gpu, VIVS_PM_PULSE_EATER);
756 pulse_eater |= BIT(18);
757 }
758
759 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
760 }
761
etnaviv_gpu_hw_init(struct etnaviv_gpu * gpu)762 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
763 {
764 WARN_ON(!(gpu->state == ETNA_GPU_STATE_IDENTIFIED ||
765 gpu->state == ETNA_GPU_STATE_RESET));
766
767 if ((etnaviv_is_model_rev(gpu, 0x320, 0x5007) ||
768 etnaviv_is_model_rev(gpu, 0x320, 0x5220)) &&
769 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
770 u32 mc_memory_debug;
771
772 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
773
774 if (gpu->identity.revision == 0x5007)
775 mc_memory_debug |= 0x0c;
776 else
777 mc_memory_debug |= 0x08;
778
779 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
780 }
781
782 /* enable module-level clock gating */
783 etnaviv_gpu_enable_mlcg(gpu);
784
785 /*
786 * Update GPU AXI cache atttribute to "cacheable, no allocate".
787 * This is necessary to prevent the iMX6 SoC locking up.
788 */
789 gpu_write(gpu, VIVS_HI_AXI_CONFIG,
790 VIVS_HI_AXI_CONFIG_AWCACHE(2) |
791 VIVS_HI_AXI_CONFIG_ARCACHE(2));
792
793 /* GC2000 rev 5108 needs a special bus config */
794 if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108)) {
795 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
796 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
797 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
798 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
799 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
800 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
801 }
802
803 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
804 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
805 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
806 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
807 }
808
809 /* setup the pulse eater */
810 etnaviv_gpu_setup_pulse_eater(gpu);
811
812 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
813
814 gpu->state = ETNA_GPU_STATE_INITIALIZED;
815 }
816
etnaviv_gpu_init(struct etnaviv_gpu * gpu)817 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
818 {
819 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
820 dma_addr_t cmdbuf_paddr;
821 int ret, i;
822
823 ret = pm_runtime_get_sync(gpu->dev);
824 if (ret < 0) {
825 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
826 goto pm_put;
827 }
828
829 ret = etnaviv_gpu_reset_deassert(gpu);
830 if (ret) {
831 dev_err(gpu->dev, "GPU reset deassert failed\n");
832 goto fail;
833 }
834
835 etnaviv_hw_identify(gpu);
836
837 if (gpu->identity.model == 0) {
838 dev_err(gpu->dev, "Unknown GPU model\n");
839 ret = -ENXIO;
840 goto fail;
841 }
842
843 if (etnaviv_flop_reset_ppu_require(&gpu->identity) &&
844 !priv->flop_reset_data_ppu) {
845 ret = etnaviv_flop_reset_ppu_init(priv);
846 if (ret) {
847 dev_err(gpu->dev,
848 "Unable to initialize PPU flop reset data\n");
849 goto fail;
850 }
851 }
852
853 if (gpu->identity.nn_core_count > 0)
854 dev_warn(gpu->dev, "etnaviv has been instantiated on a NPU, "
855 "for which the UAPI is still experimental\n");
856
857 /* Exclude VG cores with FE2.0 */
858 if (gpu->identity.features & chipFeatures_PIPE_VG &&
859 gpu->identity.features & chipFeatures_FE20) {
860 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
861 ret = -ENXIO;
862 goto fail;
863 }
864
865 /*
866 * On cores with security features supported, we claim control over the
867 * security states.
868 */
869 if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
870 (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
871 gpu->sec_mode = ETNA_SEC_KERNEL;
872
873 gpu->state = ETNA_GPU_STATE_IDENTIFIED;
874
875 ret = etnaviv_hw_reset(gpu);
876 if (ret) {
877 dev_err(gpu->dev, "GPU reset failed\n");
878 goto fail;
879 }
880
881 ret = etnaviv_iommu_global_init(gpu);
882 if (ret)
883 goto fail;
884
885 /* Create buffer: */
886 ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer, SZ_4K);
887 if (ret) {
888 dev_err(gpu->dev, "could not create command buffer\n");
889 goto fail;
890 }
891
892 /*
893 * Set the GPU linear window to cover the cmdbuf region, as the GPU
894 * won't be able to start execution otherwise. The alignment to 128M is
895 * chosen arbitrarily but helps in debugging, as the MMU offset
896 * calculations are much more straight forward this way.
897 *
898 * On MC1.0 cores the linear window offset is ignored by the TS engine,
899 * leading to inconsistent memory views. Avoid using the offset on those
900 * cores if possible, otherwise disable the TS feature. MMUv2 doesn't
901 * expose this issue, as all TS accesses are MMU translated, so the
902 * linear window offset won't be used.
903 */
904 cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M);
905
906 if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
907 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20) ||
908 (gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION)) {
909 if (cmdbuf_paddr >= SZ_2G)
910 priv->mmu_global->memory_base = SZ_2G;
911 else
912 priv->mmu_global->memory_base = cmdbuf_paddr;
913 } else if (cmdbuf_paddr + SZ_128M >= SZ_2G) {
914 dev_info(gpu->dev,
915 "Need to move linear window on MC1.0, disabling TS\n");
916 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
917 priv->mmu_global->memory_base = SZ_2G;
918 }
919
920 /* Setup event management */
921 spin_lock_init(&gpu->event_spinlock);
922 init_completion(&gpu->event_free);
923 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
924 for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
925 complete(&gpu->event_free);
926
927 /* Now program the hardware */
928 mutex_lock(&gpu->lock);
929 etnaviv_gpu_hw_init(gpu);
930 mutex_unlock(&gpu->lock);
931
932 pm_runtime_mark_last_busy(gpu->dev);
933 pm_runtime_put_autosuspend(gpu->dev);
934
935 return 0;
936
937 fail:
938 pm_runtime_mark_last_busy(gpu->dev);
939 pm_put:
940 pm_runtime_put_autosuspend(gpu->dev);
941
942 return ret;
943 }
944
945 #ifdef CONFIG_DEBUG_FS
946 struct dma_debug {
947 u32 address[2];
948 u32 state[2];
949 };
950
verify_dma(struct etnaviv_gpu * gpu,struct dma_debug * debug)951 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
952 {
953 u32 i;
954
955 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
956 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
957
958 for (i = 0; i < 500; i++) {
959 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
960 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
961
962 if (debug->address[0] != debug->address[1])
963 break;
964
965 if (debug->state[0] != debug->state[1])
966 break;
967 }
968 }
969
etnaviv_gpu_debugfs(struct etnaviv_gpu * gpu,struct seq_file * m)970 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
971 {
972 struct dma_debug debug;
973 u32 dma_lo, dma_hi, axi, idle;
974 int ret;
975
976 seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
977
978 ret = pm_runtime_get_sync(gpu->dev);
979 if (ret < 0)
980 goto pm_put;
981
982 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
983 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
984 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
985 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
986
987 verify_dma(gpu, &debug);
988
989 seq_puts(m, "\tidentity\n");
990 seq_printf(m, "\t model: 0x%x\n", gpu->identity.model);
991 seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision);
992 seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id);
993 seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id);
994 seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id);
995
996 seq_puts(m, "\tfeatures\n");
997 seq_printf(m, "\t major_features: 0x%08x\n",
998 gpu->identity.features);
999 seq_printf(m, "\t minor_features0: 0x%08x\n",
1000 gpu->identity.minor_features0);
1001 seq_printf(m, "\t minor_features1: 0x%08x\n",
1002 gpu->identity.minor_features1);
1003 seq_printf(m, "\t minor_features2: 0x%08x\n",
1004 gpu->identity.minor_features2);
1005 seq_printf(m, "\t minor_features3: 0x%08x\n",
1006 gpu->identity.minor_features3);
1007 seq_printf(m, "\t minor_features4: 0x%08x\n",
1008 gpu->identity.minor_features4);
1009 seq_printf(m, "\t minor_features5: 0x%08x\n",
1010 gpu->identity.minor_features5);
1011 seq_printf(m, "\t minor_features6: 0x%08x\n",
1012 gpu->identity.minor_features6);
1013 seq_printf(m, "\t minor_features7: 0x%08x\n",
1014 gpu->identity.minor_features7);
1015 seq_printf(m, "\t minor_features8: 0x%08x\n",
1016 gpu->identity.minor_features8);
1017 seq_printf(m, "\t minor_features9: 0x%08x\n",
1018 gpu->identity.minor_features9);
1019 seq_printf(m, "\t minor_features10: 0x%08x\n",
1020 gpu->identity.minor_features10);
1021 seq_printf(m, "\t minor_features11: 0x%08x\n",
1022 gpu->identity.minor_features11);
1023
1024 seq_puts(m, "\tspecs\n");
1025 seq_printf(m, "\t stream_count: %d\n",
1026 gpu->identity.stream_count);
1027 seq_printf(m, "\t register_max: %d\n",
1028 gpu->identity.register_max);
1029 seq_printf(m, "\t thread_count: %d\n",
1030 gpu->identity.thread_count);
1031 seq_printf(m, "\t vertex_cache_size: %d\n",
1032 gpu->identity.vertex_cache_size);
1033 seq_printf(m, "\t shader_core_count: %d\n",
1034 gpu->identity.shader_core_count);
1035 seq_printf(m, "\t nn_core_count: %d\n",
1036 gpu->identity.nn_core_count);
1037 seq_printf(m, "\t pixel_pipes: %d\n",
1038 gpu->identity.pixel_pipes);
1039 seq_printf(m, "\t vertex_output_buffer_size: %d\n",
1040 gpu->identity.vertex_output_buffer_size);
1041 seq_printf(m, "\t buffer_size: %d\n",
1042 gpu->identity.buffer_size);
1043 seq_printf(m, "\t instruction_count: %d\n",
1044 gpu->identity.instruction_count);
1045 seq_printf(m, "\t num_constants: %d\n",
1046 gpu->identity.num_constants);
1047 seq_printf(m, "\t varyings_count: %d\n",
1048 gpu->identity.varyings_count);
1049
1050 seq_printf(m, "\taxi: 0x%08x\n", axi);
1051 seq_printf(m, "\tidle: 0x%08x\n", idle);
1052 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
1053 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
1054 seq_puts(m, "\t FE is not idle\n");
1055 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
1056 seq_puts(m, "\t DE is not idle\n");
1057 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
1058 seq_puts(m, "\t PE is not idle\n");
1059 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
1060 seq_puts(m, "\t SH is not idle\n");
1061 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
1062 seq_puts(m, "\t PA is not idle\n");
1063 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
1064 seq_puts(m, "\t SE is not idle\n");
1065 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
1066 seq_puts(m, "\t RA is not idle\n");
1067 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
1068 seq_puts(m, "\t TX is not idle\n");
1069 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
1070 seq_puts(m, "\t VG is not idle\n");
1071 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
1072 seq_puts(m, "\t IM is not idle\n");
1073 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
1074 seq_puts(m, "\t FP is not idle\n");
1075 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
1076 seq_puts(m, "\t TS is not idle\n");
1077 if ((idle & VIVS_HI_IDLE_STATE_BL) == 0)
1078 seq_puts(m, "\t BL is not idle\n");
1079 if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0)
1080 seq_puts(m, "\t ASYNCFE is not idle\n");
1081 if ((idle & VIVS_HI_IDLE_STATE_MC) == 0)
1082 seq_puts(m, "\t MC is not idle\n");
1083 if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0)
1084 seq_puts(m, "\t PPA is not idle\n");
1085 if ((idle & VIVS_HI_IDLE_STATE_WD) == 0)
1086 seq_puts(m, "\t WD is not idle\n");
1087 if ((idle & VIVS_HI_IDLE_STATE_NN) == 0)
1088 seq_puts(m, "\t NN is not idle\n");
1089 if ((idle & VIVS_HI_IDLE_STATE_TP) == 0)
1090 seq_puts(m, "\t TP is not idle\n");
1091 if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
1092 seq_puts(m, "\t AXI low power mode\n");
1093
1094 if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
1095 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
1096 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
1097 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
1098
1099 seq_puts(m, "\tMC\n");
1100 seq_printf(m, "\t read0: 0x%08x\n", read0);
1101 seq_printf(m, "\t read1: 0x%08x\n", read1);
1102 seq_printf(m, "\t write: 0x%08x\n", write);
1103 }
1104
1105 seq_puts(m, "\tDMA ");
1106
1107 if (debug.address[0] == debug.address[1] &&
1108 debug.state[0] == debug.state[1]) {
1109 seq_puts(m, "seems to be stuck\n");
1110 } else if (debug.address[0] == debug.address[1]) {
1111 seq_puts(m, "address is constant\n");
1112 } else {
1113 seq_puts(m, "is running\n");
1114 }
1115
1116 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
1117 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
1118 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
1119 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
1120 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
1121 dma_lo, dma_hi);
1122
1123 ret = 0;
1124
1125 pm_runtime_mark_last_busy(gpu->dev);
1126 pm_put:
1127 pm_runtime_put_autosuspend(gpu->dev);
1128
1129 return ret;
1130 }
1131 #endif
1132
1133 /* fence object management */
1134 struct etnaviv_fence {
1135 struct etnaviv_gpu *gpu;
1136 struct dma_fence base;
1137 };
1138
to_etnaviv_fence(struct dma_fence * fence)1139 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1140 {
1141 return container_of(fence, struct etnaviv_fence, base);
1142 }
1143
etnaviv_fence_get_driver_name(struct dma_fence * fence)1144 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1145 {
1146 return "etnaviv";
1147 }
1148
etnaviv_fence_get_timeline_name(struct dma_fence * fence)1149 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1150 {
1151 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1152
1153 return dev_name(f->gpu->dev);
1154 }
1155
etnaviv_fence_signaled(struct dma_fence * fence)1156 static bool etnaviv_fence_signaled(struct dma_fence *fence)
1157 {
1158 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1159
1160 return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;
1161 }
1162
etnaviv_fence_release(struct dma_fence * fence)1163 static void etnaviv_fence_release(struct dma_fence *fence)
1164 {
1165 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1166
1167 kfree_rcu(f, base.rcu);
1168 }
1169
1170 static const struct dma_fence_ops etnaviv_fence_ops = {
1171 .get_driver_name = etnaviv_fence_get_driver_name,
1172 .get_timeline_name = etnaviv_fence_get_timeline_name,
1173 .signaled = etnaviv_fence_signaled,
1174 .release = etnaviv_fence_release,
1175 };
1176
etnaviv_gpu_fence_alloc(struct etnaviv_gpu * gpu)1177 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1178 {
1179 struct etnaviv_fence *f;
1180
1181 /*
1182 * GPU lock must already be held, otherwise fence completion order might
1183 * not match the seqno order assigned here.
1184 */
1185 lockdep_assert_held(&gpu->lock);
1186
1187 f = kzalloc_obj(*f);
1188 if (!f)
1189 return NULL;
1190
1191 f->gpu = gpu;
1192
1193 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1194 gpu->fence_context, ++gpu->next_fence);
1195
1196 return &f->base;
1197 }
1198
1199 /* returns true if fence a comes after fence b */
fence_after(u32 a,u32 b)1200 static inline bool fence_after(u32 a, u32 b)
1201 {
1202 return (s32)(a - b) > 0;
1203 }
1204
1205 /*
1206 * event management:
1207 */
1208
event_alloc(struct etnaviv_gpu * gpu,unsigned nr_events,unsigned int * events)1209 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1210 unsigned int *events)
1211 {
1212 unsigned long timeout = msecs_to_jiffies(10 * 10000);
1213 unsigned i, acquired = 0, rpm_count = 0;
1214 int ret;
1215
1216 for (i = 0; i < nr_events; i++) {
1217 unsigned long remaining;
1218
1219 remaining = wait_for_completion_timeout(&gpu->event_free, timeout);
1220
1221 if (!remaining) {
1222 dev_err(gpu->dev, "wait_for_completion_timeout failed");
1223 ret = -EBUSY;
1224 goto out;
1225 }
1226
1227 acquired++;
1228 timeout = remaining;
1229 }
1230
1231 spin_lock(&gpu->event_spinlock);
1232
1233 for (i = 0; i < nr_events; i++) {
1234 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1235
1236 events[i] = event;
1237 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
1238 set_bit(event, gpu->event_bitmap);
1239 }
1240
1241 spin_unlock(&gpu->event_spinlock);
1242
1243 for (i = 0; i < nr_events; i++) {
1244 ret = pm_runtime_resume_and_get(gpu->dev);
1245 if (ret)
1246 goto out_rpm;
1247 rpm_count++;
1248 }
1249
1250 return 0;
1251
1252 out_rpm:
1253 for (i = 0; i < rpm_count; i++)
1254 pm_runtime_put_autosuspend(gpu->dev);
1255 out:
1256 for (i = 0; i < acquired; i++)
1257 complete(&gpu->event_free);
1258
1259 return ret;
1260 }
1261
event_free(struct etnaviv_gpu * gpu,unsigned int event)1262 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1263 {
1264 if (!test_bit(event, gpu->event_bitmap)) {
1265 dev_warn(gpu->dev, "event %u is already marked as free",
1266 event);
1267 } else {
1268 clear_bit(event, gpu->event_bitmap);
1269 complete(&gpu->event_free);
1270 }
1271
1272 pm_runtime_put_autosuspend(gpu->dev);
1273 }
1274
1275 /*
1276 * Cmdstream submission/retirement:
1277 */
etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu * gpu,u32 id,struct drm_etnaviv_timespec * timeout)1278 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1279 u32 id, struct drm_etnaviv_timespec *timeout)
1280 {
1281 struct dma_fence *fence;
1282 int ret;
1283
1284 /*
1285 * Look up the fence and take a reference. We might still find a fence
1286 * whose refcount has already dropped to zero. dma_fence_get_rcu
1287 * pretends we didn't find a fence in that case.
1288 */
1289 rcu_read_lock();
1290 fence = xa_load(&gpu->user_fences, id);
1291 if (fence)
1292 fence = dma_fence_get_rcu(fence);
1293 rcu_read_unlock();
1294
1295 if (!fence)
1296 return 0;
1297
1298 if (!timeout) {
1299 /* No timeout was requested: just test for completion */
1300 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
1301 } else {
1302 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1303
1304 ret = dma_fence_wait_timeout(fence, true, remaining);
1305 if (ret == 0)
1306 ret = -ETIMEDOUT;
1307 else if (ret != -ERESTARTSYS)
1308 ret = 0;
1309
1310 }
1311
1312 dma_fence_put(fence);
1313 return ret;
1314 }
1315
1316 /*
1317 * Wait for an object to become inactive. This, on it's own, is not race
1318 * free: the object is moved by the scheduler off the active list, and
1319 * then the iova is put. Moreover, the object could be re-submitted just
1320 * after we notice that it's become inactive.
1321 *
1322 * Although the retirement happens under the gpu lock, we don't want to hold
1323 * that lock in this function while waiting.
1324 */
etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu * gpu,struct etnaviv_gem_object * etnaviv_obj,struct drm_etnaviv_timespec * timeout)1325 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1326 struct etnaviv_gem_object *etnaviv_obj,
1327 struct drm_etnaviv_timespec *timeout)
1328 {
1329 unsigned long remaining;
1330 long ret;
1331
1332 if (!timeout)
1333 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1334
1335 remaining = etnaviv_timeout_to_jiffies(timeout);
1336
1337 ret = wait_event_interruptible_timeout(gpu->fence_event,
1338 !is_active(etnaviv_obj),
1339 remaining);
1340 if (ret > 0)
1341 return 0;
1342 else if (ret == -ERESTARTSYS)
1343 return -ERESTARTSYS;
1344 else
1345 return -ETIMEDOUT;
1346 }
1347
sync_point_perfmon_sample(struct etnaviv_gpu * gpu,struct etnaviv_event * event,unsigned int flags)1348 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1349 struct etnaviv_event *event, unsigned int flags)
1350 {
1351 const struct etnaviv_gem_submit *submit = event->submit;
1352 unsigned int i;
1353
1354 for (i = 0; i < submit->nr_pmrs; i++) {
1355 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1356
1357 if (pmr->flags == flags)
1358 etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
1359 }
1360 }
1361
sync_point_perfmon_sample_pre(struct etnaviv_gpu * gpu,struct etnaviv_event * event)1362 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1363 struct etnaviv_event *event)
1364 {
1365 u32 val;
1366
1367 mutex_lock(&gpu->lock);
1368
1369 /* disable clock gating */
1370 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
1371 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1372 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val);
1373
1374 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1375
1376 mutex_unlock(&gpu->lock);
1377 }
1378
sync_point_perfmon_sample_post(struct etnaviv_gpu * gpu,struct etnaviv_event * event)1379 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1380 struct etnaviv_event *event)
1381 {
1382 const struct etnaviv_gem_submit *submit = event->submit;
1383 unsigned int i;
1384 u32 val;
1385
1386 mutex_lock(&gpu->lock);
1387
1388 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1389
1390 /* enable clock gating */
1391 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
1392 val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1393 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val);
1394
1395 mutex_unlock(&gpu->lock);
1396
1397 for (i = 0; i < submit->nr_pmrs; i++) {
1398 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1399
1400 *pmr->bo_vma = pmr->sequence;
1401 }
1402 }
1403
1404
1405 /* add bo's to gpu's ring, and kick gpu: */
etnaviv_gpu_submit(struct etnaviv_gem_submit * submit)1406 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
1407 {
1408 struct etnaviv_gpu *gpu = submit->gpu;
1409 struct dma_fence *gpu_fence;
1410 unsigned int i, nr_events = 1, event[3];
1411 int ret;
1412
1413 /*
1414 * if there are performance monitor requests we need to have
1415 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
1416 * requests.
1417 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
1418 * and update the sequence number for userspace.
1419 */
1420 if (submit->nr_pmrs)
1421 nr_events = 3;
1422
1423 ret = event_alloc(gpu, nr_events, event);
1424 if (ret) {
1425 DRM_ERROR("no free events\n");
1426 pm_runtime_put_noidle(gpu->dev);
1427 return NULL;
1428 }
1429
1430 mutex_lock(&gpu->lock);
1431
1432 gpu_fence = etnaviv_gpu_fence_alloc(gpu);
1433 if (!gpu_fence) {
1434 for (i = 0; i < nr_events; i++)
1435 event_free(gpu, event[i]);
1436
1437 goto out_unlock;
1438 }
1439
1440 if (gpu->state == ETNA_GPU_STATE_INITIALIZED)
1441 etnaviv_gpu_start_fe_idleloop(gpu, submit->mmu_context);
1442
1443 if (submit->prev_mmu_context)
1444 etnaviv_iommu_context_put(submit->prev_mmu_context);
1445 submit->prev_mmu_context = etnaviv_iommu_context_get(gpu->mmu_context);
1446
1447 if (submit->nr_pmrs) {
1448 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
1449 kref_get(&submit->refcount);
1450 gpu->event[event[1]].submit = submit;
1451 etnaviv_sync_point_queue(gpu, event[1]);
1452 }
1453
1454 gpu->event[event[0]].fence = gpu_fence;
1455 submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
1456 etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context,
1457 event[0], &submit->cmdbuf);
1458
1459 if (submit->nr_pmrs) {
1460 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
1461 kref_get(&submit->refcount);
1462 gpu->event[event[2]].submit = submit;
1463 etnaviv_sync_point_queue(gpu, event[2]);
1464 }
1465
1466 out_unlock:
1467 mutex_unlock(&gpu->lock);
1468
1469 return gpu_fence;
1470 }
1471
sync_point_worker(struct work_struct * work)1472 static void sync_point_worker(struct work_struct *work)
1473 {
1474 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1475 sync_point_work);
1476 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1477 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
1478
1479 event->sync_point(gpu, event);
1480 etnaviv_submit_put(event->submit);
1481 event_free(gpu, gpu->sync_point_event);
1482
1483 /* restart FE last to avoid GPU and IRQ racing against this worker */
1484 etnaviv_gpu_start_fe(gpu, addr + 2, 2);
1485 }
1486
etnaviv_gpu_recover_hang(struct etnaviv_gem_submit * submit)1487 void etnaviv_gpu_recover_hang(struct etnaviv_gem_submit *submit)
1488 {
1489 struct etnaviv_gpu *gpu = submit->gpu;
1490 char *comm = NULL, *cmd = NULL;
1491 struct task_struct *task;
1492 unsigned int i;
1493
1494 dev_err(gpu->dev, "recover hung GPU!\n");
1495
1496 task = get_pid_task(submit->pid, PIDTYPE_PID);
1497 if (task) {
1498 comm = kstrdup(task->comm, GFP_KERNEL);
1499 cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
1500 put_task_struct(task);
1501 }
1502
1503 if (comm && cmd)
1504 dev_err(gpu->dev, "offending task: %s (%s)\n", comm, cmd);
1505
1506 kfree(cmd);
1507 kfree(comm);
1508
1509 if (pm_runtime_get_sync(gpu->dev) < 0)
1510 goto pm_put;
1511
1512 mutex_lock(&gpu->lock);
1513
1514 etnaviv_hw_reset(gpu);
1515
1516 /* complete all events, the GPU won't do it after the reset */
1517 spin_lock(&gpu->event_spinlock);
1518 for_each_set_bit(i, gpu->event_bitmap, ETNA_NR_EVENTS)
1519 event_free(gpu, i);
1520 spin_unlock(&gpu->event_spinlock);
1521
1522 etnaviv_gpu_hw_init(gpu);
1523
1524 mutex_unlock(&gpu->lock);
1525 pm_runtime_mark_last_busy(gpu->dev);
1526 pm_put:
1527 pm_runtime_put_autosuspend(gpu->dev);
1528 }
1529
dump_mmu_fault(struct etnaviv_gpu * gpu)1530 static void dump_mmu_fault(struct etnaviv_gpu *gpu)
1531 {
1532 static const char *fault_reasons[] = {
1533 "slave not present",
1534 "page not present",
1535 "write violation",
1536 "out of bounds",
1537 "read security violation",
1538 "write security violation",
1539 };
1540
1541 u32 status_reg, status;
1542 int i;
1543
1544 if (gpu->sec_mode == ETNA_SEC_NONE)
1545 status_reg = VIVS_MMUv2_STATUS;
1546 else
1547 status_reg = VIVS_MMUv2_SEC_STATUS;
1548
1549 status = gpu_read(gpu, status_reg);
1550 dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
1551
1552 for (i = 0; i < 4; i++) {
1553 const char *reason = "unknown";
1554 u32 address_reg;
1555 u32 mmu_status;
1556
1557 mmu_status = (status >> (i * 4)) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK;
1558 if (!mmu_status)
1559 continue;
1560
1561 if ((mmu_status - 1) < ARRAY_SIZE(fault_reasons))
1562 reason = fault_reasons[mmu_status - 1];
1563
1564 if (gpu->sec_mode == ETNA_SEC_NONE)
1565 address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
1566 else
1567 address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
1568
1569 dev_err_ratelimited(gpu->dev,
1570 "MMU %d fault (%s) addr 0x%08x\n",
1571 i, reason, gpu_read(gpu, address_reg));
1572 }
1573 }
1574
irq_handler(int irq,void * data)1575 static irqreturn_t irq_handler(int irq, void *data)
1576 {
1577 struct etnaviv_gpu *gpu = data;
1578 irqreturn_t ret = IRQ_NONE;
1579
1580 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1581
1582 if (intr != 0) {
1583 ktime_t now = ktime_get();
1584 int event;
1585
1586 pm_runtime_mark_last_busy(gpu->dev);
1587
1588 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1589
1590 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1591 dev_err(gpu->dev, "AXI bus error\n");
1592 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1593 }
1594
1595 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1596 dump_mmu_fault(gpu);
1597 gpu->state = ETNA_GPU_STATE_FAULT;
1598 drm_sched_fault(&gpu->sched);
1599 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1600 }
1601
1602 while ((event = ffs(intr)) != 0) {
1603 struct dma_fence *fence;
1604
1605 event -= 1;
1606
1607 intr &= ~(1 << event);
1608
1609 dev_dbg(gpu->dev, "event %u\n", event);
1610
1611 if (gpu->event[event].sync_point) {
1612 gpu->sync_point_event = event;
1613 queue_work(gpu->wq, &gpu->sync_point_work);
1614 }
1615
1616 fence = gpu->event[event].fence;
1617 if (!fence)
1618 continue;
1619
1620 gpu->event[event].fence = NULL;
1621
1622 /*
1623 * Events can be processed out of order. Eg,
1624 * - allocate and queue event 0
1625 * - allocate event 1
1626 * - event 0 completes, we process it
1627 * - allocate and queue event 0
1628 * - event 1 and event 0 complete
1629 * we can end up processing event 0 first, then 1.
1630 */
1631 if (fence_after(fence->seqno, gpu->completed_fence))
1632 gpu->completed_fence = fence->seqno;
1633 dma_fence_signal_timestamp(fence, now);
1634
1635 event_free(gpu, event);
1636 }
1637
1638 ret = IRQ_HANDLED;
1639 }
1640
1641 return ret;
1642 }
1643
etnaviv_gpu_clk_enable(struct etnaviv_gpu * gpu)1644 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1645 {
1646 int ret;
1647
1648 ret = clk_prepare_enable(gpu->clk_reg);
1649 if (ret)
1650 return ret;
1651
1652 ret = clk_prepare_enable(gpu->clk_bus);
1653 if (ret)
1654 goto disable_clk_reg;
1655
1656 ret = clk_prepare_enable(gpu->clk_core);
1657 if (ret)
1658 goto disable_clk_bus;
1659
1660 ret = clk_prepare_enable(gpu->clk_shader);
1661 if (ret)
1662 goto disable_clk_core;
1663
1664 return 0;
1665
1666 disable_clk_core:
1667 clk_disable_unprepare(gpu->clk_core);
1668 disable_clk_bus:
1669 clk_disable_unprepare(gpu->clk_bus);
1670 disable_clk_reg:
1671 clk_disable_unprepare(gpu->clk_reg);
1672
1673 return ret;
1674 }
1675
etnaviv_gpu_clk_disable(struct etnaviv_gpu * gpu)1676 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1677 {
1678 clk_disable_unprepare(gpu->clk_shader);
1679 clk_disable_unprepare(gpu->clk_core);
1680 clk_disable_unprepare(gpu->clk_bus);
1681 clk_disable_unprepare(gpu->clk_reg);
1682
1683 return 0;
1684 }
1685
etnaviv_gpu_wait_idle(struct etnaviv_gpu * gpu,unsigned int timeout_ms)1686 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1687 {
1688 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1689
1690 do {
1691 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1692
1693 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1694 return 0;
1695
1696 if (time_is_before_jiffies(timeout)) {
1697 dev_warn(gpu->dev,
1698 "timed out waiting for idle: idle=0x%x\n",
1699 idle);
1700 return -ETIMEDOUT;
1701 }
1702
1703 udelay(5);
1704 } while (1);
1705 }
1706
etnaviv_gpu_hw_suspend(struct etnaviv_gpu * gpu)1707 static void etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1708 {
1709 if (gpu->state == ETNA_GPU_STATE_RUNNING) {
1710 /* Replace the last WAIT with END */
1711 mutex_lock(&gpu->lock);
1712 etnaviv_buffer_end(gpu);
1713 mutex_unlock(&gpu->lock);
1714
1715 /*
1716 * We know that only the FE is busy here, this should
1717 * happen quickly (as the WAIT is only 200 cycles). If
1718 * we fail, just warn and continue.
1719 */
1720 etnaviv_gpu_wait_idle(gpu, 100);
1721
1722 gpu->state = ETNA_GPU_STATE_INITIALIZED;
1723 }
1724
1725 gpu->exec_state = -1;
1726 }
1727
etnaviv_gpu_hw_resume(struct etnaviv_gpu * gpu)1728 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1729 {
1730 int ret;
1731
1732 ret = mutex_lock_killable(&gpu->lock);
1733 if (ret)
1734 return ret;
1735
1736 etnaviv_gpu_update_clock(gpu);
1737 etnaviv_gpu_hw_init(gpu);
1738
1739 mutex_unlock(&gpu->lock);
1740
1741 return 0;
1742 }
1743
1744 static int
etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device * cdev,unsigned long * state)1745 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1746 unsigned long *state)
1747 {
1748 *state = 6;
1749
1750 return 0;
1751 }
1752
1753 static int
etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device * cdev,unsigned long * state)1754 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1755 unsigned long *state)
1756 {
1757 struct etnaviv_gpu *gpu = cdev->devdata;
1758
1759 *state = gpu->freq_scale;
1760
1761 return 0;
1762 }
1763
1764 static int
etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device * cdev,unsigned long state)1765 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1766 unsigned long state)
1767 {
1768 struct etnaviv_gpu *gpu = cdev->devdata;
1769
1770 mutex_lock(&gpu->lock);
1771 gpu->freq_scale = state;
1772 if (!pm_runtime_suspended(gpu->dev))
1773 etnaviv_gpu_update_clock(gpu);
1774 mutex_unlock(&gpu->lock);
1775
1776 return 0;
1777 }
1778
1779 static const struct thermal_cooling_device_ops cooling_ops = {
1780 .get_max_state = etnaviv_gpu_cooling_get_max_state,
1781 .get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1782 .set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1783 };
1784
etnaviv_gpu_bind(struct device * dev,struct device * master,void * data)1785 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1786 void *data)
1787 {
1788 struct drm_device *drm = data;
1789 struct etnaviv_drm_private *priv = drm->dev_private;
1790 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1791 int ret;
1792
1793 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
1794 gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1795 (char *)dev_name(dev), gpu, &cooling_ops);
1796 if (IS_ERR(gpu->cooling))
1797 return PTR_ERR(gpu->cooling);
1798 }
1799
1800 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1801 if (!gpu->wq) {
1802 ret = -ENOMEM;
1803 goto out_thermal;
1804 }
1805
1806 ret = etnaviv_sched_init(gpu);
1807 if (ret)
1808 goto out_workqueue;
1809
1810 if (!IS_ENABLED(CONFIG_PM)) {
1811 ret = etnaviv_gpu_clk_enable(gpu);
1812 if (ret < 0)
1813 goto out_sched;
1814 }
1815
1816 gpu->drm = drm;
1817 gpu->fence_context = dma_fence_context_alloc(1);
1818 xa_init_flags(&gpu->user_fences, XA_FLAGS_ALLOC);
1819 spin_lock_init(&gpu->fence_spinlock);
1820
1821 INIT_WORK(&gpu->sync_point_work, sync_point_worker);
1822 init_waitqueue_head(&gpu->fence_event);
1823
1824 priv->gpu[priv->num_gpus++] = gpu;
1825
1826 return 0;
1827
1828 out_sched:
1829 etnaviv_sched_fini(gpu);
1830
1831 out_workqueue:
1832 destroy_workqueue(gpu->wq);
1833
1834 out_thermal:
1835 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1836 thermal_cooling_device_unregister(gpu->cooling);
1837
1838 return ret;
1839 }
1840
etnaviv_gpu_unbind(struct device * dev,struct device * master,void * data)1841 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1842 void *data)
1843 {
1844 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1845
1846 DBG("%s", dev_name(gpu->dev));
1847
1848 destroy_workqueue(gpu->wq);
1849
1850 etnaviv_sched_fini(gpu);
1851
1852 if (IS_ENABLED(CONFIG_PM)) {
1853 pm_runtime_get_sync(gpu->dev);
1854 pm_runtime_put_sync_suspend(gpu->dev);
1855 } else {
1856 etnaviv_gpu_hw_suspend(gpu);
1857 etnaviv_gpu_clk_disable(gpu);
1858 }
1859
1860 if (gpu->mmu_context)
1861 etnaviv_iommu_context_put(gpu->mmu_context);
1862
1863 etnaviv_cmdbuf_free(&gpu->buffer);
1864 etnaviv_iommu_global_fini(gpu);
1865
1866 gpu->drm = NULL;
1867 xa_destroy(&gpu->user_fences);
1868
1869 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1870 thermal_cooling_device_unregister(gpu->cooling);
1871 gpu->cooling = NULL;
1872 }
1873
1874 static const struct component_ops gpu_ops = {
1875 .bind = etnaviv_gpu_bind,
1876 .unbind = etnaviv_gpu_unbind,
1877 };
1878
1879 static const struct of_device_id etnaviv_gpu_match[] = {
1880 {
1881 .compatible = "vivante,gc"
1882 },
1883 { /* sentinel */ }
1884 };
1885 MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
1886
etnaviv_gpu_platform_probe(struct platform_device * pdev)1887 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1888 {
1889 struct device *dev = &pdev->dev;
1890 struct etnaviv_gpu *gpu;
1891 int err;
1892
1893 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1894 if (!gpu)
1895 return -ENOMEM;
1896
1897 gpu->dev = dev;
1898 mutex_init(&gpu->lock);
1899 mutex_init(&gpu->sched_lock);
1900
1901 /* Map registers: */
1902 gpu->mmio = devm_platform_ioremap_resource(pdev, 0);
1903 if (IS_ERR(gpu->mmio))
1904 return PTR_ERR(gpu->mmio);
1905
1906
1907 /* Get Reset: */
1908 gpu->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1909 if (IS_ERR(gpu->rst))
1910 return dev_err_probe(dev, PTR_ERR(gpu->rst),
1911 "failed to get reset\n");
1912
1913 err = reset_control_assert(gpu->rst);
1914 if (err)
1915 return dev_err_probe(dev, err, "failed to assert reset\n");
1916
1917 /* Get Interrupt: */
1918 gpu->irq = platform_get_irq(pdev, 0);
1919 if (gpu->irq < 0)
1920 return gpu->irq;
1921
1922 err = devm_request_irq(dev, gpu->irq, irq_handler, 0,
1923 dev_name(dev), gpu);
1924 if (err) {
1925 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1926 return err;
1927 }
1928
1929 /* Get Clocks: */
1930 gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg");
1931 DBG("clk_reg: %p", gpu->clk_reg);
1932 if (IS_ERR(gpu->clk_reg))
1933 return PTR_ERR(gpu->clk_reg);
1934
1935 gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus");
1936 DBG("clk_bus: %p", gpu->clk_bus);
1937 if (IS_ERR(gpu->clk_bus))
1938 return PTR_ERR(gpu->clk_bus);
1939
1940 gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1941 DBG("clk_core: %p", gpu->clk_core);
1942 if (IS_ERR(gpu->clk_core))
1943 return PTR_ERR(gpu->clk_core);
1944 gpu->base_rate_core = clk_get_rate(gpu->clk_core);
1945
1946 gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader");
1947 DBG("clk_shader: %p", gpu->clk_shader);
1948 if (IS_ERR(gpu->clk_shader))
1949 return PTR_ERR(gpu->clk_shader);
1950 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
1951
1952 /* TODO: figure out max mapped size */
1953 dev_set_drvdata(dev, gpu);
1954
1955 /*
1956 * We treat the device as initially suspended. The runtime PM
1957 * autosuspend delay is rather arbitary: no measurements have
1958 * yet been performed to determine an appropriate value.
1959 */
1960 pm_runtime_use_autosuspend(dev);
1961 pm_runtime_set_autosuspend_delay(dev, 200);
1962 pm_runtime_enable(dev);
1963
1964 err = component_add(dev, &gpu_ops);
1965 if (err < 0) {
1966 dev_err(dev, "failed to register component: %d\n", err);
1967 return err;
1968 }
1969
1970 return 0;
1971 }
1972
etnaviv_gpu_platform_remove(struct platform_device * pdev)1973 static void etnaviv_gpu_platform_remove(struct platform_device *pdev)
1974 {
1975 struct etnaviv_gpu *gpu = dev_get_drvdata(&pdev->dev);
1976
1977 component_del(&pdev->dev, &gpu_ops);
1978 pm_runtime_disable(&pdev->dev);
1979
1980 mutex_destroy(&gpu->lock);
1981 mutex_destroy(&gpu->sched_lock);
1982 }
1983
etnaviv_gpu_rpm_suspend(struct device * dev)1984 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1985 {
1986 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1987 u32 idle, mask;
1988
1989 /* If there are any jobs in the HW queue, we're not idle */
1990 if (atomic_read(&gpu->sched.credit_count))
1991 return -EBUSY;
1992
1993 /* Check whether the hardware (except FE and MC) is idle */
1994 mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE |
1995 VIVS_HI_IDLE_STATE_MC);
1996 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1997 if (idle != mask) {
1998 dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n",
1999 idle);
2000 return -EBUSY;
2001 }
2002
2003 etnaviv_gpu_hw_suspend(gpu);
2004
2005 gpu->state = ETNA_GPU_STATE_IDENTIFIED;
2006
2007 return etnaviv_gpu_clk_disable(gpu);
2008 }
2009
etnaviv_gpu_rpm_resume(struct device * dev)2010 static int etnaviv_gpu_rpm_resume(struct device *dev)
2011 {
2012 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
2013 int ret;
2014
2015 ret = etnaviv_gpu_clk_enable(gpu);
2016 if (ret)
2017 return ret;
2018
2019 /* Re-initialise the basic hardware state */
2020 if (gpu->state == ETNA_GPU_STATE_IDENTIFIED) {
2021 ret = etnaviv_gpu_hw_resume(gpu);
2022 if (ret) {
2023 etnaviv_gpu_clk_disable(gpu);
2024 return ret;
2025 }
2026 }
2027
2028 return 0;
2029 }
2030
2031 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
2032 RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, NULL)
2033 };
2034
2035 struct platform_driver etnaviv_gpu_driver = {
2036 .driver = {
2037 .name = "etnaviv-gpu",
2038 .pm = pm_ptr(&etnaviv_gpu_pm_ops),
2039 .of_match_table = etnaviv_gpu_match,
2040 },
2041 .probe = etnaviv_gpu_platform_probe,
2042 .remove = etnaviv_gpu_platform_remove,
2043 .id_table = gpu_ids,
2044 };
2045