1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <drm/drm_edid.h>
25 #include <drm/drm_fourcc.h>
26 #include <drm/drm_modeset_helper.h>
27 #include <drm/drm_modeset_helper_vtables.h>
28 #include <drm/drm_vblank.h>
29
30 #include "amdgpu.h"
31 #include "amdgpu_pm.h"
32 #include "amdgpu_i2c.h"
33 #include "vid.h"
34 #include "atom.h"
35 #include "amdgpu_atombios.h"
36 #include "atombios_crtc.h"
37 #include "atombios_encoders.h"
38 #include "amdgpu_pll.h"
39 #include "amdgpu_connectors.h"
40 #include "amdgpu_display.h"
41 #include "dce_v10_0.h"
42
43 #include "dce/dce_10_0_d.h"
44 #include "dce/dce_10_0_sh_mask.h"
45 #include "dce/dce_10_0_enum.h"
46 #include "oss/oss_3_0_d.h"
47 #include "oss/oss_3_0_sh_mask.h"
48 #include "gmc/gmc_8_1_d.h"
49 #include "gmc/gmc_8_1_sh_mask.h"
50
51 #include "ivsrcid/ivsrcid_vislands30.h"
52
53 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
54 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
55 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, int hpd);
56
57 static const u32 crtc_offsets[] = {
58 CRTC0_REGISTER_OFFSET,
59 CRTC1_REGISTER_OFFSET,
60 CRTC2_REGISTER_OFFSET,
61 CRTC3_REGISTER_OFFSET,
62 CRTC4_REGISTER_OFFSET,
63 CRTC5_REGISTER_OFFSET,
64 CRTC6_REGISTER_OFFSET
65 };
66
67 static const u32 hpd_offsets[] = {
68 HPD0_REGISTER_OFFSET,
69 HPD1_REGISTER_OFFSET,
70 HPD2_REGISTER_OFFSET,
71 HPD3_REGISTER_OFFSET,
72 HPD4_REGISTER_OFFSET,
73 HPD5_REGISTER_OFFSET
74 };
75
76 static const uint32_t dig_offsets[] = {
77 DIG0_REGISTER_OFFSET,
78 DIG1_REGISTER_OFFSET,
79 DIG2_REGISTER_OFFSET,
80 DIG3_REGISTER_OFFSET,
81 DIG4_REGISTER_OFFSET,
82 DIG5_REGISTER_OFFSET,
83 DIG6_REGISTER_OFFSET
84 };
85
86 static const struct {
87 uint32_t reg;
88 uint32_t vblank;
89 uint32_t vline;
90 uint32_t hpd;
91
92 } interrupt_status_offsets[] = { {
93 .reg = mmDISP_INTERRUPT_STATUS,
94 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
95 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
96 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
97 }, {
98 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
99 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
100 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
101 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
102 }, {
103 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
104 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
105 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
106 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
107 }, {
108 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
109 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
110 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
111 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
112 }, {
113 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
114 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
115 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
116 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
117 }, {
118 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
119 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
120 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
121 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
122 } };
123
124 static const u32 golden_settings_tonga_a11[] = {
125 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
126 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
127 mmFBC_MISC, 0x1f311fff, 0x12300000,
128 mmHDMI_CONTROL, 0x31000111, 0x00000011,
129 };
130
131 static const u32 tonga_mgcg_cgcg_init[] = {
132 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
133 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
134 };
135
136 static const u32 golden_settings_fiji_a10[] = {
137 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
138 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
139 mmFBC_MISC, 0x1f311fff, 0x12300000,
140 mmHDMI_CONTROL, 0x31000111, 0x00000011,
141 };
142
143 static const u32 fiji_mgcg_cgcg_init[] = {
144 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
145 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
146 };
147
dce_v10_0_init_golden_registers(struct amdgpu_device * adev)148 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
149 {
150 switch (adev->asic_type) {
151 case CHIP_FIJI:
152 amdgpu_device_program_register_sequence(adev,
153 fiji_mgcg_cgcg_init,
154 ARRAY_SIZE(fiji_mgcg_cgcg_init));
155 amdgpu_device_program_register_sequence(adev,
156 golden_settings_fiji_a10,
157 ARRAY_SIZE(golden_settings_fiji_a10));
158 break;
159 case CHIP_TONGA:
160 amdgpu_device_program_register_sequence(adev,
161 tonga_mgcg_cgcg_init,
162 ARRAY_SIZE(tonga_mgcg_cgcg_init));
163 amdgpu_device_program_register_sequence(adev,
164 golden_settings_tonga_a11,
165 ARRAY_SIZE(golden_settings_tonga_a11));
166 break;
167 default:
168 break;
169 }
170 }
171
dce_v10_0_audio_endpt_rreg(struct amdgpu_device * adev,u32 block_offset,u32 reg)172 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
173 u32 block_offset, u32 reg)
174 {
175 unsigned long flags;
176 u32 r;
177
178 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
179 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
180 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
181 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
182
183 return r;
184 }
185
dce_v10_0_audio_endpt_wreg(struct amdgpu_device * adev,u32 block_offset,u32 reg,u32 v)186 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
187 u32 block_offset, u32 reg, u32 v)
188 {
189 unsigned long flags;
190
191 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
192 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
193 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
194 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
195 }
196
dce_v10_0_vblank_get_counter(struct amdgpu_device * adev,int crtc)197 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
198 {
199 if (crtc >= adev->mode_info.num_crtc)
200 return 0;
201 else
202 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
203 }
204
dce_v10_0_pageflip_interrupt_init(struct amdgpu_device * adev)205 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
206 {
207 unsigned i;
208
209 /* Enable pflip interrupts */
210 for (i = 0; i < adev->mode_info.num_crtc; i++)
211 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
212 }
213
dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device * adev)214 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
215 {
216 unsigned i;
217
218 /* Disable pflip interrupts */
219 for (i = 0; i < adev->mode_info.num_crtc; i++)
220 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
221 }
222
223 /**
224 * dce_v10_0_page_flip - pageflip callback.
225 *
226 * @adev: amdgpu_device pointer
227 * @crtc_id: crtc to cleanup pageflip on
228 * @crtc_base: new address of the crtc (GPU MC address)
229 * @async: asynchronous flip
230 *
231 * Triggers the actual pageflip by updating the primary
232 * surface base address.
233 */
dce_v10_0_page_flip(struct amdgpu_device * adev,int crtc_id,u64 crtc_base,bool async)234 static void dce_v10_0_page_flip(struct amdgpu_device *adev,
235 int crtc_id, u64 crtc_base, bool async)
236 {
237 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
238 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
239 u32 tmp;
240
241 /* flip at hsync for async, default is vsync */
242 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
243 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
244 GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
245 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
246 /* update pitch */
247 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
248 fb->pitches[0] / fb->format->cpp[0]);
249 /* update the primary scanout address */
250 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
251 upper_32_bits(crtc_base));
252 /* writing to the low address triggers the update */
253 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
254 lower_32_bits(crtc_base));
255 /* post the write */
256 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
257 }
258
dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device * adev,int crtc,u32 * vbl,u32 * position)259 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
260 u32 *vbl, u32 *position)
261 {
262 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
263 return -EINVAL;
264
265 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
266 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
267
268 return 0;
269 }
270
271 /**
272 * dce_v10_0_hpd_sense - hpd sense callback.
273 *
274 * @adev: amdgpu_device pointer
275 * @hpd: hpd (hotplug detect) pin
276 *
277 * Checks if a digital monitor is connected (evergreen+).
278 * Returns true if connected, false if not connected.
279 */
dce_v10_0_hpd_sense(struct amdgpu_device * adev,enum amdgpu_hpd_id hpd)280 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
281 enum amdgpu_hpd_id hpd)
282 {
283 bool connected = false;
284
285 if (hpd >= adev->mode_info.num_hpd)
286 return connected;
287
288 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
289 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
290 connected = true;
291
292 return connected;
293 }
294
295 /**
296 * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
297 *
298 * @adev: amdgpu_device pointer
299 * @hpd: hpd (hotplug detect) pin
300 *
301 * Set the polarity of the hpd pin (evergreen+).
302 */
dce_v10_0_hpd_set_polarity(struct amdgpu_device * adev,enum amdgpu_hpd_id hpd)303 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
304 enum amdgpu_hpd_id hpd)
305 {
306 u32 tmp;
307 bool connected = dce_v10_0_hpd_sense(adev, hpd);
308
309 if (hpd >= adev->mode_info.num_hpd)
310 return;
311
312 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
313 if (connected)
314 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
315 else
316 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
317 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
318 }
319
320 /**
321 * dce_v10_0_hpd_init - hpd setup callback.
322 *
323 * @adev: amdgpu_device pointer
324 *
325 * Setup the hpd pins used by the card (evergreen+).
326 * Enable the pin, set the polarity, and enable the hpd interrupts.
327 */
dce_v10_0_hpd_init(struct amdgpu_device * adev)328 static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
329 {
330 struct drm_device *dev = adev_to_drm(adev);
331 struct drm_connector *connector;
332 struct drm_connector_list_iter iter;
333 u32 tmp;
334
335 drm_connector_list_iter_begin(dev, &iter);
336 drm_for_each_connector_iter(connector, &iter) {
337 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
338
339 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
340 continue;
341
342 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
343 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
344 /* don't try to enable hpd on eDP or LVDS avoid breaking the
345 * aux dp channel on imac and help (but not completely fix)
346 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
347 * also avoid interrupt storms during dpms.
348 */
349 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
350 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
351 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
352 continue;
353 }
354
355 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
356 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
357 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
358
359 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
360 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
361 DC_HPD_CONNECT_INT_DELAY,
362 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
363 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
364 DC_HPD_DISCONNECT_INT_DELAY,
365 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
366 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
367
368 dce_v10_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd);
369 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
370 amdgpu_irq_get(adev, &adev->hpd_irq,
371 amdgpu_connector->hpd.hpd);
372 }
373 drm_connector_list_iter_end(&iter);
374 }
375
376 /**
377 * dce_v10_0_hpd_fini - hpd tear down callback.
378 *
379 * @adev: amdgpu_device pointer
380 *
381 * Tear down the hpd pins used by the card (evergreen+).
382 * Disable the hpd interrupts.
383 */
dce_v10_0_hpd_fini(struct amdgpu_device * adev)384 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
385 {
386 struct drm_device *dev = adev_to_drm(adev);
387 struct drm_connector *connector;
388 struct drm_connector_list_iter iter;
389 u32 tmp;
390
391 drm_connector_list_iter_begin(dev, &iter);
392 drm_for_each_connector_iter(connector, &iter) {
393 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
394
395 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
396 continue;
397
398 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
399 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
400 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
401
402 amdgpu_irq_put(adev, &adev->hpd_irq,
403 amdgpu_connector->hpd.hpd);
404 }
405 drm_connector_list_iter_end(&iter);
406 }
407
dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device * adev)408 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
409 {
410 return mmDC_GPIO_HPD_A;
411 }
412
dce_v10_0_is_display_hung(struct amdgpu_device * adev)413 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
414 {
415 u32 crtc_hung = 0;
416 u32 crtc_status[6];
417 u32 i, j, tmp;
418
419 for (i = 0; i < adev->mode_info.num_crtc; i++) {
420 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
421 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
422 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
423 crtc_hung |= (1 << i);
424 }
425 }
426
427 for (j = 0; j < 10; j++) {
428 for (i = 0; i < adev->mode_info.num_crtc; i++) {
429 if (crtc_hung & (1 << i)) {
430 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
431 if (tmp != crtc_status[i])
432 crtc_hung &= ~(1 << i);
433 }
434 }
435 if (crtc_hung == 0)
436 return false;
437 udelay(100);
438 }
439
440 return true;
441 }
442
dce_v10_0_set_vga_render_state(struct amdgpu_device * adev,bool render)443 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
444 bool render)
445 {
446 u32 tmp;
447
448 /* Lockout access through VGA aperture*/
449 tmp = RREG32(mmVGA_HDP_CONTROL);
450 if (render)
451 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
452 else
453 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
454 WREG32(mmVGA_HDP_CONTROL, tmp);
455
456 /* disable VGA render */
457 tmp = RREG32(mmVGA_RENDER_CONTROL);
458 if (render)
459 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
460 else
461 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
462 WREG32(mmVGA_RENDER_CONTROL, tmp);
463 }
464
dce_v10_0_get_num_crtc(struct amdgpu_device * adev)465 static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev)
466 {
467 int num_crtc = 0;
468
469 switch (adev->asic_type) {
470 case CHIP_FIJI:
471 case CHIP_TONGA:
472 num_crtc = 6;
473 break;
474 default:
475 num_crtc = 0;
476 }
477 return num_crtc;
478 }
479
dce_v10_0_disable_dce(struct amdgpu_device * adev)480 void dce_v10_0_disable_dce(struct amdgpu_device *adev)
481 {
482 /*Disable VGA render and enabled crtc, if has DCE engine*/
483 if (amdgpu_atombios_has_dce_engine_info(adev)) {
484 u32 tmp;
485 int crtc_enabled, i;
486
487 dce_v10_0_set_vga_render_state(adev, false);
488
489 /*Disable crtc*/
490 for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) {
491 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
492 CRTC_CONTROL, CRTC_MASTER_EN);
493 if (crtc_enabled) {
494 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
495 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
496 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
497 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
498 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
499 }
500 }
501 }
502 }
503
dce_v10_0_program_fmt(struct drm_encoder * encoder)504 static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
505 {
506 struct drm_device *dev = encoder->dev;
507 struct amdgpu_device *adev = drm_to_adev(dev);
508 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
509 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
510 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
511 int bpc = 0;
512 u32 tmp = 0;
513 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
514
515 if (connector) {
516 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
517 bpc = amdgpu_connector_get_monitor_bpc(connector);
518 dither = amdgpu_connector->dither;
519 }
520
521 /* LVDS/eDP FMT is set up by atom */
522 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
523 return;
524
525 /* not needed for analog */
526 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
527 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
528 return;
529
530 if (bpc == 0)
531 return;
532
533 switch (bpc) {
534 case 6:
535 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
536 /* XXX sort out optimal dither settings */
537 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
538 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
539 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
540 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
541 } else {
542 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
543 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
544 }
545 break;
546 case 8:
547 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
548 /* XXX sort out optimal dither settings */
549 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
550 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
551 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
552 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
553 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
554 } else {
555 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
556 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
557 }
558 break;
559 case 10:
560 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
561 /* XXX sort out optimal dither settings */
562 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
563 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
564 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
565 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
566 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
567 } else {
568 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
569 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
570 }
571 break;
572 default:
573 /* not needed */
574 break;
575 }
576
577 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
578 }
579
580
581 /* display watermark setup */
582 /**
583 * dce_v10_0_line_buffer_adjust - Set up the line buffer
584 *
585 * @adev: amdgpu_device pointer
586 * @amdgpu_crtc: the selected display controller
587 * @mode: the current display mode on the selected display
588 * controller
589 *
590 * Setup up the line buffer allocation for
591 * the selected display controller (CIK).
592 * Returns the line buffer size in pixels.
593 */
dce_v10_0_line_buffer_adjust(struct amdgpu_device * adev,struct amdgpu_crtc * amdgpu_crtc,struct drm_display_mode * mode)594 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
595 struct amdgpu_crtc *amdgpu_crtc,
596 struct drm_display_mode *mode)
597 {
598 u32 tmp, buffer_alloc, i, mem_cfg;
599 u32 pipe_offset = amdgpu_crtc->crtc_id;
600 /*
601 * Line Buffer Setup
602 * There are 6 line buffers, one for each display controllers.
603 * There are 3 partitions per LB. Select the number of partitions
604 * to enable based on the display width. For display widths larger
605 * than 4096, you need use to use 2 display controllers and combine
606 * them using the stereo blender.
607 */
608 if (amdgpu_crtc->base.enabled && mode) {
609 if (mode->crtc_hdisplay < 1920) {
610 mem_cfg = 1;
611 buffer_alloc = 2;
612 } else if (mode->crtc_hdisplay < 2560) {
613 mem_cfg = 2;
614 buffer_alloc = 2;
615 } else if (mode->crtc_hdisplay < 4096) {
616 mem_cfg = 0;
617 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
618 } else {
619 DRM_DEBUG_KMS("Mode too big for LB!\n");
620 mem_cfg = 0;
621 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
622 }
623 } else {
624 mem_cfg = 1;
625 buffer_alloc = 0;
626 }
627
628 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
629 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
630 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
631
632 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
633 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
634 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
635
636 for (i = 0; i < adev->usec_timeout; i++) {
637 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
638 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
639 break;
640 udelay(1);
641 }
642
643 if (amdgpu_crtc->base.enabled && mode) {
644 switch (mem_cfg) {
645 case 0:
646 default:
647 return 4096 * 2;
648 case 1:
649 return 1920 * 2;
650 case 2:
651 return 2560 * 2;
652 }
653 }
654
655 /* controller not enabled, so no lb used */
656 return 0;
657 }
658
659 /**
660 * cik_get_number_of_dram_channels - get the number of dram channels
661 *
662 * @adev: amdgpu_device pointer
663 *
664 * Look up the number of video ram channels (CIK).
665 * Used for display watermark bandwidth calculations
666 * Returns the number of dram channels
667 */
cik_get_number_of_dram_channels(struct amdgpu_device * adev)668 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
669 {
670 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
671
672 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
673 case 0:
674 default:
675 return 1;
676 case 1:
677 return 2;
678 case 2:
679 return 4;
680 case 3:
681 return 8;
682 case 4:
683 return 3;
684 case 5:
685 return 6;
686 case 6:
687 return 10;
688 case 7:
689 return 12;
690 case 8:
691 return 16;
692 }
693 }
694
695 struct dce10_wm_params {
696 u32 dram_channels; /* number of dram channels */
697 u32 yclk; /* bandwidth per dram data pin in kHz */
698 u32 sclk; /* engine clock in kHz */
699 u32 disp_clk; /* display clock in kHz */
700 u32 src_width; /* viewport width */
701 u32 active_time; /* active display time in ns */
702 u32 blank_time; /* blank time in ns */
703 bool interlaced; /* mode is interlaced */
704 fixed20_12 vsc; /* vertical scale ratio */
705 u32 num_heads; /* number of active crtcs */
706 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
707 u32 lb_size; /* line buffer allocated to pipe */
708 u32 vtaps; /* vertical scaler taps */
709 };
710
711 /**
712 * dce_v10_0_dram_bandwidth - get the dram bandwidth
713 *
714 * @wm: watermark calculation data
715 *
716 * Calculate the raw dram bandwidth (CIK).
717 * Used for display watermark bandwidth calculations
718 * Returns the dram bandwidth in MBytes/s
719 */
dce_v10_0_dram_bandwidth(struct dce10_wm_params * wm)720 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
721 {
722 /* Calculate raw DRAM Bandwidth */
723 fixed20_12 dram_efficiency; /* 0.7 */
724 fixed20_12 yclk, dram_channels, bandwidth;
725 fixed20_12 a;
726
727 a.full = dfixed_const(1000);
728 yclk.full = dfixed_const(wm->yclk);
729 yclk.full = dfixed_div(yclk, a);
730 dram_channels.full = dfixed_const(wm->dram_channels * 4);
731 a.full = dfixed_const(10);
732 dram_efficiency.full = dfixed_const(7);
733 dram_efficiency.full = dfixed_div(dram_efficiency, a);
734 bandwidth.full = dfixed_mul(dram_channels, yclk);
735 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
736
737 return dfixed_trunc(bandwidth);
738 }
739
740 /**
741 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
742 *
743 * @wm: watermark calculation data
744 *
745 * Calculate the dram bandwidth used for display (CIK).
746 * Used for display watermark bandwidth calculations
747 * Returns the dram bandwidth for display in MBytes/s
748 */
dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params * wm)749 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
750 {
751 /* Calculate DRAM Bandwidth and the part allocated to display. */
752 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
753 fixed20_12 yclk, dram_channels, bandwidth;
754 fixed20_12 a;
755
756 a.full = dfixed_const(1000);
757 yclk.full = dfixed_const(wm->yclk);
758 yclk.full = dfixed_div(yclk, a);
759 dram_channels.full = dfixed_const(wm->dram_channels * 4);
760 a.full = dfixed_const(10);
761 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
762 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
763 bandwidth.full = dfixed_mul(dram_channels, yclk);
764 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
765
766 return dfixed_trunc(bandwidth);
767 }
768
769 /**
770 * dce_v10_0_data_return_bandwidth - get the data return bandwidth
771 *
772 * @wm: watermark calculation data
773 *
774 * Calculate the data return bandwidth used for display (CIK).
775 * Used for display watermark bandwidth calculations
776 * Returns the data return bandwidth in MBytes/s
777 */
dce_v10_0_data_return_bandwidth(struct dce10_wm_params * wm)778 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
779 {
780 /* Calculate the display Data return Bandwidth */
781 fixed20_12 return_efficiency; /* 0.8 */
782 fixed20_12 sclk, bandwidth;
783 fixed20_12 a;
784
785 a.full = dfixed_const(1000);
786 sclk.full = dfixed_const(wm->sclk);
787 sclk.full = dfixed_div(sclk, a);
788 a.full = dfixed_const(10);
789 return_efficiency.full = dfixed_const(8);
790 return_efficiency.full = dfixed_div(return_efficiency, a);
791 a.full = dfixed_const(32);
792 bandwidth.full = dfixed_mul(a, sclk);
793 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
794
795 return dfixed_trunc(bandwidth);
796 }
797
798 /**
799 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
800 *
801 * @wm: watermark calculation data
802 *
803 * Calculate the dmif bandwidth used for display (CIK).
804 * Used for display watermark bandwidth calculations
805 * Returns the dmif bandwidth in MBytes/s
806 */
dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params * wm)807 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
808 {
809 /* Calculate the DMIF Request Bandwidth */
810 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
811 fixed20_12 disp_clk, bandwidth;
812 fixed20_12 a, b;
813
814 a.full = dfixed_const(1000);
815 disp_clk.full = dfixed_const(wm->disp_clk);
816 disp_clk.full = dfixed_div(disp_clk, a);
817 a.full = dfixed_const(32);
818 b.full = dfixed_mul(a, disp_clk);
819
820 a.full = dfixed_const(10);
821 disp_clk_request_efficiency.full = dfixed_const(8);
822 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
823
824 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
825
826 return dfixed_trunc(bandwidth);
827 }
828
829 /**
830 * dce_v10_0_available_bandwidth - get the min available bandwidth
831 *
832 * @wm: watermark calculation data
833 *
834 * Calculate the min available bandwidth used for display (CIK).
835 * Used for display watermark bandwidth calculations
836 * Returns the min available bandwidth in MBytes/s
837 */
dce_v10_0_available_bandwidth(struct dce10_wm_params * wm)838 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
839 {
840 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
841 u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
842 u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
843 u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
844
845 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
846 }
847
848 /**
849 * dce_v10_0_average_bandwidth - get the average available bandwidth
850 *
851 * @wm: watermark calculation data
852 *
853 * Calculate the average available bandwidth used for display (CIK).
854 * Used for display watermark bandwidth calculations
855 * Returns the average available bandwidth in MBytes/s
856 */
dce_v10_0_average_bandwidth(struct dce10_wm_params * wm)857 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
858 {
859 /* Calculate the display mode Average Bandwidth
860 * DisplayMode should contain the source and destination dimensions,
861 * timing, etc.
862 */
863 fixed20_12 bpp;
864 fixed20_12 line_time;
865 fixed20_12 src_width;
866 fixed20_12 bandwidth;
867 fixed20_12 a;
868
869 a.full = dfixed_const(1000);
870 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
871 line_time.full = dfixed_div(line_time, a);
872 bpp.full = dfixed_const(wm->bytes_per_pixel);
873 src_width.full = dfixed_const(wm->src_width);
874 bandwidth.full = dfixed_mul(src_width, bpp);
875 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
876 bandwidth.full = dfixed_div(bandwidth, line_time);
877
878 return dfixed_trunc(bandwidth);
879 }
880
881 /**
882 * dce_v10_0_latency_watermark - get the latency watermark
883 *
884 * @wm: watermark calculation data
885 *
886 * Calculate the latency watermark (CIK).
887 * Used for display watermark bandwidth calculations
888 * Returns the latency watermark in ns
889 */
dce_v10_0_latency_watermark(struct dce10_wm_params * wm)890 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
891 {
892 /* First calculate the latency in ns */
893 u32 mc_latency = 2000; /* 2000 ns. */
894 u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
895 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
896 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
897 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
898 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
899 (wm->num_heads * cursor_line_pair_return_time);
900 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
901 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
902 u32 tmp, dmif_size = 12288;
903 fixed20_12 a, b, c;
904
905 if (wm->num_heads == 0)
906 return 0;
907
908 a.full = dfixed_const(2);
909 b.full = dfixed_const(1);
910 if ((wm->vsc.full > a.full) ||
911 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
912 (wm->vtaps >= 5) ||
913 ((wm->vsc.full >= a.full) && wm->interlaced))
914 max_src_lines_per_dst_line = 4;
915 else
916 max_src_lines_per_dst_line = 2;
917
918 a.full = dfixed_const(available_bandwidth);
919 b.full = dfixed_const(wm->num_heads);
920 a.full = dfixed_div(a, b);
921 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
922 tmp = min(dfixed_trunc(a), tmp);
923
924 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
925
926 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
927 b.full = dfixed_const(1000);
928 c.full = dfixed_const(lb_fill_bw);
929 b.full = dfixed_div(c, b);
930 a.full = dfixed_div(a, b);
931 line_fill_time = dfixed_trunc(a);
932
933 if (line_fill_time < wm->active_time)
934 return latency;
935 else
936 return latency + (line_fill_time - wm->active_time);
937
938 }
939
940 /**
941 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
942 * average and available dram bandwidth
943 *
944 * @wm: watermark calculation data
945 *
946 * Check if the display average bandwidth fits in the display
947 * dram bandwidth (CIK).
948 * Used for display watermark bandwidth calculations
949 * Returns true if the display fits, false if not.
950 */
dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params * wm)951 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
952 {
953 if (dce_v10_0_average_bandwidth(wm) <=
954 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
955 return true;
956 else
957 return false;
958 }
959
960 /**
961 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
962 * average and available bandwidth
963 *
964 * @wm: watermark calculation data
965 *
966 * Check if the display average bandwidth fits in the display
967 * available bandwidth (CIK).
968 * Used for display watermark bandwidth calculations
969 * Returns true if the display fits, false if not.
970 */
dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params * wm)971 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
972 {
973 if (dce_v10_0_average_bandwidth(wm) <=
974 (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
975 return true;
976 else
977 return false;
978 }
979
980 /**
981 * dce_v10_0_check_latency_hiding - check latency hiding
982 *
983 * @wm: watermark calculation data
984 *
985 * Check latency hiding (CIK).
986 * Used for display watermark bandwidth calculations
987 * Returns true if the display fits, false if not.
988 */
dce_v10_0_check_latency_hiding(struct dce10_wm_params * wm)989 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
990 {
991 u32 lb_partitions = wm->lb_size / wm->src_width;
992 u32 line_time = wm->active_time + wm->blank_time;
993 u32 latency_tolerant_lines;
994 u32 latency_hiding;
995 fixed20_12 a;
996
997 a.full = dfixed_const(1);
998 if (wm->vsc.full > a.full)
999 latency_tolerant_lines = 1;
1000 else {
1001 if (lb_partitions <= (wm->vtaps + 1))
1002 latency_tolerant_lines = 1;
1003 else
1004 latency_tolerant_lines = 2;
1005 }
1006
1007 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1008
1009 if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1010 return true;
1011 else
1012 return false;
1013 }
1014
1015 /**
1016 * dce_v10_0_program_watermarks - program display watermarks
1017 *
1018 * @adev: amdgpu_device pointer
1019 * @amdgpu_crtc: the selected display controller
1020 * @lb_size: line buffer size
1021 * @num_heads: number of display controllers in use
1022 *
1023 * Calculate and program the display watermarks for the
1024 * selected display controller (CIK).
1025 */
dce_v10_0_program_watermarks(struct amdgpu_device * adev,struct amdgpu_crtc * amdgpu_crtc,u32 lb_size,u32 num_heads)1026 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1027 struct amdgpu_crtc *amdgpu_crtc,
1028 u32 lb_size, u32 num_heads)
1029 {
1030 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1031 struct dce10_wm_params wm_low, wm_high;
1032 u32 active_time;
1033 u32 line_time = 0;
1034 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1035 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1036
1037 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1038 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1039 (u32)mode->clock);
1040 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1041 (u32)mode->clock);
1042 line_time = min_t(u32, line_time, 65535);
1043
1044 /* watermark for high clocks */
1045 if (adev->pm.dpm_enabled) {
1046 wm_high.yclk =
1047 amdgpu_dpm_get_mclk(adev, false) * 10;
1048 wm_high.sclk =
1049 amdgpu_dpm_get_sclk(adev, false) * 10;
1050 } else {
1051 wm_high.yclk = adev->pm.current_mclk * 10;
1052 wm_high.sclk = adev->pm.current_sclk * 10;
1053 }
1054
1055 wm_high.disp_clk = mode->clock;
1056 wm_high.src_width = mode->crtc_hdisplay;
1057 wm_high.active_time = active_time;
1058 wm_high.blank_time = line_time - wm_high.active_time;
1059 wm_high.interlaced = false;
1060 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1061 wm_high.interlaced = true;
1062 wm_high.vsc = amdgpu_crtc->vsc;
1063 wm_high.vtaps = 1;
1064 if (amdgpu_crtc->rmx_type != RMX_OFF)
1065 wm_high.vtaps = 2;
1066 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1067 wm_high.lb_size = lb_size;
1068 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1069 wm_high.num_heads = num_heads;
1070
1071 /* set for high clocks */
1072 latency_watermark_a = min_t(u32, dce_v10_0_latency_watermark(&wm_high), 65535);
1073
1074 /* possibly force display priority to high */
1075 /* should really do this at mode validation time... */
1076 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1077 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1078 !dce_v10_0_check_latency_hiding(&wm_high) ||
1079 (adev->mode_info.disp_priority == 2)) {
1080 DRM_DEBUG_KMS("force priority to high\n");
1081 }
1082
1083 /* watermark for low clocks */
1084 if (adev->pm.dpm_enabled) {
1085 wm_low.yclk =
1086 amdgpu_dpm_get_mclk(adev, true) * 10;
1087 wm_low.sclk =
1088 amdgpu_dpm_get_sclk(adev, true) * 10;
1089 } else {
1090 wm_low.yclk = adev->pm.current_mclk * 10;
1091 wm_low.sclk = adev->pm.current_sclk * 10;
1092 }
1093
1094 wm_low.disp_clk = mode->clock;
1095 wm_low.src_width = mode->crtc_hdisplay;
1096 wm_low.active_time = active_time;
1097 wm_low.blank_time = line_time - wm_low.active_time;
1098 wm_low.interlaced = false;
1099 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1100 wm_low.interlaced = true;
1101 wm_low.vsc = amdgpu_crtc->vsc;
1102 wm_low.vtaps = 1;
1103 if (amdgpu_crtc->rmx_type != RMX_OFF)
1104 wm_low.vtaps = 2;
1105 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1106 wm_low.lb_size = lb_size;
1107 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1108 wm_low.num_heads = num_heads;
1109
1110 /* set for low clocks */
1111 latency_watermark_b = min_t(u32, dce_v10_0_latency_watermark(&wm_low), 65535);
1112
1113 /* possibly force display priority to high */
1114 /* should really do this at mode validation time... */
1115 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1116 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1117 !dce_v10_0_check_latency_hiding(&wm_low) ||
1118 (adev->mode_info.disp_priority == 2)) {
1119 DRM_DEBUG_KMS("force priority to high\n");
1120 }
1121 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1122 }
1123
1124 /* select wm A */
1125 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1126 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1127 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1128 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1129 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1130 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1131 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1132 /* select wm B */
1133 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1134 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1135 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1136 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1137 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1138 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1139 /* restore original selection */
1140 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1141
1142 /* save values for DPM */
1143 amdgpu_crtc->line_time = line_time;
1144
1145 /* Save number of lines the linebuffer leads before the scanout */
1146 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1147 }
1148
1149 /**
1150 * dce_v10_0_bandwidth_update - program display watermarks
1151 *
1152 * @adev: amdgpu_device pointer
1153 *
1154 * Calculate and program the display watermarks and line
1155 * buffer allocation (CIK).
1156 */
dce_v10_0_bandwidth_update(struct amdgpu_device * adev)1157 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1158 {
1159 struct drm_display_mode *mode = NULL;
1160 u32 num_heads = 0, lb_size;
1161 int i;
1162
1163 amdgpu_display_update_priority(adev);
1164
1165 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1166 if (adev->mode_info.crtcs[i]->base.enabled)
1167 num_heads++;
1168 }
1169 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1170 mode = &adev->mode_info.crtcs[i]->base.mode;
1171 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1172 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1173 lb_size, num_heads);
1174 }
1175 }
1176
dce_v10_0_audio_get_connected_pins(struct amdgpu_device * adev)1177 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1178 {
1179 int i;
1180 u32 offset, tmp;
1181
1182 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1183 offset = adev->mode_info.audio.pin[i].offset;
1184 tmp = RREG32_AUDIO_ENDPT(offset,
1185 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1186 if (((tmp &
1187 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1188 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1189 adev->mode_info.audio.pin[i].connected = false;
1190 else
1191 adev->mode_info.audio.pin[i].connected = true;
1192 }
1193 }
1194
dce_v10_0_audio_get_pin(struct amdgpu_device * adev)1195 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1196 {
1197 int i;
1198
1199 dce_v10_0_audio_get_connected_pins(adev);
1200
1201 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1202 if (adev->mode_info.audio.pin[i].connected)
1203 return &adev->mode_info.audio.pin[i];
1204 }
1205 DRM_ERROR("No connected audio pins found!\n");
1206 return NULL;
1207 }
1208
dce_v10_0_afmt_audio_select_pin(struct drm_encoder * encoder)1209 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1210 {
1211 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
1212 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1213 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1214 u32 tmp;
1215
1216 if (!dig || !dig->afmt || !dig->afmt->pin)
1217 return;
1218
1219 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1220 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1221 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1222 }
1223
dce_v10_0_audio_write_latency_fields(struct drm_encoder * encoder,struct drm_display_mode * mode)1224 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1225 struct drm_display_mode *mode)
1226 {
1227 struct drm_device *dev = encoder->dev;
1228 struct amdgpu_device *adev = drm_to_adev(dev);
1229 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1230 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1231 struct drm_connector *connector;
1232 struct drm_connector_list_iter iter;
1233 struct amdgpu_connector *amdgpu_connector = NULL;
1234 u32 tmp;
1235 int interlace = 0;
1236
1237 if (!dig || !dig->afmt || !dig->afmt->pin)
1238 return;
1239
1240 drm_connector_list_iter_begin(dev, &iter);
1241 drm_for_each_connector_iter(connector, &iter) {
1242 if (connector->encoder == encoder) {
1243 amdgpu_connector = to_amdgpu_connector(connector);
1244 break;
1245 }
1246 }
1247 drm_connector_list_iter_end(&iter);
1248
1249 if (!amdgpu_connector) {
1250 DRM_ERROR("Couldn't find encoder's connector\n");
1251 return;
1252 }
1253
1254 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1255 interlace = 1;
1256 if (connector->latency_present[interlace]) {
1257 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1258 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1259 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1260 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1261 } else {
1262 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1263 VIDEO_LIPSYNC, 0);
1264 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1265 AUDIO_LIPSYNC, 0);
1266 }
1267 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1268 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1269 }
1270
dce_v10_0_audio_write_speaker_allocation(struct drm_encoder * encoder)1271 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1272 {
1273 struct drm_device *dev = encoder->dev;
1274 struct amdgpu_device *adev = drm_to_adev(dev);
1275 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1276 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1277 struct drm_connector *connector;
1278 struct drm_connector_list_iter iter;
1279 struct amdgpu_connector *amdgpu_connector = NULL;
1280 u32 tmp;
1281 u8 *sadb = NULL;
1282 int sad_count;
1283
1284 if (!dig || !dig->afmt || !dig->afmt->pin)
1285 return;
1286
1287 drm_connector_list_iter_begin(dev, &iter);
1288 drm_for_each_connector_iter(connector, &iter) {
1289 if (connector->encoder == encoder) {
1290 amdgpu_connector = to_amdgpu_connector(connector);
1291 break;
1292 }
1293 }
1294 drm_connector_list_iter_end(&iter);
1295
1296 if (!amdgpu_connector) {
1297 DRM_ERROR("Couldn't find encoder's connector\n");
1298 return;
1299 }
1300
1301 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb);
1302 if (sad_count < 0) {
1303 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1304 sad_count = 0;
1305 }
1306
1307 /* program the speaker allocation */
1308 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1309 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1310 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1311 DP_CONNECTION, 0);
1312 /* set HDMI mode */
1313 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1314 HDMI_CONNECTION, 1);
1315 if (sad_count)
1316 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1317 SPEAKER_ALLOCATION, sadb[0]);
1318 else
1319 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1320 SPEAKER_ALLOCATION, 5); /* stereo */
1321 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1322 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1323
1324 kfree(sadb);
1325 }
1326
dce_v10_0_audio_write_sad_regs(struct drm_encoder * encoder)1327 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1328 {
1329 struct drm_device *dev = encoder->dev;
1330 struct amdgpu_device *adev = drm_to_adev(dev);
1331 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1332 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1333 struct drm_connector *connector;
1334 struct drm_connector_list_iter iter;
1335 struct amdgpu_connector *amdgpu_connector = NULL;
1336 struct cea_sad *sads;
1337 int i, sad_count;
1338
1339 static const u16 eld_reg_to_type[][2] = {
1340 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1341 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1342 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1343 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1344 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1345 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1346 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1347 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1348 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1349 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1350 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1351 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1352 };
1353
1354 if (!dig || !dig->afmt || !dig->afmt->pin)
1355 return;
1356
1357 drm_connector_list_iter_begin(dev, &iter);
1358 drm_for_each_connector_iter(connector, &iter) {
1359 if (connector->encoder == encoder) {
1360 amdgpu_connector = to_amdgpu_connector(connector);
1361 break;
1362 }
1363 }
1364 drm_connector_list_iter_end(&iter);
1365
1366 if (!amdgpu_connector) {
1367 DRM_ERROR("Couldn't find encoder's connector\n");
1368 return;
1369 }
1370
1371 sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads);
1372 if (sad_count < 0)
1373 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1374 if (sad_count <= 0)
1375 return;
1376 BUG_ON(!sads);
1377
1378 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1379 u32 tmp = 0;
1380 u8 stereo_freqs = 0;
1381 int max_channels = -1;
1382 int j;
1383
1384 for (j = 0; j < sad_count; j++) {
1385 struct cea_sad *sad = &sads[j];
1386
1387 if (sad->format == eld_reg_to_type[i][1]) {
1388 if (sad->channels > max_channels) {
1389 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1390 MAX_CHANNELS, sad->channels);
1391 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1392 DESCRIPTOR_BYTE_2, sad->byte2);
1393 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1394 SUPPORTED_FREQUENCIES, sad->freq);
1395 max_channels = sad->channels;
1396 }
1397
1398 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1399 stereo_freqs |= sad->freq;
1400 else
1401 break;
1402 }
1403 }
1404
1405 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1406 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1407 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1408 }
1409
1410 kfree(sads);
1411 }
1412
dce_v10_0_audio_enable(struct amdgpu_device * adev,struct amdgpu_audio_pin * pin,bool enable)1413 static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1414 struct amdgpu_audio_pin *pin,
1415 bool enable)
1416 {
1417 if (!pin)
1418 return;
1419
1420 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1421 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1422 }
1423
1424 static const u32 pin_offsets[] = {
1425 AUD0_REGISTER_OFFSET,
1426 AUD1_REGISTER_OFFSET,
1427 AUD2_REGISTER_OFFSET,
1428 AUD3_REGISTER_OFFSET,
1429 AUD4_REGISTER_OFFSET,
1430 AUD5_REGISTER_OFFSET,
1431 AUD6_REGISTER_OFFSET,
1432 };
1433
dce_v10_0_audio_init(struct amdgpu_device * adev)1434 static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1435 {
1436 int i;
1437
1438 if (!amdgpu_audio)
1439 return 0;
1440
1441 adev->mode_info.audio.enabled = true;
1442
1443 adev->mode_info.audio.num_pins = 7;
1444
1445 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1446 adev->mode_info.audio.pin[i].channels = -1;
1447 adev->mode_info.audio.pin[i].rate = -1;
1448 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1449 adev->mode_info.audio.pin[i].status_bits = 0;
1450 adev->mode_info.audio.pin[i].category_code = 0;
1451 adev->mode_info.audio.pin[i].connected = false;
1452 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1453 adev->mode_info.audio.pin[i].id = i;
1454 /* disable audio. it will be set up later */
1455 /* XXX remove once we switch to ip funcs */
1456 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1457 }
1458
1459 return 0;
1460 }
1461
dce_v10_0_audio_fini(struct amdgpu_device * adev)1462 static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1463 {
1464 if (!amdgpu_audio)
1465 return;
1466
1467 if (!adev->mode_info.audio.enabled)
1468 return;
1469
1470 adev->mode_info.audio.enabled = false;
1471 }
1472
1473 /*
1474 * update the N and CTS parameters for a given pixel clock rate
1475 */
dce_v10_0_afmt_update_ACR(struct drm_encoder * encoder,uint32_t clock)1476 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1477 {
1478 struct drm_device *dev = encoder->dev;
1479 struct amdgpu_device *adev = drm_to_adev(dev);
1480 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1481 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1482 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1483 u32 tmp;
1484
1485 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1486 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1487 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1488 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1489 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1490 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1491
1492 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1493 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1494 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1495 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1496 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1497 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1498
1499 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1500 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1501 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1502 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1503 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1504 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1505
1506 }
1507
1508 /*
1509 * build a HDMI Video Info Frame
1510 */
dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder * encoder,void * buffer,size_t size)1511 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1512 void *buffer, size_t size)
1513 {
1514 struct drm_device *dev = encoder->dev;
1515 struct amdgpu_device *adev = drm_to_adev(dev);
1516 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1517 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1518 uint8_t *frame = buffer + 3;
1519 uint8_t *header = buffer;
1520
1521 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1522 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1523 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1524 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1525 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1526 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1527 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1528 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1529 }
1530
dce_v10_0_audio_set_dto(struct drm_encoder * encoder,u32 clock)1531 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1532 {
1533 struct drm_device *dev = encoder->dev;
1534 struct amdgpu_device *adev = drm_to_adev(dev);
1535 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1536 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1537 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1538 u32 dto_phase = 24 * 1000;
1539 u32 dto_modulo = clock;
1540 u32 tmp;
1541
1542 if (!dig || !dig->afmt)
1543 return;
1544
1545 /* XXX two dtos; generally use dto0 for hdmi */
1546 /* Express [24MHz / target pixel clock] as an exact rational
1547 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1548 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1549 */
1550 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1551 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1552 amdgpu_crtc->crtc_id);
1553 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1554 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1555 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1556 }
1557
1558 /*
1559 * update the info frames with the data from the current display mode
1560 */
dce_v10_0_afmt_setmode(struct drm_encoder * encoder,struct drm_display_mode * mode)1561 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1562 struct drm_display_mode *mode)
1563 {
1564 struct drm_device *dev = encoder->dev;
1565 struct amdgpu_device *adev = drm_to_adev(dev);
1566 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1567 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1568 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1569 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1570 struct hdmi_avi_infoframe frame;
1571 ssize_t err;
1572 u32 tmp;
1573 int bpc = 8;
1574
1575 if (!dig || !dig->afmt)
1576 return;
1577
1578 /* Silent, r600_hdmi_enable will raise WARN for us */
1579 if (!dig->afmt->enabled)
1580 return;
1581
1582 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1583 if (encoder->crtc) {
1584 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1585 bpc = amdgpu_crtc->bpc;
1586 }
1587
1588 /* disable audio prior to setting up hw */
1589 dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1590 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1591
1592 dce_v10_0_audio_set_dto(encoder, mode->clock);
1593
1594 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1595 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1596 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1597
1598 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1599
1600 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1601 switch (bpc) {
1602 case 0:
1603 case 6:
1604 case 8:
1605 case 16:
1606 default:
1607 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1608 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1609 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1610 connector->name, bpc);
1611 break;
1612 case 10:
1613 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1614 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1615 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1616 connector->name);
1617 break;
1618 case 12:
1619 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1620 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1621 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1622 connector->name);
1623 break;
1624 }
1625 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1626
1627 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1628 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1629 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1630 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1631 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1632
1633 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1634 /* enable audio info frames (frames won't be set until audio is enabled) */
1635 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1636 /* required for audio info values to be updated */
1637 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1638 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1639
1640 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1641 /* required for audio info values to be updated */
1642 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1643 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1644
1645 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1646 /* anything other than 0 */
1647 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1648 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1649
1650 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1651
1652 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1653 /* set the default audio delay */
1654 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1655 /* should be suffient for all audio modes and small enough for all hblanks */
1656 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1657 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1658
1659 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1660 /* allow 60958 channel status fields to be updated */
1661 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1662 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1663
1664 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1665 if (bpc > 8)
1666 /* clear SW CTS value */
1667 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1668 else
1669 /* select SW CTS value */
1670 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1671 /* allow hw to sent ACR packets when required */
1672 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1673 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1674
1675 dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1676
1677 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1678 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1679 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1680
1681 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1682 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1683 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1684
1685 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1686 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1687 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1688 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1689 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1690 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1691 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1692 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1693
1694 dce_v10_0_audio_write_speaker_allocation(encoder);
1695
1696 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1697 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1698
1699 dce_v10_0_afmt_audio_select_pin(encoder);
1700 dce_v10_0_audio_write_sad_regs(encoder);
1701 dce_v10_0_audio_write_latency_fields(encoder, mode);
1702
1703 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1704 if (err < 0) {
1705 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1706 return;
1707 }
1708
1709 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1710 if (err < 0) {
1711 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1712 return;
1713 }
1714
1715 dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1716
1717 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1718 /* enable AVI info frames */
1719 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1720 /* required for audio info values to be updated */
1721 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1722 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1723
1724 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1725 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1726 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1727
1728 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1729 /* send audio packets */
1730 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1731 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1732
1733 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1734 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1735 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1736 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1737
1738 /* enable audio after to setting up hw */
1739 dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1740 }
1741
dce_v10_0_afmt_enable(struct drm_encoder * encoder,bool enable)1742 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1743 {
1744 struct drm_device *dev = encoder->dev;
1745 struct amdgpu_device *adev = drm_to_adev(dev);
1746 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1747 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1748
1749 if (!dig || !dig->afmt)
1750 return;
1751
1752 /* Silent, r600_hdmi_enable will raise WARN for us */
1753 if (enable && dig->afmt->enabled)
1754 return;
1755 if (!enable && !dig->afmt->enabled)
1756 return;
1757
1758 if (!enable && dig->afmt->pin) {
1759 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1760 dig->afmt->pin = NULL;
1761 }
1762
1763 dig->afmt->enabled = enable;
1764
1765 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1766 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1767 }
1768
dce_v10_0_afmt_init(struct amdgpu_device * adev)1769 static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
1770 {
1771 int i;
1772
1773 for (i = 0; i < adev->mode_info.num_dig; i++)
1774 adev->mode_info.afmt[i] = NULL;
1775
1776 /* DCE10 has audio blocks tied to DIG encoders */
1777 for (i = 0; i < adev->mode_info.num_dig; i++) {
1778 adev->mode_info.afmt[i] = kzalloc_obj(struct amdgpu_afmt);
1779 if (adev->mode_info.afmt[i]) {
1780 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1781 adev->mode_info.afmt[i]->id = i;
1782 } else {
1783 int j;
1784 for (j = 0; j < i; j++) {
1785 kfree(adev->mode_info.afmt[j]);
1786 adev->mode_info.afmt[j] = NULL;
1787 }
1788 return -ENOMEM;
1789 }
1790 }
1791 return 0;
1792 }
1793
dce_v10_0_afmt_fini(struct amdgpu_device * adev)1794 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
1795 {
1796 int i;
1797
1798 for (i = 0; i < adev->mode_info.num_dig; i++) {
1799 kfree(adev->mode_info.afmt[i]);
1800 adev->mode_info.afmt[i] = NULL;
1801 }
1802 }
1803
1804 static const u32 vga_control_regs[6] = {
1805 mmD1VGA_CONTROL,
1806 mmD2VGA_CONTROL,
1807 mmD3VGA_CONTROL,
1808 mmD4VGA_CONTROL,
1809 mmD5VGA_CONTROL,
1810 mmD6VGA_CONTROL,
1811 };
1812
dce_v10_0_vga_enable(struct drm_crtc * crtc,bool enable)1813 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
1814 {
1815 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1816 struct drm_device *dev = crtc->dev;
1817 struct amdgpu_device *adev = drm_to_adev(dev);
1818 u32 vga_control;
1819
1820 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1821 if (enable)
1822 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1823 else
1824 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1825 }
1826
dce_v10_0_grph_enable(struct drm_crtc * crtc,bool enable)1827 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
1828 {
1829 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1830 struct drm_device *dev = crtc->dev;
1831 struct amdgpu_device *adev = drm_to_adev(dev);
1832
1833 if (enable)
1834 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1835 else
1836 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1837 }
1838
dce_v10_0_crtc_do_set_base(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y)1839 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
1840 struct drm_framebuffer *fb,
1841 int x, int y)
1842 {
1843 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1844 struct drm_device *dev = crtc->dev;
1845 struct amdgpu_device *adev = drm_to_adev(dev);
1846 struct drm_framebuffer *target_fb;
1847 struct drm_gem_object *obj;
1848 struct amdgpu_bo *abo;
1849 uint64_t fb_location, tiling_flags;
1850 uint32_t fb_format, fb_pitch_pixels;
1851 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1852 u32 pipe_config;
1853 u32 tmp, viewport_w, viewport_h;
1854 int r;
1855 bool bypass_lut = false;
1856
1857 /* no fb bound */
1858 if (!crtc->primary->fb) {
1859 DRM_DEBUG_KMS("No FB bound\n");
1860 return 0;
1861 }
1862
1863 target_fb = crtc->primary->fb;
1864
1865 /* If atomic, assume fb object is pinned & idle & fenced and
1866 * just update base pointers
1867 */
1868 obj = target_fb->obj[0];
1869 abo = gem_to_amdgpu_bo(obj);
1870 r = amdgpu_bo_reserve(abo, false);
1871 if (unlikely(r != 0))
1872 return r;
1873
1874 abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1875 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1876 if (unlikely(r != 0)) {
1877 amdgpu_bo_unreserve(abo);
1878 return -EINVAL;
1879 }
1880 fb_location = amdgpu_bo_gpu_offset(abo);
1881
1882 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1883 amdgpu_bo_unreserve(abo);
1884
1885 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1886
1887 switch (target_fb->format->format) {
1888 case DRM_FORMAT_C8:
1889 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1890 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1891 break;
1892 case DRM_FORMAT_XRGB4444:
1893 case DRM_FORMAT_ARGB4444:
1894 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1895 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1896 #ifdef __BIG_ENDIAN
1897 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1898 ENDIAN_8IN16);
1899 #endif
1900 break;
1901 case DRM_FORMAT_XRGB1555:
1902 case DRM_FORMAT_ARGB1555:
1903 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1904 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1905 #ifdef __BIG_ENDIAN
1906 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1907 ENDIAN_8IN16);
1908 #endif
1909 break;
1910 case DRM_FORMAT_BGRX5551:
1911 case DRM_FORMAT_BGRA5551:
1912 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1913 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1914 #ifdef __BIG_ENDIAN
1915 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1916 ENDIAN_8IN16);
1917 #endif
1918 break;
1919 case DRM_FORMAT_RGB565:
1920 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1921 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1922 #ifdef __BIG_ENDIAN
1923 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1924 ENDIAN_8IN16);
1925 #endif
1926 break;
1927 case DRM_FORMAT_XRGB8888:
1928 case DRM_FORMAT_ARGB8888:
1929 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1930 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1931 #ifdef __BIG_ENDIAN
1932 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1933 ENDIAN_8IN32);
1934 #endif
1935 break;
1936 case DRM_FORMAT_XRGB2101010:
1937 case DRM_FORMAT_ARGB2101010:
1938 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1939 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1940 #ifdef __BIG_ENDIAN
1941 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1942 ENDIAN_8IN32);
1943 #endif
1944 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1945 bypass_lut = true;
1946 break;
1947 case DRM_FORMAT_BGRX1010102:
1948 case DRM_FORMAT_BGRA1010102:
1949 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1950 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
1951 #ifdef __BIG_ENDIAN
1952 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1953 ENDIAN_8IN32);
1954 #endif
1955 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1956 bypass_lut = true;
1957 break;
1958 case DRM_FORMAT_XBGR8888:
1959 case DRM_FORMAT_ABGR8888:
1960 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1961 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1962 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
1963 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
1964 #ifdef __BIG_ENDIAN
1965 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1966 ENDIAN_8IN32);
1967 #endif
1968 break;
1969 default:
1970 DRM_ERROR("Unsupported screen format %p4cc\n",
1971 &target_fb->format->format);
1972 return -EINVAL;
1973 }
1974
1975 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1976 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1977
1978 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1979 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1980 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1981 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1982 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1983
1984 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
1985 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
1986 ARRAY_2D_TILED_THIN1);
1987 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
1988 tile_split);
1989 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
1990 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
1991 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
1992 mtaspect);
1993 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
1994 ADDR_SURF_MICRO_TILING_DISPLAY);
1995 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1996 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
1997 ARRAY_1D_TILED_THIN1);
1998 }
1999
2000 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2001 pipe_config);
2002
2003 dce_v10_0_vga_enable(crtc, false);
2004
2005 /* Make sure surface address is updated at vertical blank rather than
2006 * horizontal blank
2007 */
2008 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2009 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2010 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2011 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2012
2013 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2014 upper_32_bits(fb_location));
2015 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2016 upper_32_bits(fb_location));
2017 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2018 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2019 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2020 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2021 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2022 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2023
2024 /*
2025 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2026 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2027 * retain the full precision throughout the pipeline.
2028 */
2029 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2030 if (bypass_lut)
2031 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2032 else
2033 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2034 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2035
2036 if (bypass_lut)
2037 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2038
2039 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2040 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2041 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2042 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2043 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2044 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2045
2046 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2047 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2048
2049 dce_v10_0_grph_enable(crtc, true);
2050
2051 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2052 target_fb->height);
2053
2054 x &= ~3;
2055 y &= ~1;
2056 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2057 (x << 16) | y);
2058 viewport_w = crtc->mode.hdisplay;
2059 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2060 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2061 (viewport_w << 16) | viewport_h);
2062
2063 /* set pageflip to happen anywhere in vblank interval */
2064 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2065
2066 if (fb && fb != crtc->primary->fb) {
2067 abo = gem_to_amdgpu_bo(fb->obj[0]);
2068 r = amdgpu_bo_reserve(abo, true);
2069 if (unlikely(r != 0))
2070 return r;
2071 amdgpu_bo_unpin(abo);
2072 amdgpu_bo_unreserve(abo);
2073 }
2074
2075 /* Bytes per pixel may have changed */
2076 dce_v10_0_bandwidth_update(adev);
2077
2078 return 0;
2079 }
2080
dce_v10_0_set_interleave(struct drm_crtc * crtc,struct drm_display_mode * mode)2081 static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2082 struct drm_display_mode *mode)
2083 {
2084 struct drm_device *dev = crtc->dev;
2085 struct amdgpu_device *adev = drm_to_adev(dev);
2086 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2087 u32 tmp;
2088
2089 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2090 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2091 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2092 else
2093 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2094 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2095 }
2096
dce_v10_0_crtc_load_lut(struct drm_crtc * crtc)2097 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2098 {
2099 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2100 struct drm_device *dev = crtc->dev;
2101 struct amdgpu_device *adev = drm_to_adev(dev);
2102 u16 *r, *g, *b;
2103 int i;
2104 u32 tmp;
2105
2106 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2107
2108 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2109 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2110 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2111 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2112
2113 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2114 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2115 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2116
2117 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2118 tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2119 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2120
2121 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2122 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2123 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2124 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2125
2126 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2127
2128 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2129 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2130 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2131
2132 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2133 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2134 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2135
2136 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2137 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2138
2139 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2140 r = crtc->gamma_store;
2141 g = r + crtc->gamma_size;
2142 b = g + crtc->gamma_size;
2143 for (i = 0; i < 256; i++) {
2144 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2145 ((*r++ & 0xffc0) << 14) |
2146 ((*g++ & 0xffc0) << 4) |
2147 (*b++ >> 6));
2148 }
2149
2150 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2151 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2152 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2153 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2154 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2155
2156 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2157 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2158 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2159 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2160
2161 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2162 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2163 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2164 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2165
2166 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2167 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2168 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2169 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2170
2171 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2172 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2173 /* XXX this only needs to be programmed once per crtc at startup,
2174 * not sure where the best place for it is
2175 */
2176 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2177 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2178 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2179 }
2180
dce_v10_0_pick_dig_encoder(struct drm_encoder * encoder)2181 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2182 {
2183 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2184 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2185
2186 switch (amdgpu_encoder->encoder_id) {
2187 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2188 if (dig->linkb)
2189 return 1;
2190 else
2191 return 0;
2192 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2193 if (dig->linkb)
2194 return 3;
2195 else
2196 return 2;
2197 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2198 if (dig->linkb)
2199 return 5;
2200 else
2201 return 4;
2202 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2203 return 6;
2204 default:
2205 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2206 return 0;
2207 }
2208 }
2209
2210 /**
2211 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2212 *
2213 * @crtc: drm crtc
2214 *
2215 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2216 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2217 * monitors a dedicated PPLL must be used. If a particular board has
2218 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2219 * as there is no need to program the PLL itself. If we are not able to
2220 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2221 * avoid messing up an existing monitor.
2222 *
2223 * Asic specific PLL information
2224 *
2225 * DCE 10.x
2226 * Tonga
2227 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2228 * CI
2229 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2230 *
2231 */
dce_v10_0_pick_pll(struct drm_crtc * crtc)2232 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2233 {
2234 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2235 struct drm_device *dev = crtc->dev;
2236 struct amdgpu_device *adev = drm_to_adev(dev);
2237 u32 pll_in_use;
2238 int pll;
2239
2240 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2241 if (adev->clock.dp_extclk)
2242 /* skip PPLL programming if using ext clock */
2243 return ATOM_PPLL_INVALID;
2244 else {
2245 /* use the same PPLL for all DP monitors */
2246 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2247 if (pll != ATOM_PPLL_INVALID)
2248 return pll;
2249 }
2250 } else {
2251 /* use the same PPLL for all monitors with the same clock */
2252 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2253 if (pll != ATOM_PPLL_INVALID)
2254 return pll;
2255 }
2256
2257 /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2258 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2259 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2260 return ATOM_PPLL2;
2261 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2262 return ATOM_PPLL1;
2263 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2264 return ATOM_PPLL0;
2265 DRM_ERROR("unable to allocate a PPLL\n");
2266 return ATOM_PPLL_INVALID;
2267 }
2268
dce_v10_0_lock_cursor(struct drm_crtc * crtc,bool lock)2269 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2270 {
2271 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2272 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2273 uint32_t cur_lock;
2274
2275 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2276 if (lock)
2277 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2278 else
2279 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2280 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2281 }
2282
dce_v10_0_hide_cursor(struct drm_crtc * crtc)2283 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2284 {
2285 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2286 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2287 u32 tmp;
2288
2289 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2290 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2291 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2292 }
2293
dce_v10_0_show_cursor(struct drm_crtc * crtc)2294 static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2295 {
2296 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2297 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2298 u32 tmp;
2299
2300 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2301 upper_32_bits(amdgpu_crtc->cursor_addr));
2302 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2303 lower_32_bits(amdgpu_crtc->cursor_addr));
2304
2305 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2306 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2307 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2308 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2309 }
2310
dce_v10_0_cursor_move_locked(struct drm_crtc * crtc,int x,int y)2311 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2312 int x, int y)
2313 {
2314 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2315 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2316 int xorigin = 0, yorigin = 0;
2317
2318 amdgpu_crtc->cursor_x = x;
2319 amdgpu_crtc->cursor_y = y;
2320
2321 /* avivo cursor are offset into the total surface */
2322 x += crtc->x;
2323 y += crtc->y;
2324 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2325
2326 if (x < 0) {
2327 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2328 x = 0;
2329 }
2330 if (y < 0) {
2331 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2332 y = 0;
2333 }
2334
2335 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2336 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2337 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2338 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2339
2340 return 0;
2341 }
2342
dce_v10_0_crtc_cursor_move(struct drm_crtc * crtc,int x,int y)2343 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2344 int x, int y)
2345 {
2346 int ret;
2347
2348 dce_v10_0_lock_cursor(crtc, true);
2349 ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2350 dce_v10_0_lock_cursor(crtc, false);
2351
2352 return ret;
2353 }
2354
dce_v10_0_crtc_cursor_set2(struct drm_crtc * crtc,struct drm_file * file_priv,uint32_t handle,uint32_t width,uint32_t height,int32_t hot_x,int32_t hot_y)2355 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2356 struct drm_file *file_priv,
2357 uint32_t handle,
2358 uint32_t width,
2359 uint32_t height,
2360 int32_t hot_x,
2361 int32_t hot_y)
2362 {
2363 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2364 struct drm_gem_object *obj;
2365 struct amdgpu_bo *aobj;
2366 int ret;
2367
2368 if (!handle) {
2369 /* turn off cursor */
2370 dce_v10_0_hide_cursor(crtc);
2371 obj = NULL;
2372 goto unpin;
2373 }
2374
2375 if ((width > amdgpu_crtc->max_cursor_width) ||
2376 (height > amdgpu_crtc->max_cursor_height)) {
2377 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2378 return -EINVAL;
2379 }
2380
2381 obj = drm_gem_object_lookup(file_priv, handle);
2382 if (!obj) {
2383 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2384 return -ENOENT;
2385 }
2386
2387 aobj = gem_to_amdgpu_bo(obj);
2388 ret = amdgpu_bo_reserve(aobj, false);
2389 if (ret != 0) {
2390 drm_gem_object_put(obj);
2391 return ret;
2392 }
2393
2394 aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
2395 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2396 amdgpu_bo_unreserve(aobj);
2397 if (ret) {
2398 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2399 drm_gem_object_put(obj);
2400 return ret;
2401 }
2402 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2403
2404 dce_v10_0_lock_cursor(crtc, true);
2405
2406 if (width != amdgpu_crtc->cursor_width ||
2407 height != amdgpu_crtc->cursor_height ||
2408 hot_x != amdgpu_crtc->cursor_hot_x ||
2409 hot_y != amdgpu_crtc->cursor_hot_y) {
2410 int x, y;
2411
2412 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2413 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2414
2415 dce_v10_0_cursor_move_locked(crtc, x, y);
2416
2417 amdgpu_crtc->cursor_width = width;
2418 amdgpu_crtc->cursor_height = height;
2419 amdgpu_crtc->cursor_hot_x = hot_x;
2420 amdgpu_crtc->cursor_hot_y = hot_y;
2421 }
2422
2423 dce_v10_0_show_cursor(crtc);
2424 dce_v10_0_lock_cursor(crtc, false);
2425
2426 unpin:
2427 if (amdgpu_crtc->cursor_bo) {
2428 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2429 ret = amdgpu_bo_reserve(aobj, true);
2430 if (likely(ret == 0)) {
2431 amdgpu_bo_unpin(aobj);
2432 amdgpu_bo_unreserve(aobj);
2433 }
2434 drm_gem_object_put(amdgpu_crtc->cursor_bo);
2435 }
2436
2437 amdgpu_crtc->cursor_bo = obj;
2438 return 0;
2439 }
2440
dce_v10_0_cursor_reset(struct drm_crtc * crtc)2441 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2442 {
2443 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2444
2445 if (amdgpu_crtc->cursor_bo) {
2446 dce_v10_0_lock_cursor(crtc, true);
2447
2448 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2449 amdgpu_crtc->cursor_y);
2450
2451 dce_v10_0_show_cursor(crtc);
2452
2453 dce_v10_0_lock_cursor(crtc, false);
2454 }
2455 }
2456
dce_v10_0_crtc_gamma_set(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,uint32_t size,struct drm_modeset_acquire_ctx * ctx)2457 static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2458 u16 *blue, uint32_t size,
2459 struct drm_modeset_acquire_ctx *ctx)
2460 {
2461 dce_v10_0_crtc_load_lut(crtc);
2462
2463 return 0;
2464 }
2465
dce_v10_0_crtc_destroy(struct drm_crtc * crtc)2466 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2467 {
2468 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2469
2470 drm_crtc_cleanup(crtc);
2471 kfree(amdgpu_crtc);
2472 }
2473
2474 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2475 .cursor_set2 = dce_v10_0_crtc_cursor_set2,
2476 .cursor_move = dce_v10_0_crtc_cursor_move,
2477 .gamma_set = dce_v10_0_crtc_gamma_set,
2478 .set_config = amdgpu_display_crtc_set_config,
2479 .destroy = dce_v10_0_crtc_destroy,
2480 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2481 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
2482 .enable_vblank = amdgpu_enable_vblank_kms,
2483 .disable_vblank = amdgpu_disable_vblank_kms,
2484 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2485 };
2486
dce_v10_0_crtc_dpms(struct drm_crtc * crtc,int mode)2487 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2488 {
2489 struct drm_device *dev = crtc->dev;
2490 struct amdgpu_device *adev = drm_to_adev(dev);
2491 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2492 unsigned type;
2493
2494 switch (mode) {
2495 case DRM_MODE_DPMS_ON:
2496 amdgpu_crtc->enabled = true;
2497 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2498 dce_v10_0_vga_enable(crtc, true);
2499 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2500 dce_v10_0_vga_enable(crtc, false);
2501 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2502 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2503 amdgpu_crtc->crtc_id);
2504 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2505 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2506 drm_crtc_vblank_on(crtc);
2507 dce_v10_0_crtc_load_lut(crtc);
2508 break;
2509 case DRM_MODE_DPMS_STANDBY:
2510 case DRM_MODE_DPMS_SUSPEND:
2511 case DRM_MODE_DPMS_OFF:
2512 drm_crtc_vblank_off(crtc);
2513 if (amdgpu_crtc->enabled) {
2514 dce_v10_0_vga_enable(crtc, true);
2515 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2516 dce_v10_0_vga_enable(crtc, false);
2517 }
2518 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2519 amdgpu_crtc->enabled = false;
2520 break;
2521 }
2522 /* adjust pm to dpms */
2523 amdgpu_dpm_compute_clocks(adev);
2524 }
2525
dce_v10_0_crtc_prepare(struct drm_crtc * crtc)2526 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2527 {
2528 /* disable crtc pair power gating before programming */
2529 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2530 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2531 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2532 }
2533
dce_v10_0_crtc_commit(struct drm_crtc * crtc)2534 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2535 {
2536 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2537 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2538 }
2539
dce_v10_0_crtc_disable(struct drm_crtc * crtc)2540 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2541 {
2542 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2543 struct drm_device *dev = crtc->dev;
2544 struct amdgpu_device *adev = drm_to_adev(dev);
2545 struct amdgpu_atom_ss ss;
2546 int i;
2547
2548 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2549 if (crtc->primary->fb) {
2550 int r;
2551 struct amdgpu_bo *abo;
2552
2553 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2554 r = amdgpu_bo_reserve(abo, true);
2555 if (unlikely(r))
2556 DRM_ERROR("failed to reserve abo before unpin\n");
2557 else {
2558 amdgpu_bo_unpin(abo);
2559 amdgpu_bo_unreserve(abo);
2560 }
2561 }
2562 /* disable the GRPH */
2563 dce_v10_0_grph_enable(crtc, false);
2564
2565 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2566
2567 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2568 if (adev->mode_info.crtcs[i] &&
2569 adev->mode_info.crtcs[i]->enabled &&
2570 i != amdgpu_crtc->crtc_id &&
2571 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2572 /* one other crtc is using this pll don't turn
2573 * off the pll
2574 */
2575 goto done;
2576 }
2577 }
2578
2579 switch (amdgpu_crtc->pll_id) {
2580 case ATOM_PPLL0:
2581 case ATOM_PPLL1:
2582 case ATOM_PPLL2:
2583 /* disable the ppll */
2584 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2585 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2586 break;
2587 default:
2588 break;
2589 }
2590 done:
2591 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2592 amdgpu_crtc->adjusted_clock = 0;
2593 amdgpu_crtc->encoder = NULL;
2594 amdgpu_crtc->connector = NULL;
2595 }
2596
dce_v10_0_crtc_mode_set(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,int x,int y,struct drm_framebuffer * old_fb)2597 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2598 struct drm_display_mode *mode,
2599 struct drm_display_mode *adjusted_mode,
2600 int x, int y, struct drm_framebuffer *old_fb)
2601 {
2602 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2603
2604 if (!amdgpu_crtc->adjusted_clock)
2605 return -EINVAL;
2606
2607 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2608 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2609 dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y);
2610 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2611 amdgpu_atombios_crtc_scaler_setup(crtc);
2612 dce_v10_0_cursor_reset(crtc);
2613 /* update the hw version fpr dpm */
2614 amdgpu_crtc->hw_mode = *adjusted_mode;
2615
2616 return 0;
2617 }
2618
dce_v10_0_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)2619 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2620 const struct drm_display_mode *mode,
2621 struct drm_display_mode *adjusted_mode)
2622 {
2623 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2624 struct drm_device *dev = crtc->dev;
2625 struct drm_encoder *encoder;
2626
2627 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2628 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2629 if (encoder->crtc == crtc) {
2630 amdgpu_crtc->encoder = encoder;
2631 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2632 break;
2633 }
2634 }
2635 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2636 amdgpu_crtc->encoder = NULL;
2637 amdgpu_crtc->connector = NULL;
2638 return false;
2639 }
2640 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2641 return false;
2642 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2643 return false;
2644 /* pick pll */
2645 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2646 /* if we can't get a PPLL for a non-DP encoder, fail */
2647 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2648 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2649 return false;
2650
2651 return true;
2652 }
2653
dce_v10_0_crtc_set_base(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * old_fb)2654 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2655 struct drm_framebuffer *old_fb)
2656 {
2657 return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y);
2658 }
2659
2660 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2661 .dpms = dce_v10_0_crtc_dpms,
2662 .mode_fixup = dce_v10_0_crtc_mode_fixup,
2663 .mode_set = dce_v10_0_crtc_mode_set,
2664 .mode_set_base = dce_v10_0_crtc_set_base,
2665 .prepare = dce_v10_0_crtc_prepare,
2666 .commit = dce_v10_0_crtc_commit,
2667 .disable = dce_v10_0_crtc_disable,
2668 .get_scanout_position = amdgpu_crtc_get_scanout_position,
2669 };
2670
dce_v10_0_panic_flush(struct drm_plane * plane)2671 static void dce_v10_0_panic_flush(struct drm_plane *plane)
2672 {
2673 struct drm_framebuffer *fb;
2674 struct amdgpu_crtc *amdgpu_crtc;
2675 struct amdgpu_device *adev;
2676 uint32_t fb_format;
2677
2678 if (!plane->fb)
2679 return;
2680
2681 fb = plane->fb;
2682 amdgpu_crtc = to_amdgpu_crtc(plane->crtc);
2683 adev = drm_to_adev(fb->dev);
2684
2685 /* Disable DC tiling */
2686 fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset);
2687 fb_format &= ~GRPH_CONTROL__GRPH_ARRAY_MODE_MASK;
2688 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2689
2690 }
2691
2692 static const struct drm_plane_helper_funcs dce_v10_0_drm_primary_plane_helper_funcs = {
2693 .get_scanout_buffer = amdgpu_display_get_scanout_buffer,
2694 .panic_flush = dce_v10_0_panic_flush,
2695 };
2696
dce_v10_0_crtc_init(struct amdgpu_device * adev,int index)2697 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2698 {
2699 struct amdgpu_crtc *amdgpu_crtc;
2700
2701 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2702 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2703 if (amdgpu_crtc == NULL)
2704 return -ENOMEM;
2705
2706 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2707
2708 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2709 amdgpu_crtc->crtc_id = index;
2710 adev->mode_info.crtcs[index] = amdgpu_crtc;
2711
2712 amdgpu_crtc->max_cursor_width = 128;
2713 amdgpu_crtc->max_cursor_height = 128;
2714 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2715 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2716
2717 switch (amdgpu_crtc->crtc_id) {
2718 case 0:
2719 default:
2720 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2721 break;
2722 case 1:
2723 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2724 break;
2725 case 2:
2726 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2727 break;
2728 case 3:
2729 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2730 break;
2731 case 4:
2732 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2733 break;
2734 case 5:
2735 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2736 break;
2737 }
2738
2739 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2740 amdgpu_crtc->adjusted_clock = 0;
2741 amdgpu_crtc->encoder = NULL;
2742 amdgpu_crtc->connector = NULL;
2743 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2744 drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v10_0_drm_primary_plane_helper_funcs);
2745
2746 return 0;
2747 }
2748
dce_v10_0_early_init(struct amdgpu_ip_block * ip_block)2749 static int dce_v10_0_early_init(struct amdgpu_ip_block *ip_block)
2750 {
2751 struct amdgpu_device *adev = ip_block->adev;
2752
2753 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2754 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2755
2756 dce_v10_0_set_display_funcs(adev);
2757
2758 adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
2759
2760 switch (adev->asic_type) {
2761 case CHIP_FIJI:
2762 case CHIP_TONGA:
2763 adev->mode_info.num_hpd = 6;
2764 adev->mode_info.num_dig = 7;
2765 break;
2766 default:
2767 /* FIXME: not supported yet */
2768 return -EINVAL;
2769 }
2770
2771 dce_v10_0_set_irq_funcs(adev);
2772
2773 return 0;
2774 }
2775
dce_v10_0_sw_init(struct amdgpu_ip_block * ip_block)2776 static int dce_v10_0_sw_init(struct amdgpu_ip_block *ip_block)
2777 {
2778 int r, i;
2779 struct amdgpu_device *adev = ip_block->adev;
2780
2781 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2782 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2783 if (r)
2784 return r;
2785 }
2786
2787 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
2788 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2789 if (r)
2790 return r;
2791 }
2792
2793 /* HPD hotplug */
2794 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2795 if (r)
2796 return r;
2797
2798 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
2799
2800 adev_to_drm(adev)->mode_config.async_page_flip = true;
2801
2802 adev_to_drm(adev)->mode_config.max_width = 16384;
2803 adev_to_drm(adev)->mode_config.max_height = 16384;
2804
2805 adev_to_drm(adev)->mode_config.preferred_depth = 24;
2806 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2807
2808 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
2809
2810 r = amdgpu_display_modeset_create_props(adev);
2811 if (r)
2812 return r;
2813
2814 adev_to_drm(adev)->mode_config.max_width = 16384;
2815 adev_to_drm(adev)->mode_config.max_height = 16384;
2816
2817 /* allocate crtcs */
2818 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2819 r = dce_v10_0_crtc_init(adev, i);
2820 if (r)
2821 return r;
2822 }
2823
2824 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2825 amdgpu_display_print_display_setup(adev_to_drm(adev));
2826 else
2827 return -EINVAL;
2828
2829 /* setup afmt */
2830 r = dce_v10_0_afmt_init(adev);
2831 if (r)
2832 return r;
2833
2834 r = dce_v10_0_audio_init(adev);
2835 if (r)
2836 return r;
2837
2838 /* Disable vblank IRQs aggressively for power-saving */
2839 /* XXX: can this be enabled for DC? */
2840 adev_to_drm(adev)->vblank_disable_immediate = true;
2841
2842 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);
2843 if (r)
2844 return r;
2845
2846 INIT_DELAYED_WORK(&adev->hotplug_work,
2847 amdgpu_display_hotplug_work_func);
2848
2849 drm_kms_helper_poll_init(adev_to_drm(adev));
2850
2851 adev->mode_info.mode_config_initialized = true;
2852 return 0;
2853 }
2854
dce_v10_0_sw_fini(struct amdgpu_ip_block * ip_block)2855 static int dce_v10_0_sw_fini(struct amdgpu_ip_block *ip_block)
2856 {
2857 struct amdgpu_device *adev = ip_block->adev;
2858
2859 drm_edid_free(adev->mode_info.bios_hardcoded_edid);
2860
2861 drm_kms_helper_poll_fini(adev_to_drm(adev));
2862
2863 dce_v10_0_audio_fini(adev);
2864
2865 dce_v10_0_afmt_fini(adev);
2866
2867 drm_mode_config_cleanup(adev_to_drm(adev));
2868 adev->mode_info.mode_config_initialized = false;
2869
2870 return 0;
2871 }
2872
dce_v10_0_hw_init(struct amdgpu_ip_block * ip_block)2873 static int dce_v10_0_hw_init(struct amdgpu_ip_block *ip_block)
2874 {
2875 int i;
2876 struct amdgpu_device *adev = ip_block->adev;
2877
2878 dce_v10_0_init_golden_registers(adev);
2879
2880 /* disable vga render */
2881 dce_v10_0_set_vga_render_state(adev, false);
2882 /* init dig PHYs, disp eng pll */
2883 amdgpu_atombios_encoder_init_dig(adev);
2884 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2885
2886 /* initialize hpd */
2887 dce_v10_0_hpd_init(adev);
2888
2889 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2890 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2891 }
2892
2893 dce_v10_0_pageflip_interrupt_init(adev);
2894
2895 return 0;
2896 }
2897
dce_v10_0_hw_fini(struct amdgpu_ip_block * ip_block)2898 static int dce_v10_0_hw_fini(struct amdgpu_ip_block *ip_block)
2899 {
2900 int i;
2901 struct amdgpu_device *adev = ip_block->adev;
2902
2903 dce_v10_0_hpd_fini(adev);
2904
2905 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2906 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2907 }
2908
2909 dce_v10_0_pageflip_interrupt_fini(adev);
2910
2911 flush_delayed_work(&adev->hotplug_work);
2912
2913 return 0;
2914 }
2915
dce_v10_0_suspend(struct amdgpu_ip_block * ip_block)2916 static int dce_v10_0_suspend(struct amdgpu_ip_block *ip_block)
2917 {
2918 struct amdgpu_device *adev = ip_block->adev;
2919 int r;
2920
2921 r = amdgpu_display_suspend_helper(adev);
2922 if (r)
2923 return r;
2924
2925 adev->mode_info.bl_level =
2926 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2927
2928 return dce_v10_0_hw_fini(ip_block);
2929 }
2930
dce_v10_0_resume(struct amdgpu_ip_block * ip_block)2931 static int dce_v10_0_resume(struct amdgpu_ip_block *ip_block)
2932 {
2933 struct amdgpu_device *adev = ip_block->adev;
2934 int ret;
2935
2936 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2937 adev->mode_info.bl_level);
2938
2939 ret = dce_v10_0_hw_init(ip_block);
2940
2941 /* turn on the BL */
2942 if (adev->mode_info.bl_encoder) {
2943 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2944 adev->mode_info.bl_encoder);
2945 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2946 bl_level);
2947 }
2948 if (ret)
2949 return ret;
2950
2951 return amdgpu_display_resume_helper(adev);
2952 }
2953
dce_v10_0_is_idle(struct amdgpu_ip_block * ip_block)2954 static bool dce_v10_0_is_idle(struct amdgpu_ip_block *ip_block)
2955 {
2956 return true;
2957 }
2958
dce_v10_0_check_soft_reset(struct amdgpu_ip_block * ip_block)2959 static bool dce_v10_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
2960 {
2961 struct amdgpu_device *adev = ip_block->adev;
2962
2963 return dce_v10_0_is_display_hung(adev);
2964 }
2965
dce_v10_0_soft_reset(struct amdgpu_ip_block * ip_block)2966 static int dce_v10_0_soft_reset(struct amdgpu_ip_block *ip_block)
2967 {
2968 u32 srbm_soft_reset = 0, tmp;
2969 struct amdgpu_device *adev = ip_block->adev;
2970
2971 if (dce_v10_0_is_display_hung(adev))
2972 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2973
2974 if (srbm_soft_reset) {
2975 tmp = RREG32(mmSRBM_SOFT_RESET);
2976 tmp |= srbm_soft_reset;
2977 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2978 WREG32(mmSRBM_SOFT_RESET, tmp);
2979 tmp = RREG32(mmSRBM_SOFT_RESET);
2980
2981 udelay(50);
2982
2983 tmp &= ~srbm_soft_reset;
2984 WREG32(mmSRBM_SOFT_RESET, tmp);
2985 tmp = RREG32(mmSRBM_SOFT_RESET);
2986
2987 /* Wait a little for things to settle down */
2988 udelay(50);
2989 }
2990 return 0;
2991 }
2992
dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device * adev,int crtc,enum amdgpu_interrupt_state state)2993 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2994 int crtc,
2995 enum amdgpu_interrupt_state state)
2996 {
2997 u32 lb_interrupt_mask;
2998
2999 if (crtc >= adev->mode_info.num_crtc) {
3000 DRM_DEBUG("invalid crtc %d\n", crtc);
3001 return;
3002 }
3003
3004 switch (state) {
3005 case AMDGPU_IRQ_STATE_DISABLE:
3006 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3007 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3008 VBLANK_INTERRUPT_MASK, 0);
3009 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3010 break;
3011 case AMDGPU_IRQ_STATE_ENABLE:
3012 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3013 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3014 VBLANK_INTERRUPT_MASK, 1);
3015 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3016 break;
3017 default:
3018 break;
3019 }
3020 }
3021
dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device * adev,int crtc,enum amdgpu_interrupt_state state)3022 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3023 int crtc,
3024 enum amdgpu_interrupt_state state)
3025 {
3026 u32 lb_interrupt_mask;
3027
3028 if (crtc >= adev->mode_info.num_crtc) {
3029 DRM_DEBUG("invalid crtc %d\n", crtc);
3030 return;
3031 }
3032
3033 switch (state) {
3034 case AMDGPU_IRQ_STATE_DISABLE:
3035 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3036 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3037 VLINE_INTERRUPT_MASK, 0);
3038 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3039 break;
3040 case AMDGPU_IRQ_STATE_ENABLE:
3041 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3042 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3043 VLINE_INTERRUPT_MASK, 1);
3044 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3045 break;
3046 default:
3047 break;
3048 }
3049 }
3050
dce_v10_0_set_hpd_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned hpd,enum amdgpu_interrupt_state state)3051 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3052 struct amdgpu_irq_src *source,
3053 unsigned hpd,
3054 enum amdgpu_interrupt_state state)
3055 {
3056 u32 tmp;
3057
3058 if (hpd >= adev->mode_info.num_hpd) {
3059 DRM_DEBUG("invalid hpd %d\n", hpd);
3060 return 0;
3061 }
3062
3063 switch (state) {
3064 case AMDGPU_IRQ_STATE_DISABLE:
3065 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3066 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3067 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3068 break;
3069 case AMDGPU_IRQ_STATE_ENABLE:
3070 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3071 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3072 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3073 break;
3074 default:
3075 break;
3076 }
3077
3078 return 0;
3079 }
3080
dce_v10_0_set_crtc_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)3081 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3082 struct amdgpu_irq_src *source,
3083 unsigned type,
3084 enum amdgpu_interrupt_state state)
3085 {
3086 switch (type) {
3087 case AMDGPU_CRTC_IRQ_VBLANK1:
3088 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3089 break;
3090 case AMDGPU_CRTC_IRQ_VBLANK2:
3091 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3092 break;
3093 case AMDGPU_CRTC_IRQ_VBLANK3:
3094 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3095 break;
3096 case AMDGPU_CRTC_IRQ_VBLANK4:
3097 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3098 break;
3099 case AMDGPU_CRTC_IRQ_VBLANK5:
3100 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3101 break;
3102 case AMDGPU_CRTC_IRQ_VBLANK6:
3103 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3104 break;
3105 case AMDGPU_CRTC_IRQ_VLINE1:
3106 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3107 break;
3108 case AMDGPU_CRTC_IRQ_VLINE2:
3109 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3110 break;
3111 case AMDGPU_CRTC_IRQ_VLINE3:
3112 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3113 break;
3114 case AMDGPU_CRTC_IRQ_VLINE4:
3115 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3116 break;
3117 case AMDGPU_CRTC_IRQ_VLINE5:
3118 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3119 break;
3120 case AMDGPU_CRTC_IRQ_VLINE6:
3121 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3122 break;
3123 default:
3124 break;
3125 }
3126 return 0;
3127 }
3128
dce_v10_0_set_pageflip_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)3129 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3130 struct amdgpu_irq_src *src,
3131 unsigned type,
3132 enum amdgpu_interrupt_state state)
3133 {
3134 u32 reg;
3135
3136 if (type >= adev->mode_info.num_crtc) {
3137 DRM_ERROR("invalid pageflip crtc %d\n", type);
3138 return -EINVAL;
3139 }
3140
3141 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3142 if (state == AMDGPU_IRQ_STATE_DISABLE)
3143 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3144 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3145 else
3146 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3147 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3148
3149 return 0;
3150 }
3151
dce_v10_0_pageflip_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)3152 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3153 struct amdgpu_irq_src *source,
3154 struct amdgpu_iv_entry *entry)
3155 {
3156 unsigned long flags;
3157 unsigned crtc_id;
3158 struct amdgpu_crtc *amdgpu_crtc;
3159 struct amdgpu_flip_work *works;
3160
3161 crtc_id = (entry->src_id - 8) >> 1;
3162 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3163
3164 if (crtc_id >= adev->mode_info.num_crtc) {
3165 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3166 return -EINVAL;
3167 }
3168
3169 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3170 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3171 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3172 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3173
3174 /* IRQ could occur when in initial stage */
3175 if (amdgpu_crtc == NULL)
3176 return 0;
3177
3178 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
3179 works = amdgpu_crtc->pflip_works;
3180 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3181 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3182 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3183 amdgpu_crtc->pflip_status,
3184 AMDGPU_FLIP_SUBMITTED);
3185 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3186 return 0;
3187 }
3188
3189 /* page flip completed. clean up */
3190 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3191 amdgpu_crtc->pflip_works = NULL;
3192
3193 /* wakeup usersapce */
3194 if (works->event)
3195 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3196
3197 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3198
3199 drm_crtc_vblank_put(&amdgpu_crtc->base);
3200 schedule_work(&works->unpin_work);
3201
3202 return 0;
3203 }
3204
dce_v10_0_hpd_int_ack(struct amdgpu_device * adev,int hpd)3205 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3206 int hpd)
3207 {
3208 u32 tmp;
3209
3210 if (hpd >= adev->mode_info.num_hpd) {
3211 DRM_DEBUG("invalid hpd %d\n", hpd);
3212 return;
3213 }
3214
3215 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3216 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3217 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3218 }
3219
dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device * adev,int crtc)3220 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3221 int crtc)
3222 {
3223 u32 tmp;
3224
3225 if (crtc >= adev->mode_info.num_crtc) {
3226 DRM_DEBUG("invalid crtc %d\n", crtc);
3227 return;
3228 }
3229
3230 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3231 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3232 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3233 }
3234
dce_v10_0_crtc_vline_int_ack(struct amdgpu_device * adev,int crtc)3235 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3236 int crtc)
3237 {
3238 u32 tmp;
3239
3240 if (crtc >= adev->mode_info.num_crtc) {
3241 DRM_DEBUG("invalid crtc %d\n", crtc);
3242 return;
3243 }
3244
3245 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3246 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3247 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3248 }
3249
dce_v10_0_crtc_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)3250 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3251 struct amdgpu_irq_src *source,
3252 struct amdgpu_iv_entry *entry)
3253 {
3254 unsigned crtc = entry->src_id - 1;
3255 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3256 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, crtc);
3257
3258 switch (entry->src_data[0]) {
3259 case 0: /* vblank */
3260 if (disp_int & interrupt_status_offsets[crtc].vblank)
3261 dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3262 else
3263 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3264
3265 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3266 drm_handle_vblank(adev_to_drm(adev), crtc);
3267 }
3268 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3269
3270 break;
3271 case 1: /* vline */
3272 if (disp_int & interrupt_status_offsets[crtc].vline)
3273 dce_v10_0_crtc_vline_int_ack(adev, crtc);
3274 else
3275 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3276
3277 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3278
3279 break;
3280 default:
3281 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3282 break;
3283 }
3284
3285 return 0;
3286 }
3287
dce_v10_0_hpd_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)3288 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3289 struct amdgpu_irq_src *source,
3290 struct amdgpu_iv_entry *entry)
3291 {
3292 uint32_t disp_int, mask;
3293 unsigned hpd;
3294
3295 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3296 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3297 return 0;
3298 }
3299
3300 hpd = entry->src_data[0];
3301 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3302 mask = interrupt_status_offsets[hpd].hpd;
3303
3304 if (disp_int & mask) {
3305 dce_v10_0_hpd_int_ack(adev, hpd);
3306 schedule_delayed_work(&adev->hotplug_work, 0);
3307 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3308 }
3309
3310 return 0;
3311 }
3312
dce_v10_0_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)3313 static int dce_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
3314 enum amd_clockgating_state state)
3315 {
3316 return 0;
3317 }
3318
dce_v10_0_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)3319 static int dce_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
3320 enum amd_powergating_state state)
3321 {
3322 return 0;
3323 }
3324
3325 static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3326 .name = "dce_v10_0",
3327 .early_init = dce_v10_0_early_init,
3328 .sw_init = dce_v10_0_sw_init,
3329 .sw_fini = dce_v10_0_sw_fini,
3330 .hw_init = dce_v10_0_hw_init,
3331 .hw_fini = dce_v10_0_hw_fini,
3332 .suspend = dce_v10_0_suspend,
3333 .resume = dce_v10_0_resume,
3334 .is_idle = dce_v10_0_is_idle,
3335 .check_soft_reset = dce_v10_0_check_soft_reset,
3336 .soft_reset = dce_v10_0_soft_reset,
3337 .set_clockgating_state = dce_v10_0_set_clockgating_state,
3338 .set_powergating_state = dce_v10_0_set_powergating_state,
3339 };
3340
3341 static void
dce_v10_0_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)3342 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3343 struct drm_display_mode *mode,
3344 struct drm_display_mode *adjusted_mode)
3345 {
3346 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3347
3348 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3349
3350 /* need to call this here rather than in prepare() since we need some crtc info */
3351 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3352
3353 /* set scaler clears this on some chips */
3354 dce_v10_0_set_interleave(encoder->crtc, mode);
3355
3356 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3357 dce_v10_0_afmt_enable(encoder, true);
3358 dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3359 }
3360 }
3361
dce_v10_0_encoder_prepare(struct drm_encoder * encoder)3362 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3363 {
3364 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
3365 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3366 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3367
3368 if ((amdgpu_encoder->active_device &
3369 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3370 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3371 ENCODER_OBJECT_ID_NONE)) {
3372 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3373 if (dig) {
3374 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3375 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3376 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3377 }
3378 }
3379
3380 amdgpu_atombios_scratch_regs_lock(adev, true);
3381
3382 if (connector) {
3383 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3384
3385 /* select the clock/data port if it uses a router */
3386 if (amdgpu_connector->router.cd_valid)
3387 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3388
3389 /* turn eDP panel on for mode set */
3390 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3391 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3392 ATOM_TRANSMITTER_ACTION_POWER_ON);
3393 }
3394
3395 /* this is needed for the pll/ss setup to work correctly in some cases */
3396 amdgpu_atombios_encoder_set_crtc_source(encoder);
3397 /* set up the FMT blocks */
3398 dce_v10_0_program_fmt(encoder);
3399 }
3400
dce_v10_0_encoder_commit(struct drm_encoder * encoder)3401 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3402 {
3403 struct drm_device *dev = encoder->dev;
3404 struct amdgpu_device *adev = drm_to_adev(dev);
3405
3406 /* need to call this here as we need the crtc set up */
3407 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3408 amdgpu_atombios_scratch_regs_lock(adev, false);
3409 }
3410
dce_v10_0_encoder_disable(struct drm_encoder * encoder)3411 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3412 {
3413 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3414 struct amdgpu_encoder_atom_dig *dig;
3415
3416 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3417
3418 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3419 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3420 dce_v10_0_afmt_enable(encoder, false);
3421 dig = amdgpu_encoder->enc_priv;
3422 dig->dig_encoder = -1;
3423 }
3424 amdgpu_encoder->active_device = 0;
3425 }
3426
3427 /* these are handled by the primary encoders */
dce_v10_0_ext_prepare(struct drm_encoder * encoder)3428 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3429 {
3430
3431 }
3432
dce_v10_0_ext_commit(struct drm_encoder * encoder)3433 static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3434 {
3435
3436 }
3437
3438 static void
dce_v10_0_ext_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)3439 dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3440 struct drm_display_mode *mode,
3441 struct drm_display_mode *adjusted_mode)
3442 {
3443
3444 }
3445
dce_v10_0_ext_disable(struct drm_encoder * encoder)3446 static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3447 {
3448
3449 }
3450
3451 static void
dce_v10_0_ext_dpms(struct drm_encoder * encoder,int mode)3452 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3453 {
3454
3455 }
3456
3457 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3458 .dpms = dce_v10_0_ext_dpms,
3459 .prepare = dce_v10_0_ext_prepare,
3460 .mode_set = dce_v10_0_ext_mode_set,
3461 .commit = dce_v10_0_ext_commit,
3462 .disable = dce_v10_0_ext_disable,
3463 /* no detect for TMDS/LVDS yet */
3464 };
3465
3466 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3467 .dpms = amdgpu_atombios_encoder_dpms,
3468 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3469 .prepare = dce_v10_0_encoder_prepare,
3470 .mode_set = dce_v10_0_encoder_mode_set,
3471 .commit = dce_v10_0_encoder_commit,
3472 .disable = dce_v10_0_encoder_disable,
3473 .detect = amdgpu_atombios_encoder_dig_detect,
3474 };
3475
3476 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3477 .dpms = amdgpu_atombios_encoder_dpms,
3478 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3479 .prepare = dce_v10_0_encoder_prepare,
3480 .mode_set = dce_v10_0_encoder_mode_set,
3481 .commit = dce_v10_0_encoder_commit,
3482 .detect = amdgpu_atombios_encoder_dac_detect,
3483 };
3484
dce_v10_0_encoder_destroy(struct drm_encoder * encoder)3485 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3486 {
3487 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3488 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3489 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3490 kfree(amdgpu_encoder->enc_priv);
3491 drm_encoder_cleanup(encoder);
3492 kfree(amdgpu_encoder);
3493 }
3494
3495 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3496 .destroy = dce_v10_0_encoder_destroy,
3497 };
3498
dce_v10_0_encoder_add(struct amdgpu_device * adev,uint32_t encoder_enum,uint32_t supported_device,u16 caps)3499 static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3500 uint32_t encoder_enum,
3501 uint32_t supported_device,
3502 u16 caps)
3503 {
3504 struct drm_device *dev = adev_to_drm(adev);
3505 struct drm_encoder *encoder;
3506 struct amdgpu_encoder *amdgpu_encoder;
3507
3508 /* see if we already added it */
3509 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3510 amdgpu_encoder = to_amdgpu_encoder(encoder);
3511 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3512 amdgpu_encoder->devices |= supported_device;
3513 return;
3514 }
3515
3516 }
3517
3518 /* add a new one */
3519 amdgpu_encoder = kzalloc_obj(struct amdgpu_encoder);
3520 if (!amdgpu_encoder)
3521 return;
3522
3523 encoder = &amdgpu_encoder->base;
3524 switch (adev->mode_info.num_crtc) {
3525 case 1:
3526 encoder->possible_crtcs = 0x1;
3527 break;
3528 case 2:
3529 default:
3530 encoder->possible_crtcs = 0x3;
3531 break;
3532 case 4:
3533 encoder->possible_crtcs = 0xf;
3534 break;
3535 case 6:
3536 encoder->possible_crtcs = 0x3f;
3537 break;
3538 }
3539
3540 amdgpu_encoder->enc_priv = NULL;
3541
3542 amdgpu_encoder->encoder_enum = encoder_enum;
3543 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3544 amdgpu_encoder->devices = supported_device;
3545 amdgpu_encoder->rmx_type = RMX_OFF;
3546 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3547 amdgpu_encoder->is_ext_encoder = false;
3548 amdgpu_encoder->caps = caps;
3549
3550 switch (amdgpu_encoder->encoder_id) {
3551 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3552 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3553 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3554 DRM_MODE_ENCODER_DAC, NULL);
3555 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3556 break;
3557 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3558 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3559 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3560 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3561 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3562 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3563 amdgpu_encoder->rmx_type = RMX_FULL;
3564 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3565 DRM_MODE_ENCODER_LVDS, NULL);
3566 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3567 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3568 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3569 DRM_MODE_ENCODER_DAC, NULL);
3570 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3571 } else {
3572 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3573 DRM_MODE_ENCODER_TMDS, NULL);
3574 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3575 }
3576 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3577 break;
3578 case ENCODER_OBJECT_ID_SI170B:
3579 case ENCODER_OBJECT_ID_CH7303:
3580 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3581 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3582 case ENCODER_OBJECT_ID_TITFP513:
3583 case ENCODER_OBJECT_ID_VT1623:
3584 case ENCODER_OBJECT_ID_HDMI_SI1930:
3585 case ENCODER_OBJECT_ID_TRAVIS:
3586 case ENCODER_OBJECT_ID_NUTMEG:
3587 /* these are handled by the primary encoders */
3588 amdgpu_encoder->is_ext_encoder = true;
3589 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3590 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3591 DRM_MODE_ENCODER_LVDS, NULL);
3592 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3593 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3594 DRM_MODE_ENCODER_DAC, NULL);
3595 else
3596 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3597 DRM_MODE_ENCODER_TMDS, NULL);
3598 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3599 break;
3600 }
3601 }
3602
3603 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3604 .bandwidth_update = &dce_v10_0_bandwidth_update,
3605 .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3606 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3607 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3608 .hpd_sense = &dce_v10_0_hpd_sense,
3609 .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3610 .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3611 .page_flip = &dce_v10_0_page_flip,
3612 .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3613 .add_encoder = &dce_v10_0_encoder_add,
3614 .add_connector = &amdgpu_connector_add,
3615 };
3616
dce_v10_0_set_display_funcs(struct amdgpu_device * adev)3617 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3618 {
3619 adev->mode_info.funcs = &dce_v10_0_display_funcs;
3620 }
3621
3622 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3623 .set = dce_v10_0_set_crtc_irq_state,
3624 .process = dce_v10_0_crtc_irq,
3625 };
3626
3627 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3628 .set = dce_v10_0_set_pageflip_irq_state,
3629 .process = dce_v10_0_pageflip_irq,
3630 };
3631
3632 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3633 .set = dce_v10_0_set_hpd_irq_state,
3634 .process = dce_v10_0_hpd_irq,
3635 };
3636
dce_v10_0_set_irq_funcs(struct amdgpu_device * adev)3637 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3638 {
3639 if (adev->mode_info.num_crtc > 0)
3640 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3641 else
3642 adev->crtc_irq.num_types = 0;
3643 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3644
3645 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3646 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3647
3648 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3649 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3650 }
3651
3652 const struct amdgpu_ip_block_version dce_v10_0_ip_block = {
3653 .type = AMD_IP_BLOCK_TYPE_DCE,
3654 .major = 10,
3655 .minor = 0,
3656 .rev = 0,
3657 .funcs = &dce_v10_0_ip_funcs,
3658 };
3659
3660 const struct amdgpu_ip_block_version dce_v10_1_ip_block = {
3661 .type = AMD_IP_BLOCK_TYPE_DCE,
3662 .major = 10,
3663 .minor = 1,
3664 .rev = 0,
3665 .funcs = &dce_v10_0_ip_funcs,
3666 };
3667