1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/irqdomain.h> 27 #include <linux/pci.h> 28 #include <linux/pm_domain.h> 29 #include <linux/platform_device.h> 30 #include <sound/designware_i2s.h> 31 #include <sound/pcm.h> 32 #include <linux/acpi.h> 33 #include <linux/dmi.h> 34 35 #include "amdgpu.h" 36 #include "atom.h" 37 #include "amdgpu_acp.h" 38 39 #include "acp_gfx_if.h" 40 41 #define ST_JADEITE 1 42 #define ACP_TILE_ON_MASK 0x03 43 #define ACP_TILE_OFF_MASK 0x02 44 #define ACP_TILE_ON_RETAIN_REG_MASK 0x1f 45 #define ACP_TILE_OFF_RETAIN_REG_MASK 0x20 46 47 #define ACP_TILE_P1_MASK 0x3e 48 #define ACP_TILE_P2_MASK 0x3d 49 #define ACP_TILE_DSP0_MASK 0x3b 50 #define ACP_TILE_DSP1_MASK 0x37 51 52 #define ACP_TILE_DSP2_MASK 0x2f 53 54 #define ACP_DMA_REGS_END 0x146c0 55 #define ACP_I2S_PLAY_REGS_START 0x14840 56 #define ACP_I2S_PLAY_REGS_END 0x148b4 57 #define ACP_I2S_CAP_REGS_START 0x148b8 58 #define ACP_I2S_CAP_REGS_END 0x1496c 59 60 #define ACP_I2S_COMP1_CAP_REG_OFFSET 0xac 61 #define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8 62 #define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c 63 #define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68 64 #define ACP_BT_PLAY_REGS_START 0x14970 65 #define ACP_BT_PLAY_REGS_END 0x14a24 66 #define ACP_BT_COMP1_REG_OFFSET 0xac 67 #define ACP_BT_COMP2_REG_OFFSET 0xa8 68 69 #define mmACP_PGFSM_RETAIN_REG 0x51c9 70 #define mmACP_PGFSM_CONFIG_REG 0x51ca 71 #define mmACP_PGFSM_READ_REG_0 0x51cc 72 73 #define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8 74 #define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9 75 #define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa 76 #define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb 77 78 #define mmACP_CONTROL 0x5131 79 #define mmACP_STATUS 0x5133 80 #define mmACP_SOFT_RESET 0x5134 81 #define ACP_CONTROL__ClkEn_MASK 0x1 82 #define ACP_SOFT_RESET__SoftResetAud_MASK 0x100 83 #define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000 84 #define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF 85 #define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF 86 87 #define ACP_TIMEOUT_LOOP 0x000000FF 88 #define ACP_DEVS 4 89 #define ACP_SRC_ID 162 90 91 static unsigned long acp_machine_id; 92 93 enum { 94 ACP_TILE_P1 = 0, 95 ACP_TILE_P2, 96 ACP_TILE_DSP0, 97 ACP_TILE_DSP1, 98 ACP_TILE_DSP2, 99 }; 100 101 static int acp_sw_init(struct amdgpu_ip_block *ip_block) 102 { 103 struct amdgpu_device *adev = ip_block->adev; 104 105 adev->acp.parent = adev->dev; 106 107 adev->acp.cgs_device = 108 amdgpu_cgs_create_device(adev); 109 if (!adev->acp.cgs_device) 110 return -EINVAL; 111 112 return 0; 113 } 114 115 static int acp_sw_fini(struct amdgpu_ip_block *ip_block) 116 { 117 struct amdgpu_device *adev = ip_block->adev; 118 119 if (adev->acp.cgs_device) 120 amdgpu_cgs_destroy_device(adev->acp.cgs_device); 121 122 return 0; 123 } 124 125 struct acp_pm_domain { 126 void *adev; 127 struct generic_pm_domain gpd; 128 }; 129 130 static int acp_poweroff(struct generic_pm_domain *genpd) 131 { 132 struct acp_pm_domain *apd; 133 struct amdgpu_device *adev; 134 135 apd = container_of(genpd, struct acp_pm_domain, gpd); 136 adev = apd->adev; 137 /* call smu to POWER GATE ACP block 138 * smu will 139 * 1. turn off the acp clock 140 * 2. power off the acp tiles 141 * 3. check and enter ulv state 142 */ 143 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0); 144 return 0; 145 } 146 147 static int acp_poweron(struct generic_pm_domain *genpd) 148 { 149 struct acp_pm_domain *apd; 150 struct amdgpu_device *adev; 151 152 apd = container_of(genpd, struct acp_pm_domain, gpd); 153 adev = apd->adev; 154 /* call smu to UNGATE ACP block 155 * smu will 156 * 1. exit ulv 157 * 2. turn on acp clock 158 * 3. power on acp tiles 159 */ 160 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0); 161 return 0; 162 } 163 164 static int acp_genpd_add_device(struct device *dev, void *data) 165 { 166 struct generic_pm_domain *gpd = data; 167 int ret; 168 169 ret = pm_genpd_add_device(gpd, dev); 170 if (ret) 171 dev_err(dev, "Failed to add dev to genpd %d\n", ret); 172 173 return ret; 174 } 175 176 static int acp_genpd_remove_device(struct device *dev, void *data) 177 { 178 int ret; 179 180 ret = pm_genpd_remove_device(dev); 181 if (ret) 182 dev_err(dev, "Failed to remove dev from genpd %d\n", ret); 183 184 /* Continue to remove */ 185 return 0; 186 } 187 188 static int acp_quirk_cb(const struct dmi_system_id *id) 189 { 190 acp_machine_id = ST_JADEITE; 191 return 1; 192 } 193 194 static const struct dmi_system_id acp_quirk_table[] = { 195 { 196 .callback = acp_quirk_cb, 197 .matches = { 198 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMD"), 199 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Jadeite"), 200 } 201 }, 202 { 203 .callback = acp_quirk_cb, 204 .matches = { 205 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "IP3 Technology CO.,Ltd."), 206 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "ASN1D"), 207 }, 208 }, 209 { 210 .callback = acp_quirk_cb, 211 .matches = { 212 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Standard"), 213 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "ASN10"), 214 }, 215 }, 216 {} 217 }; 218 219 /** 220 * acp_hw_init - start and test ACP block 221 * 222 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 223 * 224 */ 225 static int acp_hw_init(struct amdgpu_ip_block *ip_block) 226 { 227 int r; 228 u64 acp_base; 229 u32 val = 0; 230 u32 count = 0; 231 struct i2s_platform_data *i2s_pdata = NULL; 232 233 struct amdgpu_device *adev = ip_block->adev; 234 235 r = amd_acp_hw_init(adev->acp.cgs_device, 236 ip_block->version->major, ip_block->version->minor); 237 /* -ENODEV means board uses AZ rather than ACP */ 238 if (r == -ENODEV) { 239 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0); 240 return 0; 241 } else if (r) { 242 return r; 243 } 244 245 if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289) 246 return -EINVAL; 247 248 acp_base = adev->rmmio_base; 249 adev->acp.acp_genpd = kzalloc_obj(struct acp_pm_domain, GFP_KERNEL); 250 if (!adev->acp.acp_genpd) 251 return -ENOMEM; 252 253 adev->acp.acp_genpd->gpd.name = "ACP_AUDIO"; 254 adev->acp.acp_genpd->gpd.power_off = acp_poweroff; 255 adev->acp.acp_genpd->gpd.power_on = acp_poweron; 256 adev->acp.acp_genpd->adev = adev; 257 258 pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false); 259 dmi_check_system(acp_quirk_table); 260 switch (acp_machine_id) { 261 case ST_JADEITE: 262 { 263 adev->acp.acp_cell = kzalloc_objs(struct mfd_cell, 2, 264 GFP_KERNEL); 265 if (!adev->acp.acp_cell) { 266 r = -ENOMEM; 267 goto failure; 268 } 269 270 adev->acp.acp_res = kzalloc_objs(struct resource, 3, GFP_KERNEL); 271 if (!adev->acp.acp_res) { 272 r = -ENOMEM; 273 goto failure; 274 } 275 276 i2s_pdata = kzalloc_objs(struct i2s_platform_data, 1, 277 GFP_KERNEL); 278 if (!i2s_pdata) { 279 r = -ENOMEM; 280 goto failure; 281 } 282 283 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 284 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 285 i2s_pdata[0].cap = DWC_I2S_PLAY | DWC_I2S_RECORD; 286 i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000; 287 i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET; 288 i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET; 289 290 adev->acp.acp_res[0].name = "acp2x_dma"; 291 adev->acp.acp_res[0].flags = IORESOURCE_MEM; 292 adev->acp.acp_res[0].start = acp_base; 293 adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END; 294 295 adev->acp.acp_res[1].name = "acp2x_dw_i2s_play_cap"; 296 adev->acp.acp_res[1].flags = IORESOURCE_MEM; 297 adev->acp.acp_res[1].start = acp_base + ACP_I2S_CAP_REGS_START; 298 adev->acp.acp_res[1].end = acp_base + ACP_I2S_CAP_REGS_END; 299 300 adev->acp.acp_res[2].name = "acp2x_dma_irq"; 301 adev->acp.acp_res[2].flags = IORESOURCE_IRQ; 302 adev->acp.acp_res[2].start = amdgpu_irq_create_mapping(adev, 162); 303 adev->acp.acp_res[2].end = adev->acp.acp_res[2].start; 304 305 adev->acp.acp_cell[0].name = "acp_audio_dma"; 306 adev->acp.acp_cell[0].id = 0; 307 adev->acp.acp_cell[0].num_resources = 3; 308 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0]; 309 adev->acp.acp_cell[0].platform_data = &adev->asic_type; 310 adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type); 311 312 adev->acp.acp_cell[1].name = "designware-i2s"; 313 adev->acp.acp_cell[1].id = 1; 314 adev->acp.acp_cell[1].num_resources = 1; 315 adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1]; 316 adev->acp.acp_cell[1].platform_data = &i2s_pdata[0]; 317 adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data); 318 r = mfd_add_devices(adev->acp.parent, 0, adev->acp.acp_cell, 2, NULL, 0, NULL); 319 if (r) 320 goto failure; 321 r = device_for_each_child(adev->acp.parent, &adev->acp.acp_genpd->gpd, 322 acp_genpd_add_device); 323 if (r) 324 goto failure; 325 break; 326 } 327 default: 328 adev->acp.acp_cell = kzalloc_objs(struct mfd_cell, ACP_DEVS, 329 GFP_KERNEL); 330 331 if (!adev->acp.acp_cell) { 332 r = -ENOMEM; 333 goto failure; 334 } 335 336 adev->acp.acp_res = kzalloc_objs(struct resource, 5, GFP_KERNEL); 337 if (!adev->acp.acp_res) { 338 r = -ENOMEM; 339 goto failure; 340 } 341 342 i2s_pdata = kzalloc_objs(struct i2s_platform_data, 3, 343 GFP_KERNEL); 344 if (!i2s_pdata) { 345 r = -ENOMEM; 346 goto failure; 347 } 348 349 switch (adev->asic_type) { 350 case CHIP_STONEY: 351 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 352 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 353 break; 354 default: 355 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; 356 } 357 i2s_pdata[0].cap = DWC_I2S_PLAY; 358 i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000; 359 i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET; 360 i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET; 361 switch (adev->asic_type) { 362 case CHIP_STONEY: 363 i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 364 DW_I2S_QUIRK_COMP_PARAM1 | 365 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 366 break; 367 default: 368 i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 369 DW_I2S_QUIRK_COMP_PARAM1; 370 } 371 372 i2s_pdata[1].cap = DWC_I2S_RECORD; 373 i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000; 374 i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET; 375 i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET; 376 377 i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; 378 switch (adev->asic_type) { 379 case CHIP_STONEY: 380 i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 381 break; 382 default: 383 break; 384 } 385 386 i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD; 387 i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000; 388 i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET; 389 i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET; 390 391 adev->acp.acp_res[0].name = "acp2x_dma"; 392 adev->acp.acp_res[0].flags = IORESOURCE_MEM; 393 adev->acp.acp_res[0].start = acp_base; 394 adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END; 395 396 adev->acp.acp_res[1].name = "acp2x_dw_i2s_play"; 397 adev->acp.acp_res[1].flags = IORESOURCE_MEM; 398 adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START; 399 adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END; 400 401 adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap"; 402 adev->acp.acp_res[2].flags = IORESOURCE_MEM; 403 adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START; 404 adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END; 405 406 adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap"; 407 adev->acp.acp_res[3].flags = IORESOURCE_MEM; 408 adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START; 409 adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END; 410 411 adev->acp.acp_res[4].name = "acp2x_dma_irq"; 412 adev->acp.acp_res[4].flags = IORESOURCE_IRQ; 413 adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162); 414 adev->acp.acp_res[4].end = adev->acp.acp_res[4].start; 415 416 adev->acp.acp_cell[0].name = "acp_audio_dma"; 417 adev->acp.acp_cell[0].id = 0; 418 adev->acp.acp_cell[0].num_resources = 5; 419 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0]; 420 adev->acp.acp_cell[0].platform_data = &adev->asic_type; 421 adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type); 422 423 adev->acp.acp_cell[1].name = "designware-i2s"; 424 adev->acp.acp_cell[1].id = 1; 425 adev->acp.acp_cell[1].num_resources = 1; 426 adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1]; 427 adev->acp.acp_cell[1].platform_data = &i2s_pdata[0]; 428 adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data); 429 430 adev->acp.acp_cell[2].name = "designware-i2s"; 431 adev->acp.acp_cell[2].id = 2; 432 adev->acp.acp_cell[2].num_resources = 1; 433 adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2]; 434 adev->acp.acp_cell[2].platform_data = &i2s_pdata[1]; 435 adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data); 436 437 adev->acp.acp_cell[3].name = "designware-i2s"; 438 adev->acp.acp_cell[3].id = 3; 439 adev->acp.acp_cell[3].num_resources = 1; 440 adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3]; 441 adev->acp.acp_cell[3].platform_data = &i2s_pdata[2]; 442 adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data); 443 444 r = mfd_add_devices(adev->acp.parent, 0, adev->acp.acp_cell, ACP_DEVS, NULL, 0, NULL); 445 if (r) 446 goto failure; 447 448 r = device_for_each_child(adev->acp.parent, &adev->acp.acp_genpd->gpd, 449 acp_genpd_add_device); 450 if (r) 451 goto failure; 452 } 453 454 /* Assert Soft reset of ACP */ 455 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 456 457 val |= ACP_SOFT_RESET__SoftResetAud_MASK; 458 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 459 460 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 461 while (true) { 462 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 463 if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 464 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 465 break; 466 if (--count == 0) { 467 dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 468 r = -ETIMEDOUT; 469 goto failure; 470 } 471 udelay(100); 472 } 473 /* Enable clock to ACP and wait until the clock is enabled */ 474 val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL); 475 val = val | ACP_CONTROL__ClkEn_MASK; 476 cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val); 477 478 count = ACP_CLOCK_EN_TIME_OUT_VALUE; 479 480 while (true) { 481 val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS); 482 if (val & (u32) 0x1) 483 break; 484 if (--count == 0) { 485 dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 486 r = -ETIMEDOUT; 487 goto failure; 488 } 489 udelay(100); 490 } 491 /* Deassert the SOFT RESET flags */ 492 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 493 val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; 494 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 495 return 0; 496 497 failure: 498 kfree(i2s_pdata); 499 kfree(adev->acp.acp_res); 500 kfree(adev->acp.acp_cell); 501 kfree(adev->acp.acp_genpd); 502 return r; 503 } 504 505 /** 506 * acp_hw_fini - stop the hardware block 507 * 508 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 509 * 510 */ 511 static int acp_hw_fini(struct amdgpu_ip_block *ip_block) 512 { 513 u32 val = 0; 514 u32 count = 0; 515 struct amdgpu_device *adev = ip_block->adev; 516 517 /* return early if no ACP */ 518 if (!adev->acp.acp_genpd) { 519 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0); 520 return 0; 521 } 522 523 /* Assert Soft reset of ACP */ 524 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 525 526 val |= ACP_SOFT_RESET__SoftResetAud_MASK; 527 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 528 529 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 530 while (true) { 531 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 532 if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 533 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 534 break; 535 if (--count == 0) { 536 dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 537 return -ETIMEDOUT; 538 } 539 udelay(100); 540 } 541 /* Disable ACP clock */ 542 val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL); 543 val &= ~ACP_CONTROL__ClkEn_MASK; 544 cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val); 545 546 count = ACP_CLOCK_EN_TIME_OUT_VALUE; 547 548 while (true) { 549 val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS); 550 if (val & (u32) 0x1) 551 break; 552 if (--count == 0) { 553 dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 554 return -ETIMEDOUT; 555 } 556 udelay(100); 557 } 558 559 device_for_each_child(adev->acp.parent, NULL, 560 acp_genpd_remove_device); 561 562 mfd_remove_devices(adev->acp.parent); 563 kfree(adev->acp.acp_res); 564 kfree(adev->acp.acp_genpd); 565 kfree(adev->acp.acp_cell); 566 567 return 0; 568 } 569 570 static int acp_suspend(struct amdgpu_ip_block *ip_block) 571 { 572 struct amdgpu_device *adev = ip_block->adev; 573 574 /* power up on suspend */ 575 if (!adev->acp.acp_cell) 576 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0); 577 return 0; 578 } 579 580 static int acp_resume(struct amdgpu_ip_block *ip_block) 581 { 582 struct amdgpu_device *adev = ip_block->adev; 583 584 /* power down again on resume */ 585 if (!adev->acp.acp_cell) 586 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0); 587 return 0; 588 } 589 590 static bool acp_is_idle(struct amdgpu_ip_block *ip_block) 591 { 592 return true; 593 } 594 595 static int acp_set_clockgating_state(struct amdgpu_ip_block *ip_block, 596 enum amd_clockgating_state state) 597 { 598 return 0; 599 } 600 601 static int acp_set_powergating_state(struct amdgpu_ip_block *ip_block, 602 enum amd_powergating_state state) 603 { 604 struct amdgpu_device *adev = ip_block->adev; 605 bool enable = (state == AMD_PG_STATE_GATE); 606 607 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable, 0); 608 609 return 0; 610 } 611 612 static const struct amd_ip_funcs acp_ip_funcs = { 613 .name = "acp_ip", 614 .sw_init = acp_sw_init, 615 .sw_fini = acp_sw_fini, 616 .hw_init = acp_hw_init, 617 .hw_fini = acp_hw_fini, 618 .suspend = acp_suspend, 619 .resume = acp_resume, 620 .is_idle = acp_is_idle, 621 .set_clockgating_state = acp_set_clockgating_state, 622 .set_powergating_state = acp_set_powergating_state, 623 }; 624 625 const struct amdgpu_ip_block_version acp_ip_block = { 626 .type = AMD_IP_BLOCK_TYPE_ACP, 627 .major = 2, 628 .minor = 2, 629 .rev = 0, 630 .funcs = &acp_ip_funcs, 631 }; 632