1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */ 2 /* 3 * Copyright 1996-1999 Thomas Bogendoerfer 4 * 5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker. 6 * 7 * Copyright 1993 United States Government as represented by the 8 * Director, National Security Agency. 9 * 10 * This software may be used and distributed according to the terms 11 * of the GNU General Public License, incorporated herein by reference. 12 * 13 * This driver is for PCnet32 and PCnetPCI based ethercards 14 */ 15 /************************************************************************** 16 * 23 Oct, 2000. 17 * Fixed a few bugs, related to running the controller in 32bit mode. 18 * 19 * Carsten Langgaard, carstenl@mips.com 20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 21 * 22 *************************************************************************/ 23 24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 25 26 #define DRV_NAME "pcnet32" 27 #define DRV_RELDATE "21.Apr.2008" 28 #define PFX DRV_NAME ": " 29 30 #include <linux/module.h> 31 #include <linux/kernel.h> 32 #include <linux/sched.h> 33 #include <linux/string.h> 34 #include <linux/errno.h> 35 #include <linux/ioport.h> 36 #include <linux/slab.h> 37 #include <linux/interrupt.h> 38 #include <linux/pci.h> 39 #include <linux/delay.h> 40 #include <linux/init.h> 41 #include <linux/ethtool.h> 42 #include <linux/mii.h> 43 #include <linux/crc32.h> 44 #include <linux/netdevice.h> 45 #include <linux/etherdevice.h> 46 #include <linux/if_ether.h> 47 #include <linux/skbuff.h> 48 #include <linux/spinlock.h> 49 #include <linux/moduleparam.h> 50 #include <linux/bitops.h> 51 #include <linux/io.h> 52 #include <linux/uaccess.h> 53 54 #include <asm/dma.h> 55 #include <asm/irq.h> 56 57 /* 58 * PCI device identifiers for "new style" Linux PCI Device Drivers 59 */ 60 static const struct pci_device_id pcnet32_pci_tbl[] = { 61 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), }, 62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), }, 63 64 /* 65 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have 66 * the incorrect vendor id. 67 */ 68 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE), 69 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, }, 70 71 { } /* terminate list */ 72 }; 73 74 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl); 75 76 static int cards_found; 77 78 /* 79 * VLB I/O addresses 80 */ 81 static unsigned int pcnet32_portlist[] = 82 { 0x300, 0x320, 0x340, 0x360, 0 }; 83 84 static int pcnet32_debug; 85 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */ 86 static int pcnet32vlb; /* check for VLB cards ? */ 87 88 static struct net_device *pcnet32_dev; 89 90 static int max_interrupt_work = 2; 91 static int rx_copybreak = 200; 92 93 #define PCNET32_PORT_AUI 0x00 94 #define PCNET32_PORT_10BT 0x01 95 #define PCNET32_PORT_GPSI 0x02 96 #define PCNET32_PORT_MII 0x03 97 98 #define PCNET32_PORT_PORTSEL 0x03 99 #define PCNET32_PORT_ASEL 0x04 100 #define PCNET32_PORT_100 0x40 101 #define PCNET32_PORT_FD 0x80 102 103 #define PCNET32_DMA_MASK 0xffffffff 104 105 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ)) 106 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4)) 107 108 /* 109 * table to translate option values from tulip 110 * to internal options 111 */ 112 static const unsigned char options_mapping[] = { 113 PCNET32_PORT_ASEL, /* 0 Auto-select */ 114 PCNET32_PORT_AUI, /* 1 BNC/AUI */ 115 PCNET32_PORT_AUI, /* 2 AUI/BNC */ 116 PCNET32_PORT_ASEL, /* 3 not supported */ 117 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */ 118 PCNET32_PORT_ASEL, /* 5 not supported */ 119 PCNET32_PORT_ASEL, /* 6 not supported */ 120 PCNET32_PORT_ASEL, /* 7 not supported */ 121 PCNET32_PORT_ASEL, /* 8 not supported */ 122 PCNET32_PORT_MII, /* 9 MII 10baseT */ 123 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */ 124 PCNET32_PORT_MII, /* 11 MII (autosel) */ 125 PCNET32_PORT_10BT, /* 12 10BaseT */ 126 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */ 127 /* 14 MII 100BaseTx-FD */ 128 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, 129 PCNET32_PORT_ASEL /* 15 not supported */ 130 }; 131 132 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = { 133 "Loopback test (offline)" 134 }; 135 136 #define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test) 137 138 #define PCNET32_NUM_REGS 136 139 140 #define MAX_UNITS 8 /* More are supported, limit only on options */ 141 static int options[MAX_UNITS]; 142 static int full_duplex[MAX_UNITS]; 143 static int homepna[MAX_UNITS]; 144 145 /* 146 * Theory of Operation 147 * 148 * This driver uses the same software structure as the normal lance 149 * driver. So look for a verbose description in lance.c. The differences 150 * to the normal lance driver is the use of the 32bit mode of PCnet32 151 * and PCnetPCI chips. Because these chips are 32bit chips, there is no 152 * 16MB limitation and we don't need bounce buffers. 153 */ 154 155 /* 156 * Set the number of Tx and Rx buffers, using Log_2(# buffers). 157 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. 158 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). 159 */ 160 #ifndef PCNET32_LOG_TX_BUFFERS 161 #define PCNET32_LOG_TX_BUFFERS 4 162 #define PCNET32_LOG_RX_BUFFERS 5 163 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */ 164 #define PCNET32_LOG_MAX_RX_BUFFERS 9 165 #endif 166 167 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS)) 168 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS)) 169 170 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS)) 171 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS)) 172 173 #define PKT_BUF_SKB 1544 174 /* actual buffer length after being aligned */ 175 #define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN) 176 /* chip wants twos complement of the (aligned) buffer length */ 177 #define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB) 178 179 /* Offsets from base I/O address. */ 180 #define PCNET32_WIO_RDP 0x10 181 #define PCNET32_WIO_RAP 0x12 182 #define PCNET32_WIO_RESET 0x14 183 #define PCNET32_WIO_BDP 0x16 184 185 #define PCNET32_DWIO_RDP 0x10 186 #define PCNET32_DWIO_RAP 0x14 187 #define PCNET32_DWIO_RESET 0x18 188 #define PCNET32_DWIO_BDP 0x1C 189 190 #define PCNET32_TOTAL_SIZE 0x20 191 192 #define CSR0 0 193 #define CSR0_INIT 0x1 194 #define CSR0_START 0x2 195 #define CSR0_STOP 0x4 196 #define CSR0_TXPOLL 0x8 197 #define CSR0_INTEN 0x40 198 #define CSR0_IDON 0x0100 199 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN) 200 #define PCNET32_INIT_LOW 1 201 #define PCNET32_INIT_HIGH 2 202 #define CSR3 3 203 #define CSR4 4 204 #define CSR5 5 205 #define CSR5_SUSPEND 0x0001 206 #define CSR15 15 207 #define PCNET32_MC_FILTER 8 208 209 #define PCNET32_79C970A 0x2621 210 211 /* The PCNET32 Rx and Tx ring descriptors. */ 212 struct pcnet32_rx_head { 213 __le32 base; 214 __le16 buf_length; /* two`s complement of length */ 215 __le16 status; 216 __le32 msg_length; 217 __le32 reserved; 218 }; 219 220 struct pcnet32_tx_head { 221 __le32 base; 222 __le16 length; /* two`s complement of length */ 223 __le16 status; 224 __le32 misc; 225 __le32 reserved; 226 }; 227 228 /* The PCNET32 32-Bit initialization block, described in databook. */ 229 struct pcnet32_init_block { 230 __le16 mode; 231 __le16 tlen_rlen; 232 u8 phys_addr[6]; 233 __le16 reserved; 234 __le32 filter[2]; 235 /* Receive and transmit ring base, along with extra bits. */ 236 __le32 rx_ring; 237 __le32 tx_ring; 238 }; 239 240 /* PCnet32 access functions */ 241 struct pcnet32_access { 242 u16 (*read_csr) (unsigned long, int); 243 void (*write_csr) (unsigned long, int, u16); 244 u16 (*read_bcr) (unsigned long, int); 245 void (*write_bcr) (unsigned long, int, u16); 246 u16 (*read_rap) (unsigned long); 247 void (*write_rap) (unsigned long, u16); 248 void (*reset) (unsigned long); 249 }; 250 251 /* 252 * The first field of pcnet32_private is read by the ethernet device 253 * so the structure should be allocated using dma_alloc_coherent(). 254 */ 255 struct pcnet32_private { 256 struct pcnet32_init_block *init_block; 257 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */ 258 struct pcnet32_rx_head *rx_ring; 259 struct pcnet32_tx_head *tx_ring; 260 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block, 261 returned by dma_alloc_coherent */ 262 struct pci_dev *pci_dev; 263 const char *name; 264 /* The saved address of a sent-in-place packet/buffer, for skfree(). */ 265 struct sk_buff **tx_skbuff; 266 struct sk_buff **rx_skbuff; 267 dma_addr_t *tx_dma_addr; 268 dma_addr_t *rx_dma_addr; 269 const struct pcnet32_access *a; 270 spinlock_t lock; /* Guard lock */ 271 unsigned int cur_rx, cur_tx; /* The next free ring entry */ 272 unsigned int rx_ring_size; /* current rx ring size */ 273 unsigned int tx_ring_size; /* current tx ring size */ 274 unsigned int rx_mod_mask; /* rx ring modular mask */ 275 unsigned int tx_mod_mask; /* tx ring modular mask */ 276 unsigned short rx_len_bits; 277 unsigned short tx_len_bits; 278 dma_addr_t rx_ring_dma_addr; 279 dma_addr_t tx_ring_dma_addr; 280 unsigned int dirty_rx, /* ring entries to be freed. */ 281 dirty_tx; 282 283 struct net_device *dev; 284 struct napi_struct napi; 285 char tx_full; 286 char phycount; /* number of phys found */ 287 int options; 288 unsigned int shared_irq:1, /* shared irq possible */ 289 dxsuflo:1, /* disable transmit stop on uflo */ 290 mii:1, /* mii port available */ 291 autoneg:1, /* autoneg enabled */ 292 port_tp:1, /* port set to TP */ 293 fdx:1; /* full duplex enabled */ 294 struct net_device *next; 295 struct mii_if_info mii_if; 296 struct timer_list watchdog_timer; 297 u32 msg_enable; /* debug message level */ 298 299 /* each bit indicates an available PHY */ 300 u32 phymask; 301 unsigned short chip_version; /* which variant this is */ 302 303 /* saved registers during ethtool blink */ 304 u16 save_regs[4]; 305 }; 306 307 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *); 308 static int pcnet32_probe1(unsigned long, int, struct pci_dev *); 309 static int pcnet32_open(struct net_device *); 310 static int pcnet32_init_ring(struct net_device *); 311 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *, 312 struct net_device *); 313 static void pcnet32_tx_timeout(struct net_device *dev, unsigned int txqueue); 314 static irqreturn_t pcnet32_interrupt(int, void *); 315 static int pcnet32_close(struct net_device *); 316 static struct net_device_stats *pcnet32_get_stats(struct net_device *); 317 static void pcnet32_load_multicast(struct net_device *dev); 318 static void pcnet32_set_multicast_list(struct net_device *); 319 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int); 320 static void pcnet32_watchdog(struct timer_list *); 321 static int mdio_read(struct net_device *dev, int phy_id, int reg_num); 322 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, 323 int val); 324 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits); 325 static void pcnet32_ethtool_test(struct net_device *dev, 326 struct ethtool_test *eth_test, u64 * data); 327 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1); 328 static int pcnet32_get_regs_len(struct net_device *dev); 329 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, 330 void *ptr); 331 static void pcnet32_purge_tx_ring(struct net_device *dev); 332 static int pcnet32_alloc_ring(struct net_device *dev, const char *name); 333 static void pcnet32_free_ring(struct net_device *dev); 334 static void pcnet32_check_media(struct net_device *dev, int verbose); 335 336 static u16 pcnet32_wio_read_csr(unsigned long addr, int index) 337 { 338 outw(index, addr + PCNET32_WIO_RAP); 339 return inw(addr + PCNET32_WIO_RDP); 340 } 341 342 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val) 343 { 344 outw(index, addr + PCNET32_WIO_RAP); 345 outw(val, addr + PCNET32_WIO_RDP); 346 } 347 348 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index) 349 { 350 outw(index, addr + PCNET32_WIO_RAP); 351 return inw(addr + PCNET32_WIO_BDP); 352 } 353 354 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val) 355 { 356 outw(index, addr + PCNET32_WIO_RAP); 357 outw(val, addr + PCNET32_WIO_BDP); 358 } 359 360 static u16 pcnet32_wio_read_rap(unsigned long addr) 361 { 362 return inw(addr + PCNET32_WIO_RAP); 363 } 364 365 static void pcnet32_wio_write_rap(unsigned long addr, u16 val) 366 { 367 outw(val, addr + PCNET32_WIO_RAP); 368 } 369 370 static void pcnet32_wio_reset(unsigned long addr) 371 { 372 inw(addr + PCNET32_WIO_RESET); 373 } 374 375 static int pcnet32_wio_check(unsigned long addr) 376 { 377 outw(88, addr + PCNET32_WIO_RAP); 378 return inw(addr + PCNET32_WIO_RAP) == 88; 379 } 380 381 static const struct pcnet32_access pcnet32_wio = { 382 .read_csr = pcnet32_wio_read_csr, 383 .write_csr = pcnet32_wio_write_csr, 384 .read_bcr = pcnet32_wio_read_bcr, 385 .write_bcr = pcnet32_wio_write_bcr, 386 .read_rap = pcnet32_wio_read_rap, 387 .write_rap = pcnet32_wio_write_rap, 388 .reset = pcnet32_wio_reset 389 }; 390 391 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index) 392 { 393 outl(index, addr + PCNET32_DWIO_RAP); 394 return inl(addr + PCNET32_DWIO_RDP) & 0xffff; 395 } 396 397 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val) 398 { 399 outl(index, addr + PCNET32_DWIO_RAP); 400 outl(val, addr + PCNET32_DWIO_RDP); 401 } 402 403 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index) 404 { 405 outl(index, addr + PCNET32_DWIO_RAP); 406 return inl(addr + PCNET32_DWIO_BDP) & 0xffff; 407 } 408 409 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val) 410 { 411 outl(index, addr + PCNET32_DWIO_RAP); 412 outl(val, addr + PCNET32_DWIO_BDP); 413 } 414 415 static u16 pcnet32_dwio_read_rap(unsigned long addr) 416 { 417 return inl(addr + PCNET32_DWIO_RAP) & 0xffff; 418 } 419 420 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val) 421 { 422 outl(val, addr + PCNET32_DWIO_RAP); 423 } 424 425 static void pcnet32_dwio_reset(unsigned long addr) 426 { 427 inl(addr + PCNET32_DWIO_RESET); 428 } 429 430 static int pcnet32_dwio_check(unsigned long addr) 431 { 432 outl(88, addr + PCNET32_DWIO_RAP); 433 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88; 434 } 435 436 static const struct pcnet32_access pcnet32_dwio = { 437 .read_csr = pcnet32_dwio_read_csr, 438 .write_csr = pcnet32_dwio_write_csr, 439 .read_bcr = pcnet32_dwio_read_bcr, 440 .write_bcr = pcnet32_dwio_write_bcr, 441 .read_rap = pcnet32_dwio_read_rap, 442 .write_rap = pcnet32_dwio_write_rap, 443 .reset = pcnet32_dwio_reset 444 }; 445 446 static void pcnet32_netif_stop(struct net_device *dev) 447 { 448 struct pcnet32_private *lp = netdev_priv(dev); 449 450 netif_trans_update(dev); /* prevent tx timeout */ 451 napi_disable(&lp->napi); 452 netif_tx_disable(dev); 453 } 454 455 static void pcnet32_netif_start(struct net_device *dev) 456 { 457 struct pcnet32_private *lp = netdev_priv(dev); 458 ulong ioaddr = dev->base_addr; 459 u16 val; 460 461 netif_wake_queue(dev); 462 val = lp->a->read_csr(ioaddr, CSR3); 463 val &= 0x00ff; 464 lp->a->write_csr(ioaddr, CSR3, val); 465 napi_enable_locked(&lp->napi); 466 } 467 468 /* 469 * Allocate space for the new sized tx ring. 470 * Free old resources 471 * Save new resources. 472 * Any failure keeps old resources. 473 * Must be called with lp->lock held. 474 */ 475 static void pcnet32_realloc_tx_ring(struct net_device *dev, 476 struct pcnet32_private *lp, 477 unsigned int size) 478 { 479 dma_addr_t new_ring_dma_addr; 480 dma_addr_t *new_dma_addr_list; 481 struct pcnet32_tx_head *new_tx_ring; 482 struct sk_buff **new_skb_list; 483 unsigned int entries = BIT(size); 484 485 pcnet32_purge_tx_ring(dev); 486 487 new_tx_ring = 488 dma_alloc_coherent(&lp->pci_dev->dev, 489 sizeof(struct pcnet32_tx_head) * entries, 490 &new_ring_dma_addr, GFP_ATOMIC); 491 if (!new_tx_ring) 492 return; 493 494 new_dma_addr_list = kzalloc_objs(dma_addr_t, entries, GFP_ATOMIC); 495 if (!new_dma_addr_list) 496 goto free_new_tx_ring; 497 498 new_skb_list = kzalloc_objs(struct sk_buff *, entries, GFP_ATOMIC); 499 if (!new_skb_list) 500 goto free_new_lists; 501 502 kfree(lp->tx_skbuff); 503 kfree(lp->tx_dma_addr); 504 dma_free_coherent(&lp->pci_dev->dev, 505 sizeof(struct pcnet32_tx_head) * lp->tx_ring_size, 506 lp->tx_ring, lp->tx_ring_dma_addr); 507 508 lp->tx_ring_size = entries; 509 lp->tx_mod_mask = lp->tx_ring_size - 1; 510 lp->tx_len_bits = (size << 12); 511 lp->tx_ring = new_tx_ring; 512 lp->tx_ring_dma_addr = new_ring_dma_addr; 513 lp->tx_dma_addr = new_dma_addr_list; 514 lp->tx_skbuff = new_skb_list; 515 return; 516 517 free_new_lists: 518 kfree(new_dma_addr_list); 519 free_new_tx_ring: 520 dma_free_coherent(&lp->pci_dev->dev, 521 sizeof(struct pcnet32_tx_head) * entries, 522 new_tx_ring, new_ring_dma_addr); 523 } 524 525 /* 526 * Allocate space for the new sized rx ring. 527 * Re-use old receive buffers. 528 * alloc extra buffers 529 * free unneeded buffers 530 * free unneeded buffers 531 * Save new resources. 532 * Any failure keeps old resources. 533 * Must be called with lp->lock held. 534 */ 535 static void pcnet32_realloc_rx_ring(struct net_device *dev, 536 struct pcnet32_private *lp, 537 unsigned int size) 538 { 539 dma_addr_t new_ring_dma_addr; 540 dma_addr_t *new_dma_addr_list; 541 struct pcnet32_rx_head *new_rx_ring; 542 struct sk_buff **new_skb_list; 543 int new, overlap; 544 unsigned int entries = BIT(size); 545 546 new_rx_ring = 547 dma_alloc_coherent(&lp->pci_dev->dev, 548 sizeof(struct pcnet32_rx_head) * entries, 549 &new_ring_dma_addr, GFP_ATOMIC); 550 if (!new_rx_ring) 551 return; 552 553 new_dma_addr_list = kzalloc_objs(dma_addr_t, entries, GFP_ATOMIC); 554 if (!new_dma_addr_list) 555 goto free_new_rx_ring; 556 557 new_skb_list = kzalloc_objs(struct sk_buff *, entries, GFP_ATOMIC); 558 if (!new_skb_list) 559 goto free_new_lists; 560 561 /* first copy the current receive buffers */ 562 overlap = min(entries, lp->rx_ring_size); 563 for (new = 0; new < overlap; new++) { 564 new_rx_ring[new] = lp->rx_ring[new]; 565 new_dma_addr_list[new] = lp->rx_dma_addr[new]; 566 new_skb_list[new] = lp->rx_skbuff[new]; 567 } 568 /* now allocate any new buffers needed */ 569 for (; new < entries; new++) { 570 struct sk_buff *rx_skbuff; 571 new_skb_list[new] = netdev_alloc_skb(dev, PKT_BUF_SKB); 572 rx_skbuff = new_skb_list[new]; 573 if (!rx_skbuff) { 574 /* keep the original lists and buffers */ 575 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n", 576 __func__); 577 goto free_all_new; 578 } 579 skb_reserve(rx_skbuff, NET_IP_ALIGN); 580 581 new_dma_addr_list[new] = 582 dma_map_single(&lp->pci_dev->dev, rx_skbuff->data, 583 PKT_BUF_SIZE, DMA_FROM_DEVICE); 584 if (dma_mapping_error(&lp->pci_dev->dev, new_dma_addr_list[new])) { 585 netif_err(lp, drv, dev, "%s dma mapping failed\n", 586 __func__); 587 dev_kfree_skb(new_skb_list[new]); 588 goto free_all_new; 589 } 590 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]); 591 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE); 592 new_rx_ring[new].status = cpu_to_le16(0x8000); 593 } 594 /* and free any unneeded buffers */ 595 for (; new < lp->rx_ring_size; new++) { 596 if (lp->rx_skbuff[new]) { 597 if (!dma_mapping_error(&lp->pci_dev->dev, lp->rx_dma_addr[new])) 598 dma_unmap_single(&lp->pci_dev->dev, 599 lp->rx_dma_addr[new], 600 PKT_BUF_SIZE, 601 DMA_FROM_DEVICE); 602 dev_kfree_skb(lp->rx_skbuff[new]); 603 } 604 } 605 606 kfree(lp->rx_skbuff); 607 kfree(lp->rx_dma_addr); 608 dma_free_coherent(&lp->pci_dev->dev, 609 sizeof(struct pcnet32_rx_head) * lp->rx_ring_size, 610 lp->rx_ring, lp->rx_ring_dma_addr); 611 612 lp->rx_ring_size = entries; 613 lp->rx_mod_mask = lp->rx_ring_size - 1; 614 lp->rx_len_bits = (size << 4); 615 lp->rx_ring = new_rx_ring; 616 lp->rx_ring_dma_addr = new_ring_dma_addr; 617 lp->rx_dma_addr = new_dma_addr_list; 618 lp->rx_skbuff = new_skb_list; 619 return; 620 621 free_all_new: 622 while (--new >= lp->rx_ring_size) { 623 if (new_skb_list[new]) { 624 if (!dma_mapping_error(&lp->pci_dev->dev, new_dma_addr_list[new])) 625 dma_unmap_single(&lp->pci_dev->dev, 626 new_dma_addr_list[new], 627 PKT_BUF_SIZE, 628 DMA_FROM_DEVICE); 629 dev_kfree_skb(new_skb_list[new]); 630 } 631 } 632 kfree(new_skb_list); 633 free_new_lists: 634 kfree(new_dma_addr_list); 635 free_new_rx_ring: 636 dma_free_coherent(&lp->pci_dev->dev, 637 sizeof(struct pcnet32_rx_head) * entries, 638 new_rx_ring, new_ring_dma_addr); 639 } 640 641 static void pcnet32_purge_rx_ring(struct net_device *dev) 642 { 643 struct pcnet32_private *lp = netdev_priv(dev); 644 int i; 645 646 /* free all allocated skbuffs */ 647 for (i = 0; i < lp->rx_ring_size; i++) { 648 lp->rx_ring[i].status = 0; /* CPU owns buffer */ 649 wmb(); /* Make sure adapter sees owner change */ 650 if (lp->rx_skbuff[i]) { 651 if (!dma_mapping_error(&lp->pci_dev->dev, lp->rx_dma_addr[i])) 652 dma_unmap_single(&lp->pci_dev->dev, 653 lp->rx_dma_addr[i], 654 PKT_BUF_SIZE, 655 DMA_FROM_DEVICE); 656 dev_kfree_skb_any(lp->rx_skbuff[i]); 657 } 658 lp->rx_skbuff[i] = NULL; 659 lp->rx_dma_addr[i] = 0; 660 } 661 } 662 663 #ifdef CONFIG_NET_POLL_CONTROLLER 664 static void pcnet32_poll_controller(struct net_device *dev) 665 { 666 disable_irq(dev->irq); 667 pcnet32_interrupt(0, dev); 668 enable_irq(dev->irq); 669 } 670 #endif 671 672 /* 673 * lp->lock must be held. 674 */ 675 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags, 676 int can_sleep) 677 { 678 int csr5; 679 struct pcnet32_private *lp = netdev_priv(dev); 680 const struct pcnet32_access *a = lp->a; 681 ulong ioaddr = dev->base_addr; 682 int ticks; 683 684 /* really old chips have to be stopped. */ 685 if (lp->chip_version < PCNET32_79C970A) 686 return 0; 687 688 /* set SUSPEND (SPND) - CSR5 bit 0 */ 689 csr5 = a->read_csr(ioaddr, CSR5); 690 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND); 691 692 /* poll waiting for bit to be set */ 693 ticks = 0; 694 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) { 695 spin_unlock_irqrestore(&lp->lock, *flags); 696 if (can_sleep) 697 msleep(1); 698 else 699 mdelay(1); 700 spin_lock_irqsave(&lp->lock, *flags); 701 ticks++; 702 if (ticks > 200) { 703 netif_printk(lp, hw, KERN_DEBUG, dev, 704 "Error getting into suspend!\n"); 705 return 0; 706 } 707 } 708 return 1; 709 } 710 711 static void pcnet32_clr_suspend(struct pcnet32_private *lp, ulong ioaddr) 712 { 713 int csr5 = lp->a->read_csr(ioaddr, CSR5); 714 /* clear SUSPEND (SPND) - CSR5 bit 0 */ 715 lp->a->write_csr(ioaddr, CSR5, csr5 & ~CSR5_SUSPEND); 716 } 717 718 static int pcnet32_get_link_ksettings(struct net_device *dev, 719 struct ethtool_link_ksettings *cmd) 720 { 721 struct pcnet32_private *lp = netdev_priv(dev); 722 unsigned long flags; 723 724 spin_lock_irqsave(&lp->lock, flags); 725 if (lp->mii) { 726 mii_ethtool_get_link_ksettings(&lp->mii_if, cmd); 727 } else if (lp->chip_version == PCNET32_79C970A) { 728 if (lp->autoneg) { 729 cmd->base.autoneg = AUTONEG_ENABLE; 730 if (lp->a->read_bcr(dev->base_addr, 4) == 0xc0) 731 cmd->base.port = PORT_AUI; 732 else 733 cmd->base.port = PORT_TP; 734 } else { 735 cmd->base.autoneg = AUTONEG_DISABLE; 736 cmd->base.port = lp->port_tp ? PORT_TP : PORT_AUI; 737 } 738 cmd->base.duplex = lp->fdx ? DUPLEX_FULL : DUPLEX_HALF; 739 cmd->base.speed = SPEED_10; 740 ethtool_convert_legacy_u32_to_link_mode( 741 cmd->link_modes.supported, 742 SUPPORTED_TP | SUPPORTED_AUI); 743 } 744 spin_unlock_irqrestore(&lp->lock, flags); 745 return 0; 746 } 747 748 static int pcnet32_set_link_ksettings(struct net_device *dev, 749 const struct ethtool_link_ksettings *cmd) 750 { 751 struct pcnet32_private *lp = netdev_priv(dev); 752 ulong ioaddr = dev->base_addr; 753 unsigned long flags; 754 int r = -EOPNOTSUPP; 755 int suspended, bcr2, bcr9, csr15; 756 757 spin_lock_irqsave(&lp->lock, flags); 758 if (lp->mii) { 759 r = mii_ethtool_set_link_ksettings(&lp->mii_if, cmd); 760 } else if (lp->chip_version == PCNET32_79C970A) { 761 suspended = pcnet32_suspend(dev, &flags, 0); 762 if (!suspended) 763 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); 764 765 lp->autoneg = cmd->base.autoneg == AUTONEG_ENABLE; 766 bcr2 = lp->a->read_bcr(ioaddr, 2); 767 if (cmd->base.autoneg == AUTONEG_ENABLE) { 768 lp->a->write_bcr(ioaddr, 2, bcr2 | 0x0002); 769 } else { 770 lp->a->write_bcr(ioaddr, 2, bcr2 & ~0x0002); 771 772 lp->port_tp = cmd->base.port == PORT_TP; 773 csr15 = lp->a->read_csr(ioaddr, CSR15) & ~0x0180; 774 if (cmd->base.port == PORT_TP) 775 csr15 |= 0x0080; 776 lp->a->write_csr(ioaddr, CSR15, csr15); 777 lp->init_block->mode = cpu_to_le16(csr15); 778 779 lp->fdx = cmd->base.duplex == DUPLEX_FULL; 780 bcr9 = lp->a->read_bcr(ioaddr, 9) & ~0x0003; 781 if (cmd->base.duplex == DUPLEX_FULL) 782 bcr9 |= 0x0003; 783 lp->a->write_bcr(ioaddr, 9, bcr9); 784 } 785 if (suspended) 786 pcnet32_clr_suspend(lp, ioaddr); 787 else if (netif_running(dev)) 788 pcnet32_restart(dev, CSR0_NORMAL); 789 r = 0; 790 } 791 spin_unlock_irqrestore(&lp->lock, flags); 792 return r; 793 } 794 795 static void pcnet32_get_drvinfo(struct net_device *dev, 796 struct ethtool_drvinfo *info) 797 { 798 struct pcnet32_private *lp = netdev_priv(dev); 799 800 strscpy(info->driver, DRV_NAME, sizeof(info->driver)); 801 if (lp->pci_dev) 802 strscpy(info->bus_info, pci_name(lp->pci_dev), 803 sizeof(info->bus_info)); 804 else 805 snprintf(info->bus_info, sizeof(info->bus_info), 806 "VLB 0x%lx", dev->base_addr); 807 } 808 809 static u32 pcnet32_get_link(struct net_device *dev) 810 { 811 struct pcnet32_private *lp = netdev_priv(dev); 812 unsigned long flags; 813 int r; 814 815 spin_lock_irqsave(&lp->lock, flags); 816 if (lp->mii) { 817 r = mii_link_ok(&lp->mii_if); 818 } else if (lp->chip_version == PCNET32_79C970A) { 819 ulong ioaddr = dev->base_addr; /* card base I/O address */ 820 /* only read link if port is set to TP */ 821 if (!lp->autoneg && lp->port_tp) 822 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0); 823 else /* link always up for AUI port or port auto select */ 824 r = 1; 825 } else if (lp->chip_version > PCNET32_79C970A) { 826 ulong ioaddr = dev->base_addr; /* card base I/O address */ 827 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0); 828 } else { /* can not detect link on really old chips */ 829 r = 1; 830 } 831 spin_unlock_irqrestore(&lp->lock, flags); 832 833 return r; 834 } 835 836 static u32 pcnet32_get_msglevel(struct net_device *dev) 837 { 838 struct pcnet32_private *lp = netdev_priv(dev); 839 return lp->msg_enable; 840 } 841 842 static void pcnet32_set_msglevel(struct net_device *dev, u32 value) 843 { 844 struct pcnet32_private *lp = netdev_priv(dev); 845 lp->msg_enable = value; 846 } 847 848 static int pcnet32_nway_reset(struct net_device *dev) 849 { 850 struct pcnet32_private *lp = netdev_priv(dev); 851 unsigned long flags; 852 int r = -EOPNOTSUPP; 853 854 if (lp->mii) { 855 spin_lock_irqsave(&lp->lock, flags); 856 r = mii_nway_restart(&lp->mii_if); 857 spin_unlock_irqrestore(&lp->lock, flags); 858 } 859 return r; 860 } 861 862 static void pcnet32_get_ringparam(struct net_device *dev, 863 struct ethtool_ringparam *ering, 864 struct kernel_ethtool_ringparam *kernel_ering, 865 struct netlink_ext_ack *extack) 866 { 867 struct pcnet32_private *lp = netdev_priv(dev); 868 869 ering->tx_max_pending = TX_MAX_RING_SIZE; 870 ering->tx_pending = lp->tx_ring_size; 871 ering->rx_max_pending = RX_MAX_RING_SIZE; 872 ering->rx_pending = lp->rx_ring_size; 873 } 874 875 static int pcnet32_set_ringparam(struct net_device *dev, 876 struct ethtool_ringparam *ering, 877 struct kernel_ethtool_ringparam *kernel_ering, 878 struct netlink_ext_ack *extack) 879 { 880 struct pcnet32_private *lp = netdev_priv(dev); 881 unsigned long flags; 882 unsigned int size; 883 ulong ioaddr = dev->base_addr; 884 int i; 885 886 if (ering->rx_mini_pending || ering->rx_jumbo_pending) 887 return -EINVAL; 888 889 if (netif_running(dev)) 890 pcnet32_netif_stop(dev); 891 892 netdev_lock(dev); 893 spin_lock_irqsave(&lp->lock, flags); 894 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ 895 896 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE); 897 898 /* set the minimum ring size to 4, to allow the loopback test to work 899 * unchanged. 900 */ 901 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) { 902 if (size <= (1 << i)) 903 break; 904 } 905 if ((1 << i) != lp->tx_ring_size) 906 pcnet32_realloc_tx_ring(dev, lp, i); 907 908 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE); 909 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) { 910 if (size <= (1 << i)) 911 break; 912 } 913 if ((1 << i) != lp->rx_ring_size) 914 pcnet32_realloc_rx_ring(dev, lp, i); 915 916 lp->napi.weight = lp->rx_ring_size / 2; 917 918 if (netif_running(dev)) { 919 pcnet32_netif_start(dev); 920 pcnet32_restart(dev, CSR0_NORMAL); 921 } 922 923 spin_unlock_irqrestore(&lp->lock, flags); 924 netdev_unlock(dev); 925 926 netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n", 927 lp->rx_ring_size, lp->tx_ring_size); 928 929 return 0; 930 } 931 932 static void pcnet32_get_strings(struct net_device *dev, u32 stringset, 933 u8 *data) 934 { 935 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test)); 936 } 937 938 static int pcnet32_get_sset_count(struct net_device *dev, int sset) 939 { 940 switch (sset) { 941 case ETH_SS_TEST: 942 return PCNET32_TEST_LEN; 943 default: 944 return -EOPNOTSUPP; 945 } 946 } 947 948 static void pcnet32_ethtool_test(struct net_device *dev, 949 struct ethtool_test *test, u64 * data) 950 { 951 struct pcnet32_private *lp = netdev_priv(dev); 952 int rc; 953 954 if (test->flags == ETH_TEST_FL_OFFLINE) { 955 rc = pcnet32_loopback_test(dev, data); 956 if (rc) { 957 netif_printk(lp, hw, KERN_DEBUG, dev, 958 "Loopback test failed\n"); 959 test->flags |= ETH_TEST_FL_FAILED; 960 } else 961 netif_printk(lp, hw, KERN_DEBUG, dev, 962 "Loopback test passed\n"); 963 } else 964 netif_printk(lp, hw, KERN_DEBUG, dev, 965 "No tests to run (specify 'Offline' on ethtool)\n"); 966 } /* end pcnet32_ethtool_test */ 967 968 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1) 969 { 970 struct pcnet32_private *lp = netdev_priv(dev); 971 const struct pcnet32_access *a = lp->a; /* access to registers */ 972 ulong ioaddr = dev->base_addr; /* card base I/O address */ 973 struct sk_buff *skb; /* sk buff */ 974 int x, i; /* counters */ 975 int numbuffs = 4; /* number of TX/RX buffers and descs */ 976 u16 status = 0x8300; /* TX ring status */ 977 __le16 teststatus; /* test of ring status */ 978 int rc; /* return code */ 979 int size; /* size of packets */ 980 unsigned char *packet; /* source packet data */ 981 static const int data_len = 60; /* length of source packets */ 982 unsigned long flags; 983 unsigned long ticks; 984 985 rc = 1; /* default to fail */ 986 987 if (netif_running(dev)) 988 pcnet32_netif_stop(dev); 989 990 netdev_lock(dev); 991 spin_lock_irqsave(&lp->lock, flags); 992 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ 993 994 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size)); 995 996 /* Reset the PCNET32 */ 997 lp->a->reset(ioaddr); 998 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ 999 1000 /* switch pcnet32 to 32bit mode */ 1001 lp->a->write_bcr(ioaddr, 20, 2); 1002 1003 /* purge & init rings but don't actually restart */ 1004 pcnet32_restart(dev, 0x0000); 1005 1006 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ 1007 1008 /* Initialize Transmit buffers. */ 1009 size = data_len + 15; 1010 for (x = 0; x < numbuffs; x++) { 1011 skb = netdev_alloc_skb(dev, size); 1012 if (!skb) { 1013 netif_printk(lp, hw, KERN_DEBUG, dev, 1014 "Cannot allocate skb at line: %d!\n", 1015 __LINE__); 1016 goto clean_up; 1017 } 1018 packet = skb->data; 1019 skb_put(skb, size); /* create space for data */ 1020 lp->tx_skbuff[x] = skb; 1021 lp->tx_ring[x].length = cpu_to_le16(-skb->len); 1022 lp->tx_ring[x].misc = 0; 1023 1024 /* put DA and SA into the skb */ 1025 for (i = 0; i < 6; i++) 1026 *packet++ = dev->dev_addr[i]; 1027 for (i = 0; i < 6; i++) 1028 *packet++ = dev->dev_addr[i]; 1029 /* type */ 1030 *packet++ = 0x08; 1031 *packet++ = 0x06; 1032 /* packet number */ 1033 *packet++ = x; 1034 /* fill packet with data */ 1035 for (i = 0; i < data_len; i++) 1036 *packet++ = i; 1037 1038 lp->tx_dma_addr[x] = 1039 dma_map_single(&lp->pci_dev->dev, skb->data, skb->len, 1040 DMA_TO_DEVICE); 1041 if (dma_mapping_error(&lp->pci_dev->dev, lp->tx_dma_addr[x])) { 1042 netif_printk(lp, hw, KERN_DEBUG, dev, 1043 "DMA mapping error at line: %d!\n", 1044 __LINE__); 1045 goto clean_up; 1046 } 1047 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]); 1048 wmb(); /* Make sure owner changes after all others are visible */ 1049 lp->tx_ring[x].status = cpu_to_le16(status); 1050 } 1051 1052 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */ 1053 a->write_bcr(ioaddr, 32, x | 0x0002); 1054 1055 /* set int loopback in CSR15 */ 1056 x = a->read_csr(ioaddr, CSR15) & 0xfffc; 1057 lp->a->write_csr(ioaddr, CSR15, x | 0x0044); 1058 1059 teststatus = cpu_to_le16(0x8000); 1060 lp->a->write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */ 1061 1062 /* Check status of descriptors */ 1063 for (x = 0; x < numbuffs; x++) { 1064 ticks = 0; 1065 rmb(); 1066 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) { 1067 spin_unlock_irqrestore(&lp->lock, flags); 1068 msleep(1); 1069 spin_lock_irqsave(&lp->lock, flags); 1070 rmb(); 1071 ticks++; 1072 } 1073 if (ticks == 200) { 1074 netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x); 1075 break; 1076 } 1077 } 1078 1079 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ 1080 wmb(); 1081 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) { 1082 netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n"); 1083 1084 for (x = 0; x < numbuffs; x++) { 1085 netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x); 1086 skb = lp->rx_skbuff[x]; 1087 for (i = 0; i < size; i++) 1088 pr_cont(" %02x", *(skb->data + i)); 1089 pr_cont("\n"); 1090 } 1091 } 1092 1093 x = 0; 1094 rc = 0; 1095 while (x < numbuffs && !rc) { 1096 skb = lp->rx_skbuff[x]; 1097 packet = lp->tx_skbuff[x]->data; 1098 for (i = 0; i < size; i++) { 1099 if (*(skb->data + i) != packet[i]) { 1100 netif_printk(lp, hw, KERN_DEBUG, dev, 1101 "Error in compare! %2x - %02x %02x\n", 1102 i, *(skb->data + i), packet[i]); 1103 rc = 1; 1104 break; 1105 } 1106 } 1107 x++; 1108 } 1109 1110 clean_up: 1111 *data1 = rc; 1112 pcnet32_purge_tx_ring(dev); 1113 1114 x = a->read_csr(ioaddr, CSR15); 1115 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */ 1116 1117 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */ 1118 a->write_bcr(ioaddr, 32, (x & ~0x0002)); 1119 1120 if (netif_running(dev)) { 1121 pcnet32_netif_start(dev); 1122 pcnet32_restart(dev, CSR0_NORMAL); 1123 } else { 1124 pcnet32_purge_rx_ring(dev); 1125 lp->a->write_bcr(ioaddr, 20, 4); /* return to 16bit mode */ 1126 } 1127 spin_unlock_irqrestore(&lp->lock, flags); 1128 netdev_unlock(dev); 1129 1130 return rc; 1131 } /* end pcnet32_loopback_test */ 1132 1133 static int pcnet32_set_phys_id(struct net_device *dev, 1134 enum ethtool_phys_id_state state) 1135 { 1136 struct pcnet32_private *lp = netdev_priv(dev); 1137 const struct pcnet32_access *a = lp->a; 1138 ulong ioaddr = dev->base_addr; 1139 unsigned long flags; 1140 int i; 1141 1142 switch (state) { 1143 case ETHTOOL_ID_ACTIVE: 1144 /* Save the current value of the bcrs */ 1145 spin_lock_irqsave(&lp->lock, flags); 1146 for (i = 4; i < 8; i++) 1147 lp->save_regs[i - 4] = a->read_bcr(ioaddr, i); 1148 spin_unlock_irqrestore(&lp->lock, flags); 1149 return 2; /* cycle on/off twice per second */ 1150 1151 case ETHTOOL_ID_ON: 1152 case ETHTOOL_ID_OFF: 1153 /* Blink the led */ 1154 spin_lock_irqsave(&lp->lock, flags); 1155 for (i = 4; i < 8; i++) 1156 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000); 1157 spin_unlock_irqrestore(&lp->lock, flags); 1158 break; 1159 1160 case ETHTOOL_ID_INACTIVE: 1161 /* Restore the original value of the bcrs */ 1162 spin_lock_irqsave(&lp->lock, flags); 1163 for (i = 4; i < 8; i++) 1164 a->write_bcr(ioaddr, i, lp->save_regs[i - 4]); 1165 spin_unlock_irqrestore(&lp->lock, flags); 1166 } 1167 return 0; 1168 } 1169 1170 /* 1171 * process one receive descriptor entry 1172 */ 1173 1174 static void pcnet32_rx_entry(struct net_device *dev, 1175 struct pcnet32_private *lp, 1176 struct pcnet32_rx_head *rxp, 1177 int entry) 1178 { 1179 int status = (short)le16_to_cpu(rxp->status) >> 8; 1180 int rx_in_place = 0; 1181 struct sk_buff *skb; 1182 short pkt_len; 1183 1184 if (status != 0x03) { /* There was an error. */ 1185 /* 1186 * There is a tricky error noted by John Murphy, 1187 * <murf@perftech.com> to Russ Nelson: Even with full-sized 1188 * buffers it's possible for a jabber packet to use two 1189 * buffers, with only the last correctly noting the error. 1190 */ 1191 if (status & 0x01) /* Only count a general error at the */ 1192 dev->stats.rx_errors++; /* end of a packet. */ 1193 if (status & 0x20) 1194 dev->stats.rx_frame_errors++; 1195 if (status & 0x10) 1196 dev->stats.rx_over_errors++; 1197 if (status & 0x08) 1198 dev->stats.rx_crc_errors++; 1199 if (status & 0x04) 1200 dev->stats.rx_fifo_errors++; 1201 return; 1202 } 1203 1204 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4; 1205 1206 /* Discard oversize frames. */ 1207 if (unlikely(pkt_len > PKT_BUF_SIZE)) { 1208 netif_err(lp, drv, dev, "Impossible packet size %d!\n", 1209 pkt_len); 1210 dev->stats.rx_errors++; 1211 return; 1212 } 1213 if (pkt_len < 60) { 1214 netif_err(lp, rx_err, dev, "Runt packet!\n"); 1215 dev->stats.rx_errors++; 1216 return; 1217 } 1218 1219 if (pkt_len > rx_copybreak) { 1220 struct sk_buff *newskb; 1221 dma_addr_t new_dma_addr; 1222 1223 newskb = netdev_alloc_skb(dev, PKT_BUF_SKB); 1224 /* 1225 * map the new buffer, if mapping fails, drop the packet and 1226 * reuse the old buffer 1227 */ 1228 if (newskb) { 1229 skb_reserve(newskb, NET_IP_ALIGN); 1230 new_dma_addr = dma_map_single(&lp->pci_dev->dev, 1231 newskb->data, 1232 PKT_BUF_SIZE, 1233 DMA_FROM_DEVICE); 1234 if (dma_mapping_error(&lp->pci_dev->dev, new_dma_addr)) { 1235 netif_err(lp, rx_err, dev, 1236 "DMA mapping error.\n"); 1237 dev_kfree_skb(newskb); 1238 skb = NULL; 1239 } else { 1240 skb = lp->rx_skbuff[entry]; 1241 dma_unmap_single(&lp->pci_dev->dev, 1242 lp->rx_dma_addr[entry], 1243 PKT_BUF_SIZE, 1244 DMA_FROM_DEVICE); 1245 skb_put(skb, pkt_len); 1246 lp->rx_skbuff[entry] = newskb; 1247 lp->rx_dma_addr[entry] = new_dma_addr; 1248 rxp->base = cpu_to_le32(new_dma_addr); 1249 rx_in_place = 1; 1250 } 1251 } else 1252 skb = NULL; 1253 } else 1254 skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN); 1255 1256 if (!skb) { 1257 dev->stats.rx_dropped++; 1258 return; 1259 } 1260 if (!rx_in_place) { 1261 skb_reserve(skb, NET_IP_ALIGN); 1262 skb_put(skb, pkt_len); /* Make room */ 1263 dma_sync_single_for_cpu(&lp->pci_dev->dev, 1264 lp->rx_dma_addr[entry], pkt_len, 1265 DMA_FROM_DEVICE); 1266 skb_copy_to_linear_data(skb, 1267 (unsigned char *)(lp->rx_skbuff[entry]->data), 1268 pkt_len); 1269 dma_sync_single_for_device(&lp->pci_dev->dev, 1270 lp->rx_dma_addr[entry], pkt_len, 1271 DMA_FROM_DEVICE); 1272 } 1273 dev->stats.rx_bytes += skb->len; 1274 skb->protocol = eth_type_trans(skb, dev); 1275 netif_receive_skb(skb); 1276 dev->stats.rx_packets++; 1277 } 1278 1279 static int pcnet32_rx(struct net_device *dev, int budget) 1280 { 1281 struct pcnet32_private *lp = netdev_priv(dev); 1282 int entry = lp->cur_rx & lp->rx_mod_mask; 1283 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry]; 1284 int npackets = 0; 1285 1286 /* If we own the next entry, it's a new packet. Send it up. */ 1287 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) { 1288 pcnet32_rx_entry(dev, lp, rxp, entry); 1289 npackets += 1; 1290 /* 1291 * The docs say that the buffer length isn't touched, but Andrew 1292 * Boyd of QNX reports that some revs of the 79C965 clear it. 1293 */ 1294 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE); 1295 wmb(); /* Make sure owner changes after others are visible */ 1296 rxp->status = cpu_to_le16(0x8000); 1297 entry = (++lp->cur_rx) & lp->rx_mod_mask; 1298 rxp = &lp->rx_ring[entry]; 1299 } 1300 1301 return npackets; 1302 } 1303 1304 static int pcnet32_tx(struct net_device *dev) 1305 { 1306 struct pcnet32_private *lp = netdev_priv(dev); 1307 unsigned int dirty_tx = lp->dirty_tx; 1308 int delta; 1309 int must_restart = 0; 1310 1311 while (dirty_tx != lp->cur_tx) { 1312 int entry = dirty_tx & lp->tx_mod_mask; 1313 int status = (short)le16_to_cpu(lp->tx_ring[entry].status); 1314 1315 if (status < 0) 1316 break; /* It still hasn't been Txed */ 1317 1318 lp->tx_ring[entry].base = 0; 1319 1320 if (status & 0x4000) { 1321 /* There was a major error, log it. */ 1322 int err_status = le32_to_cpu(lp->tx_ring[entry].misc); 1323 dev->stats.tx_errors++; 1324 netif_err(lp, tx_err, dev, 1325 "Tx error status=%04x err_status=%08x\n", 1326 status, err_status); 1327 if (err_status & 0x04000000) 1328 dev->stats.tx_aborted_errors++; 1329 if (err_status & 0x08000000) 1330 dev->stats.tx_carrier_errors++; 1331 if (err_status & 0x10000000) 1332 dev->stats.tx_window_errors++; 1333 #ifndef DO_DXSUFLO 1334 if (err_status & 0x40000000) { 1335 dev->stats.tx_fifo_errors++; 1336 /* Ackk! On FIFO errors the Tx unit is turned off! */ 1337 /* Remove this verbosity later! */ 1338 netif_err(lp, tx_err, dev, "Tx FIFO error!\n"); 1339 must_restart = 1; 1340 } 1341 #else 1342 if (err_status & 0x40000000) { 1343 dev->stats.tx_fifo_errors++; 1344 if (!lp->dxsuflo) { /* If controller doesn't recover ... */ 1345 /* Ackk! On FIFO errors the Tx unit is turned off! */ 1346 /* Remove this verbosity later! */ 1347 netif_err(lp, tx_err, dev, "Tx FIFO error!\n"); 1348 must_restart = 1; 1349 } 1350 } 1351 #endif 1352 } else { 1353 if (status & 0x1800) 1354 dev->stats.collisions++; 1355 dev->stats.tx_packets++; 1356 } 1357 1358 /* We must free the original skb */ 1359 if (lp->tx_skbuff[entry]) { 1360 dma_unmap_single(&lp->pci_dev->dev, 1361 lp->tx_dma_addr[entry], 1362 lp->tx_skbuff[entry]->len, 1363 DMA_TO_DEVICE); 1364 dev_kfree_skb_any(lp->tx_skbuff[entry]); 1365 lp->tx_skbuff[entry] = NULL; 1366 lp->tx_dma_addr[entry] = 0; 1367 } 1368 dirty_tx++; 1369 } 1370 1371 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size); 1372 if (delta > lp->tx_ring_size) { 1373 netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n", 1374 dirty_tx, lp->cur_tx, lp->tx_full); 1375 dirty_tx += lp->tx_ring_size; 1376 delta -= lp->tx_ring_size; 1377 } 1378 1379 if (lp->tx_full && 1380 netif_queue_stopped(dev) && 1381 delta < lp->tx_ring_size - 2) { 1382 /* The ring is no longer full, clear tbusy. */ 1383 lp->tx_full = 0; 1384 netif_wake_queue(dev); 1385 } 1386 lp->dirty_tx = dirty_tx; 1387 1388 return must_restart; 1389 } 1390 1391 static int pcnet32_poll(struct napi_struct *napi, int budget) 1392 { 1393 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi); 1394 struct net_device *dev = lp->dev; 1395 unsigned long ioaddr = dev->base_addr; 1396 unsigned long flags; 1397 int work_done; 1398 u16 val; 1399 1400 work_done = pcnet32_rx(dev, budget); 1401 1402 spin_lock_irqsave(&lp->lock, flags); 1403 if (pcnet32_tx(dev)) { 1404 /* reset the chip to clear the error condition, then restart */ 1405 lp->a->reset(ioaddr); 1406 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ 1407 pcnet32_restart(dev, CSR0_START); 1408 netif_wake_queue(dev); 1409 } 1410 1411 if (work_done < budget && napi_complete_done(napi, work_done)) { 1412 /* clear interrupt masks */ 1413 val = lp->a->read_csr(ioaddr, CSR3); 1414 val &= 0x00ff; 1415 lp->a->write_csr(ioaddr, CSR3, val); 1416 1417 /* Set interrupt enable. */ 1418 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN); 1419 } 1420 1421 spin_unlock_irqrestore(&lp->lock, flags); 1422 return work_done; 1423 } 1424 1425 #define PCNET32_REGS_PER_PHY 32 1426 #define PCNET32_MAX_PHYS 32 1427 static int pcnet32_get_regs_len(struct net_device *dev) 1428 { 1429 struct pcnet32_private *lp = netdev_priv(dev); 1430 int j = lp->phycount * PCNET32_REGS_PER_PHY; 1431 1432 return (PCNET32_NUM_REGS + j) * sizeof(u16); 1433 } 1434 1435 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1436 void *ptr) 1437 { 1438 int i, csr0; 1439 u16 *buff = ptr; 1440 struct pcnet32_private *lp = netdev_priv(dev); 1441 const struct pcnet32_access *a = lp->a; 1442 ulong ioaddr = dev->base_addr; 1443 unsigned long flags; 1444 1445 spin_lock_irqsave(&lp->lock, flags); 1446 1447 csr0 = a->read_csr(ioaddr, CSR0); 1448 if (!(csr0 & CSR0_STOP)) /* If not stopped */ 1449 pcnet32_suspend(dev, &flags, 1); 1450 1451 /* read address PROM */ 1452 for (i = 0; i < 16; i += 2) 1453 *buff++ = inw(ioaddr + i); 1454 1455 /* read control and status registers */ 1456 for (i = 0; i < 90; i++) 1457 *buff++ = a->read_csr(ioaddr, i); 1458 1459 *buff++ = a->read_csr(ioaddr, 112); 1460 *buff++ = a->read_csr(ioaddr, 114); 1461 1462 /* read bus configuration registers */ 1463 for (i = 0; i < 30; i++) 1464 *buff++ = a->read_bcr(ioaddr, i); 1465 1466 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */ 1467 1468 for (i = 31; i < 36; i++) 1469 *buff++ = a->read_bcr(ioaddr, i); 1470 1471 /* read mii phy registers */ 1472 if (lp->mii) { 1473 int j; 1474 for (j = 0; j < PCNET32_MAX_PHYS; j++) { 1475 if (lp->phymask & (1 << j)) { 1476 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) { 1477 lp->a->write_bcr(ioaddr, 33, 1478 (j << 5) | i); 1479 *buff++ = lp->a->read_bcr(ioaddr, 34); 1480 } 1481 } 1482 } 1483 } 1484 1485 if (!(csr0 & CSR0_STOP)) /* If not stopped */ 1486 pcnet32_clr_suspend(lp, ioaddr); 1487 1488 spin_unlock_irqrestore(&lp->lock, flags); 1489 } 1490 1491 static const struct ethtool_ops pcnet32_ethtool_ops = { 1492 .get_drvinfo = pcnet32_get_drvinfo, 1493 .get_msglevel = pcnet32_get_msglevel, 1494 .set_msglevel = pcnet32_set_msglevel, 1495 .nway_reset = pcnet32_nway_reset, 1496 .get_link = pcnet32_get_link, 1497 .get_ringparam = pcnet32_get_ringparam, 1498 .set_ringparam = pcnet32_set_ringparam, 1499 .get_strings = pcnet32_get_strings, 1500 .self_test = pcnet32_ethtool_test, 1501 .set_phys_id = pcnet32_set_phys_id, 1502 .get_regs_len = pcnet32_get_regs_len, 1503 .get_regs = pcnet32_get_regs, 1504 .get_sset_count = pcnet32_get_sset_count, 1505 .get_link_ksettings = pcnet32_get_link_ksettings, 1506 .set_link_ksettings = pcnet32_set_link_ksettings, 1507 }; 1508 1509 /* only probes for non-PCI devices, the rest are handled by 1510 * pci_register_driver via pcnet32_probe_pci */ 1511 1512 static void pcnet32_probe_vlbus(unsigned int *pcnet32_portlist) 1513 { 1514 unsigned int *port, ioaddr; 1515 1516 /* search for PCnet32 VLB cards at known addresses */ 1517 for (port = pcnet32_portlist; (ioaddr = *port); port++) { 1518 if (request_region 1519 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) { 1520 /* check if there is really a pcnet chip on that ioaddr */ 1521 if ((inb(ioaddr + 14) == 0x57) && 1522 (inb(ioaddr + 15) == 0x57)) { 1523 pcnet32_probe1(ioaddr, 0, NULL); 1524 } else { 1525 release_region(ioaddr, PCNET32_TOTAL_SIZE); 1526 } 1527 } 1528 } 1529 } 1530 1531 static int 1532 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent) 1533 { 1534 unsigned long ioaddr; 1535 int err; 1536 1537 err = pci_enable_device(pdev); 1538 if (err < 0) { 1539 if (pcnet32_debug & NETIF_MSG_PROBE) 1540 pr_err("failed to enable device -- err=%d\n", err); 1541 return err; 1542 } 1543 pci_set_master(pdev); 1544 1545 if (!pci_resource_len(pdev, 0)) { 1546 if (pcnet32_debug & NETIF_MSG_PROBE) 1547 pr_err("card has no PCI IO resources, aborting\n"); 1548 err = -ENODEV; 1549 goto err_disable_dev; 1550 } 1551 1552 err = dma_set_mask(&pdev->dev, PCNET32_DMA_MASK); 1553 if (err) { 1554 if (pcnet32_debug & NETIF_MSG_PROBE) 1555 pr_err("architecture does not support 32bit PCI busmaster DMA\n"); 1556 goto err_disable_dev; 1557 } 1558 1559 ioaddr = pci_resource_start(pdev, 0); 1560 if (!request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci")) { 1561 if (pcnet32_debug & NETIF_MSG_PROBE) 1562 pr_err("io address range already allocated\n"); 1563 err = -EBUSY; 1564 goto err_disable_dev; 1565 } 1566 1567 err = pcnet32_probe1(ioaddr, 1, pdev); 1568 1569 err_disable_dev: 1570 if (err < 0) 1571 pci_disable_device(pdev); 1572 1573 return err; 1574 } 1575 1576 static const struct net_device_ops pcnet32_netdev_ops = { 1577 .ndo_open = pcnet32_open, 1578 .ndo_stop = pcnet32_close, 1579 .ndo_start_xmit = pcnet32_start_xmit, 1580 .ndo_tx_timeout = pcnet32_tx_timeout, 1581 .ndo_get_stats = pcnet32_get_stats, 1582 .ndo_set_rx_mode = pcnet32_set_multicast_list, 1583 .ndo_eth_ioctl = pcnet32_ioctl, 1584 .ndo_set_mac_address = eth_mac_addr, 1585 .ndo_validate_addr = eth_validate_addr, 1586 #ifdef CONFIG_NET_POLL_CONTROLLER 1587 .ndo_poll_controller = pcnet32_poll_controller, 1588 #endif 1589 }; 1590 1591 /* pcnet32_probe1 1592 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci. 1593 * pdev will be NULL when called from pcnet32_probe_vlbus. 1594 */ 1595 static int 1596 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev) 1597 { 1598 struct pcnet32_private *lp; 1599 int i, media; 1600 int fdx, mii, fset, dxsuflo, sram; 1601 int chip_version; 1602 char *chipname; 1603 struct net_device *dev; 1604 const struct pcnet32_access *a = NULL; 1605 u8 promaddr[ETH_ALEN]; 1606 u8 addr[ETH_ALEN]; 1607 int ret = -ENODEV; 1608 1609 /* reset the chip */ 1610 pcnet32_wio_reset(ioaddr); 1611 1612 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */ 1613 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) { 1614 a = &pcnet32_wio; 1615 } else { 1616 pcnet32_dwio_reset(ioaddr); 1617 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 && 1618 pcnet32_dwio_check(ioaddr)) { 1619 a = &pcnet32_dwio; 1620 } else { 1621 if (pcnet32_debug & NETIF_MSG_PROBE) 1622 pr_err("No access methods\n"); 1623 goto err_release_region; 1624 } 1625 } 1626 1627 chip_version = 1628 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16); 1629 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW)) 1630 pr_info(" PCnet chip version is %#x\n", chip_version); 1631 if ((chip_version & 0xfff) != 0x003) { 1632 if (pcnet32_debug & NETIF_MSG_PROBE) 1633 pr_info("Unsupported chip version\n"); 1634 goto err_release_region; 1635 } 1636 1637 /* initialize variables */ 1638 fdx = mii = fset = dxsuflo = sram = 0; 1639 chip_version = (chip_version >> 12) & 0xffff; 1640 1641 switch (chip_version) { 1642 case 0x2420: 1643 chipname = "PCnet/PCI 79C970"; /* PCI */ 1644 break; 1645 case 0x2430: 1646 if (shared) 1647 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */ 1648 else 1649 chipname = "PCnet/32 79C965"; /* 486/VL bus */ 1650 break; 1651 case 0x2621: 1652 chipname = "PCnet/PCI II 79C970A"; /* PCI */ 1653 fdx = 1; 1654 break; 1655 case 0x2623: 1656 chipname = "PCnet/FAST 79C971"; /* PCI */ 1657 fdx = 1; 1658 mii = 1; 1659 fset = 1; 1660 break; 1661 case 0x2624: 1662 chipname = "PCnet/FAST+ 79C972"; /* PCI */ 1663 fdx = 1; 1664 mii = 1; 1665 fset = 1; 1666 break; 1667 case 0x2625: 1668 chipname = "PCnet/FAST III 79C973"; /* PCI */ 1669 fdx = 1; 1670 mii = 1; 1671 sram = 1; 1672 break; 1673 case 0x2626: 1674 chipname = "PCnet/Home 79C978"; /* PCI */ 1675 fdx = 1; 1676 /* 1677 * This is based on specs published at www.amd.com. This section 1678 * assumes that a card with a 79C978 wants to go into standard 1679 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode, 1680 * and the module option homepna=1 can select this instead. 1681 */ 1682 media = a->read_bcr(ioaddr, 49); 1683 media &= ~3; /* default to 10Mb ethernet */ 1684 if (cards_found < MAX_UNITS && homepna[cards_found]) 1685 media |= 1; /* switch to home wiring mode */ 1686 if (pcnet32_debug & NETIF_MSG_PROBE) 1687 printk(KERN_DEBUG PFX "media set to %sMbit mode\n", 1688 (media & 1) ? "1" : "10"); 1689 a->write_bcr(ioaddr, 49, media); 1690 break; 1691 case 0x2627: 1692 chipname = "PCnet/FAST III 79C975"; /* PCI */ 1693 fdx = 1; 1694 mii = 1; 1695 sram = 1; 1696 break; 1697 case 0x2628: 1698 chipname = "PCnet/PRO 79C976"; 1699 fdx = 1; 1700 mii = 1; 1701 break; 1702 default: 1703 if (pcnet32_debug & NETIF_MSG_PROBE) 1704 pr_info("PCnet version %#x, no PCnet32 chip\n", 1705 chip_version); 1706 goto err_release_region; 1707 } 1708 1709 /* 1710 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit 1711 * starting until the packet is loaded. Strike one for reliability, lose 1712 * one for latency - although on PCI this isn't a big loss. Older chips 1713 * have FIFO's smaller than a packet, so you can't do this. 1714 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn. 1715 */ 1716 1717 if (fset) { 1718 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860)); 1719 a->write_csr(ioaddr, 80, 1720 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00); 1721 dxsuflo = 1; 1722 } 1723 1724 /* 1725 * The Am79C973/Am79C975 controllers come with 12K of SRAM 1726 * which we can use for the Tx/Rx buffers but most importantly, 1727 * the use of SRAM allow us to use the BCR18:NOUFLO bit to avoid 1728 * Tx fifo underflows. 1729 */ 1730 if (sram) { 1731 /* 1732 * The SRAM is being configured in two steps. First we 1733 * set the SRAM size in the BCR25:SRAM_SIZE bits. According 1734 * to the datasheet, each bit corresponds to a 512-byte 1735 * page so we can have at most 24 pages. The SRAM_SIZE 1736 * holds the value of the upper 8 bits of the 16-bit SRAM size. 1737 * The low 8-bits start at 0x00 and end at 0xff. So the 1738 * address range is from 0x0000 up to 0x17ff. Therefore, 1739 * the SRAM_SIZE is set to 0x17. The next step is to set 1740 * the BCR26:SRAM_BND midway through so the Tx and Rx 1741 * buffers can share the SRAM equally. 1742 */ 1743 a->write_bcr(ioaddr, 25, 0x17); 1744 a->write_bcr(ioaddr, 26, 0xc); 1745 /* And finally enable the NOUFLO bit */ 1746 a->write_bcr(ioaddr, 18, a->read_bcr(ioaddr, 18) | (1 << 11)); 1747 } 1748 1749 dev = alloc_etherdev(sizeof(*lp)); 1750 if (!dev) { 1751 ret = -ENOMEM; 1752 goto err_release_region; 1753 } 1754 1755 if (pdev) 1756 SET_NETDEV_DEV(dev, &pdev->dev); 1757 1758 if (pcnet32_debug & NETIF_MSG_PROBE) 1759 pr_info("%s at %#3lx,", chipname, ioaddr); 1760 1761 /* In most chips, after a chip reset, the ethernet address is read from the 1762 * station address PROM at the base address and programmed into the 1763 * "Physical Address Registers" CSR12-14. 1764 * As a precautionary measure, we read the PROM values and complain if 1765 * they disagree with the CSRs. If they miscompare, and the PROM addr 1766 * is valid, then the PROM addr is used. 1767 */ 1768 for (i = 0; i < 3; i++) { 1769 unsigned int val; 1770 val = a->read_csr(ioaddr, i + 12) & 0x0ffff; 1771 /* There may be endianness issues here. */ 1772 addr[2 * i] = val & 0x0ff; 1773 addr[2 * i + 1] = (val >> 8) & 0x0ff; 1774 } 1775 eth_hw_addr_set(dev, addr); 1776 1777 /* read PROM address and compare with CSR address */ 1778 for (i = 0; i < ETH_ALEN; i++) 1779 promaddr[i] = inb(ioaddr + i); 1780 1781 if (!ether_addr_equal(promaddr, dev->dev_addr) || 1782 !is_valid_ether_addr(dev->dev_addr)) { 1783 if (is_valid_ether_addr(promaddr)) { 1784 if (pcnet32_debug & NETIF_MSG_PROBE) { 1785 pr_cont(" warning: CSR address invalid,\n"); 1786 pr_info(" using instead PROM address of"); 1787 } 1788 eth_hw_addr_set(dev, promaddr); 1789 } 1790 } 1791 1792 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */ 1793 if (!is_valid_ether_addr(dev->dev_addr)) { 1794 static const u8 zero_addr[ETH_ALEN] = {}; 1795 1796 eth_hw_addr_set(dev, zero_addr); 1797 } 1798 1799 if (pcnet32_debug & NETIF_MSG_PROBE) { 1800 pr_cont(" %pM", dev->dev_addr); 1801 1802 /* Version 0x2623 and 0x2624 */ 1803 if (((chip_version + 1) & 0xfffe) == 0x2624) { 1804 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */ 1805 pr_info(" tx_start_pt(0x%04x):", i); 1806 switch (i >> 10) { 1807 case 0: 1808 pr_cont(" 20 bytes,"); 1809 break; 1810 case 1: 1811 pr_cont(" 64 bytes,"); 1812 break; 1813 case 2: 1814 pr_cont(" 128 bytes,"); 1815 break; 1816 case 3: 1817 pr_cont("~220 bytes,"); 1818 break; 1819 } 1820 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */ 1821 pr_cont(" BCR18(%x):", i & 0xffff); 1822 if (i & (1 << 5)) 1823 pr_cont("BurstWrEn "); 1824 if (i & (1 << 6)) 1825 pr_cont("BurstRdEn "); 1826 if (i & (1 << 7)) 1827 pr_cont("DWordIO "); 1828 if (i & (1 << 11)) 1829 pr_cont("NoUFlow "); 1830 i = a->read_bcr(ioaddr, 25); 1831 pr_info(" SRAMSIZE=0x%04x,", i << 8); 1832 i = a->read_bcr(ioaddr, 26); 1833 pr_cont(" SRAM_BND=0x%04x,", i << 8); 1834 i = a->read_bcr(ioaddr, 27); 1835 if (i & (1 << 14)) 1836 pr_cont("LowLatRx"); 1837 } 1838 } 1839 1840 dev->base_addr = ioaddr; 1841 lp = netdev_priv(dev); 1842 /* dma_alloc_coherent returns page-aligned memory, so we do not have to check the alignment */ 1843 lp->init_block = dma_alloc_coherent(&pdev->dev, 1844 sizeof(*lp->init_block), 1845 &lp->init_dma_addr, GFP_KERNEL); 1846 if (!lp->init_block) { 1847 if (pcnet32_debug & NETIF_MSG_PROBE) 1848 pr_err("Coherent memory allocation failed\n"); 1849 ret = -ENOMEM; 1850 goto err_free_netdev; 1851 } 1852 lp->pci_dev = pdev; 1853 1854 lp->dev = dev; 1855 1856 spin_lock_init(&lp->lock); 1857 1858 lp->name = chipname; 1859 lp->shared_irq = shared; 1860 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */ 1861 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */ 1862 lp->tx_mod_mask = lp->tx_ring_size - 1; 1863 lp->rx_mod_mask = lp->rx_ring_size - 1; 1864 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12); 1865 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4); 1866 lp->mii_if.full_duplex = fdx; 1867 lp->mii_if.phy_id_mask = 0x1f; 1868 lp->mii_if.reg_num_mask = 0x1f; 1869 lp->dxsuflo = dxsuflo; 1870 lp->mii = mii; 1871 lp->chip_version = chip_version; 1872 lp->msg_enable = pcnet32_debug; 1873 if ((cards_found >= MAX_UNITS) || 1874 (options[cards_found] >= sizeof(options_mapping))) 1875 lp->options = PCNET32_PORT_ASEL; 1876 else 1877 lp->options = options_mapping[options[cards_found]]; 1878 /* force default port to TP on 79C970A so link detection can work */ 1879 if (lp->chip_version == PCNET32_79C970A) 1880 lp->options = PCNET32_PORT_10BT; 1881 lp->mii_if.dev = dev; 1882 lp->mii_if.mdio_read = mdio_read; 1883 lp->mii_if.mdio_write = mdio_write; 1884 1885 /* napi.weight is used in both the napi and non-napi cases */ 1886 lp->napi.weight = lp->rx_ring_size / 2; 1887 1888 netif_napi_add_weight(dev, &lp->napi, pcnet32_poll, 1889 lp->rx_ring_size / 2); 1890 1891 if (fdx && !(lp->options & PCNET32_PORT_ASEL) && 1892 ((cards_found >= MAX_UNITS) || full_duplex[cards_found])) 1893 lp->options |= PCNET32_PORT_FD; 1894 1895 lp->a = a; 1896 1897 /* prior to register_netdev, dev->name is not yet correct */ 1898 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) { 1899 ret = -ENOMEM; 1900 goto err_free_ring; 1901 } 1902 /* detect special T1/E1 WAN card by checking for MAC address */ 1903 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 && 1904 dev->dev_addr[2] == 0x75) 1905 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI; 1906 1907 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */ 1908 lp->init_block->tlen_rlen = 1909 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits); 1910 for (i = 0; i < 6; i++) 1911 lp->init_block->phys_addr[i] = dev->dev_addr[i]; 1912 lp->init_block->filter[0] = 0x00000000; 1913 lp->init_block->filter[1] = 0x00000000; 1914 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr); 1915 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr); 1916 1917 /* switch pcnet32 to 32bit mode */ 1918 a->write_bcr(ioaddr, 20, 2); 1919 1920 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff)); 1921 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16)); 1922 1923 if (pdev) { /* use the IRQ provided by PCI */ 1924 dev->irq = pdev->irq; 1925 if (pcnet32_debug & NETIF_MSG_PROBE) 1926 pr_cont(" assigned IRQ %d\n", dev->irq); 1927 } else { 1928 unsigned long irq_mask = probe_irq_on(); 1929 1930 /* 1931 * To auto-IRQ we enable the initialization-done and DMA error 1932 * interrupts. For ISA boards we get a DMA error, but VLB and PCI 1933 * boards will work. 1934 */ 1935 /* Trigger an initialization just for the interrupt. */ 1936 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT); 1937 mdelay(1); 1938 1939 dev->irq = probe_irq_off(irq_mask); 1940 if (!dev->irq) { 1941 if (pcnet32_debug & NETIF_MSG_PROBE) 1942 pr_cont(", failed to detect IRQ line\n"); 1943 ret = -ENODEV; 1944 goto err_free_ring; 1945 } 1946 if (pcnet32_debug & NETIF_MSG_PROBE) 1947 pr_cont(", probed IRQ %d\n", dev->irq); 1948 } 1949 1950 /* Set the mii phy_id so that we can query the link state */ 1951 if (lp->mii) { 1952 /* lp->phycount and lp->phymask are set to 0 by memset above */ 1953 1954 lp->mii_if.phy_id = ((lp->a->read_bcr(ioaddr, 33)) >> 5) & 0x1f; 1955 /* scan for PHYs */ 1956 for (i = 0; i < PCNET32_MAX_PHYS; i++) { 1957 unsigned short id1, id2; 1958 1959 id1 = mdio_read(dev, i, MII_PHYSID1); 1960 if (id1 == 0xffff) 1961 continue; 1962 id2 = mdio_read(dev, i, MII_PHYSID2); 1963 if (id2 == 0xffff) 1964 continue; 1965 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624) 1966 continue; /* 79C971 & 79C972 have phantom phy at id 31 */ 1967 lp->phycount++; 1968 lp->phymask |= (1 << i); 1969 lp->mii_if.phy_id = i; 1970 if (pcnet32_debug & NETIF_MSG_PROBE) 1971 pr_info("Found PHY %04x:%04x at address %d\n", 1972 id1, id2, i); 1973 } 1974 lp->a->write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5); 1975 if (lp->phycount > 1) 1976 lp->options |= PCNET32_PORT_MII; 1977 } 1978 1979 timer_setup(&lp->watchdog_timer, pcnet32_watchdog, 0); 1980 1981 /* The PCNET32-specific entries in the device structure. */ 1982 dev->netdev_ops = &pcnet32_netdev_ops; 1983 dev->ethtool_ops = &pcnet32_ethtool_ops; 1984 dev->watchdog_timeo = (5 * HZ); 1985 1986 /* Fill in the generic fields of the device structure. */ 1987 if (register_netdev(dev)) 1988 goto err_free_ring; 1989 1990 if (pdev) { 1991 pci_set_drvdata(pdev, dev); 1992 } else { 1993 lp->next = pcnet32_dev; 1994 pcnet32_dev = dev; 1995 } 1996 1997 if (pcnet32_debug & NETIF_MSG_PROBE) 1998 pr_info("%s: registered as %s\n", dev->name, lp->name); 1999 cards_found++; 2000 2001 /* enable LED writes */ 2002 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000); 2003 2004 return 0; 2005 2006 err_free_ring: 2007 pcnet32_free_ring(dev); 2008 dma_free_coherent(&lp->pci_dev->dev, sizeof(*lp->init_block), 2009 lp->init_block, lp->init_dma_addr); 2010 err_free_netdev: 2011 free_netdev(dev); 2012 err_release_region: 2013 release_region(ioaddr, PCNET32_TOTAL_SIZE); 2014 return ret; 2015 } 2016 2017 /* if any allocation fails, caller must also call pcnet32_free_ring */ 2018 static int pcnet32_alloc_ring(struct net_device *dev, const char *name) 2019 { 2020 struct pcnet32_private *lp = netdev_priv(dev); 2021 2022 lp->tx_ring = dma_alloc_coherent(&lp->pci_dev->dev, 2023 sizeof(struct pcnet32_tx_head) * lp->tx_ring_size, 2024 &lp->tx_ring_dma_addr, GFP_KERNEL); 2025 if (!lp->tx_ring) { 2026 netif_err(lp, drv, dev, "Coherent memory allocation failed\n"); 2027 return -ENOMEM; 2028 } 2029 2030 lp->rx_ring = dma_alloc_coherent(&lp->pci_dev->dev, 2031 sizeof(struct pcnet32_rx_head) * lp->rx_ring_size, 2032 &lp->rx_ring_dma_addr, GFP_KERNEL); 2033 if (!lp->rx_ring) { 2034 netif_err(lp, drv, dev, "Coherent memory allocation failed\n"); 2035 return -ENOMEM; 2036 } 2037 2038 lp->tx_dma_addr = kzalloc_objs(dma_addr_t, lp->tx_ring_size, GFP_KERNEL); 2039 if (!lp->tx_dma_addr) 2040 return -ENOMEM; 2041 2042 lp->rx_dma_addr = kzalloc_objs(dma_addr_t, lp->rx_ring_size, GFP_KERNEL); 2043 if (!lp->rx_dma_addr) 2044 return -ENOMEM; 2045 2046 lp->tx_skbuff = kzalloc_objs(struct sk_buff *, lp->tx_ring_size, 2047 GFP_KERNEL); 2048 if (!lp->tx_skbuff) 2049 return -ENOMEM; 2050 2051 lp->rx_skbuff = kzalloc_objs(struct sk_buff *, lp->rx_ring_size, 2052 GFP_KERNEL); 2053 if (!lp->rx_skbuff) 2054 return -ENOMEM; 2055 2056 return 0; 2057 } 2058 2059 static void pcnet32_free_ring(struct net_device *dev) 2060 { 2061 struct pcnet32_private *lp = netdev_priv(dev); 2062 2063 kfree(lp->tx_skbuff); 2064 lp->tx_skbuff = NULL; 2065 2066 kfree(lp->rx_skbuff); 2067 lp->rx_skbuff = NULL; 2068 2069 kfree(lp->tx_dma_addr); 2070 lp->tx_dma_addr = NULL; 2071 2072 kfree(lp->rx_dma_addr); 2073 lp->rx_dma_addr = NULL; 2074 2075 if (lp->tx_ring) { 2076 dma_free_coherent(&lp->pci_dev->dev, 2077 sizeof(struct pcnet32_tx_head) * lp->tx_ring_size, 2078 lp->tx_ring, lp->tx_ring_dma_addr); 2079 lp->tx_ring = NULL; 2080 } 2081 2082 if (lp->rx_ring) { 2083 dma_free_coherent(&lp->pci_dev->dev, 2084 sizeof(struct pcnet32_rx_head) * lp->rx_ring_size, 2085 lp->rx_ring, lp->rx_ring_dma_addr); 2086 lp->rx_ring = NULL; 2087 } 2088 } 2089 2090 static int pcnet32_open(struct net_device *dev) 2091 { 2092 struct pcnet32_private *lp = netdev_priv(dev); 2093 struct pci_dev *pdev = lp->pci_dev; 2094 unsigned long ioaddr = dev->base_addr; 2095 u16 val; 2096 int i; 2097 int rc; 2098 unsigned long flags; 2099 2100 if (request_irq(dev->irq, pcnet32_interrupt, 2101 lp->shared_irq ? IRQF_SHARED : 0, dev->name, 2102 (void *)dev)) { 2103 return -EAGAIN; 2104 } 2105 2106 netdev_lock(dev); 2107 spin_lock_irqsave(&lp->lock, flags); 2108 /* Check for a valid station address */ 2109 if (!is_valid_ether_addr(dev->dev_addr)) { 2110 rc = -EINVAL; 2111 goto err_free_irq; 2112 } 2113 2114 /* Reset the PCNET32 */ 2115 lp->a->reset(ioaddr); 2116 2117 /* switch pcnet32 to 32bit mode */ 2118 lp->a->write_bcr(ioaddr, 20, 2); 2119 2120 netif_printk(lp, ifup, KERN_DEBUG, dev, 2121 "%s() irq %d tx/rx rings %#x/%#x init %#x\n", 2122 __func__, dev->irq, (u32) (lp->tx_ring_dma_addr), 2123 (u32) (lp->rx_ring_dma_addr), 2124 (u32) (lp->init_dma_addr)); 2125 2126 lp->autoneg = !!(lp->options & PCNET32_PORT_ASEL); 2127 lp->port_tp = !!(lp->options & PCNET32_PORT_10BT); 2128 lp->fdx = !!(lp->options & PCNET32_PORT_FD); 2129 2130 /* set/reset autoselect bit */ 2131 val = lp->a->read_bcr(ioaddr, 2) & ~2; 2132 if (lp->options & PCNET32_PORT_ASEL) 2133 val |= 2; 2134 lp->a->write_bcr(ioaddr, 2, val); 2135 2136 /* handle full duplex setting */ 2137 if (lp->mii_if.full_duplex) { 2138 val = lp->a->read_bcr(ioaddr, 9) & ~3; 2139 if (lp->options & PCNET32_PORT_FD) { 2140 val |= 1; 2141 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI)) 2142 val |= 2; 2143 } else if (lp->options & PCNET32_PORT_ASEL) { 2144 /* workaround of xSeries250, turn on for 79C975 only */ 2145 if (lp->chip_version == 0x2627) 2146 val |= 3; 2147 } 2148 lp->a->write_bcr(ioaddr, 9, val); 2149 } 2150 2151 /* set/reset GPSI bit in test register */ 2152 val = lp->a->read_csr(ioaddr, 124) & ~0x10; 2153 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI) 2154 val |= 0x10; 2155 lp->a->write_csr(ioaddr, 124, val); 2156 2157 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */ 2158 if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT && 2159 (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX || 2160 pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) { 2161 if (lp->options & PCNET32_PORT_ASEL) { 2162 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100; 2163 netif_printk(lp, link, KERN_DEBUG, dev, 2164 "Setting 100Mb-Full Duplex\n"); 2165 } 2166 } 2167 if (lp->phycount < 2) { 2168 /* 2169 * 24 Jun 2004 according AMD, in order to change the PHY, 2170 * DANAS (or DISPM for 79C976) must be set; then select the speed, 2171 * duplex, and/or enable auto negotiation, and clear DANAS 2172 */ 2173 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) { 2174 lp->a->write_bcr(ioaddr, 32, 2175 lp->a->read_bcr(ioaddr, 32) | 0x0080); 2176 /* disable Auto Negotiation, set 10Mpbs, HD */ 2177 val = lp->a->read_bcr(ioaddr, 32) & ~0xb8; 2178 if (lp->options & PCNET32_PORT_FD) 2179 val |= 0x10; 2180 if (lp->options & PCNET32_PORT_100) 2181 val |= 0x08; 2182 lp->a->write_bcr(ioaddr, 32, val); 2183 } else { 2184 if (lp->options & PCNET32_PORT_ASEL) { 2185 lp->a->write_bcr(ioaddr, 32, 2186 lp->a->read_bcr(ioaddr, 2187 32) | 0x0080); 2188 /* enable auto negotiate, setup, disable fd */ 2189 val = lp->a->read_bcr(ioaddr, 32) & ~0x98; 2190 val |= 0x20; 2191 lp->a->write_bcr(ioaddr, 32, val); 2192 } 2193 } 2194 } else { 2195 int first_phy = -1; 2196 u16 bmcr; 2197 u32 bcr9; 2198 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 2199 2200 /* 2201 * There is really no good other way to handle multiple PHYs 2202 * other than turning off all automatics 2203 */ 2204 val = lp->a->read_bcr(ioaddr, 2); 2205 lp->a->write_bcr(ioaddr, 2, val & ~2); 2206 val = lp->a->read_bcr(ioaddr, 32); 2207 lp->a->write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */ 2208 2209 if (!(lp->options & PCNET32_PORT_ASEL)) { 2210 /* setup ecmd */ 2211 ecmd.port = PORT_MII; 2212 ecmd.transceiver = XCVR_INTERNAL; 2213 ecmd.autoneg = AUTONEG_DISABLE; 2214 ethtool_cmd_speed_set(&ecmd, 2215 (lp->options & PCNET32_PORT_100) ? 2216 SPEED_100 : SPEED_10); 2217 bcr9 = lp->a->read_bcr(ioaddr, 9); 2218 2219 if (lp->options & PCNET32_PORT_FD) { 2220 ecmd.duplex = DUPLEX_FULL; 2221 bcr9 |= (1 << 0); 2222 } else { 2223 ecmd.duplex = DUPLEX_HALF; 2224 bcr9 |= ~(1 << 0); 2225 } 2226 lp->a->write_bcr(ioaddr, 9, bcr9); 2227 } 2228 2229 for (i = 0; i < PCNET32_MAX_PHYS; i++) { 2230 if (lp->phymask & (1 << i)) { 2231 /* isolate all but the first PHY */ 2232 bmcr = mdio_read(dev, i, MII_BMCR); 2233 if (first_phy == -1) { 2234 first_phy = i; 2235 mdio_write(dev, i, MII_BMCR, 2236 bmcr & ~BMCR_ISOLATE); 2237 } else { 2238 mdio_write(dev, i, MII_BMCR, 2239 bmcr | BMCR_ISOLATE); 2240 } 2241 /* use mii_ethtool_sset to setup PHY */ 2242 lp->mii_if.phy_id = i; 2243 ecmd.phy_address = i; 2244 if (lp->options & PCNET32_PORT_ASEL) { 2245 mii_ethtool_gset(&lp->mii_if, &ecmd); 2246 ecmd.autoneg = AUTONEG_ENABLE; 2247 } 2248 mii_ethtool_sset(&lp->mii_if, &ecmd); 2249 } 2250 } 2251 lp->mii_if.phy_id = first_phy; 2252 netif_info(lp, link, dev, "Using PHY number %d\n", first_phy); 2253 } 2254 2255 #ifdef DO_DXSUFLO 2256 if (lp->dxsuflo) { /* Disable transmit stop on underflow */ 2257 val = lp->a->read_csr(ioaddr, CSR3); 2258 val |= 0x40; 2259 lp->a->write_csr(ioaddr, CSR3, val); 2260 } 2261 #endif 2262 2263 lp->init_block->mode = 2264 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7); 2265 pcnet32_load_multicast(dev); 2266 2267 if (pcnet32_init_ring(dev)) { 2268 rc = -ENOMEM; 2269 goto err_free_ring; 2270 } 2271 2272 napi_enable_locked(&lp->napi); 2273 2274 /* Re-initialize the PCNET32, and start it when done. */ 2275 lp->a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff)); 2276 lp->a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16)); 2277 2278 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ 2279 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT); 2280 2281 netif_start_queue(dev); 2282 2283 if (lp->chip_version >= PCNET32_79C970A) { 2284 /* Print the link status and start the watchdog */ 2285 pcnet32_check_media(dev, 1); 2286 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT); 2287 } 2288 2289 i = 0; 2290 while (i++ < 100) 2291 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON) 2292 break; 2293 /* 2294 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton 2295 * reports that doing so triggers a bug in the '974. 2296 */ 2297 lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL); 2298 2299 netif_printk(lp, ifup, KERN_DEBUG, dev, 2300 "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n", 2301 i, 2302 (u32) (lp->init_dma_addr), 2303 lp->a->read_csr(ioaddr, CSR0)); 2304 2305 spin_unlock_irqrestore(&lp->lock, flags); 2306 netdev_unlock(dev); 2307 2308 return 0; /* Always succeed */ 2309 2310 err_free_ring: 2311 /* free any allocated skbuffs */ 2312 pcnet32_purge_rx_ring(dev); 2313 2314 /* 2315 * Switch back to 16bit mode to avoid problems with dumb 2316 * DOS packet driver after a warm reboot 2317 */ 2318 lp->a->write_bcr(ioaddr, 20, 4); 2319 2320 err_free_irq: 2321 spin_unlock_irqrestore(&lp->lock, flags); 2322 netdev_unlock(dev); 2323 free_irq(dev->irq, dev); 2324 return rc; 2325 } 2326 2327 /* 2328 * The LANCE has been halted for one reason or another (busmaster memory 2329 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure, 2330 * etc.). Modern LANCE variants always reload their ring-buffer 2331 * configuration when restarted, so we must reinitialize our ring 2332 * context before restarting. As part of this reinitialization, 2333 * find all packets still on the Tx ring and pretend that they had been 2334 * sent (in effect, drop the packets on the floor) - the higher-level 2335 * protocols will time out and retransmit. It'd be better to shuffle 2336 * these skbs to a temp list and then actually re-Tx them after 2337 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com 2338 */ 2339 2340 static void pcnet32_purge_tx_ring(struct net_device *dev) 2341 { 2342 struct pcnet32_private *lp = netdev_priv(dev); 2343 int i; 2344 2345 for (i = 0; i < lp->tx_ring_size; i++) { 2346 lp->tx_ring[i].status = 0; /* CPU owns buffer */ 2347 wmb(); /* Make sure adapter sees owner change */ 2348 if (lp->tx_skbuff[i]) { 2349 if (!dma_mapping_error(&lp->pci_dev->dev, lp->tx_dma_addr[i])) 2350 dma_unmap_single(&lp->pci_dev->dev, 2351 lp->tx_dma_addr[i], 2352 lp->tx_skbuff[i]->len, 2353 DMA_TO_DEVICE); 2354 dev_kfree_skb_any(lp->tx_skbuff[i]); 2355 } 2356 lp->tx_skbuff[i] = NULL; 2357 lp->tx_dma_addr[i] = 0; 2358 } 2359 } 2360 2361 /* Initialize the PCNET32 Rx and Tx rings. */ 2362 static int pcnet32_init_ring(struct net_device *dev) 2363 { 2364 struct pcnet32_private *lp = netdev_priv(dev); 2365 int i; 2366 2367 lp->tx_full = 0; 2368 lp->cur_rx = lp->cur_tx = 0; 2369 lp->dirty_rx = lp->dirty_tx = 0; 2370 2371 for (i = 0; i < lp->rx_ring_size; i++) { 2372 struct sk_buff *rx_skbuff = lp->rx_skbuff[i]; 2373 if (!rx_skbuff) { 2374 lp->rx_skbuff[i] = netdev_alloc_skb(dev, PKT_BUF_SKB); 2375 rx_skbuff = lp->rx_skbuff[i]; 2376 if (!rx_skbuff) { 2377 /* there is not much we can do at this point */ 2378 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n", 2379 __func__); 2380 return -1; 2381 } 2382 skb_reserve(rx_skbuff, NET_IP_ALIGN); 2383 } 2384 2385 rmb(); 2386 if (lp->rx_dma_addr[i] == 0) { 2387 lp->rx_dma_addr[i] = 2388 dma_map_single(&lp->pci_dev->dev, rx_skbuff->data, 2389 PKT_BUF_SIZE, DMA_FROM_DEVICE); 2390 if (dma_mapping_error(&lp->pci_dev->dev, lp->rx_dma_addr[i])) { 2391 /* there is not much we can do at this point */ 2392 netif_err(lp, drv, dev, 2393 "%s pci dma mapping error\n", 2394 __func__); 2395 return -1; 2396 } 2397 } 2398 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]); 2399 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE); 2400 wmb(); /* Make sure owner changes after all others are visible */ 2401 lp->rx_ring[i].status = cpu_to_le16(0x8000); 2402 } 2403 /* The Tx buffer address is filled in as needed, but we do need to clear 2404 * the upper ownership bit. */ 2405 for (i = 0; i < lp->tx_ring_size; i++) { 2406 lp->tx_ring[i].status = 0; /* CPU owns buffer */ 2407 wmb(); /* Make sure adapter sees owner change */ 2408 lp->tx_ring[i].base = 0; 2409 lp->tx_dma_addr[i] = 0; 2410 } 2411 2412 lp->init_block->tlen_rlen = 2413 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits); 2414 for (i = 0; i < 6; i++) 2415 lp->init_block->phys_addr[i] = dev->dev_addr[i]; 2416 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr); 2417 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr); 2418 wmb(); /* Make sure all changes are visible */ 2419 return 0; 2420 } 2421 2422 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit 2423 * then flush the pending transmit operations, re-initialize the ring, 2424 * and tell the chip to initialize. 2425 */ 2426 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits) 2427 { 2428 struct pcnet32_private *lp = netdev_priv(dev); 2429 unsigned long ioaddr = dev->base_addr; 2430 int i; 2431 2432 /* wait for stop */ 2433 for (i = 0; i < 100; i++) 2434 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP) 2435 break; 2436 2437 if (i >= 100) 2438 netif_err(lp, drv, dev, "%s timed out waiting for stop\n", 2439 __func__); 2440 2441 pcnet32_purge_tx_ring(dev); 2442 if (pcnet32_init_ring(dev)) 2443 return; 2444 2445 /* ReInit Ring */ 2446 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT); 2447 i = 0; 2448 while (i++ < 1000) 2449 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON) 2450 break; 2451 2452 lp->a->write_csr(ioaddr, CSR0, csr0_bits); 2453 } 2454 2455 static void pcnet32_tx_timeout(struct net_device *dev, unsigned int txqueue) 2456 { 2457 struct pcnet32_private *lp = netdev_priv(dev); 2458 unsigned long ioaddr = dev->base_addr, flags; 2459 2460 spin_lock_irqsave(&lp->lock, flags); 2461 /* Transmitter timeout, serious problems. */ 2462 if (pcnet32_debug & NETIF_MSG_DRV) 2463 pr_err("%s: transmit timed out, status %4.4x, resetting\n", 2464 dev->name, lp->a->read_csr(ioaddr, CSR0)); 2465 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); 2466 dev->stats.tx_errors++; 2467 if (netif_msg_tx_err(lp)) { 2468 int i; 2469 printk(KERN_DEBUG 2470 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.", 2471 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "", 2472 lp->cur_rx); 2473 for (i = 0; i < lp->rx_ring_size; i++) 2474 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", 2475 le32_to_cpu(lp->rx_ring[i].base), 2476 (-le16_to_cpu(lp->rx_ring[i].buf_length)) & 2477 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length), 2478 le16_to_cpu(lp->rx_ring[i].status)); 2479 for (i = 0; i < lp->tx_ring_size; i++) 2480 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", 2481 le32_to_cpu(lp->tx_ring[i].base), 2482 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff, 2483 le32_to_cpu(lp->tx_ring[i].misc), 2484 le16_to_cpu(lp->tx_ring[i].status)); 2485 printk("\n"); 2486 } 2487 pcnet32_restart(dev, CSR0_NORMAL); 2488 2489 netif_trans_update(dev); /* prevent tx timeout */ 2490 netif_wake_queue(dev); 2491 2492 spin_unlock_irqrestore(&lp->lock, flags); 2493 } 2494 2495 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb, 2496 struct net_device *dev) 2497 { 2498 struct pcnet32_private *lp = netdev_priv(dev); 2499 unsigned long ioaddr = dev->base_addr; 2500 u16 status; 2501 int entry; 2502 unsigned long flags; 2503 2504 spin_lock_irqsave(&lp->lock, flags); 2505 2506 netif_printk(lp, tx_queued, KERN_DEBUG, dev, 2507 "%s() called, csr0 %4.4x\n", 2508 __func__, lp->a->read_csr(ioaddr, CSR0)); 2509 2510 /* Default status -- will not enable Successful-TxDone 2511 * interrupt when that option is available to us. 2512 */ 2513 status = 0x8300; 2514 2515 /* Fill in a Tx ring entry */ 2516 2517 /* Mask to ring buffer boundary. */ 2518 entry = lp->cur_tx & lp->tx_mod_mask; 2519 2520 /* Caution: the write order is important here, set the status 2521 * with the "ownership" bits last. */ 2522 2523 lp->tx_ring[entry].length = cpu_to_le16(-skb->len); 2524 2525 lp->tx_ring[entry].misc = 0x00000000; 2526 2527 lp->tx_dma_addr[entry] = 2528 dma_map_single(&lp->pci_dev->dev, skb->data, skb->len, 2529 DMA_TO_DEVICE); 2530 if (dma_mapping_error(&lp->pci_dev->dev, lp->tx_dma_addr[entry])) { 2531 dev_kfree_skb_any(skb); 2532 dev->stats.tx_dropped++; 2533 goto drop_packet; 2534 } 2535 lp->tx_skbuff[entry] = skb; 2536 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]); 2537 wmb(); /* Make sure owner changes after all others are visible */ 2538 lp->tx_ring[entry].status = cpu_to_le16(status); 2539 2540 lp->cur_tx++; 2541 dev->stats.tx_bytes += skb->len; 2542 2543 /* Trigger an immediate send poll. */ 2544 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL); 2545 2546 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) { 2547 lp->tx_full = 1; 2548 netif_stop_queue(dev); 2549 } 2550 drop_packet: 2551 spin_unlock_irqrestore(&lp->lock, flags); 2552 return NETDEV_TX_OK; 2553 } 2554 2555 /* The PCNET32 interrupt handler. */ 2556 static irqreturn_t 2557 pcnet32_interrupt(int irq, void *dev_id) 2558 { 2559 struct net_device *dev = dev_id; 2560 struct pcnet32_private *lp; 2561 unsigned long ioaddr; 2562 u16 csr0; 2563 int boguscnt = max_interrupt_work; 2564 2565 ioaddr = dev->base_addr; 2566 lp = netdev_priv(dev); 2567 2568 spin_lock(&lp->lock); 2569 2570 csr0 = lp->a->read_csr(ioaddr, CSR0); 2571 while ((csr0 & 0x8f00) && --boguscnt >= 0) { 2572 if (csr0 == 0xffff) 2573 break; /* PCMCIA remove happened */ 2574 /* Acknowledge all of the current interrupt sources ASAP. */ 2575 lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f); 2576 2577 netif_printk(lp, intr, KERN_DEBUG, dev, 2578 "interrupt csr0=%#2.2x new csr=%#2.2x\n", 2579 csr0, lp->a->read_csr(ioaddr, CSR0)); 2580 2581 /* Log misc errors. */ 2582 if (csr0 & 0x4000) 2583 dev->stats.tx_errors++; /* Tx babble. */ 2584 if (csr0 & 0x1000) { 2585 /* 2586 * This happens when our receive ring is full. This 2587 * shouldn't be a problem as we will see normal rx 2588 * interrupts for the frames in the receive ring. But 2589 * there are some PCI chipsets (I can reproduce this 2590 * on SP3G with Intel saturn chipset) which have 2591 * sometimes problems and will fill up the receive 2592 * ring with error descriptors. In this situation we 2593 * don't get a rx interrupt, but a missed frame 2594 * interrupt sooner or later. 2595 */ 2596 dev->stats.rx_errors++; /* Missed a Rx frame. */ 2597 } 2598 if (csr0 & 0x0800) { 2599 netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n", 2600 csr0); 2601 /* unlike for the lance, there is no restart needed */ 2602 } 2603 if (napi_schedule_prep(&lp->napi)) { 2604 u16 val; 2605 /* set interrupt masks */ 2606 val = lp->a->read_csr(ioaddr, CSR3); 2607 val |= 0x5f00; 2608 lp->a->write_csr(ioaddr, CSR3, val); 2609 2610 __napi_schedule(&lp->napi); 2611 break; 2612 } 2613 csr0 = lp->a->read_csr(ioaddr, CSR0); 2614 } 2615 2616 netif_printk(lp, intr, KERN_DEBUG, dev, 2617 "exiting interrupt, csr0=%#4.4x\n", 2618 lp->a->read_csr(ioaddr, CSR0)); 2619 2620 spin_unlock(&lp->lock); 2621 2622 return IRQ_HANDLED; 2623 } 2624 2625 static int pcnet32_close(struct net_device *dev) 2626 { 2627 unsigned long ioaddr = dev->base_addr; 2628 struct pcnet32_private *lp = netdev_priv(dev); 2629 unsigned long flags; 2630 2631 timer_delete_sync(&lp->watchdog_timer); 2632 2633 netif_stop_queue(dev); 2634 napi_disable(&lp->napi); 2635 2636 spin_lock_irqsave(&lp->lock, flags); 2637 2638 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112); 2639 2640 netif_printk(lp, ifdown, KERN_DEBUG, dev, 2641 "Shutting down ethercard, status was %2.2x\n", 2642 lp->a->read_csr(ioaddr, CSR0)); 2643 2644 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */ 2645 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); 2646 2647 /* 2648 * Switch back to 16bit mode to avoid problems with dumb 2649 * DOS packet driver after a warm reboot 2650 */ 2651 lp->a->write_bcr(ioaddr, 20, 4); 2652 2653 spin_unlock_irqrestore(&lp->lock, flags); 2654 2655 free_irq(dev->irq, dev); 2656 2657 spin_lock_irqsave(&lp->lock, flags); 2658 2659 pcnet32_purge_rx_ring(dev); 2660 pcnet32_purge_tx_ring(dev); 2661 2662 spin_unlock_irqrestore(&lp->lock, flags); 2663 2664 return 0; 2665 } 2666 2667 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev) 2668 { 2669 struct pcnet32_private *lp = netdev_priv(dev); 2670 unsigned long ioaddr = dev->base_addr; 2671 unsigned long flags; 2672 2673 spin_lock_irqsave(&lp->lock, flags); 2674 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112); 2675 spin_unlock_irqrestore(&lp->lock, flags); 2676 2677 return &dev->stats; 2678 } 2679 2680 /* taken from the sunlance driver, which it took from the depca driver */ 2681 static void pcnet32_load_multicast(struct net_device *dev) 2682 { 2683 struct pcnet32_private *lp = netdev_priv(dev); 2684 volatile struct pcnet32_init_block *ib = lp->init_block; 2685 volatile __le16 *mcast_table = (__le16 *)ib->filter; 2686 struct netdev_hw_addr *ha; 2687 unsigned long ioaddr = dev->base_addr; 2688 int i; 2689 u32 crc; 2690 2691 /* set all multicast bits */ 2692 if (dev->flags & IFF_ALLMULTI) { 2693 ib->filter[0] = cpu_to_le32(~0U); 2694 ib->filter[1] = cpu_to_le32(~0U); 2695 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff); 2696 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff); 2697 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff); 2698 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff); 2699 return; 2700 } 2701 /* clear the multicast filter */ 2702 ib->filter[0] = 0; 2703 ib->filter[1] = 0; 2704 2705 /* Add addresses */ 2706 netdev_for_each_mc_addr(ha, dev) { 2707 crc = ether_crc_le(6, ha->addr); 2708 crc = crc >> 26; 2709 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf)); 2710 } 2711 for (i = 0; i < 4; i++) 2712 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER + i, 2713 le16_to_cpu(mcast_table[i])); 2714 } 2715 2716 /* 2717 * Set or clear the multicast filter for this adaptor. 2718 */ 2719 static void pcnet32_set_multicast_list(struct net_device *dev) 2720 { 2721 unsigned long ioaddr = dev->base_addr, flags; 2722 struct pcnet32_private *lp = netdev_priv(dev); 2723 int csr15, suspended; 2724 2725 spin_lock_irqsave(&lp->lock, flags); 2726 suspended = pcnet32_suspend(dev, &flags, 0); 2727 csr15 = lp->a->read_csr(ioaddr, CSR15); 2728 if (dev->flags & IFF_PROMISC) { 2729 /* Log any net taps. */ 2730 netif_info(lp, hw, dev, "Promiscuous mode enabled\n"); 2731 lp->init_block->mode = 2732 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << 2733 7); 2734 lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000); 2735 } else { 2736 lp->init_block->mode = 2737 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7); 2738 lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff); 2739 pcnet32_load_multicast(dev); 2740 } 2741 2742 if (suspended) { 2743 pcnet32_clr_suspend(lp, ioaddr); 2744 } else { 2745 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); 2746 pcnet32_restart(dev, CSR0_NORMAL); 2747 netif_wake_queue(dev); 2748 } 2749 2750 spin_unlock_irqrestore(&lp->lock, flags); 2751 } 2752 2753 /* This routine assumes that the lp->lock is held */ 2754 static int mdio_read(struct net_device *dev, int phy_id, int reg_num) 2755 { 2756 struct pcnet32_private *lp = netdev_priv(dev); 2757 unsigned long ioaddr = dev->base_addr; 2758 u16 val_out; 2759 2760 if (!lp->mii) 2761 return 0; 2762 2763 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); 2764 val_out = lp->a->read_bcr(ioaddr, 34); 2765 2766 return val_out; 2767 } 2768 2769 /* This routine assumes that the lp->lock is held */ 2770 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val) 2771 { 2772 struct pcnet32_private *lp = netdev_priv(dev); 2773 unsigned long ioaddr = dev->base_addr; 2774 2775 if (!lp->mii) 2776 return; 2777 2778 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); 2779 lp->a->write_bcr(ioaddr, 34, val); 2780 } 2781 2782 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2783 { 2784 struct pcnet32_private *lp = netdev_priv(dev); 2785 int rc; 2786 unsigned long flags; 2787 2788 /* SIOC[GS]MIIxxx ioctls */ 2789 if (lp->mii) { 2790 spin_lock_irqsave(&lp->lock, flags); 2791 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL); 2792 spin_unlock_irqrestore(&lp->lock, flags); 2793 } else { 2794 rc = -EOPNOTSUPP; 2795 } 2796 2797 return rc; 2798 } 2799 2800 static int pcnet32_check_otherphy(struct net_device *dev) 2801 { 2802 struct pcnet32_private *lp = netdev_priv(dev); 2803 struct mii_if_info mii = lp->mii_if; 2804 u16 bmcr; 2805 int i; 2806 2807 for (i = 0; i < PCNET32_MAX_PHYS; i++) { 2808 if (i == lp->mii_if.phy_id) 2809 continue; /* skip active phy */ 2810 if (lp->phymask & (1 << i)) { 2811 mii.phy_id = i; 2812 if (mii_link_ok(&mii)) { 2813 /* found PHY with active link */ 2814 netif_info(lp, link, dev, "Using PHY number %d\n", 2815 i); 2816 2817 /* isolate inactive phy */ 2818 bmcr = 2819 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR); 2820 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR, 2821 bmcr | BMCR_ISOLATE); 2822 2823 /* de-isolate new phy */ 2824 bmcr = mdio_read(dev, i, MII_BMCR); 2825 mdio_write(dev, i, MII_BMCR, 2826 bmcr & ~BMCR_ISOLATE); 2827 2828 /* set new phy address */ 2829 lp->mii_if.phy_id = i; 2830 return 1; 2831 } 2832 } 2833 } 2834 return 0; 2835 } 2836 2837 /* 2838 * Show the status of the media. Similar to mii_check_media however it 2839 * correctly shows the link speed for all (tested) pcnet32 variants. 2840 * Devices with no mii just report link state without speed. 2841 * 2842 * Caller is assumed to hold and release the lp->lock. 2843 */ 2844 2845 static void pcnet32_check_media(struct net_device *dev, int verbose) 2846 { 2847 struct pcnet32_private *lp = netdev_priv(dev); 2848 int curr_link; 2849 int prev_link = netif_carrier_ok(dev) ? 1 : 0; 2850 u32 bcr9; 2851 2852 if (lp->mii) { 2853 curr_link = mii_link_ok(&lp->mii_if); 2854 } else if (lp->chip_version == PCNET32_79C970A) { 2855 ulong ioaddr = dev->base_addr; /* card base I/O address */ 2856 /* only read link if port is set to TP */ 2857 if (!lp->autoneg && lp->port_tp) 2858 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0); 2859 else /* link always up for AUI port or port auto select */ 2860 curr_link = 1; 2861 } else { 2862 ulong ioaddr = dev->base_addr; /* card base I/O address */ 2863 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0); 2864 } 2865 if (!curr_link) { 2866 if (prev_link || verbose) { 2867 netif_carrier_off(dev); 2868 netif_info(lp, link, dev, "link down\n"); 2869 } 2870 if (lp->phycount > 1) { 2871 pcnet32_check_otherphy(dev); 2872 } 2873 } else if (verbose || !prev_link) { 2874 netif_carrier_on(dev); 2875 if (lp->mii) { 2876 if (netif_msg_link(lp)) { 2877 struct ethtool_cmd ecmd = { 2878 .cmd = ETHTOOL_GSET }; 2879 mii_ethtool_gset(&lp->mii_if, &ecmd); 2880 netdev_info(dev, "link up, %uMbps, %s-duplex\n", 2881 ethtool_cmd_speed(&ecmd), 2882 (ecmd.duplex == DUPLEX_FULL) 2883 ? "full" : "half"); 2884 } 2885 bcr9 = lp->a->read_bcr(dev->base_addr, 9); 2886 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) { 2887 if (lp->mii_if.full_duplex) 2888 bcr9 |= (1 << 0); 2889 else 2890 bcr9 &= ~(1 << 0); 2891 lp->a->write_bcr(dev->base_addr, 9, bcr9); 2892 } 2893 } else { 2894 netif_info(lp, link, dev, "link up\n"); 2895 } 2896 } 2897 } 2898 2899 /* 2900 * Check for loss of link and link establishment. 2901 * Could possibly be changed to use mii_check_media instead. 2902 */ 2903 2904 static void pcnet32_watchdog(struct timer_list *t) 2905 { 2906 struct pcnet32_private *lp = timer_container_of(lp, t, watchdog_timer); 2907 struct net_device *dev = lp->dev; 2908 unsigned long flags; 2909 2910 /* Print the link status if it has changed */ 2911 spin_lock_irqsave(&lp->lock, flags); 2912 pcnet32_check_media(dev, 0); 2913 spin_unlock_irqrestore(&lp->lock, flags); 2914 2915 mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT)); 2916 } 2917 2918 static int __maybe_unused pcnet32_pm_suspend(struct device *device_d) 2919 { 2920 struct net_device *dev = dev_get_drvdata(device_d); 2921 2922 if (netif_running(dev)) { 2923 netif_device_detach(dev); 2924 pcnet32_close(dev); 2925 } 2926 2927 return 0; 2928 } 2929 2930 static int __maybe_unused pcnet32_pm_resume(struct device *device_d) 2931 { 2932 struct net_device *dev = dev_get_drvdata(device_d); 2933 2934 if (netif_running(dev)) { 2935 pcnet32_open(dev); 2936 netif_device_attach(dev); 2937 } 2938 2939 return 0; 2940 } 2941 2942 static void pcnet32_remove_one(struct pci_dev *pdev) 2943 { 2944 struct net_device *dev = pci_get_drvdata(pdev); 2945 2946 if (dev) { 2947 struct pcnet32_private *lp = netdev_priv(dev); 2948 2949 unregister_netdev(dev); 2950 pcnet32_free_ring(dev); 2951 release_region(dev->base_addr, PCNET32_TOTAL_SIZE); 2952 dma_free_coherent(&lp->pci_dev->dev, sizeof(*lp->init_block), 2953 lp->init_block, lp->init_dma_addr); 2954 free_netdev(dev); 2955 pci_disable_device(pdev); 2956 } 2957 } 2958 2959 static SIMPLE_DEV_PM_OPS(pcnet32_pm_ops, pcnet32_pm_suspend, pcnet32_pm_resume); 2960 2961 static struct pci_driver pcnet32_driver = { 2962 .name = DRV_NAME, 2963 .probe = pcnet32_probe_pci, 2964 .remove = pcnet32_remove_one, 2965 .id_table = pcnet32_pci_tbl, 2966 .driver = { 2967 .pm = &pcnet32_pm_ops, 2968 }, 2969 }; 2970 2971 /* An additional parameter that may be passed in... */ 2972 static int debug = -1; 2973 static int tx_start_pt = -1; 2974 static int pcnet32_have_pci; 2975 2976 module_param(debug, int, 0); 2977 MODULE_PARM_DESC(debug, DRV_NAME " debug level"); 2978 module_param(max_interrupt_work, int, 0); 2979 MODULE_PARM_DESC(max_interrupt_work, 2980 DRV_NAME " maximum events handled per interrupt"); 2981 module_param(rx_copybreak, int, 0); 2982 MODULE_PARM_DESC(rx_copybreak, 2983 DRV_NAME " copy breakpoint for copy-only-tiny-frames"); 2984 module_param(tx_start_pt, int, 0); 2985 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)"); 2986 module_param(pcnet32vlb, int, 0); 2987 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)"); 2988 module_param_array(options, int, NULL, 0); 2989 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)"); 2990 module_param_array(full_duplex, int, NULL, 0); 2991 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)"); 2992 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */ 2993 module_param_array(homepna, int, NULL, 0); 2994 MODULE_PARM_DESC(homepna, 2995 DRV_NAME 2996 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet"); 2997 2998 MODULE_AUTHOR("Thomas Bogendoerfer"); 2999 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards"); 3000 MODULE_LICENSE("GPL"); 3001 3002 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 3003 3004 static int __init pcnet32_init_module(void) 3005 { 3006 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT); 3007 3008 if ((tx_start_pt >= 0) && (tx_start_pt <= 3)) 3009 tx_start = tx_start_pt; 3010 3011 /* find the PCI devices */ 3012 if (!pci_register_driver(&pcnet32_driver)) 3013 pcnet32_have_pci = 1; 3014 3015 /* should we find any remaining VLbus devices ? */ 3016 if (pcnet32vlb) 3017 pcnet32_probe_vlbus(pcnet32_portlist); 3018 3019 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE)) 3020 pr_info("%d cards_found\n", cards_found); 3021 3022 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV; 3023 } 3024 3025 static void __exit pcnet32_cleanup_module(void) 3026 { 3027 struct net_device *next_dev; 3028 3029 while (pcnet32_dev) { 3030 struct pcnet32_private *lp = netdev_priv(pcnet32_dev); 3031 next_dev = lp->next; 3032 unregister_netdev(pcnet32_dev); 3033 pcnet32_free_ring(pcnet32_dev); 3034 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE); 3035 dma_free_coherent(&lp->pci_dev->dev, sizeof(*lp->init_block), 3036 lp->init_block, lp->init_dma_addr); 3037 free_netdev(pcnet32_dev); 3038 pcnet32_dev = next_dev; 3039 } 3040 3041 if (pcnet32_have_pci) 3042 pci_unregister_driver(&pcnet32_driver); 3043 } 3044 3045 module_init(pcnet32_init_module); 3046 module_exit(pcnet32_cleanup_module); 3047