1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2020 Facebook */
3
4 #include <linux/bits.h>
5 #include <linux/err.h>
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/debugfs.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/serial_8250.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk-provider.h>
14 #include <linux/platform_device.h>
15 #include <linux/platform_data/i2c-xiic.h>
16 #include <linux/platform_data/i2c-ocores.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/xilinx_spi.h>
20 #include <linux/spi/altera.h>
21 #include <net/devlink.h>
22 #include <linux/i2c.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/nvmem-consumer.h>
25 #include <linux/crc16.h>
26 #include <linux/dpll.h>
27
28 #define PCI_DEVICE_ID_META_TIMECARD 0x0400
29
30 #define PCI_VENDOR_ID_CELESTICA 0x18d4
31 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008
32
33 #define PCI_VENDOR_ID_OROLIA 0x1ad7
34 #define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000
35
36 #define PCI_VENDOR_ID_ADVA 0xad5a
37 #define PCI_DEVICE_ID_ADVA_TIMECARD 0x0400
38
39 static struct class timecard_class = {
40 .name = "timecard",
41 };
42
43 struct ocp_reg {
44 u32 ctrl;
45 u32 status;
46 u32 select;
47 u32 version;
48 u32 time_ns;
49 u32 time_sec;
50 u32 __pad0[2];
51 u32 adjust_ns;
52 u32 adjust_sec;
53 u32 __pad1[2];
54 u32 offset_ns;
55 u32 offset_window_ns;
56 u32 __pad2[2];
57 u32 drift_ns;
58 u32 drift_window_ns;
59 u32 __pad3[6];
60 u32 servo_offset_p;
61 u32 servo_offset_i;
62 u32 servo_drift_p;
63 u32 servo_drift_i;
64 u32 status_offset;
65 u32 status_drift;
66 };
67
68 struct ptp_ocp_servo_conf {
69 u32 servo_offset_p;
70 u32 servo_offset_i;
71 u32 servo_drift_p;
72 u32 servo_drift_i;
73 };
74
75 #define OCP_CTRL_ENABLE BIT(0)
76 #define OCP_CTRL_ADJUST_TIME BIT(1)
77 #define OCP_CTRL_ADJUST_OFFSET BIT(2)
78 #define OCP_CTRL_ADJUST_DRIFT BIT(3)
79 #define OCP_CTRL_ADJUST_SERVO BIT(8)
80 #define OCP_CTRL_READ_TIME_REQ BIT(30)
81 #define OCP_CTRL_READ_TIME_DONE BIT(31)
82
83 #define OCP_STATUS_IN_SYNC BIT(0)
84 #define OCP_STATUS_IN_HOLDOVER BIT(1)
85
86 #define OCP_SELECT_CLK_NONE 0
87 #define OCP_SELECT_CLK_REG 0xfe
88
89 struct tod_reg {
90 u32 ctrl;
91 u32 status;
92 u32 uart_polarity;
93 u32 version;
94 u32 adj_sec;
95 u32 __pad0[3];
96 u32 uart_baud;
97 u32 __pad1[3];
98 u32 utc_status;
99 u32 leap;
100 };
101
102 #define TOD_CTRL_PROTOCOL BIT(28)
103 #define TOD_CTRL_DISABLE_FMT_A BIT(17)
104 #define TOD_CTRL_DISABLE_FMT_B BIT(16)
105 #define TOD_CTRL_ENABLE BIT(0)
106 #define TOD_CTRL_GNSS_MASK GENMASK(3, 0)
107 #define TOD_CTRL_GNSS_SHIFT 24
108
109 #define TOD_STATUS_UTC_MASK GENMASK(7, 0)
110 #define TOD_STATUS_UTC_VALID BIT(8)
111 #define TOD_STATUS_LEAP_ANNOUNCE BIT(12)
112 #define TOD_STATUS_LEAP_VALID BIT(16)
113
114 struct ts_reg {
115 u32 enable;
116 u32 error;
117 u32 polarity;
118 u32 version;
119 u32 __pad0[4];
120 u32 cable_delay;
121 u32 __pad1[3];
122 u32 intr;
123 u32 intr_mask;
124 u32 event_count;
125 u32 __pad2[1];
126 u32 ts_count;
127 u32 time_ns;
128 u32 time_sec;
129 u32 data_width;
130 u32 data;
131 };
132
133 struct pps_reg {
134 u32 ctrl;
135 u32 status;
136 u32 __pad0[6];
137 u32 cable_delay;
138 };
139
140 #define PPS_STATUS_FILTER_ERR BIT(0)
141 #define PPS_STATUS_SUPERV_ERR BIT(1)
142
143 struct img_reg {
144 u32 version;
145 };
146
147 struct gpio_reg {
148 u32 gpio1;
149 u32 __pad0;
150 u32 gpio2;
151 u32 __pad1;
152 };
153
154 struct irig_master_reg {
155 u32 ctrl;
156 u32 status;
157 u32 __pad0;
158 u32 version;
159 u32 adj_sec;
160 u32 mode_ctrl;
161 };
162
163 #define IRIG_M_CTRL_ENABLE BIT(0)
164
165 struct irig_slave_reg {
166 u32 ctrl;
167 u32 status;
168 u32 __pad0;
169 u32 version;
170 u32 adj_sec;
171 u32 mode_ctrl;
172 };
173
174 #define IRIG_S_CTRL_ENABLE BIT(0)
175
176 struct dcf_master_reg {
177 u32 ctrl;
178 u32 status;
179 u32 __pad0;
180 u32 version;
181 u32 adj_sec;
182 };
183
184 #define DCF_M_CTRL_ENABLE BIT(0)
185
186 struct dcf_slave_reg {
187 u32 ctrl;
188 u32 status;
189 u32 __pad0;
190 u32 version;
191 u32 adj_sec;
192 };
193
194 #define DCF_S_CTRL_ENABLE BIT(0)
195
196 struct signal_reg {
197 u32 enable;
198 u32 status;
199 u32 polarity;
200 u32 version;
201 u32 __pad0[4];
202 u32 cable_delay;
203 u32 __pad1[3];
204 u32 intr;
205 u32 intr_mask;
206 u32 __pad2[2];
207 u32 start_ns;
208 u32 start_sec;
209 u32 pulse_ns;
210 u32 pulse_sec;
211 u32 period_ns;
212 u32 period_sec;
213 u32 repeat_count;
214 };
215
216 struct frequency_reg {
217 u32 ctrl;
218 u32 status;
219 };
220
221 struct board_config_reg {
222 u32 mro50_serial_activate;
223 };
224
225 #define FREQ_STATUS_VALID BIT(31)
226 #define FREQ_STATUS_ERROR BIT(30)
227 #define FREQ_STATUS_OVERRUN BIT(29)
228 #define FREQ_STATUS_MASK GENMASK(23, 0)
229
230 struct ptp_ocp_flash_info {
231 const char *name;
232 int pci_offset;
233 int data_size;
234 void *data;
235 };
236
237 struct ptp_ocp_firmware_header {
238 char magic[4];
239 __be16 pci_vendor_id;
240 __be16 pci_device_id;
241 __be32 image_size;
242 __be16 hw_revision;
243 __be16 crc;
244 };
245
246 #define OCP_FIRMWARE_MAGIC_HEADER "OCPC"
247
248 struct ptp_ocp_i2c_info {
249 const char *name;
250 unsigned long fixed_rate;
251 size_t data_size;
252 void *data;
253 };
254
255 struct ptp_ocp_ext_info {
256 int index;
257 irqreturn_t (*irq_fcn)(int irq, void *priv);
258 int (*enable)(void *priv, u32 req, bool enable);
259 };
260
261 struct ptp_ocp_ext_src {
262 void __iomem *mem;
263 struct ptp_ocp *bp;
264 struct ptp_ocp_ext_info *info;
265 int irq_vec;
266 };
267
268 enum ptp_ocp_sma_mode {
269 SMA_MODE_IN,
270 SMA_MODE_OUT,
271 };
272
273 static struct dpll_pin_frequency ptp_ocp_sma_freq[] = {
274 DPLL_PIN_FREQUENCY_1PPS,
275 DPLL_PIN_FREQUENCY_10MHZ,
276 DPLL_PIN_FREQUENCY_IRIG_B,
277 DPLL_PIN_FREQUENCY_DCF77,
278 };
279
280 struct ptp_ocp_sma_connector {
281 enum ptp_ocp_sma_mode mode;
282 bool fixed_fcn;
283 bool fixed_dir;
284 bool disabled;
285 u8 default_fcn;
286 struct dpll_pin *dpll_pin;
287 struct dpll_pin_properties dpll_prop;
288 dpll_tracker tracker;
289 };
290
291 struct ocp_attr_group {
292 u64 cap;
293 const struct attribute_group *group;
294 };
295
296 #define OCP_CAP_BASIC BIT(0)
297 #define OCP_CAP_SIGNAL BIT(1)
298 #define OCP_CAP_FREQ BIT(2)
299
300 struct ptp_ocp_signal {
301 ktime_t period;
302 ktime_t pulse;
303 ktime_t phase;
304 ktime_t start;
305 int duty;
306 bool polarity;
307 bool running;
308 };
309
310 struct ptp_ocp_serial_port {
311 int line;
312 int baud;
313 };
314
315 #define OCP_BOARD_ID_LEN 13
316 #define OCP_SERIAL_LEN 6
317 #define OCP_SMA_NUM 4
318 #define OCP_SIGNAL_NUM 4
319 #define OCP_FREQ_NUM 4
320
321 enum {
322 PORT_GNSS,
323 PORT_GNSS2,
324 PORT_MAC, /* miniature atomic clock */
325 PORT_NMEA,
326
327 __PORT_COUNT,
328 };
329
330 struct ptp_ocp {
331 struct pci_dev *pdev;
332 struct device dev;
333 spinlock_t lock;
334 struct ocp_reg __iomem *reg;
335 struct tod_reg __iomem *tod;
336 struct pps_reg __iomem *pps_to_ext;
337 struct pps_reg __iomem *pps_to_clk;
338 struct board_config_reg __iomem *board_config;
339 struct gpio_reg __iomem *pps_select;
340 struct gpio_reg __iomem *sma_map1;
341 struct gpio_reg __iomem *sma_map2;
342 struct irig_master_reg __iomem *irig_out;
343 struct irig_slave_reg __iomem *irig_in;
344 struct dcf_master_reg __iomem *dcf_out;
345 struct dcf_slave_reg __iomem *dcf_in;
346 struct tod_reg __iomem *nmea_out;
347 struct frequency_reg __iomem *freq_in[OCP_FREQ_NUM];
348 struct ptp_ocp_ext_src *signal_out[OCP_SIGNAL_NUM];
349 struct ptp_ocp_ext_src *pps;
350 struct ptp_ocp_ext_src *ts0;
351 struct ptp_ocp_ext_src *ts1;
352 struct ptp_ocp_ext_src *ts2;
353 struct ptp_ocp_ext_src *ts3;
354 struct ptp_ocp_ext_src *ts4;
355 struct ocp_art_gpio_reg __iomem *art_sma;
356 struct img_reg __iomem *image;
357 struct ptp_clock *ptp;
358 struct ptp_clock_info ptp_info;
359 struct platform_device *i2c_ctrl;
360 struct platform_device *spi_flash;
361 struct clk_hw *i2c_clk;
362 struct timer_list watchdog;
363 const struct attribute_group **attr_group;
364 const struct ptp_ocp_eeprom_map *eeprom_map;
365 struct dentry *debug_root;
366 bool sync;
367 time64_t gnss_lost;
368 struct delayed_work sync_work;
369 int id;
370 int n_irqs;
371 struct ptp_ocp_serial_port port[__PORT_COUNT];
372 bool fw_loader;
373 u8 fw_tag;
374 u16 fw_version;
375 u8 board_id[OCP_BOARD_ID_LEN];
376 u8 serial[OCP_SERIAL_LEN];
377 bool has_eeprom_data;
378 u32 pps_req_map;
379 int flash_start;
380 u32 utc_tai_offset;
381 u32 ts_window_adjust;
382 u64 fw_cap;
383 struct ptp_ocp_signal signal[OCP_SIGNAL_NUM];
384 struct ptp_ocp_sma_connector sma[OCP_SMA_NUM];
385 const struct ocp_sma_op *sma_op;
386 struct dpll_device *dpll;
387 dpll_tracker tracker;
388 int signals_nr;
389 int freq_in_nr;
390 };
391
392 #define OCP_REQ_TIMESTAMP BIT(0)
393 #define OCP_REQ_PPS BIT(1)
394
395 struct ocp_resource {
396 unsigned long offset;
397 int size;
398 int irq_vec;
399 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r);
400 void *extra;
401 unsigned long bp_offset;
402 const char * const name;
403 };
404
405 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r);
406 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r);
407 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r);
408 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r);
409 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r);
410 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
411 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv);
412 static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv);
413 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable);
414 static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
415 struct ptp_perout_request *req);
416 static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable);
417 static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr);
418
419 static int ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
420
421 static int ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
422
423 static const struct ocp_attr_group fb_timecard_groups[];
424
425 static const struct ocp_attr_group art_timecard_groups[];
426
427 static const struct ocp_attr_group adva_timecard_groups[];
428
429 struct ptp_ocp_eeprom_map {
430 u16 off;
431 u16 len;
432 u32 bp_offset;
433 const void * const tag;
434 };
435
436 #define EEPROM_ENTRY(addr, member) \
437 .off = addr, \
438 .len = sizeof_field(struct ptp_ocp, member), \
439 .bp_offset = offsetof(struct ptp_ocp, member)
440
441 #define BP_MAP_ENTRY_ADDR(bp, map) ({ \
442 (void *)((uintptr_t)(bp) + (map)->bp_offset); \
443 })
444
445 static struct ptp_ocp_eeprom_map fb_eeprom_map[] = {
446 { EEPROM_ENTRY(0x43, board_id) },
447 { EEPROM_ENTRY(0x00, serial), .tag = "mac" },
448 { }
449 };
450
451 static struct ptp_ocp_eeprom_map art_eeprom_map[] = {
452 { EEPROM_ENTRY(0x200 + 0x43, board_id) },
453 { EEPROM_ENTRY(0x200 + 0x63, serial) },
454 { }
455 };
456
457 #define bp_assign_entry(bp, res, val) ({ \
458 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \
459 *(typeof(val) *)addr = val; \
460 })
461
462 #define OCP_RES_LOCATION(member) \
463 .name = #member, .bp_offset = offsetof(struct ptp_ocp, member)
464
465 #define OCP_MEM_RESOURCE(member) \
466 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem
467
468 #define OCP_SERIAL_RESOURCE(member) \
469 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial
470
471 #define OCP_I2C_RESOURCE(member) \
472 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c
473
474 #define OCP_SPI_RESOURCE(member) \
475 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi
476
477 #define OCP_EXT_RESOURCE(member) \
478 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext
479
480 /* This is the MSI vector mapping used.
481 * 0: PPS (TS5)
482 * 1: TS0
483 * 2: TS1
484 * 3: GNSS1
485 * 4: GNSS2
486 * 5: MAC
487 * 6: TS2
488 * 7: I2C controller
489 * 8: HWICAP (notused)
490 * 9: SPI Flash
491 * 10: NMEA
492 * 11: Signal Generator 1
493 * 12: Signal Generator 2
494 * 13: Signal Generator 3
495 * 14: Signal Generator 4
496 * 15: TS3
497 * 16: TS4
498 --
499 * 8: Orolia TS1
500 * 10: Orolia TS2
501 * 11: Orolia TS0 (GNSS)
502 * 12: Orolia PPS
503 * 14: Orolia TS3
504 * 15: Orolia TS4
505 */
506
507 static struct ocp_resource ocp_fb_resource[] = {
508 {
509 OCP_MEM_RESOURCE(reg),
510 .offset = 0x01000000, .size = 0x10000,
511 },
512 {
513 OCP_EXT_RESOURCE(ts0),
514 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
515 .extra = &(struct ptp_ocp_ext_info) {
516 .index = 0,
517 .irq_fcn = ptp_ocp_ts_irq,
518 .enable = ptp_ocp_ts_enable,
519 },
520 },
521 {
522 OCP_EXT_RESOURCE(ts1),
523 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
524 .extra = &(struct ptp_ocp_ext_info) {
525 .index = 1,
526 .irq_fcn = ptp_ocp_ts_irq,
527 .enable = ptp_ocp_ts_enable,
528 },
529 },
530 {
531 OCP_EXT_RESOURCE(ts2),
532 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
533 .extra = &(struct ptp_ocp_ext_info) {
534 .index = 2,
535 .irq_fcn = ptp_ocp_ts_irq,
536 .enable = ptp_ocp_ts_enable,
537 },
538 },
539 {
540 OCP_EXT_RESOURCE(ts3),
541 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
542 .extra = &(struct ptp_ocp_ext_info) {
543 .index = 3,
544 .irq_fcn = ptp_ocp_ts_irq,
545 .enable = ptp_ocp_ts_enable,
546 },
547 },
548 {
549 OCP_EXT_RESOURCE(ts4),
550 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
551 .extra = &(struct ptp_ocp_ext_info) {
552 .index = 4,
553 .irq_fcn = ptp_ocp_ts_irq,
554 .enable = ptp_ocp_ts_enable,
555 },
556 },
557 /* Timestamp for PHC and/or PPS generator */
558 {
559 OCP_EXT_RESOURCE(pps),
560 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
561 .extra = &(struct ptp_ocp_ext_info) {
562 .index = 5,
563 .irq_fcn = ptp_ocp_ts_irq,
564 .enable = ptp_ocp_ts_enable,
565 },
566 },
567 {
568 OCP_EXT_RESOURCE(signal_out[0]),
569 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
570 .extra = &(struct ptp_ocp_ext_info) {
571 .index = 1,
572 .irq_fcn = ptp_ocp_signal_irq,
573 .enable = ptp_ocp_signal_enable,
574 },
575 },
576 {
577 OCP_EXT_RESOURCE(signal_out[1]),
578 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
579 .extra = &(struct ptp_ocp_ext_info) {
580 .index = 2,
581 .irq_fcn = ptp_ocp_signal_irq,
582 .enable = ptp_ocp_signal_enable,
583 },
584 },
585 {
586 OCP_EXT_RESOURCE(signal_out[2]),
587 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
588 .extra = &(struct ptp_ocp_ext_info) {
589 .index = 3,
590 .irq_fcn = ptp_ocp_signal_irq,
591 .enable = ptp_ocp_signal_enable,
592 },
593 },
594 {
595 OCP_EXT_RESOURCE(signal_out[3]),
596 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
597 .extra = &(struct ptp_ocp_ext_info) {
598 .index = 4,
599 .irq_fcn = ptp_ocp_signal_irq,
600 .enable = ptp_ocp_signal_enable,
601 },
602 },
603 {
604 OCP_MEM_RESOURCE(pps_to_ext),
605 .offset = 0x01030000, .size = 0x10000,
606 },
607 {
608 OCP_MEM_RESOURCE(pps_to_clk),
609 .offset = 0x01040000, .size = 0x10000,
610 },
611 {
612 OCP_MEM_RESOURCE(tod),
613 .offset = 0x01050000, .size = 0x10000,
614 },
615 {
616 OCP_MEM_RESOURCE(irig_in),
617 .offset = 0x01070000, .size = 0x10000,
618 },
619 {
620 OCP_MEM_RESOURCE(irig_out),
621 .offset = 0x01080000, .size = 0x10000,
622 },
623 {
624 OCP_MEM_RESOURCE(dcf_in),
625 .offset = 0x01090000, .size = 0x10000,
626 },
627 {
628 OCP_MEM_RESOURCE(dcf_out),
629 .offset = 0x010A0000, .size = 0x10000,
630 },
631 {
632 OCP_MEM_RESOURCE(nmea_out),
633 .offset = 0x010B0000, .size = 0x10000,
634 },
635 {
636 OCP_MEM_RESOURCE(image),
637 .offset = 0x00020000, .size = 0x1000,
638 },
639 {
640 OCP_MEM_RESOURCE(pps_select),
641 .offset = 0x00130000, .size = 0x1000,
642 },
643 {
644 OCP_MEM_RESOURCE(sma_map1),
645 .offset = 0x00140000, .size = 0x1000,
646 },
647 {
648 OCP_MEM_RESOURCE(sma_map2),
649 .offset = 0x00220000, .size = 0x1000,
650 },
651 {
652 OCP_I2C_RESOURCE(i2c_ctrl),
653 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
654 .extra = &(struct ptp_ocp_i2c_info) {
655 .name = "xiic-i2c",
656 .fixed_rate = 50000000,
657 .data_size = sizeof(struct xiic_i2c_platform_data),
658 .data = &(struct xiic_i2c_platform_data) {
659 .num_devices = 2,
660 .devices = (struct i2c_board_info[]) {
661 { I2C_BOARD_INFO("24c02", 0x50) },
662 { I2C_BOARD_INFO("24mac402", 0x58),
663 .platform_data = "mac" },
664 },
665 },
666 },
667 },
668 {
669 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
670 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
671 .extra = &(struct ptp_ocp_serial_port) {
672 .baud = 115200,
673 },
674 },
675 {
676 OCP_SERIAL_RESOURCE(port[PORT_GNSS2]),
677 .offset = 0x00170000 + 0x1000, .irq_vec = 4,
678 .extra = &(struct ptp_ocp_serial_port) {
679 .baud = 115200,
680 },
681 },
682 {
683 OCP_SERIAL_RESOURCE(port[PORT_MAC]),
684 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
685 .extra = &(struct ptp_ocp_serial_port) {
686 .baud = 57600,
687 },
688 },
689 {
690 OCP_SERIAL_RESOURCE(port[PORT_NMEA]),
691 .offset = 0x00190000 + 0x1000, .irq_vec = 10,
692 },
693 {
694 OCP_SPI_RESOURCE(spi_flash),
695 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
696 .extra = &(struct ptp_ocp_flash_info) {
697 .name = "xilinx_spi", .pci_offset = 0,
698 .data_size = sizeof(struct xspi_platform_data),
699 .data = &(struct xspi_platform_data) {
700 .num_chipselect = 1,
701 .bits_per_word = 8,
702 .num_devices = 1,
703 .force_irq = true,
704 .devices = &(struct spi_board_info) {
705 .modalias = "spi-nor",
706 },
707 },
708 },
709 },
710 {
711 OCP_MEM_RESOURCE(freq_in[0]),
712 .offset = 0x01200000, .size = 0x10000,
713 },
714 {
715 OCP_MEM_RESOURCE(freq_in[1]),
716 .offset = 0x01210000, .size = 0x10000,
717 },
718 {
719 OCP_MEM_RESOURCE(freq_in[2]),
720 .offset = 0x01220000, .size = 0x10000,
721 },
722 {
723 OCP_MEM_RESOURCE(freq_in[3]),
724 .offset = 0x01230000, .size = 0x10000,
725 },
726 {
727 .setup = ptp_ocp_fb_board_init,
728 .extra = &(struct ptp_ocp_servo_conf) {
729 .servo_offset_p = 0x2000,
730 .servo_offset_i = 0x1000,
731 .servo_drift_p = 0,
732 .servo_drift_i = 0,
733 },
734 },
735 { }
736 };
737
738 #define OCP_ART_CONFIG_SIZE 144
739 #define OCP_ART_TEMP_TABLE_SIZE 368
740
741 struct ocp_art_gpio_reg {
742 struct {
743 u32 gpio;
744 u32 __pad[3];
745 } map[4];
746 };
747
748 static struct ocp_resource ocp_art_resource[] = {
749 {
750 OCP_MEM_RESOURCE(reg),
751 .offset = 0x01000000, .size = 0x10000,
752 },
753 {
754 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
755 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
756 .extra = &(struct ptp_ocp_serial_port) {
757 .baud = 115200,
758 },
759 },
760 {
761 OCP_MEM_RESOURCE(art_sma),
762 .offset = 0x003C0000, .size = 0x1000,
763 },
764 /* Timestamp associated with GNSS1 receiver PPS */
765 {
766 OCP_EXT_RESOURCE(ts0),
767 .offset = 0x360000, .size = 0x20, .irq_vec = 12,
768 .extra = &(struct ptp_ocp_ext_info) {
769 .index = 0,
770 .irq_fcn = ptp_ocp_ts_irq,
771 .enable = ptp_ocp_ts_enable,
772 },
773 },
774 {
775 OCP_EXT_RESOURCE(ts1),
776 .offset = 0x380000, .size = 0x20, .irq_vec = 8,
777 .extra = &(struct ptp_ocp_ext_info) {
778 .index = 1,
779 .irq_fcn = ptp_ocp_ts_irq,
780 .enable = ptp_ocp_ts_enable,
781 },
782 },
783 {
784 OCP_EXT_RESOURCE(ts2),
785 .offset = 0x390000, .size = 0x20, .irq_vec = 10,
786 .extra = &(struct ptp_ocp_ext_info) {
787 .index = 2,
788 .irq_fcn = ptp_ocp_ts_irq,
789 .enable = ptp_ocp_ts_enable,
790 },
791 },
792 {
793 OCP_EXT_RESOURCE(ts3),
794 .offset = 0x3A0000, .size = 0x20, .irq_vec = 14,
795 .extra = &(struct ptp_ocp_ext_info) {
796 .index = 3,
797 .irq_fcn = ptp_ocp_ts_irq,
798 .enable = ptp_ocp_ts_enable,
799 },
800 },
801 {
802 OCP_EXT_RESOURCE(ts4),
803 .offset = 0x3B0000, .size = 0x20, .irq_vec = 15,
804 .extra = &(struct ptp_ocp_ext_info) {
805 .index = 4,
806 .irq_fcn = ptp_ocp_ts_irq,
807 .enable = ptp_ocp_ts_enable,
808 },
809 },
810 /* Timestamp associated with Internal PPS of the card */
811 {
812 OCP_EXT_RESOURCE(pps),
813 .offset = 0x00330000, .size = 0x20, .irq_vec = 11,
814 .extra = &(struct ptp_ocp_ext_info) {
815 .index = 5,
816 .irq_fcn = ptp_ocp_ts_irq,
817 .enable = ptp_ocp_ts_enable,
818 },
819 },
820 {
821 OCP_SPI_RESOURCE(spi_flash),
822 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
823 .extra = &(struct ptp_ocp_flash_info) {
824 .name = "spi_altera", .pci_offset = 0,
825 .data_size = sizeof(struct altera_spi_platform_data),
826 .data = &(struct altera_spi_platform_data) {
827 .num_chipselect = 1,
828 .num_devices = 1,
829 .devices = &(struct spi_board_info) {
830 .modalias = "spi-nor",
831 },
832 },
833 },
834 },
835 {
836 OCP_I2C_RESOURCE(i2c_ctrl),
837 .offset = 0x350000, .size = 0x100, .irq_vec = 4,
838 .extra = &(struct ptp_ocp_i2c_info) {
839 .name = "ocores-i2c",
840 .fixed_rate = 400000,
841 .data_size = sizeof(struct ocores_i2c_platform_data),
842 .data = &(struct ocores_i2c_platform_data) {
843 .clock_khz = 125000,
844 .bus_khz = 400,
845 .num_devices = 1,
846 .devices = &(struct i2c_board_info) {
847 I2C_BOARD_INFO("24c08", 0x50),
848 },
849 },
850 },
851 },
852 {
853 OCP_SERIAL_RESOURCE(port[PORT_MAC]),
854 .offset = 0x00190000, .irq_vec = 7,
855 .extra = &(struct ptp_ocp_serial_port) {
856 .baud = 9600,
857 },
858 },
859 {
860 OCP_MEM_RESOURCE(board_config),
861 .offset = 0x210000, .size = 0x1000,
862 },
863 {
864 .setup = ptp_ocp_art_board_init,
865 .extra = &(struct ptp_ocp_servo_conf) {
866 .servo_offset_p = 0x2000,
867 .servo_offset_i = 0x1000,
868 .servo_drift_p = 0,
869 .servo_drift_i = 0,
870 },
871 },
872 { }
873 };
874
875 static struct ocp_resource ocp_adva_resource[] = {
876 {
877 OCP_MEM_RESOURCE(reg),
878 .offset = 0x01000000, .size = 0x10000,
879 },
880 {
881 OCP_EXT_RESOURCE(ts0),
882 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
883 .extra = &(struct ptp_ocp_ext_info) {
884 .index = 0,
885 .irq_fcn = ptp_ocp_ts_irq,
886 .enable = ptp_ocp_ts_enable,
887 },
888 },
889 {
890 OCP_EXT_RESOURCE(ts1),
891 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
892 .extra = &(struct ptp_ocp_ext_info) {
893 .index = 1,
894 .irq_fcn = ptp_ocp_ts_irq,
895 .enable = ptp_ocp_ts_enable,
896 },
897 },
898 {
899 OCP_EXT_RESOURCE(ts2),
900 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
901 .extra = &(struct ptp_ocp_ext_info) {
902 .index = 2,
903 .irq_fcn = ptp_ocp_ts_irq,
904 .enable = ptp_ocp_ts_enable,
905 },
906 },
907 /* Timestamp for PHC and/or PPS generator */
908 {
909 OCP_EXT_RESOURCE(pps),
910 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
911 .extra = &(struct ptp_ocp_ext_info) {
912 .index = 5,
913 .irq_fcn = ptp_ocp_ts_irq,
914 .enable = ptp_ocp_ts_enable,
915 },
916 },
917 {
918 OCP_EXT_RESOURCE(signal_out[0]),
919 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
920 .extra = &(struct ptp_ocp_ext_info) {
921 .index = 1,
922 .irq_fcn = ptp_ocp_signal_irq,
923 .enable = ptp_ocp_signal_enable,
924 },
925 },
926 {
927 OCP_EXT_RESOURCE(signal_out[1]),
928 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
929 .extra = &(struct ptp_ocp_ext_info) {
930 .index = 2,
931 .irq_fcn = ptp_ocp_signal_irq,
932 .enable = ptp_ocp_signal_enable,
933 },
934 },
935 {
936 OCP_MEM_RESOURCE(pps_to_ext),
937 .offset = 0x01030000, .size = 0x10000,
938 },
939 {
940 OCP_MEM_RESOURCE(pps_to_clk),
941 .offset = 0x01040000, .size = 0x10000,
942 },
943 {
944 OCP_MEM_RESOURCE(tod),
945 .offset = 0x01050000, .size = 0x10000,
946 },
947 {
948 OCP_MEM_RESOURCE(image),
949 .offset = 0x00020000, .size = 0x1000,
950 },
951 {
952 OCP_MEM_RESOURCE(pps_select),
953 .offset = 0x00130000, .size = 0x1000,
954 },
955 {
956 OCP_MEM_RESOURCE(sma_map1),
957 .offset = 0x00140000, .size = 0x1000,
958 },
959 {
960 OCP_MEM_RESOURCE(sma_map2),
961 .offset = 0x00220000, .size = 0x1000,
962 },
963 {
964 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
965 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
966 .extra = &(struct ptp_ocp_serial_port) {
967 .baud = 9600,
968 },
969 },
970 {
971 OCP_SERIAL_RESOURCE(port[PORT_MAC]),
972 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
973 .extra = &(struct ptp_ocp_serial_port) {
974 .baud = 115200,
975 },
976 },
977 {
978 OCP_MEM_RESOURCE(freq_in[0]),
979 .offset = 0x01200000, .size = 0x10000,
980 },
981 {
982 OCP_MEM_RESOURCE(freq_in[1]),
983 .offset = 0x01210000, .size = 0x10000,
984 },
985 {
986 OCP_SPI_RESOURCE(spi_flash),
987 .offset = 0x00310400, .size = 0x10000, .irq_vec = 9,
988 .extra = &(struct ptp_ocp_flash_info) {
989 .name = "spi_altera", .pci_offset = 0,
990 .data_size = sizeof(struct altera_spi_platform_data),
991 .data = &(struct altera_spi_platform_data) {
992 .num_chipselect = 1,
993 .num_devices = 1,
994 .devices = &(struct spi_board_info) {
995 .modalias = "spi-nor",
996 },
997 },
998 },
999 },
1000 {
1001 OCP_I2C_RESOURCE(i2c_ctrl),
1002 .offset = 0x150000, .size = 0x100, .irq_vec = 7,
1003 .extra = &(struct ptp_ocp_i2c_info) {
1004 .name = "ocores-i2c",
1005 .fixed_rate = 50000000,
1006 .data_size = sizeof(struct ocores_i2c_platform_data),
1007 .data = &(struct ocores_i2c_platform_data) {
1008 .clock_khz = 50000,
1009 .bus_khz = 100,
1010 .reg_io_width = 4, // 32-bit/4-byte
1011 .reg_shift = 2, // 32-bit addressing
1012 .num_devices = 2,
1013 .devices = (struct i2c_board_info[]) {
1014 { I2C_BOARD_INFO("24c02", 0x50) },
1015 { I2C_BOARD_INFO("24mac402", 0x58),
1016 .platform_data = "mac" },
1017 },
1018 },
1019 },
1020 },
1021 {
1022 .setup = ptp_ocp_adva_board_init,
1023 .extra = &(struct ptp_ocp_servo_conf) {
1024 .servo_offset_p = 0xc000,
1025 .servo_offset_i = 0x1000,
1026 .servo_drift_p = 0,
1027 .servo_drift_i = 0,
1028 },
1029 },
1030 { }
1031 };
1032
1033 static const struct pci_device_id ptp_ocp_pcidev_id[] = {
1034 { PCI_DEVICE_DATA(META, TIMECARD, &ocp_fb_resource) },
1035 { PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) },
1036 { PCI_DEVICE_DATA(OROLIA, ARTCARD, &ocp_art_resource) },
1037 { PCI_DEVICE_DATA(ADVA, TIMECARD, &ocp_adva_resource) },
1038 { }
1039 };
1040 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);
1041
1042 static DEFINE_MUTEX(ptp_ocp_lock);
1043 static DEFINE_IDR(ptp_ocp_idr);
1044
1045 struct ocp_selector {
1046 const char *name;
1047 int value;
1048 u64 frequency;
1049 };
1050
1051 static const struct ocp_selector ptp_ocp_clock[] = {
1052 { .name = "NONE", .value = 0 },
1053 { .name = "TOD", .value = 1 },
1054 { .name = "IRIG", .value = 2 },
1055 { .name = "PPS", .value = 3 },
1056 { .name = "PTP", .value = 4 },
1057 { .name = "RTC", .value = 5 },
1058 { .name = "DCF", .value = 6 },
1059 { .name = "REGS", .value = 0xfe },
1060 { .name = "EXT", .value = 0xff },
1061 { }
1062 };
1063
1064 #define SMA_DISABLE BIT(16)
1065 #define SMA_ENABLE BIT(15)
1066 #define SMA_SELECT_MASK GENMASK(14, 0)
1067
1068 static const struct ocp_selector ptp_ocp_sma_in[] = {
1069 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
1070 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1071 { .name = "PPS2", .value = 0x0002, .frequency = 1 },
1072 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1073 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1074 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },
1075 { .name = "DCF", .value = 0x0020, .frequency = 77500 },
1076 { .name = "TS3", .value = 0x0040, .frequency = 0 },
1077 { .name = "TS4", .value = 0x0080, .frequency = 0 },
1078 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1079 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1080 { .name = "FREQ3", .value = 0x0400, .frequency = 0 },
1081 { .name = "FREQ4", .value = 0x0800, .frequency = 0 },
1082 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1083 { }
1084 };
1085
1086 static const struct ocp_selector ptp_ocp_sma_out[] = {
1087 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
1088 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1089 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1090 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1091 { .name = "GNSS2", .value = 0x0008, .frequency = 1 },
1092 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },
1093 { .name = "DCF", .value = 0x0020, .frequency = 77000 },
1094 { .name = "GEN1", .value = 0x0040 },
1095 { .name = "GEN2", .value = 0x0080 },
1096 { .name = "GEN3", .value = 0x0100 },
1097 { .name = "GEN4", .value = 0x0200 },
1098 { .name = "GND", .value = 0x2000 },
1099 { .name = "VCC", .value = 0x4000 },
1100 { }
1101 };
1102
1103 static const struct ocp_selector ptp_ocp_art_sma_in[] = {
1104 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1105 { .name = "10Mhz", .value = 0x0008, .frequency = 1000000 },
1106 { }
1107 };
1108
1109 static const struct ocp_selector ptp_ocp_art_sma_out[] = {
1110 { .name = "PHC", .value = 0x0002, .frequency = 1 },
1111 { .name = "GNSS", .value = 0x0004, .frequency = 1 },
1112 { .name = "10Mhz", .value = 0x0010, .frequency = 10000000 },
1113 { }
1114 };
1115
1116 static const struct ocp_selector ptp_ocp_adva_sma_in[] = {
1117 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1118 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1119 { .name = "PPS2", .value = 0x0002, .frequency = 1 },
1120 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1121 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1122 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1123 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1124 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1125 { }
1126 };
1127
1128 static const struct ocp_selector ptp_ocp_adva_sma_out[] = {
1129 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1130 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1131 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1132 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1133 { .name = "GEN1", .value = 0x0040 },
1134 { .name = "GEN2", .value = 0x0080 },
1135 { .name = "GND", .value = 0x2000 },
1136 { .name = "VCC", .value = 0x4000 },
1137 { }
1138 };
1139
1140 struct ocp_sma_op {
1141 const struct ocp_selector *tbl[2];
1142 void (*init)(struct ptp_ocp *bp);
1143 u32 (*get)(struct ptp_ocp *bp, int sma_nr);
1144 int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val);
1145 int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val);
1146 };
1147
1148 static void
ptp_ocp_sma_init(struct ptp_ocp * bp)1149 ptp_ocp_sma_init(struct ptp_ocp *bp)
1150 {
1151 return bp->sma_op->init(bp);
1152 }
1153
1154 static u32
ptp_ocp_sma_get(struct ptp_ocp * bp,int sma_nr)1155 ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr)
1156 {
1157 return bp->sma_op->get(bp, sma_nr);
1158 }
1159
1160 static int
ptp_ocp_sma_set_inputs(struct ptp_ocp * bp,int sma_nr,u32 val)1161 ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
1162 {
1163 return bp->sma_op->set_inputs(bp, sma_nr, val);
1164 }
1165
1166 static int
ptp_ocp_sma_set_output(struct ptp_ocp * bp,int sma_nr,u32 val)1167 ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
1168 {
1169 return bp->sma_op->set_output(bp, sma_nr, val);
1170 }
1171
1172 static const char *
ptp_ocp_select_name_from_val(const struct ocp_selector * tbl,int val)1173 ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val)
1174 {
1175 int i;
1176
1177 for (i = 0; tbl[i].name; i++)
1178 if (tbl[i].value == val)
1179 return tbl[i].name;
1180 return NULL;
1181 }
1182
1183 static int
ptp_ocp_select_val_from_name(const struct ocp_selector * tbl,const char * name)1184 ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name)
1185 {
1186 const char *select;
1187 int i;
1188
1189 for (i = 0; tbl[i].name; i++) {
1190 select = tbl[i].name;
1191 if (!strncasecmp(name, select, strlen(select)))
1192 return tbl[i].value;
1193 }
1194 return -EINVAL;
1195 }
1196
1197 static ssize_t
ptp_ocp_select_table_show(const struct ocp_selector * tbl,char * buf)1198 ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf)
1199 {
1200 ssize_t count;
1201 int i;
1202
1203 count = 0;
1204 for (i = 0; tbl[i].name; i++)
1205 count += sysfs_emit_at(buf, count, "%s ", tbl[i].name);
1206 if (count)
1207 count--;
1208 count += sysfs_emit_at(buf, count, "\n");
1209 return count;
1210 }
1211
1212 static int
__ptp_ocp_gettime_locked(struct ptp_ocp * bp,struct timespec64 * ts,struct ptp_system_timestamp * sts)1213 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,
1214 struct ptp_system_timestamp *sts)
1215 {
1216 u32 ctrl, time_sec, time_ns;
1217 int i;
1218
1219 ptp_read_system_prets(sts);
1220
1221 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1222 iowrite32(ctrl, &bp->reg->ctrl);
1223
1224 for (i = 0; i < 100; i++) {
1225 ctrl = ioread32(&bp->reg->ctrl);
1226 if (ctrl & OCP_CTRL_READ_TIME_DONE)
1227 break;
1228 }
1229 ptp_read_system_postts(sts);
1230
1231 if (sts && bp->ts_window_adjust) {
1232 s64 ns = timespec64_to_ns(&sts->post_ts);
1233
1234 sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust);
1235 }
1236
1237 time_ns = ioread32(&bp->reg->time_ns);
1238 time_sec = ioread32(&bp->reg->time_sec);
1239
1240 ts->tv_sec = time_sec;
1241 ts->tv_nsec = time_ns;
1242
1243 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;
1244 }
1245
1246 static int
ptp_ocp_gettimex(struct ptp_clock_info * ptp_info,struct timespec64 * ts,struct ptp_system_timestamp * sts)1247 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,
1248 struct ptp_system_timestamp *sts)
1249 {
1250 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1251 unsigned long flags;
1252 int err;
1253
1254 spin_lock_irqsave(&bp->lock, flags);
1255 err = __ptp_ocp_gettime_locked(bp, ts, sts);
1256 spin_unlock_irqrestore(&bp->lock, flags);
1257
1258 return err;
1259 }
1260
1261 static void
__ptp_ocp_settime_locked(struct ptp_ocp * bp,const struct timespec64 * ts)1262 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)
1263 {
1264 u32 ctrl, time_sec, time_ns;
1265 u32 select;
1266
1267 time_ns = ts->tv_nsec;
1268 time_sec = ts->tv_sec;
1269
1270 select = ioread32(&bp->reg->select);
1271 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1272
1273 iowrite32(time_ns, &bp->reg->adjust_ns);
1274 iowrite32(time_sec, &bp->reg->adjust_sec);
1275
1276 ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE;
1277 iowrite32(ctrl, &bp->reg->ctrl);
1278
1279 /* restore clock selection */
1280 iowrite32(select >> 16, &bp->reg->select);
1281 }
1282
1283 static int
ptp_ocp_settime(struct ptp_clock_info * ptp_info,const struct timespec64 * ts)1284 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)
1285 {
1286 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1287 unsigned long flags;
1288
1289 spin_lock_irqsave(&bp->lock, flags);
1290 __ptp_ocp_settime_locked(bp, ts);
1291 spin_unlock_irqrestore(&bp->lock, flags);
1292
1293 return 0;
1294 }
1295
1296 static void
__ptp_ocp_adjtime_locked(struct ptp_ocp * bp,u32 adj_val)1297 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val)
1298 {
1299 u32 select, ctrl;
1300
1301 select = ioread32(&bp->reg->select);
1302 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1303
1304 iowrite32(adj_val, &bp->reg->offset_ns);
1305 iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns);
1306
1307 ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE;
1308 iowrite32(ctrl, &bp->reg->ctrl);
1309
1310 /* restore clock selection */
1311 iowrite32(select >> 16, &bp->reg->select);
1312 }
1313
1314 static void
ptp_ocp_adjtime_coarse(struct ptp_ocp * bp,s64 delta_ns)1315 ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns)
1316 {
1317 struct timespec64 ts;
1318 unsigned long flags;
1319 int err;
1320
1321 spin_lock_irqsave(&bp->lock, flags);
1322 err = __ptp_ocp_gettime_locked(bp, &ts, NULL);
1323 if (likely(!err)) {
1324 set_normalized_timespec64(&ts, ts.tv_sec,
1325 ts.tv_nsec + delta_ns);
1326 __ptp_ocp_settime_locked(bp, &ts);
1327 }
1328 spin_unlock_irqrestore(&bp->lock, flags);
1329 }
1330
1331 static int
ptp_ocp_adjtime(struct ptp_clock_info * ptp_info,s64 delta_ns)1332 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)
1333 {
1334 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1335 unsigned long flags;
1336 u32 adj_ns, sign;
1337
1338 if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) {
1339 ptp_ocp_adjtime_coarse(bp, delta_ns);
1340 return 0;
1341 }
1342
1343 sign = delta_ns < 0 ? BIT(31) : 0;
1344 adj_ns = sign ? -delta_ns : delta_ns;
1345
1346 spin_lock_irqsave(&bp->lock, flags);
1347 __ptp_ocp_adjtime_locked(bp, sign | adj_ns);
1348 spin_unlock_irqrestore(&bp->lock, flags);
1349
1350 return 0;
1351 }
1352
1353 static int
ptp_ocp_null_adjfine(struct ptp_clock_info * ptp_info,long scaled_ppm)1354 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
1355 {
1356 if (scaled_ppm == 0)
1357 return 0;
1358
1359 return -EOPNOTSUPP;
1360 }
1361
1362 static s32
ptp_ocp_null_getmaxphase(struct ptp_clock_info * ptp_info)1363 ptp_ocp_null_getmaxphase(struct ptp_clock_info *ptp_info)
1364 {
1365 return 0;
1366 }
1367
1368 static int
ptp_ocp_null_adjphase(struct ptp_clock_info * ptp_info,s32 phase_ns)1369 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)
1370 {
1371 return -EOPNOTSUPP;
1372 }
1373
1374 static int
ptp_ocp_enable(struct ptp_clock_info * ptp_info,struct ptp_clock_request * rq,int on)1375 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq,
1376 int on)
1377 {
1378 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1379 struct ptp_ocp_ext_src *ext = NULL;
1380 u32 req;
1381 int err;
1382
1383 switch (rq->type) {
1384 case PTP_CLK_REQ_EXTTS:
1385 req = OCP_REQ_TIMESTAMP;
1386 switch (rq->extts.index) {
1387 case 0:
1388 ext = bp->ts0;
1389 break;
1390 case 1:
1391 ext = bp->ts1;
1392 break;
1393 case 2:
1394 ext = bp->ts2;
1395 break;
1396 case 3:
1397 ext = bp->ts3;
1398 break;
1399 case 4:
1400 ext = bp->ts4;
1401 break;
1402 case 5:
1403 ext = bp->pps;
1404 break;
1405 }
1406 break;
1407 case PTP_CLK_REQ_PPS:
1408 req = OCP_REQ_PPS;
1409 ext = bp->pps;
1410 break;
1411 case PTP_CLK_REQ_PEROUT:
1412 switch (rq->perout.index) {
1413 case 0:
1414 /* This is a request for 1PPS on an output SMA.
1415 * Allow, but assume manual configuration.
1416 */
1417 if (on && (rq->perout.period.sec != 1 ||
1418 rq->perout.period.nsec != 0))
1419 return -EINVAL;
1420 return 0;
1421 case 1:
1422 case 2:
1423 case 3:
1424 case 4:
1425 req = rq->perout.index - 1;
1426 ext = bp->signal_out[req];
1427 err = ptp_ocp_signal_from_perout(bp, req, &rq->perout);
1428 if (err)
1429 return err;
1430 break;
1431 }
1432 break;
1433 default:
1434 return -EOPNOTSUPP;
1435 }
1436
1437 err = -ENXIO;
1438 if (ext)
1439 err = ext->info->enable(ext, req, on);
1440
1441 return err;
1442 }
1443
1444 static int
ptp_ocp_verify(struct ptp_clock_info * ptp_info,unsigned pin,enum ptp_pin_function func,unsigned chan)1445 ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin,
1446 enum ptp_pin_function func, unsigned chan)
1447 {
1448 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1449 char buf[16];
1450
1451 switch (func) {
1452 case PTP_PF_NONE:
1453 snprintf(buf, sizeof(buf), "IN: None");
1454 break;
1455 case PTP_PF_EXTTS:
1456 /* Allow timestamps, but require sysfs configuration. */
1457 return 0;
1458 case PTP_PF_PEROUT:
1459 /* channel 0 is 1PPS from PHC.
1460 * channels 1..4 are the frequency generators.
1461 */
1462 if (chan)
1463 snprintf(buf, sizeof(buf), "OUT: GEN%d", chan);
1464 else
1465 snprintf(buf, sizeof(buf), "OUT: PHC");
1466 break;
1467 default:
1468 return -EOPNOTSUPP;
1469 }
1470
1471 return ptp_ocp_sma_store(bp, buf, pin + 1);
1472 }
1473
1474 static const struct ptp_clock_info ptp_ocp_clock_info = {
1475 .owner = THIS_MODULE,
1476 .name = KBUILD_MODNAME,
1477 .max_adj = 100000000,
1478 .gettimex64 = ptp_ocp_gettimex,
1479 .settime64 = ptp_ocp_settime,
1480 .adjtime = ptp_ocp_adjtime,
1481 .adjfine = ptp_ocp_null_adjfine,
1482 .adjphase = ptp_ocp_null_adjphase,
1483 .getmaxphase = ptp_ocp_null_getmaxphase,
1484 .enable = ptp_ocp_enable,
1485 .verify = ptp_ocp_verify,
1486 .pps = true,
1487 .n_ext_ts = 6,
1488 .n_per_out = 5,
1489 .supported_extts_flags = PTP_STRICT_FLAGS | PTP_RISING_EDGE,
1490 .supported_perout_flags = PTP_PEROUT_DUTY_CYCLE | PTP_PEROUT_PHASE,
1491 };
1492
1493 static void
__ptp_ocp_clear_drift_locked(struct ptp_ocp * bp)1494 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp)
1495 {
1496 u32 ctrl, select;
1497
1498 select = ioread32(&bp->reg->select);
1499 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1500
1501 iowrite32(0, &bp->reg->drift_ns);
1502
1503 ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE;
1504 iowrite32(ctrl, &bp->reg->ctrl);
1505
1506 /* restore clock selection */
1507 iowrite32(select >> 16, &bp->reg->select);
1508 }
1509
1510 static void
ptp_ocp_utc_distribute(struct ptp_ocp * bp,u32 val)1511 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val)
1512 {
1513 unsigned long flags;
1514
1515 spin_lock_irqsave(&bp->lock, flags);
1516
1517 bp->utc_tai_offset = val;
1518
1519 if (bp->irig_out)
1520 iowrite32(val, &bp->irig_out->adj_sec);
1521 if (bp->dcf_out)
1522 iowrite32(val, &bp->dcf_out->adj_sec);
1523 if (bp->nmea_out)
1524 iowrite32(val, &bp->nmea_out->adj_sec);
1525
1526 spin_unlock_irqrestore(&bp->lock, flags);
1527 }
1528
1529 static void
ptp_ocp_watchdog(struct timer_list * t)1530 ptp_ocp_watchdog(struct timer_list *t)
1531 {
1532 struct ptp_ocp *bp = timer_container_of(bp, t, watchdog);
1533 unsigned long flags;
1534 u32 status, utc_offset;
1535
1536 status = ioread32(&bp->pps_to_clk->status);
1537
1538 if (status & PPS_STATUS_SUPERV_ERR) {
1539 iowrite32(status, &bp->pps_to_clk->status);
1540 if (!bp->gnss_lost) {
1541 spin_lock_irqsave(&bp->lock, flags);
1542 __ptp_ocp_clear_drift_locked(bp);
1543 spin_unlock_irqrestore(&bp->lock, flags);
1544 bp->gnss_lost = ktime_get_real_seconds();
1545 }
1546
1547 } else if (bp->gnss_lost) {
1548 bp->gnss_lost = 0;
1549 }
1550
1551 /* if GNSS provides correct data we can rely on
1552 * it to get leap second information
1553 */
1554 if (bp->tod) {
1555 status = ioread32(&bp->tod->utc_status);
1556 utc_offset = status & TOD_STATUS_UTC_MASK;
1557 if (status & TOD_STATUS_UTC_VALID &&
1558 utc_offset != bp->utc_tai_offset)
1559 ptp_ocp_utc_distribute(bp, utc_offset);
1560 }
1561
1562 mod_timer(&bp->watchdog, jiffies + HZ);
1563 }
1564
1565 static void
ptp_ocp_estimate_pci_timing(struct ptp_ocp * bp)1566 ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp)
1567 {
1568 ktime_t start, end, delay = U64_MAX;
1569 u32 ctrl;
1570 int i;
1571
1572 for (i = 0; i < 3; i++) {
1573 ctrl = ioread32(&bp->reg->ctrl);
1574 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1575
1576 iowrite32(ctrl, &bp->reg->ctrl);
1577
1578 start = ktime_get_raw_ns();
1579
1580 ctrl = ioread32(&bp->reg->ctrl);
1581
1582 end = ktime_get_raw_ns();
1583
1584 delay = min(delay, end - start);
1585 }
1586 bp->ts_window_adjust = (delay >> 5) * 3;
1587 }
1588
1589 static int
ptp_ocp_init_clock(struct ptp_ocp * bp,struct ptp_ocp_servo_conf * servo_conf)1590 ptp_ocp_init_clock(struct ptp_ocp *bp, struct ptp_ocp_servo_conf *servo_conf)
1591 {
1592 struct timespec64 ts;
1593 u32 ctrl;
1594
1595 ctrl = OCP_CTRL_ENABLE;
1596 iowrite32(ctrl, &bp->reg->ctrl);
1597
1598 /* servo configuration */
1599 iowrite32(servo_conf->servo_offset_p, &bp->reg->servo_offset_p);
1600 iowrite32(servo_conf->servo_offset_i, &bp->reg->servo_offset_i);
1601 iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_p);
1602 iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_i);
1603
1604 /* latch servo values */
1605 ctrl |= OCP_CTRL_ADJUST_SERVO;
1606 iowrite32(ctrl, &bp->reg->ctrl);
1607
1608 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {
1609 dev_err(&bp->pdev->dev, "clock not enabled\n");
1610 return -ENODEV;
1611 }
1612
1613 ptp_ocp_estimate_pci_timing(bp);
1614
1615 bp->sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
1616 if (!bp->sync) {
1617 ktime_get_clocktai_ts64(&ts);
1618 ptp_ocp_settime(&bp->ptp_info, &ts);
1619 }
1620
1621 /* If there is a clock supervisor, then enable the watchdog */
1622 if (bp->pps_to_clk) {
1623 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0);
1624 mod_timer(&bp->watchdog, jiffies + HZ);
1625 }
1626
1627 return 0;
1628 }
1629
1630 static void
ptp_ocp_tod_init(struct ptp_ocp * bp)1631 ptp_ocp_tod_init(struct ptp_ocp *bp)
1632 {
1633 u32 ctrl, reg;
1634
1635 ctrl = ioread32(&bp->tod->ctrl);
1636 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;
1637 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);
1638 iowrite32(ctrl, &bp->tod->ctrl);
1639
1640 reg = ioread32(&bp->tod->utc_status);
1641 if (reg & TOD_STATUS_UTC_VALID)
1642 ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK);
1643 }
1644
1645 static const char *
ptp_ocp_tod_proto_name(const int idx)1646 ptp_ocp_tod_proto_name(const int idx)
1647 {
1648 static const char * const proto_name[] = {
1649 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",
1650 "UBX", "UBX_UTC", "UBX_LS", "UBX_none"
1651 };
1652 return proto_name[idx];
1653 }
1654
1655 static const char *
ptp_ocp_tod_gnss_name(int idx)1656 ptp_ocp_tod_gnss_name(int idx)
1657 {
1658 static const char * const gnss_name[] = {
1659 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",
1660 "Unknown"
1661 };
1662 if (idx >= ARRAY_SIZE(gnss_name))
1663 idx = ARRAY_SIZE(gnss_name) - 1;
1664 return gnss_name[idx];
1665 }
1666
1667 static const char *
ptp_ocp_tty_port_name(int idx)1668 ptp_ocp_tty_port_name(int idx)
1669 {
1670 static const char * const tty_name[] = {
1671 "GNSS", "GNSS2", "MAC", "NMEA"
1672 };
1673 return tty_name[idx];
1674 }
1675
1676 struct ptp_ocp_nvmem_match_info {
1677 struct ptp_ocp *bp;
1678 const void * const tag;
1679 };
1680
1681 static int
ptp_ocp_nvmem_match(struct device * dev,const void * data)1682 ptp_ocp_nvmem_match(struct device *dev, const void *data)
1683 {
1684 const struct ptp_ocp_nvmem_match_info *info = data;
1685
1686 dev = dev->parent;
1687 if (!i2c_verify_client(dev) || info->tag != dev->platform_data)
1688 return 0;
1689
1690 while ((dev = dev->parent))
1691 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
1692 return info->bp == dev_get_drvdata(dev);
1693 return 0;
1694 }
1695
1696 static inline struct nvmem_device *
ptp_ocp_nvmem_device_get(struct ptp_ocp * bp,const void * const tag)1697 ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag)
1698 {
1699 struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag };
1700
1701 return nvmem_device_find(&info, ptp_ocp_nvmem_match);
1702 }
1703
1704 static inline void
ptp_ocp_nvmem_device_put(struct nvmem_device ** nvmemp)1705 ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp)
1706 {
1707 if (!IS_ERR_OR_NULL(*nvmemp))
1708 nvmem_device_put(*nvmemp);
1709 *nvmemp = NULL;
1710 }
1711
1712 static void
ptp_ocp_read_eeprom(struct ptp_ocp * bp)1713 ptp_ocp_read_eeprom(struct ptp_ocp *bp)
1714 {
1715 const struct ptp_ocp_eeprom_map *map;
1716 struct nvmem_device *nvmem;
1717 const void *tag;
1718 int ret;
1719
1720 if (!bp->i2c_ctrl)
1721 return;
1722
1723 tag = NULL;
1724 nvmem = NULL;
1725
1726 for (map = bp->eeprom_map; map->len; map++) {
1727 if (map->tag != tag) {
1728 tag = map->tag;
1729 ptp_ocp_nvmem_device_put(&nvmem);
1730 }
1731 if (!nvmem) {
1732 nvmem = ptp_ocp_nvmem_device_get(bp, tag);
1733 if (IS_ERR(nvmem)) {
1734 ret = PTR_ERR(nvmem);
1735 goto fail;
1736 }
1737 }
1738 ret = nvmem_device_read(nvmem, map->off, map->len,
1739 BP_MAP_ENTRY_ADDR(bp, map));
1740 if (ret != map->len)
1741 goto fail;
1742 }
1743
1744 bp->has_eeprom_data = true;
1745
1746 out:
1747 ptp_ocp_nvmem_device_put(&nvmem);
1748 return;
1749
1750 fail:
1751 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret);
1752 goto out;
1753 }
1754
1755 static struct device *
ptp_ocp_find_flash(struct ptp_ocp * bp)1756 ptp_ocp_find_flash(struct ptp_ocp *bp)
1757 {
1758 struct device *dev, *last;
1759
1760 last = NULL;
1761 dev = &bp->spi_flash->dev;
1762
1763 while ((dev = device_find_any_child(dev))) {
1764 if (!strcmp("mtd", dev_bus_name(dev)))
1765 break;
1766 put_device(last);
1767 last = dev;
1768 }
1769 put_device(last);
1770
1771 return dev;
1772 }
1773
1774 static int
ptp_ocp_devlink_fw_image(struct devlink * devlink,const struct firmware * fw,const u8 ** data,size_t * size)1775 ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw,
1776 const u8 **data, size_t *size)
1777 {
1778 struct ptp_ocp *bp = devlink_priv(devlink);
1779 const struct ptp_ocp_firmware_header *hdr;
1780 size_t offset, length;
1781 u16 crc;
1782
1783 hdr = (const struct ptp_ocp_firmware_header *)fw->data;
1784 if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) {
1785 devlink_flash_update_status_notify(devlink,
1786 "No firmware header found, cancel firmware upgrade",
1787 NULL, 0, 0);
1788 return -EINVAL;
1789 }
1790
1791 if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor ||
1792 be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) {
1793 devlink_flash_update_status_notify(devlink,
1794 "Firmware image compatibility check failed",
1795 NULL, 0, 0);
1796 return -EINVAL;
1797 }
1798
1799 offset = sizeof(*hdr);
1800 length = be32_to_cpu(hdr->image_size);
1801 if (length != (fw->size - offset)) {
1802 devlink_flash_update_status_notify(devlink,
1803 "Firmware image size check failed",
1804 NULL, 0, 0);
1805 return -EINVAL;
1806 }
1807
1808 crc = crc16(0xffff, &fw->data[offset], length);
1809 if (be16_to_cpu(hdr->crc) != crc) {
1810 devlink_flash_update_status_notify(devlink,
1811 "Firmware image CRC check failed",
1812 NULL, 0, 0);
1813 return -EINVAL;
1814 }
1815
1816 *data = &fw->data[offset];
1817 *size = length;
1818
1819 return 0;
1820 }
1821
1822 static int
ptp_ocp_devlink_flash(struct devlink * devlink,struct device * dev,const struct firmware * fw)1823 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev,
1824 const struct firmware *fw)
1825 {
1826 struct mtd_info *mtd = dev_get_drvdata(dev);
1827 struct ptp_ocp *bp = devlink_priv(devlink);
1828 size_t off, len, size, resid, wrote;
1829 struct erase_info erase;
1830 size_t base, blksz;
1831 const u8 *data;
1832 int err;
1833
1834 err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size);
1835 if (err)
1836 goto out;
1837
1838 off = 0;
1839 base = bp->flash_start;
1840 blksz = 4096;
1841 resid = size;
1842
1843 while (resid) {
1844 devlink_flash_update_status_notify(devlink, "Flashing",
1845 NULL, off, size);
1846
1847 len = min_t(size_t, resid, blksz);
1848 erase.addr = base + off;
1849 erase.len = blksz;
1850
1851 err = mtd_erase(mtd, &erase);
1852 if (err)
1853 goto out;
1854
1855 err = mtd_write(mtd, base + off, len, &wrote, data + off);
1856 if (err)
1857 goto out;
1858
1859 off += blksz;
1860 resid -= len;
1861 }
1862 out:
1863 return err;
1864 }
1865
1866 static int
ptp_ocp_devlink_flash_update(struct devlink * devlink,struct devlink_flash_update_params * params,struct netlink_ext_ack * extack)1867 ptp_ocp_devlink_flash_update(struct devlink *devlink,
1868 struct devlink_flash_update_params *params,
1869 struct netlink_ext_ack *extack)
1870 {
1871 struct ptp_ocp *bp = devlink_priv(devlink);
1872 struct device *dev;
1873 const char *msg;
1874 int err;
1875
1876 dev = ptp_ocp_find_flash(bp);
1877 if (!dev) {
1878 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n");
1879 return -ENODEV;
1880 }
1881
1882 devlink_flash_update_status_notify(devlink, "Preparing to flash",
1883 NULL, 0, 0);
1884
1885 err = ptp_ocp_devlink_flash(devlink, dev, params->fw);
1886
1887 msg = err ? "Flash error" : "Flash complete";
1888 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0);
1889
1890 put_device(dev);
1891 return err;
1892 }
1893
1894 static int
ptp_ocp_devlink_info_get(struct devlink * devlink,struct devlink_info_req * req,struct netlink_ext_ack * extack)1895 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
1896 struct netlink_ext_ack *extack)
1897 {
1898 struct ptp_ocp *bp = devlink_priv(devlink);
1899 const char *fw_image;
1900 char buf[32];
1901 int err;
1902
1903 fw_image = bp->fw_loader ? "loader" : "fw";
1904 sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version);
1905 err = devlink_info_version_running_put(req, fw_image, buf);
1906 if (err)
1907 return err;
1908
1909 if (!bp->has_eeprom_data) {
1910 ptp_ocp_read_eeprom(bp);
1911 if (!bp->has_eeprom_data)
1912 return 0;
1913 }
1914
1915 sprintf(buf, "%pM", bp->serial);
1916 err = devlink_info_serial_number_put(req, buf);
1917 if (err)
1918 return err;
1919
1920 err = devlink_info_version_fixed_put(req,
1921 DEVLINK_INFO_VERSION_GENERIC_BOARD_ID,
1922 bp->board_id);
1923 if (err)
1924 return err;
1925
1926 return 0;
1927 }
1928
1929 static const struct devlink_ops ptp_ocp_devlink_ops = {
1930 .flash_update = ptp_ocp_devlink_flash_update,
1931 .info_get = ptp_ocp_devlink_info_get,
1932 };
1933
1934 static void __iomem *
__ptp_ocp_get_mem(struct ptp_ocp * bp,resource_size_t start,int size)1935 __ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size)
1936 {
1937 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp");
1938
1939 return devm_ioremap_resource(&bp->pdev->dev, &res);
1940 }
1941
1942 static void __iomem *
ptp_ocp_get_mem(struct ptp_ocp * bp,struct ocp_resource * r)1943 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r)
1944 {
1945 resource_size_t start;
1946
1947 start = pci_resource_start(bp->pdev, 0) + r->offset;
1948 return __ptp_ocp_get_mem(bp, start, r->size);
1949 }
1950
1951 static int
ptp_ocp_register_spi(struct ptp_ocp * bp,struct ocp_resource * r)1952 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r)
1953 {
1954 struct ptp_ocp_flash_info *info;
1955 struct pci_dev *pdev = bp->pdev;
1956 struct platform_device *p;
1957 struct resource res[2];
1958 resource_size_t start;
1959 int id;
1960
1961 start = pci_resource_start(pdev, 0) + r->offset;
1962 res[0] = DEFINE_RES_MEM(start, r->size);
1963 res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));
1964
1965 info = r->extra;
1966 id = pci_dev_id(pdev) << 1;
1967 id += info->pci_offset;
1968
1969 p = platform_device_register_resndata(&pdev->dev, info->name, id,
1970 res, ARRAY_SIZE(res), info->data,
1971 info->data_size);
1972 if (IS_ERR(p))
1973 return PTR_ERR(p);
1974
1975 bp_assign_entry(bp, r, p);
1976
1977 return 0;
1978 }
1979
1980 static struct platform_device *
ptp_ocp_i2c_bus(struct pci_dev * pdev,struct ocp_resource * r,int id)1981 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id)
1982 {
1983 struct ptp_ocp_i2c_info *info;
1984 struct resource res[2];
1985 resource_size_t start;
1986
1987 info = r->extra;
1988 start = pci_resource_start(pdev, 0) + r->offset;
1989 res[0] = DEFINE_RES_MEM(start, r->size);
1990 res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));
1991
1992 return platform_device_register_resndata(&pdev->dev, info->name,
1993 id, res, ARRAY_SIZE(res),
1994 info->data, info->data_size);
1995 }
1996
1997 static int
ptp_ocp_register_i2c(struct ptp_ocp * bp,struct ocp_resource * r)1998 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r)
1999 {
2000 struct pci_dev *pdev = bp->pdev;
2001 struct ptp_ocp_i2c_info *info;
2002 struct platform_device *p;
2003 struct clk_hw *clk;
2004 char buf[32];
2005 int id;
2006
2007 info = r->extra;
2008 id = pci_dev_id(bp->pdev);
2009
2010 sprintf(buf, "AXI.%d", id);
2011 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0,
2012 info->fixed_rate);
2013 if (IS_ERR(clk))
2014 return PTR_ERR(clk);
2015 bp->i2c_clk = clk;
2016
2017 sprintf(buf, "%s.%d", info->name, id);
2018 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf);
2019 p = ptp_ocp_i2c_bus(bp->pdev, r, id);
2020 if (IS_ERR(p))
2021 return PTR_ERR(p);
2022
2023 bp_assign_entry(bp, r, p);
2024
2025 return 0;
2026 }
2027
2028 /* The expectation is that this is triggered only on error. */
2029 static irqreturn_t
ptp_ocp_signal_irq(int irq,void * priv)2030 ptp_ocp_signal_irq(int irq, void *priv)
2031 {
2032 struct ptp_ocp_ext_src *ext = priv;
2033 struct signal_reg __iomem *reg = ext->mem;
2034 struct ptp_ocp *bp = ext->bp;
2035 u32 enable, status;
2036 int gen;
2037
2038 gen = ext->info->index - 1;
2039
2040 enable = ioread32(®->enable);
2041 status = ioread32(®->status);
2042
2043 /* disable generator on error */
2044 if (status || !enable) {
2045 iowrite32(0, ®->intr_mask);
2046 iowrite32(0, ®->enable);
2047 bp->signal[gen].running = false;
2048 }
2049
2050 iowrite32(0, ®->intr); /* ack interrupt */
2051
2052 return IRQ_HANDLED;
2053 }
2054
2055 static int
ptp_ocp_signal_set(struct ptp_ocp * bp,int gen,struct ptp_ocp_signal * s)2056 ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s)
2057 {
2058 struct ptp_system_timestamp sts;
2059 struct timespec64 ts;
2060 ktime_t start_ns;
2061 int err;
2062
2063 if (!s->period)
2064 return 0;
2065
2066 if (!s->pulse)
2067 s->pulse = ktime_divns(s->period * s->duty, 100);
2068
2069 err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts);
2070 if (err)
2071 return err;
2072
2073 start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC;
2074 if (!s->start) {
2075 /* roundup() does not work on 32-bit systems */
2076 s->start = DIV64_U64_ROUND_UP(start_ns, s->period);
2077 s->start *= s->period;
2078 s->start = ktime_add(s->start, s->phase);
2079 }
2080
2081 if (s->duty < 1 || s->duty > 99)
2082 return -EINVAL;
2083
2084 if (s->pulse < 1 || s->pulse > s->period)
2085 return -EINVAL;
2086
2087 if (s->start < start_ns)
2088 return -EINVAL;
2089
2090 bp->signal[gen] = *s;
2091
2092 return 0;
2093 }
2094
2095 static int
ptp_ocp_signal_from_perout(struct ptp_ocp * bp,int gen,struct ptp_perout_request * req)2096 ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
2097 struct ptp_perout_request *req)
2098 {
2099 struct ptp_ocp_signal s = { };
2100
2101 s.polarity = bp->signal[gen].polarity;
2102 s.period = ktime_set(req->period.sec, req->period.nsec);
2103 if (!s.period)
2104 return 0;
2105
2106 if (req->flags & PTP_PEROUT_DUTY_CYCLE) {
2107 s.pulse = ktime_set(req->on.sec, req->on.nsec);
2108 s.duty = ktime_divns(s.pulse * 100, s.period);
2109 }
2110
2111 if (req->flags & PTP_PEROUT_PHASE)
2112 s.phase = ktime_set(req->phase.sec, req->phase.nsec);
2113 else
2114 s.start = ktime_set(req->start.sec, req->start.nsec);
2115
2116 return ptp_ocp_signal_set(bp, gen, &s);
2117 }
2118
2119 static int
ptp_ocp_signal_enable(void * priv,u32 req,bool enable)2120 ptp_ocp_signal_enable(void *priv, u32 req, bool enable)
2121 {
2122 struct ptp_ocp_ext_src *ext = priv;
2123 struct signal_reg __iomem *reg = ext->mem;
2124 struct ptp_ocp *bp = ext->bp;
2125 struct timespec64 ts;
2126 int gen;
2127
2128 gen = ext->info->index - 1;
2129
2130 iowrite32(0, ®->intr_mask);
2131 iowrite32(0, ®->enable);
2132 bp->signal[gen].running = false;
2133 if (!enable)
2134 return 0;
2135
2136 ts = ktime_to_timespec64(bp->signal[gen].start);
2137 iowrite32(ts.tv_sec, ®->start_sec);
2138 iowrite32(ts.tv_nsec, ®->start_ns);
2139
2140 ts = ktime_to_timespec64(bp->signal[gen].period);
2141 iowrite32(ts.tv_sec, ®->period_sec);
2142 iowrite32(ts.tv_nsec, ®->period_ns);
2143
2144 ts = ktime_to_timespec64(bp->signal[gen].pulse);
2145 iowrite32(ts.tv_sec, ®->pulse_sec);
2146 iowrite32(ts.tv_nsec, ®->pulse_ns);
2147
2148 iowrite32(bp->signal[gen].polarity, ®->polarity);
2149 iowrite32(0, ®->repeat_count);
2150
2151 iowrite32(0, ®->intr); /* clear interrupt state */
2152 iowrite32(1, ®->intr_mask); /* enable interrupt */
2153 iowrite32(3, ®->enable); /* valid & enable */
2154
2155 bp->signal[gen].running = true;
2156
2157 return 0;
2158 }
2159
2160 static irqreturn_t
ptp_ocp_ts_irq(int irq,void * priv)2161 ptp_ocp_ts_irq(int irq, void *priv)
2162 {
2163 struct ptp_ocp_ext_src *ext = priv;
2164 struct ts_reg __iomem *reg = ext->mem;
2165 struct ptp_clock_event ev;
2166 u32 sec, nsec;
2167
2168 if (ext == ext->bp->pps) {
2169 if (ext->bp->pps_req_map & OCP_REQ_PPS) {
2170 ev.type = PTP_CLOCK_PPS;
2171 ptp_clock_event(ext->bp->ptp, &ev);
2172 }
2173
2174 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0)
2175 goto out;
2176 }
2177
2178 /* XXX should fix API - this converts s/ns -> ts -> s/ns */
2179 sec = ioread32(®->time_sec);
2180 nsec = ioread32(®->time_ns);
2181
2182 ev.type = PTP_CLOCK_EXTTS;
2183 ev.index = ext->info->index;
2184 ev.timestamp = sec * NSEC_PER_SEC + nsec;
2185
2186 ptp_clock_event(ext->bp->ptp, &ev);
2187
2188 out:
2189 iowrite32(1, ®->intr); /* write 1 to ack */
2190
2191 return IRQ_HANDLED;
2192 }
2193
2194 static int
ptp_ocp_ts_enable(void * priv,u32 req,bool enable)2195 ptp_ocp_ts_enable(void *priv, u32 req, bool enable)
2196 {
2197 struct ptp_ocp_ext_src *ext = priv;
2198 struct ts_reg __iomem *reg = ext->mem;
2199 struct ptp_ocp *bp = ext->bp;
2200
2201 if (ext == bp->pps) {
2202 u32 old_map = bp->pps_req_map;
2203
2204 if (enable)
2205 bp->pps_req_map |= req;
2206 else
2207 bp->pps_req_map &= ~req;
2208
2209 /* if no state change, just return */
2210 if ((!!old_map ^ !!bp->pps_req_map) == 0)
2211 return 0;
2212 }
2213
2214 if (enable) {
2215 iowrite32(1, ®->enable);
2216 iowrite32(1, ®->intr_mask);
2217 iowrite32(1, ®->intr);
2218 } else {
2219 iowrite32(0, ®->intr_mask);
2220 iowrite32(0, ®->enable);
2221 }
2222
2223 return 0;
2224 }
2225
2226 static void
ptp_ocp_unregister_ext(struct ptp_ocp_ext_src * ext)2227 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext)
2228 {
2229 if (!ext)
2230 return;
2231
2232 ext->info->enable(ext, ~0, false);
2233 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext);
2234 kfree(ext);
2235 }
2236
2237 static int
ptp_ocp_register_ext(struct ptp_ocp * bp,struct ocp_resource * r)2238 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r)
2239 {
2240 struct pci_dev *pdev = bp->pdev;
2241 struct ptp_ocp_ext_src *ext;
2242 int err;
2243
2244 ext = kzalloc_obj(*ext);
2245 if (!ext)
2246 return -ENOMEM;
2247
2248 ext->mem = ptp_ocp_get_mem(bp, r);
2249 if (IS_ERR(ext->mem)) {
2250 err = PTR_ERR(ext->mem);
2251 goto out;
2252 }
2253
2254 ext->bp = bp;
2255 ext->info = r->extra;
2256 ext->irq_vec = r->irq_vec;
2257
2258 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL,
2259 ext, "ocp%d.%s", bp->id, r->name);
2260 if (err) {
2261 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec);
2262 goto out;
2263 }
2264
2265 bp_assign_entry(bp, r, ext);
2266
2267 return 0;
2268
2269 out:
2270 kfree(ext);
2271 return err;
2272 }
2273
2274 static int
ptp_ocp_serial_line(struct ptp_ocp * bp,struct ocp_resource * r)2275 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r)
2276 {
2277 struct pci_dev *pdev = bp->pdev;
2278 struct uart_8250_port uart;
2279
2280 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets
2281 * the serial port device claim and release the pci resource.
2282 */
2283 memset(&uart, 0, sizeof(uart));
2284 uart.port.dev = &pdev->dev;
2285 uart.port.iotype = UPIO_MEM;
2286 uart.port.regshift = 2;
2287 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset;
2288 uart.port.irq = pci_irq_vector(pdev, r->irq_vec);
2289 uart.port.uartclk = 50000000;
2290 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST;
2291 uart.port.type = PORT_16550A;
2292
2293 return serial8250_register_8250_port(&uart);
2294 }
2295
2296 static int
ptp_ocp_register_serial(struct ptp_ocp * bp,struct ocp_resource * r)2297 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r)
2298 {
2299 struct ptp_ocp_serial_port *p = (struct ptp_ocp_serial_port *)r->extra;
2300 struct ptp_ocp_serial_port port = {};
2301
2302 port.line = ptp_ocp_serial_line(bp, r);
2303 if (port.line < 0)
2304 return port.line;
2305
2306 if (p)
2307 port.baud = p->baud;
2308
2309 bp_assign_entry(bp, r, port);
2310
2311 return 0;
2312 }
2313
2314 static int
ptp_ocp_register_mem(struct ptp_ocp * bp,struct ocp_resource * r)2315 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r)
2316 {
2317 void __iomem *mem;
2318
2319 mem = ptp_ocp_get_mem(bp, r);
2320 if (IS_ERR(mem))
2321 return PTR_ERR(mem);
2322
2323 bp_assign_entry(bp, r, mem);
2324
2325 return 0;
2326 }
2327
2328 static void
ptp_ocp_nmea_out_init(struct ptp_ocp * bp)2329 ptp_ocp_nmea_out_init(struct ptp_ocp *bp)
2330 {
2331 if (!bp->nmea_out)
2332 return;
2333
2334 iowrite32(0, &bp->nmea_out->ctrl); /* disable */
2335 iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */
2336 iowrite32(1, &bp->nmea_out->ctrl); /* enable */
2337 }
2338
2339 static void
_ptp_ocp_signal_init(struct ptp_ocp_signal * s,struct signal_reg __iomem * reg)2340 _ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg)
2341 {
2342 u32 val;
2343
2344 iowrite32(0, ®->enable); /* disable */
2345
2346 val = ioread32(®->polarity);
2347 s->polarity = val ? true : false;
2348 s->duty = 50;
2349 }
2350
2351 static void
ptp_ocp_signal_init(struct ptp_ocp * bp)2352 ptp_ocp_signal_init(struct ptp_ocp *bp)
2353 {
2354 int i;
2355
2356 for (i = 0; i < 4; i++)
2357 if (bp->signal_out[i])
2358 _ptp_ocp_signal_init(&bp->signal[i],
2359 bp->signal_out[i]->mem);
2360 }
2361
2362 static void
ptp_ocp_attr_group_del(struct ptp_ocp * bp)2363 ptp_ocp_attr_group_del(struct ptp_ocp *bp)
2364 {
2365 sysfs_remove_groups(&bp->dev.kobj, bp->attr_group);
2366 kfree(bp->attr_group);
2367 }
2368
2369 static int
ptp_ocp_attr_group_add(struct ptp_ocp * bp,const struct ocp_attr_group * attr_tbl)2370 ptp_ocp_attr_group_add(struct ptp_ocp *bp,
2371 const struct ocp_attr_group *attr_tbl)
2372 {
2373 int count, i;
2374 int err;
2375
2376 count = 0;
2377 for (i = 0; attr_tbl[i].cap; i++)
2378 if (attr_tbl[i].cap & bp->fw_cap)
2379 count++;
2380
2381 bp->attr_group = kzalloc_objs(*bp->attr_group, count + 1);
2382 if (!bp->attr_group)
2383 return -ENOMEM;
2384
2385 count = 0;
2386 for (i = 0; attr_tbl[i].cap; i++)
2387 if (attr_tbl[i].cap & bp->fw_cap)
2388 bp->attr_group[count++] = attr_tbl[i].group;
2389
2390 err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group);
2391 if (err)
2392 bp->attr_group[0] = NULL;
2393
2394 return err;
2395 }
2396
2397 static void
ptp_ocp_enable_fpga(u32 __iomem * reg,u32 bit,bool enable)2398 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable)
2399 {
2400 u32 ctrl;
2401 bool on;
2402
2403 ctrl = ioread32(reg);
2404 on = ctrl & bit;
2405 if (on ^ enable) {
2406 ctrl &= ~bit;
2407 ctrl |= enable ? bit : 0;
2408 iowrite32(ctrl, reg);
2409 }
2410 }
2411
2412 static void
ptp_ocp_irig_out(struct ptp_ocp * bp,bool enable)2413 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable)
2414 {
2415 return ptp_ocp_enable_fpga(&bp->irig_out->ctrl,
2416 IRIG_M_CTRL_ENABLE, enable);
2417 }
2418
2419 static void
ptp_ocp_irig_in(struct ptp_ocp * bp,bool enable)2420 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable)
2421 {
2422 return ptp_ocp_enable_fpga(&bp->irig_in->ctrl,
2423 IRIG_S_CTRL_ENABLE, enable);
2424 }
2425
2426 static void
ptp_ocp_dcf_out(struct ptp_ocp * bp,bool enable)2427 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable)
2428 {
2429 return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl,
2430 DCF_M_CTRL_ENABLE, enable);
2431 }
2432
2433 static void
ptp_ocp_dcf_in(struct ptp_ocp * bp,bool enable)2434 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable)
2435 {
2436 return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl,
2437 DCF_S_CTRL_ENABLE, enable);
2438 }
2439
2440 static void
__handle_signal_outputs(struct ptp_ocp * bp,u32 val)2441 __handle_signal_outputs(struct ptp_ocp *bp, u32 val)
2442 {
2443 ptp_ocp_irig_out(bp, val & 0x00100010);
2444 ptp_ocp_dcf_out(bp, val & 0x00200020);
2445 }
2446
2447 static void
__handle_signal_inputs(struct ptp_ocp * bp,u32 val)2448 __handle_signal_inputs(struct ptp_ocp *bp, u32 val)
2449 {
2450 ptp_ocp_irig_in(bp, val & 0x00100010);
2451 ptp_ocp_dcf_in(bp, val & 0x00200020);
2452 }
2453
2454 static u32
ptp_ocp_sma_fb_get(struct ptp_ocp * bp,int sma_nr)2455 ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr)
2456 {
2457 u32 __iomem *gpio;
2458 u32 shift;
2459
2460 if (bp->sma[sma_nr - 1].fixed_fcn)
2461 return (sma_nr - 1) & 1;
2462
2463 if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN)
2464 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2465 else
2466 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2467 shift = sma_nr & 1 ? 0 : 16;
2468
2469 return (ioread32(gpio) >> shift) & 0xffff;
2470 }
2471
2472 static int
ptp_ocp_sma_fb_set_output(struct ptp_ocp * bp,int sma_nr,u32 val)2473 ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2474 {
2475 u32 reg, mask, shift;
2476 unsigned long flags;
2477 u32 __iomem *gpio;
2478
2479 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2480 shift = sma_nr & 1 ? 0 : 16;
2481
2482 mask = 0xffff << (16 - shift);
2483
2484 spin_lock_irqsave(&bp->lock, flags);
2485
2486 reg = ioread32(gpio);
2487 reg = (reg & mask) | (val << shift);
2488
2489 __handle_signal_outputs(bp, reg);
2490
2491 iowrite32(reg, gpio);
2492
2493 spin_unlock_irqrestore(&bp->lock, flags);
2494
2495 return 0;
2496 }
2497
2498 static int
ptp_ocp_sma_fb_set_inputs(struct ptp_ocp * bp,int sma_nr,u32 val)2499 ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2500 {
2501 u32 reg, mask, shift;
2502 unsigned long flags;
2503 u32 __iomem *gpio;
2504
2505 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2506 shift = sma_nr & 1 ? 0 : 16;
2507
2508 mask = 0xffff << (16 - shift);
2509
2510 spin_lock_irqsave(&bp->lock, flags);
2511
2512 reg = ioread32(gpio);
2513 reg = (reg & mask) | (val << shift);
2514
2515 __handle_signal_inputs(bp, reg);
2516
2517 iowrite32(reg, gpio);
2518
2519 spin_unlock_irqrestore(&bp->lock, flags);
2520
2521 return 0;
2522 }
2523
2524 static void
ptp_ocp_sma_fb_init(struct ptp_ocp * bp)2525 ptp_ocp_sma_fb_init(struct ptp_ocp *bp)
2526 {
2527 struct dpll_pin_properties prop = {
2528 .board_label = NULL,
2529 .type = DPLL_PIN_TYPE_EXT,
2530 .capabilities = DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE,
2531 .freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
2532 .freq_supported = ptp_ocp_sma_freq,
2533
2534 };
2535 u32 reg;
2536 int i;
2537
2538 /* defaults */
2539 for (i = 0; i < OCP_SMA_NUM; i++) {
2540 bp->sma[i].default_fcn = i & 1;
2541 bp->sma[i].dpll_prop = prop;
2542 bp->sma[i].dpll_prop.board_label =
2543 bp->ptp_info.pin_config[i].name;
2544 }
2545 bp->sma[0].mode = SMA_MODE_IN;
2546 bp->sma[1].mode = SMA_MODE_IN;
2547 bp->sma[2].mode = SMA_MODE_OUT;
2548 bp->sma[3].mode = SMA_MODE_OUT;
2549 /* If no SMA1 map, the pin functions and directions are fixed. */
2550 if (!bp->sma_map1) {
2551 for (i = 0; i < OCP_SMA_NUM; i++) {
2552 bp->sma[i].fixed_fcn = true;
2553 bp->sma[i].fixed_dir = true;
2554 bp->sma[i].dpll_prop.capabilities &=
2555 ~DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2556 }
2557 return;
2558 }
2559
2560 /* If SMA2 GPIO output map is all 1, it is not present.
2561 * This indicates the firmware has fixed direction SMA pins.
2562 */
2563 reg = ioread32(&bp->sma_map2->gpio2);
2564 if (reg == 0xffffffff) {
2565 for (i = 0; i < OCP_SMA_NUM; i++)
2566 bp->sma[i].fixed_dir = true;
2567 } else {
2568 reg = ioread32(&bp->sma_map1->gpio1);
2569 bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT;
2570 bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT;
2571
2572 reg = ioread32(&bp->sma_map1->gpio2);
2573 bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN;
2574 bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN;
2575 }
2576 }
2577
2578 static const struct ocp_sma_op ocp_fb_sma_op = {
2579 .tbl = { ptp_ocp_sma_in, ptp_ocp_sma_out },
2580 .init = ptp_ocp_sma_fb_init,
2581 .get = ptp_ocp_sma_fb_get,
2582 .set_inputs = ptp_ocp_sma_fb_set_inputs,
2583 .set_output = ptp_ocp_sma_fb_set_output,
2584 };
2585
2586 static int
ptp_ocp_sma_adva_set_output(struct ptp_ocp * bp,int sma_nr,u32 val)2587 ptp_ocp_sma_adva_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2588 {
2589 u32 reg, mask, shift;
2590 unsigned long flags;
2591 u32 __iomem *gpio;
2592
2593 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2594 shift = sma_nr & 1 ? 0 : 16;
2595
2596 mask = 0xffff << (16 - shift);
2597
2598 spin_lock_irqsave(&bp->lock, flags);
2599
2600 reg = ioread32(gpio);
2601 reg = (reg & mask) | (val << shift);
2602
2603 iowrite32(reg, gpio);
2604
2605 spin_unlock_irqrestore(&bp->lock, flags);
2606
2607 return 0;
2608 }
2609
2610 static int
ptp_ocp_sma_adva_set_inputs(struct ptp_ocp * bp,int sma_nr,u32 val)2611 ptp_ocp_sma_adva_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2612 {
2613 u32 reg, mask, shift;
2614 unsigned long flags;
2615 u32 __iomem *gpio;
2616
2617 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2618 shift = sma_nr & 1 ? 0 : 16;
2619
2620 mask = 0xffff << (16 - shift);
2621
2622 spin_lock_irqsave(&bp->lock, flags);
2623
2624 reg = ioread32(gpio);
2625 reg = (reg & mask) | (val << shift);
2626
2627 iowrite32(reg, gpio);
2628
2629 spin_unlock_irqrestore(&bp->lock, flags);
2630
2631 return 0;
2632 }
2633
2634 static const struct ocp_sma_op ocp_adva_sma_op = {
2635 .tbl = { ptp_ocp_adva_sma_in, ptp_ocp_adva_sma_out },
2636 .init = ptp_ocp_sma_fb_init,
2637 .get = ptp_ocp_sma_fb_get,
2638 .set_inputs = ptp_ocp_sma_adva_set_inputs,
2639 .set_output = ptp_ocp_sma_adva_set_output,
2640 };
2641
2642 static int
ptp_ocp_set_pins(struct ptp_ocp * bp)2643 ptp_ocp_set_pins(struct ptp_ocp *bp)
2644 {
2645 struct ptp_pin_desc *config;
2646 int i;
2647
2648 config = kzalloc_objs(*config, 4);
2649 if (!config)
2650 return -ENOMEM;
2651
2652 for (i = 0; i < 4; i++) {
2653 sprintf(config[i].name, "sma%d", i + 1);
2654 config[i].index = i;
2655 }
2656
2657 bp->ptp_info.n_pins = 4;
2658 bp->ptp_info.pin_config = config;
2659
2660 return 0;
2661 }
2662
2663 static void
ptp_ocp_fb_set_version(struct ptp_ocp * bp)2664 ptp_ocp_fb_set_version(struct ptp_ocp *bp)
2665 {
2666 u64 cap = OCP_CAP_BASIC;
2667 u32 version;
2668
2669 version = ioread32(&bp->image->version);
2670
2671 /* if lower 16 bits are empty, this is the fw loader. */
2672 if ((version & 0xffff) == 0) {
2673 version = version >> 16;
2674 bp->fw_loader = true;
2675 }
2676
2677 bp->fw_tag = version >> 15;
2678 bp->fw_version = version & 0x7fff;
2679
2680 if (bp->fw_tag) {
2681 /* FPGA firmware */
2682 if (version >= 5)
2683 cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2684 } else {
2685 /* SOM firmware */
2686 if (version >= 19)
2687 cap |= OCP_CAP_SIGNAL;
2688 if (version >= 20)
2689 cap |= OCP_CAP_FREQ;
2690 }
2691
2692 bp->fw_cap = cap;
2693 }
2694
2695 /* FB specific board initializers; last "resource" registered. */
2696 static int
ptp_ocp_fb_board_init(struct ptp_ocp * bp,struct ocp_resource * r)2697 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2698 {
2699 int err;
2700
2701 bp->flash_start = 1024 * 4096;
2702 bp->eeprom_map = fb_eeprom_map;
2703 bp->fw_version = ioread32(&bp->image->version);
2704 bp->sma_op = &ocp_fb_sma_op;
2705 bp->signals_nr = 4;
2706 bp->freq_in_nr = 4;
2707
2708 ptp_ocp_fb_set_version(bp);
2709
2710 ptp_ocp_tod_init(bp);
2711 ptp_ocp_nmea_out_init(bp);
2712 ptp_ocp_signal_init(bp);
2713
2714 err = ptp_ocp_attr_group_add(bp, fb_timecard_groups);
2715 if (err)
2716 return err;
2717
2718 err = ptp_ocp_set_pins(bp);
2719 if (err)
2720 return err;
2721 ptp_ocp_sma_init(bp);
2722
2723 return ptp_ocp_init_clock(bp, r->extra);
2724 }
2725
2726 static bool
ptp_ocp_allow_irq(struct ptp_ocp * bp,struct ocp_resource * r)2727 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r)
2728 {
2729 bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs;
2730
2731 if (!allow)
2732 dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n",
2733 r->irq_vec, r->name);
2734 return allow;
2735 }
2736
2737 static int
ptp_ocp_register_resources(struct ptp_ocp * bp,kernel_ulong_t driver_data)2738 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)
2739 {
2740 struct ocp_resource *r, *table;
2741 int err = 0;
2742
2743 table = (struct ocp_resource *)driver_data;
2744 for (r = table; r->setup; r++) {
2745 if (!ptp_ocp_allow_irq(bp, r))
2746 continue;
2747 err = r->setup(bp, r);
2748 if (err) {
2749 dev_err(&bp->pdev->dev,
2750 "Could not register %s: err %d\n",
2751 r->name, err);
2752 break;
2753 }
2754 }
2755 return err;
2756 }
2757
2758 static void
ptp_ocp_art_sma_init(struct ptp_ocp * bp)2759 ptp_ocp_art_sma_init(struct ptp_ocp *bp)
2760 {
2761 struct dpll_pin_properties prop = {
2762 .board_label = NULL,
2763 .type = DPLL_PIN_TYPE_EXT,
2764 .capabilities = 0,
2765 .freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
2766 .freq_supported = ptp_ocp_sma_freq,
2767
2768 };
2769 u32 reg;
2770 int i;
2771
2772 /* defaults */
2773 bp->sma[0].mode = SMA_MODE_IN;
2774 bp->sma[1].mode = SMA_MODE_IN;
2775 bp->sma[2].mode = SMA_MODE_OUT;
2776 bp->sma[3].mode = SMA_MODE_OUT;
2777
2778 bp->sma[0].default_fcn = 0x08; /* IN: 10Mhz */
2779 bp->sma[1].default_fcn = 0x01; /* IN: PPS1 */
2780 bp->sma[2].default_fcn = 0x10; /* OUT: 10Mhz */
2781 bp->sma[3].default_fcn = 0x02; /* OUT: PHC */
2782
2783 for (i = 0; i < OCP_SMA_NUM; i++) {
2784 /* If no SMA map, the pin functions and directions are fixed. */
2785 bp->sma[i].dpll_prop = prop;
2786 bp->sma[i].dpll_prop.board_label =
2787 bp->ptp_info.pin_config[i].name;
2788 if (!bp->art_sma) {
2789 bp->sma[i].fixed_fcn = true;
2790 bp->sma[i].fixed_dir = true;
2791 continue;
2792 }
2793 reg = ioread32(&bp->art_sma->map[i].gpio);
2794
2795 switch (reg & 0xff) {
2796 case 0:
2797 bp->sma[i].fixed_fcn = true;
2798 bp->sma[i].fixed_dir = true;
2799 break;
2800 case 1:
2801 case 8:
2802 bp->sma[i].mode = SMA_MODE_IN;
2803 bp->sma[i].dpll_prop.capabilities =
2804 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2805 break;
2806 default:
2807 bp->sma[i].mode = SMA_MODE_OUT;
2808 bp->sma[i].dpll_prop.capabilities =
2809 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2810 break;
2811 }
2812 }
2813 }
2814
2815 static u32
ptp_ocp_art_sma_get(struct ptp_ocp * bp,int sma_nr)2816 ptp_ocp_art_sma_get(struct ptp_ocp *bp, int sma_nr)
2817 {
2818 if (bp->sma[sma_nr - 1].fixed_fcn)
2819 return bp->sma[sma_nr - 1].default_fcn;
2820
2821 return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff;
2822 }
2823
2824 /* note: store 0 is considered invalid. */
2825 static int
ptp_ocp_art_sma_set(struct ptp_ocp * bp,int sma_nr,u32 val)2826 ptp_ocp_art_sma_set(struct ptp_ocp *bp, int sma_nr, u32 val)
2827 {
2828 unsigned long flags;
2829 u32 __iomem *gpio;
2830 int err = 0;
2831 u32 reg;
2832
2833 val &= SMA_SELECT_MASK;
2834 if (hweight32(val) > 1)
2835 return -EINVAL;
2836
2837 gpio = &bp->art_sma->map[sma_nr - 1].gpio;
2838
2839 spin_lock_irqsave(&bp->lock, flags);
2840 reg = ioread32(gpio);
2841 if (((reg >> 16) & val) == 0) {
2842 err = -EOPNOTSUPP;
2843 } else {
2844 reg = (reg & 0xff00) | (val & 0xff);
2845 iowrite32(reg, gpio);
2846 }
2847 spin_unlock_irqrestore(&bp->lock, flags);
2848
2849 return err;
2850 }
2851
2852 static const struct ocp_sma_op ocp_art_sma_op = {
2853 .tbl = { ptp_ocp_art_sma_in, ptp_ocp_art_sma_out },
2854 .init = ptp_ocp_art_sma_init,
2855 .get = ptp_ocp_art_sma_get,
2856 .set_inputs = ptp_ocp_art_sma_set,
2857 .set_output = ptp_ocp_art_sma_set,
2858 };
2859
2860 /* ART specific board initializers; last "resource" registered. */
2861 static int
ptp_ocp_art_board_init(struct ptp_ocp * bp,struct ocp_resource * r)2862 ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2863 {
2864 int err;
2865
2866 bp->flash_start = 0x1000000;
2867 bp->eeprom_map = art_eeprom_map;
2868 bp->fw_cap = OCP_CAP_BASIC;
2869 bp->fw_version = ioread32(&bp->reg->version);
2870 bp->fw_tag = 2;
2871 bp->sma_op = &ocp_art_sma_op;
2872 bp->signals_nr = 4;
2873 bp->freq_in_nr = 4;
2874
2875 /* Enable MAC serial port during initialisation */
2876 iowrite32(1, &bp->board_config->mro50_serial_activate);
2877
2878 err = ptp_ocp_set_pins(bp);
2879 if (err)
2880 return err;
2881 ptp_ocp_sma_init(bp);
2882
2883 err = ptp_ocp_attr_group_add(bp, art_timecard_groups);
2884 if (err)
2885 return err;
2886
2887 return ptp_ocp_init_clock(bp, r->extra);
2888 }
2889
2890 /* ADVA specific board initializers; last "resource" registered. */
2891 static int
ptp_ocp_adva_board_init(struct ptp_ocp * bp,struct ocp_resource * r)2892 ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2893 {
2894 int err;
2895 u32 version;
2896
2897 bp->flash_start = 0xA00000;
2898 bp->eeprom_map = fb_eeprom_map;
2899 bp->sma_op = &ocp_adva_sma_op;
2900 bp->signals_nr = 2;
2901 bp->freq_in_nr = 2;
2902
2903 version = ioread32(&bp->image->version);
2904 /* if lower 16 bits are empty, this is the fw loader. */
2905 if ((version & 0xffff) == 0) {
2906 version = version >> 16;
2907 bp->fw_loader = true;
2908 }
2909 bp->fw_tag = 3;
2910 bp->fw_version = version & 0xffff;
2911 bp->fw_cap = OCP_CAP_BASIC | OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2912
2913 ptp_ocp_tod_init(bp);
2914 ptp_ocp_nmea_out_init(bp);
2915 ptp_ocp_signal_init(bp);
2916
2917 err = ptp_ocp_attr_group_add(bp, adva_timecard_groups);
2918 if (err)
2919 return err;
2920
2921 err = ptp_ocp_set_pins(bp);
2922 if (err)
2923 return err;
2924 ptp_ocp_sma_init(bp);
2925
2926 return ptp_ocp_init_clock(bp, r->extra);
2927 }
2928
2929 static ssize_t
ptp_ocp_show_output(const struct ocp_selector * tbl,u32 val,char * buf,int def_val)2930 ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf,
2931 int def_val)
2932 {
2933 const char *name;
2934 ssize_t count;
2935
2936 count = sysfs_emit(buf, "OUT: ");
2937 name = ptp_ocp_select_name_from_val(tbl, val);
2938 if (!name)
2939 name = ptp_ocp_select_name_from_val(tbl, def_val);
2940 count += sysfs_emit_at(buf, count, "%s\n", name);
2941 return count;
2942 }
2943
2944 static ssize_t
ptp_ocp_show_inputs(const struct ocp_selector * tbl,u32 val,char * buf,int def_val)2945 ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf,
2946 int def_val)
2947 {
2948 const char *name;
2949 ssize_t count;
2950 int i;
2951
2952 count = sysfs_emit(buf, "IN: ");
2953 for (i = 0; tbl[i].name; i++) {
2954 if (val & tbl[i].value) {
2955 name = tbl[i].name;
2956 count += sysfs_emit_at(buf, count, "%s ", name);
2957 }
2958 }
2959 if (!val && def_val >= 0) {
2960 name = ptp_ocp_select_name_from_val(tbl, def_val);
2961 count += sysfs_emit_at(buf, count, "%s ", name);
2962 }
2963 if (count)
2964 count--;
2965 count += sysfs_emit_at(buf, count, "\n");
2966 return count;
2967 }
2968
2969 static int
sma_parse_inputs(const struct ocp_selector * const tbl[],const char * buf,enum ptp_ocp_sma_mode * mode)2970 sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf,
2971 enum ptp_ocp_sma_mode *mode)
2972 {
2973 int idx, count, dir;
2974 char **argv;
2975 int ret;
2976
2977 argv = argv_split(GFP_KERNEL, buf, &count);
2978 if (!argv)
2979 return -ENOMEM;
2980
2981 ret = -EINVAL;
2982 if (!count)
2983 goto out;
2984
2985 idx = 0;
2986 dir = *mode == SMA_MODE_IN ? 0 : 1;
2987 if (!strcasecmp("IN:", argv[0])) {
2988 dir = 0;
2989 idx++;
2990 }
2991 if (!strcasecmp("OUT:", argv[0])) {
2992 dir = 1;
2993 idx++;
2994 }
2995 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT;
2996
2997 ret = 0;
2998 for (; idx < count; idx++)
2999 ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]);
3000 if (ret < 0)
3001 ret = -EINVAL;
3002
3003 out:
3004 argv_free(argv);
3005 return ret;
3006 }
3007
3008 static ssize_t
ptp_ocp_sma_show(struct ptp_ocp * bp,int sma_nr,char * buf,int default_in_val,int default_out_val)3009 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf,
3010 int default_in_val, int default_out_val)
3011 {
3012 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3013 const struct ocp_selector * const *tbl;
3014 u32 val;
3015
3016 tbl = bp->sma_op->tbl;
3017 val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK;
3018
3019 if (sma->mode == SMA_MODE_IN) {
3020 if (sma->disabled)
3021 val = SMA_DISABLE;
3022 return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val);
3023 }
3024
3025 return ptp_ocp_show_output(tbl[1], val, buf, default_out_val);
3026 }
3027
3028 static ssize_t
sma1_show(struct device * dev,struct device_attribute * attr,char * buf)3029 sma1_show(struct device *dev, struct device_attribute *attr, char *buf)
3030 {
3031 struct ptp_ocp *bp = dev_get_drvdata(dev);
3032
3033 return ptp_ocp_sma_show(bp, 1, buf, 0, 1);
3034 }
3035
3036 static ssize_t
sma2_show(struct device * dev,struct device_attribute * attr,char * buf)3037 sma2_show(struct device *dev, struct device_attribute *attr, char *buf)
3038 {
3039 struct ptp_ocp *bp = dev_get_drvdata(dev);
3040
3041 return ptp_ocp_sma_show(bp, 2, buf, -1, 1);
3042 }
3043
3044 static ssize_t
sma3_show(struct device * dev,struct device_attribute * attr,char * buf)3045 sma3_show(struct device *dev, struct device_attribute *attr, char *buf)
3046 {
3047 struct ptp_ocp *bp = dev_get_drvdata(dev);
3048
3049 return ptp_ocp_sma_show(bp, 3, buf, -1, 0);
3050 }
3051
3052 static ssize_t
sma4_show(struct device * dev,struct device_attribute * attr,char * buf)3053 sma4_show(struct device *dev, struct device_attribute *attr, char *buf)
3054 {
3055 struct ptp_ocp *bp = dev_get_drvdata(dev);
3056
3057 return ptp_ocp_sma_show(bp, 4, buf, -1, 1);
3058 }
3059
3060 static int
ptp_ocp_sma_store_val(struct ptp_ocp * bp,int val,enum ptp_ocp_sma_mode mode,int sma_nr)3061 ptp_ocp_sma_store_val(struct ptp_ocp *bp, int val, enum ptp_ocp_sma_mode mode, int sma_nr)
3062 {
3063 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3064
3065 if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE))
3066 return -EOPNOTSUPP;
3067
3068 if (sma->fixed_fcn) {
3069 if (val != sma->default_fcn)
3070 return -EOPNOTSUPP;
3071 return 0;
3072 }
3073
3074 sma->disabled = !!(val & SMA_DISABLE);
3075
3076 if (mode != sma->mode) {
3077 if (mode == SMA_MODE_IN)
3078 ptp_ocp_sma_set_output(bp, sma_nr, 0);
3079 else
3080 ptp_ocp_sma_set_inputs(bp, sma_nr, 0);
3081 sma->mode = mode;
3082 }
3083
3084 if (!sma->fixed_dir)
3085 val |= SMA_ENABLE; /* add enable bit */
3086
3087 if (sma->disabled)
3088 val = 0;
3089
3090 if (mode == SMA_MODE_IN)
3091 val = ptp_ocp_sma_set_inputs(bp, sma_nr, val);
3092 else
3093 val = ptp_ocp_sma_set_output(bp, sma_nr, val);
3094
3095 return val;
3096 }
3097
3098 static int
ptp_ocp_sma_store(struct ptp_ocp * bp,const char * buf,int sma_nr)3099 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)
3100 {
3101 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3102 enum ptp_ocp_sma_mode mode;
3103 int val;
3104
3105 mode = sma->mode;
3106 val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode);
3107 if (val < 0)
3108 return val;
3109 return ptp_ocp_sma_store_val(bp, val, mode, sma_nr);
3110 }
3111
3112 static ssize_t
sma1_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3113 sma1_store(struct device *dev, struct device_attribute *attr,
3114 const char *buf, size_t count)
3115 {
3116 struct ptp_ocp *bp = dev_get_drvdata(dev);
3117 int err;
3118
3119 err = ptp_ocp_sma_store(bp, buf, 1);
3120 return err ? err : count;
3121 }
3122
3123 static ssize_t
sma2_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3124 sma2_store(struct device *dev, struct device_attribute *attr,
3125 const char *buf, size_t count)
3126 {
3127 struct ptp_ocp *bp = dev_get_drvdata(dev);
3128 int err;
3129
3130 err = ptp_ocp_sma_store(bp, buf, 2);
3131 return err ? err : count;
3132 }
3133
3134 static ssize_t
sma3_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3135 sma3_store(struct device *dev, struct device_attribute *attr,
3136 const char *buf, size_t count)
3137 {
3138 struct ptp_ocp *bp = dev_get_drvdata(dev);
3139 int err;
3140
3141 err = ptp_ocp_sma_store(bp, buf, 3);
3142 return err ? err : count;
3143 }
3144
3145 static ssize_t
sma4_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3146 sma4_store(struct device *dev, struct device_attribute *attr,
3147 const char *buf, size_t count)
3148 {
3149 struct ptp_ocp *bp = dev_get_drvdata(dev);
3150 int err;
3151
3152 err = ptp_ocp_sma_store(bp, buf, 4);
3153 return err ? err : count;
3154 }
3155 static DEVICE_ATTR_RW(sma1);
3156 static DEVICE_ATTR_RW(sma2);
3157 static DEVICE_ATTR_RW(sma3);
3158 static DEVICE_ATTR_RW(sma4);
3159
3160 static ssize_t
available_sma_inputs_show(struct device * dev,struct device_attribute * attr,char * buf)3161 available_sma_inputs_show(struct device *dev,
3162 struct device_attribute *attr, char *buf)
3163 {
3164 struct ptp_ocp *bp = dev_get_drvdata(dev);
3165
3166 return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf);
3167 }
3168 static DEVICE_ATTR_RO(available_sma_inputs);
3169
3170 static ssize_t
available_sma_outputs_show(struct device * dev,struct device_attribute * attr,char * buf)3171 available_sma_outputs_show(struct device *dev,
3172 struct device_attribute *attr, char *buf)
3173 {
3174 struct ptp_ocp *bp = dev_get_drvdata(dev);
3175
3176 return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf);
3177 }
3178 static DEVICE_ATTR_RO(available_sma_outputs);
3179
3180 #define EXT_ATTR_RO(_group, _name, _val) \
3181 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
3182 { __ATTR_RO(_name), (void *)_val }
3183 #define EXT_ATTR_RW(_group, _name, _val) \
3184 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
3185 { __ATTR_RW(_name), (void *)_val }
3186 #define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr)
3187
3188 /* period [duty [phase [polarity]]] */
3189 static ssize_t
signal_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3190 signal_store(struct device *dev, struct device_attribute *attr,
3191 const char *buf, size_t count)
3192 {
3193 struct dev_ext_attribute *ea = to_ext_attr(attr);
3194 struct ptp_ocp *bp = dev_get_drvdata(dev);
3195 struct ptp_ocp_signal s = { };
3196 int gen = (uintptr_t)ea->var;
3197 int argc, err;
3198 char **argv;
3199
3200 argv = argv_split(GFP_KERNEL, buf, &argc);
3201 if (!argv)
3202 return -ENOMEM;
3203
3204 err = -EINVAL;
3205 s.duty = bp->signal[gen].duty;
3206 s.phase = bp->signal[gen].phase;
3207 s.period = bp->signal[gen].period;
3208 s.polarity = bp->signal[gen].polarity;
3209
3210 switch (argc) {
3211 case 4:
3212 argc--;
3213 err = kstrtobool(argv[argc], &s.polarity);
3214 if (err)
3215 goto out;
3216 fallthrough;
3217 case 3:
3218 argc--;
3219 err = kstrtou64(argv[argc], 0, &s.phase);
3220 if (err)
3221 goto out;
3222 fallthrough;
3223 case 2:
3224 argc--;
3225 err = kstrtoint(argv[argc], 0, &s.duty);
3226 if (err)
3227 goto out;
3228 fallthrough;
3229 case 1:
3230 argc--;
3231 err = kstrtou64(argv[argc], 0, &s.period);
3232 if (err)
3233 goto out;
3234 break;
3235 default:
3236 goto out;
3237 }
3238
3239 err = ptp_ocp_signal_set(bp, gen, &s);
3240 if (err)
3241 goto out;
3242
3243 err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0);
3244
3245 out:
3246 argv_free(argv);
3247 return err ? err : count;
3248 }
3249
3250 static ssize_t
signal_show(struct device * dev,struct device_attribute * attr,char * buf)3251 signal_show(struct device *dev, struct device_attribute *attr, char *buf)
3252 {
3253 struct dev_ext_attribute *ea = to_ext_attr(attr);
3254 struct ptp_ocp *bp = dev_get_drvdata(dev);
3255 struct ptp_ocp_signal *signal;
3256 int gen = (uintptr_t)ea->var;
3257 struct timespec64 ts;
3258
3259 signal = &bp->signal[gen];
3260
3261 ts = ktime_to_timespec64(signal->start);
3262
3263 return sysfs_emit(buf, "%llu %d %llu %d %ptT TAI\n",
3264 signal->period, signal->duty, signal->phase, signal->polarity,
3265 &ts.tv_sec);
3266 }
3267 static EXT_ATTR_RW(signal, signal, 0);
3268 static EXT_ATTR_RW(signal, signal, 1);
3269 static EXT_ATTR_RW(signal, signal, 2);
3270 static EXT_ATTR_RW(signal, signal, 3);
3271
3272 static ssize_t
duty_show(struct device * dev,struct device_attribute * attr,char * buf)3273 duty_show(struct device *dev, struct device_attribute *attr, char *buf)
3274 {
3275 struct dev_ext_attribute *ea = to_ext_attr(attr);
3276 struct ptp_ocp *bp = dev_get_drvdata(dev);
3277 int i = (uintptr_t)ea->var;
3278
3279 return sysfs_emit(buf, "%d\n", bp->signal[i].duty);
3280 }
3281 static EXT_ATTR_RO(signal, duty, 0);
3282 static EXT_ATTR_RO(signal, duty, 1);
3283 static EXT_ATTR_RO(signal, duty, 2);
3284 static EXT_ATTR_RO(signal, duty, 3);
3285
3286 static ssize_t
period_show(struct device * dev,struct device_attribute * attr,char * buf)3287 period_show(struct device *dev, struct device_attribute *attr, char *buf)
3288 {
3289 struct dev_ext_attribute *ea = to_ext_attr(attr);
3290 struct ptp_ocp *bp = dev_get_drvdata(dev);
3291 int i = (uintptr_t)ea->var;
3292
3293 return sysfs_emit(buf, "%llu\n", bp->signal[i].period);
3294 }
3295 static EXT_ATTR_RO(signal, period, 0);
3296 static EXT_ATTR_RO(signal, period, 1);
3297 static EXT_ATTR_RO(signal, period, 2);
3298 static EXT_ATTR_RO(signal, period, 3);
3299
3300 static ssize_t
phase_show(struct device * dev,struct device_attribute * attr,char * buf)3301 phase_show(struct device *dev, struct device_attribute *attr, char *buf)
3302 {
3303 struct dev_ext_attribute *ea = to_ext_attr(attr);
3304 struct ptp_ocp *bp = dev_get_drvdata(dev);
3305 int i = (uintptr_t)ea->var;
3306
3307 return sysfs_emit(buf, "%llu\n", bp->signal[i].phase);
3308 }
3309 static EXT_ATTR_RO(signal, phase, 0);
3310 static EXT_ATTR_RO(signal, phase, 1);
3311 static EXT_ATTR_RO(signal, phase, 2);
3312 static EXT_ATTR_RO(signal, phase, 3);
3313
3314 static ssize_t
polarity_show(struct device * dev,struct device_attribute * attr,char * buf)3315 polarity_show(struct device *dev, struct device_attribute *attr,
3316 char *buf)
3317 {
3318 struct dev_ext_attribute *ea = to_ext_attr(attr);
3319 struct ptp_ocp *bp = dev_get_drvdata(dev);
3320 int i = (uintptr_t)ea->var;
3321
3322 return sysfs_emit(buf, "%d\n", bp->signal[i].polarity);
3323 }
3324 static EXT_ATTR_RO(signal, polarity, 0);
3325 static EXT_ATTR_RO(signal, polarity, 1);
3326 static EXT_ATTR_RO(signal, polarity, 2);
3327 static EXT_ATTR_RO(signal, polarity, 3);
3328
3329 static ssize_t
running_show(struct device * dev,struct device_attribute * attr,char * buf)3330 running_show(struct device *dev, struct device_attribute *attr, char *buf)
3331 {
3332 struct dev_ext_attribute *ea = to_ext_attr(attr);
3333 struct ptp_ocp *bp = dev_get_drvdata(dev);
3334 int i = (uintptr_t)ea->var;
3335
3336 return sysfs_emit(buf, "%d\n", bp->signal[i].running);
3337 }
3338 static EXT_ATTR_RO(signal, running, 0);
3339 static EXT_ATTR_RO(signal, running, 1);
3340 static EXT_ATTR_RO(signal, running, 2);
3341 static EXT_ATTR_RO(signal, running, 3);
3342
3343 static ssize_t
start_show(struct device * dev,struct device_attribute * attr,char * buf)3344 start_show(struct device *dev, struct device_attribute *attr, char *buf)
3345 {
3346 struct dev_ext_attribute *ea = to_ext_attr(attr);
3347 struct ptp_ocp *bp = dev_get_drvdata(dev);
3348 int i = (uintptr_t)ea->var;
3349 struct timespec64 ts;
3350
3351 ts = ktime_to_timespec64(bp->signal[i].start);
3352 return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec);
3353 }
3354 static EXT_ATTR_RO(signal, start, 0);
3355 static EXT_ATTR_RO(signal, start, 1);
3356 static EXT_ATTR_RO(signal, start, 2);
3357 static EXT_ATTR_RO(signal, start, 3);
3358
3359 static ssize_t
seconds_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3360 seconds_store(struct device *dev, struct device_attribute *attr,
3361 const char *buf, size_t count)
3362 {
3363 struct dev_ext_attribute *ea = to_ext_attr(attr);
3364 struct ptp_ocp *bp = dev_get_drvdata(dev);
3365 int idx = (uintptr_t)ea->var;
3366 u32 val;
3367 int err;
3368
3369 err = kstrtou32(buf, 0, &val);
3370 if (err)
3371 return err;
3372 if (val > 0xff)
3373 return -EINVAL;
3374
3375 if (val)
3376 val = (val << 8) | 0x1;
3377
3378 iowrite32(val, &bp->freq_in[idx]->ctrl);
3379
3380 return count;
3381 }
3382
3383 static ssize_t
seconds_show(struct device * dev,struct device_attribute * attr,char * buf)3384 seconds_show(struct device *dev, struct device_attribute *attr, char *buf)
3385 {
3386 struct dev_ext_attribute *ea = to_ext_attr(attr);
3387 struct ptp_ocp *bp = dev_get_drvdata(dev);
3388 int idx = (uintptr_t)ea->var;
3389 u32 val;
3390
3391 val = ioread32(&bp->freq_in[idx]->ctrl);
3392 if (val & 1)
3393 val = (val >> 8) & 0xff;
3394 else
3395 val = 0;
3396
3397 return sysfs_emit(buf, "%u\n", val);
3398 }
3399 static EXT_ATTR_RW(freq, seconds, 0);
3400 static EXT_ATTR_RW(freq, seconds, 1);
3401 static EXT_ATTR_RW(freq, seconds, 2);
3402 static EXT_ATTR_RW(freq, seconds, 3);
3403
3404 static ssize_t
frequency_show(struct device * dev,struct device_attribute * attr,char * buf)3405 frequency_show(struct device *dev, struct device_attribute *attr, char *buf)
3406 {
3407 struct dev_ext_attribute *ea = to_ext_attr(attr);
3408 struct ptp_ocp *bp = dev_get_drvdata(dev);
3409 int idx = (uintptr_t)ea->var;
3410 u32 val;
3411
3412 val = ioread32(&bp->freq_in[idx]->status);
3413 if (val & FREQ_STATUS_ERROR)
3414 return sysfs_emit(buf, "error\n");
3415 if (val & FREQ_STATUS_OVERRUN)
3416 return sysfs_emit(buf, "overrun\n");
3417 if (val & FREQ_STATUS_VALID)
3418 return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK);
3419 return 0;
3420 }
3421 static EXT_ATTR_RO(freq, frequency, 0);
3422 static EXT_ATTR_RO(freq, frequency, 1);
3423 static EXT_ATTR_RO(freq, frequency, 2);
3424 static EXT_ATTR_RO(freq, frequency, 3);
3425
3426 static ssize_t
ptp_ocp_tty_show(struct device * dev,struct device_attribute * attr,char * buf)3427 ptp_ocp_tty_show(struct device *dev, struct device_attribute *attr, char *buf)
3428 {
3429 struct dev_ext_attribute *ea = to_ext_attr(attr);
3430 struct ptp_ocp *bp = dev_get_drvdata(dev);
3431
3432 /*
3433 * NOTE: This output does not include a trailing newline for backward
3434 * compatibility. Existing userspace software uses this value directly
3435 * as a device path (e.g., "/dev/ttyS4"), and adding a newline would
3436 * break those applications. Do not add a newline to this output.
3437 */
3438 return sysfs_emit(buf, "ttyS%d", bp->port[(uintptr_t)ea->var].line);
3439 }
3440
3441 static umode_t
ptp_ocp_timecard_tty_is_visible(struct kobject * kobj,struct attribute * attr,int n)3442 ptp_ocp_timecard_tty_is_visible(struct kobject *kobj, struct attribute *attr, int n)
3443 {
3444 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3445 struct ptp_ocp_serial_port *port;
3446 struct device_attribute *dattr;
3447 struct dev_ext_attribute *ea;
3448
3449 if (strncmp(attr->name, "tty", 3))
3450 return attr->mode;
3451
3452 dattr = container_of(attr, struct device_attribute, attr);
3453 ea = container_of(dattr, struct dev_ext_attribute, attr);
3454 port = &bp->port[(uintptr_t)ea->var];
3455 return port->line == -1 ? 0 : 0444;
3456 }
3457
3458 #define EXT_TTY_ATTR_RO(_name, _val) \
3459 struct dev_ext_attribute dev_attr_tty##_name = \
3460 { __ATTR(tty##_name, 0444, ptp_ocp_tty_show, NULL), (void *)_val }
3461
3462 static EXT_TTY_ATTR_RO(GNSS, PORT_GNSS);
3463 static EXT_TTY_ATTR_RO(GNSS2, PORT_GNSS2);
3464 static EXT_TTY_ATTR_RO(MAC, PORT_MAC);
3465 static EXT_TTY_ATTR_RO(NMEA, PORT_NMEA);
3466 static struct attribute *ptp_ocp_timecard_tty_attrs[] = {
3467 &dev_attr_ttyGNSS.attr.attr,
3468 &dev_attr_ttyGNSS2.attr.attr,
3469 &dev_attr_ttyMAC.attr.attr,
3470 &dev_attr_ttyNMEA.attr.attr,
3471 NULL,
3472 };
3473
3474 static const struct attribute_group ptp_ocp_timecard_tty_group = {
3475 .name = "tty",
3476 .attrs = ptp_ocp_timecard_tty_attrs,
3477 .is_visible = ptp_ocp_timecard_tty_is_visible,
3478 };
3479
3480 static ssize_t
serialnum_show(struct device * dev,struct device_attribute * attr,char * buf)3481 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf)
3482 {
3483 struct ptp_ocp *bp = dev_get_drvdata(dev);
3484
3485 if (!bp->has_eeprom_data)
3486 ptp_ocp_read_eeprom(bp);
3487
3488 return sysfs_emit(buf, "%pM\n", bp->serial);
3489 }
3490 static DEVICE_ATTR_RO(serialnum);
3491
3492 static ssize_t
gnss_sync_show(struct device * dev,struct device_attribute * attr,char * buf)3493 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf)
3494 {
3495 struct ptp_ocp *bp = dev_get_drvdata(dev);
3496 ssize_t ret;
3497
3498 if (bp->gnss_lost)
3499 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost);
3500 else
3501 ret = sysfs_emit(buf, "SYNC\n");
3502
3503 return ret;
3504 }
3505 static DEVICE_ATTR_RO(gnss_sync);
3506
3507 static ssize_t
utc_tai_offset_show(struct device * dev,struct device_attribute * attr,char * buf)3508 utc_tai_offset_show(struct device *dev,
3509 struct device_attribute *attr, char *buf)
3510 {
3511 struct ptp_ocp *bp = dev_get_drvdata(dev);
3512
3513 return sysfs_emit(buf, "%d\n", bp->utc_tai_offset);
3514 }
3515
3516 static ssize_t
utc_tai_offset_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3517 utc_tai_offset_store(struct device *dev,
3518 struct device_attribute *attr,
3519 const char *buf, size_t count)
3520 {
3521 struct ptp_ocp *bp = dev_get_drvdata(dev);
3522 int err;
3523 u32 val;
3524
3525 err = kstrtou32(buf, 0, &val);
3526 if (err)
3527 return err;
3528
3529 ptp_ocp_utc_distribute(bp, val);
3530
3531 return count;
3532 }
3533 static DEVICE_ATTR_RW(utc_tai_offset);
3534
3535 static ssize_t
ts_window_adjust_show(struct device * dev,struct device_attribute * attr,char * buf)3536 ts_window_adjust_show(struct device *dev,
3537 struct device_attribute *attr, char *buf)
3538 {
3539 struct ptp_ocp *bp = dev_get_drvdata(dev);
3540
3541 return sysfs_emit(buf, "%d\n", bp->ts_window_adjust);
3542 }
3543
3544 static ssize_t
ts_window_adjust_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3545 ts_window_adjust_store(struct device *dev,
3546 struct device_attribute *attr,
3547 const char *buf, size_t count)
3548 {
3549 struct ptp_ocp *bp = dev_get_drvdata(dev);
3550 int err;
3551 u32 val;
3552
3553 err = kstrtou32(buf, 0, &val);
3554 if (err)
3555 return err;
3556
3557 bp->ts_window_adjust = val;
3558
3559 return count;
3560 }
3561 static DEVICE_ATTR_RW(ts_window_adjust);
3562
3563 static ssize_t
irig_b_mode_show(struct device * dev,struct device_attribute * attr,char * buf)3564 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
3565 {
3566 struct ptp_ocp *bp = dev_get_drvdata(dev);
3567 u32 val;
3568
3569 val = ioread32(&bp->irig_out->ctrl);
3570 val = (val >> 16) & 0x07;
3571 return sysfs_emit(buf, "%d\n", val);
3572 }
3573
3574 static ssize_t
irig_b_mode_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3575 irig_b_mode_store(struct device *dev,
3576 struct device_attribute *attr,
3577 const char *buf, size_t count)
3578 {
3579 struct ptp_ocp *bp = dev_get_drvdata(dev);
3580 unsigned long flags;
3581 int err;
3582 u32 reg;
3583 u8 val;
3584
3585 err = kstrtou8(buf, 0, &val);
3586 if (err)
3587 return err;
3588 if (val > 7)
3589 return -EINVAL;
3590
3591 reg = ((val & 0x7) << 16);
3592
3593 spin_lock_irqsave(&bp->lock, flags);
3594 iowrite32(0, &bp->irig_out->ctrl); /* disable */
3595 iowrite32(reg, &bp->irig_out->ctrl); /* change mode */
3596 iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl);
3597 spin_unlock_irqrestore(&bp->lock, flags);
3598
3599 return count;
3600 }
3601 static DEVICE_ATTR_RW(irig_b_mode);
3602
3603 static ssize_t
clock_source_show(struct device * dev,struct device_attribute * attr,char * buf)3604 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf)
3605 {
3606 struct ptp_ocp *bp = dev_get_drvdata(dev);
3607 const char *p;
3608 u32 select;
3609
3610 select = ioread32(&bp->reg->select);
3611 p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16);
3612
3613 return sysfs_emit(buf, "%s\n", p);
3614 }
3615
3616 static ssize_t
clock_source_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3617 clock_source_store(struct device *dev, struct device_attribute *attr,
3618 const char *buf, size_t count)
3619 {
3620 struct ptp_ocp *bp = dev_get_drvdata(dev);
3621 unsigned long flags;
3622 int val;
3623
3624 val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf);
3625 if (val < 0)
3626 return val;
3627
3628 spin_lock_irqsave(&bp->lock, flags);
3629 iowrite32(val, &bp->reg->select);
3630 spin_unlock_irqrestore(&bp->lock, flags);
3631
3632 return count;
3633 }
3634 static DEVICE_ATTR_RW(clock_source);
3635
3636 static ssize_t
available_clock_sources_show(struct device * dev,struct device_attribute * attr,char * buf)3637 available_clock_sources_show(struct device *dev,
3638 struct device_attribute *attr, char *buf)
3639 {
3640 return ptp_ocp_select_table_show(ptp_ocp_clock, buf);
3641 }
3642 static DEVICE_ATTR_RO(available_clock_sources);
3643
3644 static ssize_t
clock_status_drift_show(struct device * dev,struct device_attribute * attr,char * buf)3645 clock_status_drift_show(struct device *dev,
3646 struct device_attribute *attr, char *buf)
3647 {
3648 struct ptp_ocp *bp = dev_get_drvdata(dev);
3649 u32 val;
3650 int res;
3651
3652 val = ioread32(&bp->reg->status_drift);
3653 res = (val & ~INT_MAX) ? -1 : 1;
3654 res *= (val & INT_MAX);
3655 return sysfs_emit(buf, "%d\n", res);
3656 }
3657 static DEVICE_ATTR_RO(clock_status_drift);
3658
3659 static ssize_t
clock_status_offset_show(struct device * dev,struct device_attribute * attr,char * buf)3660 clock_status_offset_show(struct device *dev,
3661 struct device_attribute *attr, char *buf)
3662 {
3663 struct ptp_ocp *bp = dev_get_drvdata(dev);
3664 u32 val;
3665 int res;
3666
3667 val = ioread32(&bp->reg->status_offset);
3668 res = (val & ~INT_MAX) ? -1 : 1;
3669 res *= (val & INT_MAX);
3670 return sysfs_emit(buf, "%d\n", res);
3671 }
3672 static DEVICE_ATTR_RO(clock_status_offset);
3673
3674 static ssize_t
tod_correction_show(struct device * dev,struct device_attribute * attr,char * buf)3675 tod_correction_show(struct device *dev,
3676 struct device_attribute *attr, char *buf)
3677 {
3678 struct ptp_ocp *bp = dev_get_drvdata(dev);
3679 u32 val;
3680 int res;
3681
3682 val = ioread32(&bp->tod->adj_sec);
3683 res = (val & ~INT_MAX) ? -1 : 1;
3684 res *= (val & INT_MAX);
3685 return sysfs_emit(buf, "%d\n", res);
3686 }
3687
3688 static ssize_t
tod_correction_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3689 tod_correction_store(struct device *dev, struct device_attribute *attr,
3690 const char *buf, size_t count)
3691 {
3692 struct ptp_ocp *bp = dev_get_drvdata(dev);
3693 unsigned long flags;
3694 int err, res;
3695 u32 val = 0;
3696
3697 err = kstrtos32(buf, 0, &res);
3698 if (err)
3699 return err;
3700 if (res < 0) {
3701 res *= -1;
3702 val |= BIT(31);
3703 }
3704 val |= res;
3705
3706 spin_lock_irqsave(&bp->lock, flags);
3707 iowrite32(val, &bp->tod->adj_sec);
3708 spin_unlock_irqrestore(&bp->lock, flags);
3709
3710 return count;
3711 }
3712 static DEVICE_ATTR_RW(tod_correction);
3713
3714 #define _DEVICE_SIGNAL_GROUP_ATTRS(_nr) \
3715 static struct attribute *fb_timecard_signal##_nr##_attrs[] = { \
3716 &dev_attr_signal##_nr##_signal.attr.attr, \
3717 &dev_attr_signal##_nr##_duty.attr.attr, \
3718 &dev_attr_signal##_nr##_phase.attr.attr, \
3719 &dev_attr_signal##_nr##_period.attr.attr, \
3720 &dev_attr_signal##_nr##_polarity.attr.attr, \
3721 &dev_attr_signal##_nr##_running.attr.attr, \
3722 &dev_attr_signal##_nr##_start.attr.attr, \
3723 NULL, \
3724 }
3725
3726 #define DEVICE_SIGNAL_GROUP(_name, _nr) \
3727 _DEVICE_SIGNAL_GROUP_ATTRS(_nr); \
3728 static const struct attribute_group \
3729 fb_timecard_signal##_nr##_group = { \
3730 .name = #_name, \
3731 .attrs = fb_timecard_signal##_nr##_attrs, \
3732 }
3733
3734 DEVICE_SIGNAL_GROUP(gen1, 0);
3735 DEVICE_SIGNAL_GROUP(gen2, 1);
3736 DEVICE_SIGNAL_GROUP(gen3, 2);
3737 DEVICE_SIGNAL_GROUP(gen4, 3);
3738
3739 #define _DEVICE_FREQ_GROUP_ATTRS(_nr) \
3740 static struct attribute *fb_timecard_freq##_nr##_attrs[] = { \
3741 &dev_attr_freq##_nr##_seconds.attr.attr, \
3742 &dev_attr_freq##_nr##_frequency.attr.attr, \
3743 NULL, \
3744 }
3745
3746 #define DEVICE_FREQ_GROUP(_name, _nr) \
3747 _DEVICE_FREQ_GROUP_ATTRS(_nr); \
3748 static const struct attribute_group \
3749 fb_timecard_freq##_nr##_group = { \
3750 .name = #_name, \
3751 .attrs = fb_timecard_freq##_nr##_attrs, \
3752 }
3753
3754 DEVICE_FREQ_GROUP(freq1, 0);
3755 DEVICE_FREQ_GROUP(freq2, 1);
3756 DEVICE_FREQ_GROUP(freq3, 2);
3757 DEVICE_FREQ_GROUP(freq4, 3);
3758
3759 static ssize_t
disciplining_config_read(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3760 disciplining_config_read(struct file *filp, struct kobject *kobj,
3761 const struct bin_attribute *bin_attr, char *buf,
3762 loff_t off, size_t count)
3763 {
3764 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3765 size_t size = OCP_ART_CONFIG_SIZE;
3766 struct nvmem_device *nvmem;
3767 ssize_t err;
3768
3769 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3770 if (IS_ERR(nvmem))
3771 return PTR_ERR(nvmem);
3772
3773 if (off > size) {
3774 err = 0;
3775 goto out;
3776 }
3777
3778 if (off + count > size)
3779 count = size - off;
3780
3781 // the configuration is in the very beginning of the EEPROM
3782 err = nvmem_device_read(nvmem, off, count, buf);
3783 if (err != count) {
3784 err = -EFAULT;
3785 goto out;
3786 }
3787
3788 out:
3789 ptp_ocp_nvmem_device_put(&nvmem);
3790
3791 return err;
3792 }
3793
3794 static ssize_t
disciplining_config_write(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3795 disciplining_config_write(struct file *filp, struct kobject *kobj,
3796 const struct bin_attribute *bin_attr, char *buf,
3797 loff_t off, size_t count)
3798 {
3799 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3800 struct nvmem_device *nvmem;
3801 ssize_t err;
3802
3803 /* Allow write of the whole area only */
3804 if (off || count != OCP_ART_CONFIG_SIZE)
3805 return -EFAULT;
3806
3807 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3808 if (IS_ERR(nvmem))
3809 return PTR_ERR(nvmem);
3810
3811 err = nvmem_device_write(nvmem, 0x00, count, buf);
3812 if (err != count)
3813 err = -EFAULT;
3814
3815 ptp_ocp_nvmem_device_put(&nvmem);
3816
3817 return err;
3818 }
3819 static const BIN_ATTR_RW(disciplining_config, OCP_ART_CONFIG_SIZE);
3820
3821 static ssize_t
temperature_table_read(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3822 temperature_table_read(struct file *filp, struct kobject *kobj,
3823 const struct bin_attribute *bin_attr, char *buf,
3824 loff_t off, size_t count)
3825 {
3826 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3827 size_t size = OCP_ART_TEMP_TABLE_SIZE;
3828 struct nvmem_device *nvmem;
3829 ssize_t err;
3830
3831 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3832 if (IS_ERR(nvmem))
3833 return PTR_ERR(nvmem);
3834
3835 if (off > size) {
3836 err = 0;
3837 goto out;
3838 }
3839
3840 if (off + count > size)
3841 count = size - off;
3842
3843 // the configuration is in the very beginning of the EEPROM
3844 err = nvmem_device_read(nvmem, 0x90 + off, count, buf);
3845 if (err != count) {
3846 err = -EFAULT;
3847 goto out;
3848 }
3849
3850 out:
3851 ptp_ocp_nvmem_device_put(&nvmem);
3852
3853 return err;
3854 }
3855
3856 static ssize_t
temperature_table_write(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3857 temperature_table_write(struct file *filp, struct kobject *kobj,
3858 const struct bin_attribute *bin_attr, char *buf,
3859 loff_t off, size_t count)
3860 {
3861 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3862 struct nvmem_device *nvmem;
3863 ssize_t err;
3864
3865 /* Allow write of the whole area only */
3866 if (off || count != OCP_ART_TEMP_TABLE_SIZE)
3867 return -EFAULT;
3868
3869 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3870 if (IS_ERR(nvmem))
3871 return PTR_ERR(nvmem);
3872
3873 err = nvmem_device_write(nvmem, 0x90, count, buf);
3874 if (err != count)
3875 err = -EFAULT;
3876
3877 ptp_ocp_nvmem_device_put(&nvmem);
3878
3879 return err;
3880 }
3881 static const BIN_ATTR_RW(temperature_table, OCP_ART_TEMP_TABLE_SIZE);
3882
3883 static struct attribute *fb_timecard_attrs[] = {
3884 &dev_attr_serialnum.attr,
3885 &dev_attr_gnss_sync.attr,
3886 &dev_attr_clock_source.attr,
3887 &dev_attr_available_clock_sources.attr,
3888 &dev_attr_sma1.attr,
3889 &dev_attr_sma2.attr,
3890 &dev_attr_sma3.attr,
3891 &dev_attr_sma4.attr,
3892 &dev_attr_available_sma_inputs.attr,
3893 &dev_attr_available_sma_outputs.attr,
3894 &dev_attr_clock_status_drift.attr,
3895 &dev_attr_clock_status_offset.attr,
3896 &dev_attr_irig_b_mode.attr,
3897 &dev_attr_utc_tai_offset.attr,
3898 &dev_attr_ts_window_adjust.attr,
3899 &dev_attr_tod_correction.attr,
3900 NULL,
3901 };
3902
3903 static const struct attribute_group fb_timecard_group = {
3904 .attrs = fb_timecard_attrs,
3905 };
3906
3907 static const struct ocp_attr_group fb_timecard_groups[] = {
3908 { .cap = OCP_CAP_BASIC, .group = &fb_timecard_group },
3909 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },
3910 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
3911 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
3912 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal2_group },
3913 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal3_group },
3914 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
3915 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
3916 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq2_group },
3917 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq3_group },
3918 { },
3919 };
3920
3921 static struct attribute *art_timecard_attrs[] = {
3922 &dev_attr_serialnum.attr,
3923 &dev_attr_clock_source.attr,
3924 &dev_attr_available_clock_sources.attr,
3925 &dev_attr_utc_tai_offset.attr,
3926 &dev_attr_ts_window_adjust.attr,
3927 &dev_attr_sma1.attr,
3928 &dev_attr_sma2.attr,
3929 &dev_attr_sma3.attr,
3930 &dev_attr_sma4.attr,
3931 &dev_attr_available_sma_inputs.attr,
3932 &dev_attr_available_sma_outputs.attr,
3933 NULL,
3934 };
3935
3936 static const struct bin_attribute *const bin_art_timecard_attrs[] = {
3937 &bin_attr_disciplining_config,
3938 &bin_attr_temperature_table,
3939 NULL,
3940 };
3941
3942 static const struct attribute_group art_timecard_group = {
3943 .attrs = art_timecard_attrs,
3944 .bin_attrs = bin_art_timecard_attrs,
3945 };
3946
3947 static const struct ocp_attr_group art_timecard_groups[] = {
3948 { .cap = OCP_CAP_BASIC, .group = &art_timecard_group },
3949 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },
3950 { },
3951 };
3952
3953 static struct attribute *adva_timecard_attrs[] = {
3954 &dev_attr_serialnum.attr,
3955 &dev_attr_gnss_sync.attr,
3956 &dev_attr_clock_source.attr,
3957 &dev_attr_available_clock_sources.attr,
3958 &dev_attr_sma1.attr,
3959 &dev_attr_sma2.attr,
3960 &dev_attr_sma3.attr,
3961 &dev_attr_sma4.attr,
3962 &dev_attr_available_sma_inputs.attr,
3963 &dev_attr_available_sma_outputs.attr,
3964 &dev_attr_clock_status_drift.attr,
3965 &dev_attr_clock_status_offset.attr,
3966 &dev_attr_ts_window_adjust.attr,
3967 &dev_attr_tod_correction.attr,
3968 NULL,
3969 };
3970
3971 static const struct attribute_group adva_timecard_group = {
3972 .attrs = adva_timecard_attrs,
3973 };
3974
3975 static const struct ocp_attr_group adva_timecard_groups[] = {
3976 { .cap = OCP_CAP_BASIC, .group = &adva_timecard_group },
3977 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },
3978 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
3979 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
3980 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
3981 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
3982 { },
3983 };
3984
3985 static void
gpio_input_map(char * buf,struct ptp_ocp * bp,u16 map[][2],u16 bit,const char * def)3986 gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit,
3987 const char *def)
3988 {
3989 int i;
3990
3991 for (i = 0; i < 4; i++) {
3992 if (bp->sma[i].mode != SMA_MODE_IN)
3993 continue;
3994 if (map[i][0] & (1 << bit)) {
3995 sprintf(buf, "sma%d", i + 1);
3996 return;
3997 }
3998 }
3999 if (!def)
4000 def = "----";
4001 strcpy(buf, def);
4002 }
4003
4004 static void
gpio_output_map(char * buf,struct ptp_ocp * bp,u16 map[][2],u16 bit)4005 gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit)
4006 {
4007 char *ans = buf;
4008 int i;
4009
4010 strcpy(ans, "----");
4011 for (i = 0; i < 4; i++) {
4012 if (bp->sma[i].mode != SMA_MODE_OUT)
4013 continue;
4014 if (map[i][1] & (1 << bit))
4015 ans += sprintf(ans, "sma%d ", i + 1);
4016 }
4017 }
4018
4019 static void
_signal_summary_show(struct seq_file * s,struct ptp_ocp * bp,int nr)4020 _signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr)
4021 {
4022 struct signal_reg __iomem *reg = bp->signal_out[nr]->mem;
4023 struct ptp_ocp_signal *signal = &bp->signal[nr];
4024 char label[16];
4025 bool on;
4026 u32 val;
4027
4028 on = signal->running;
4029 sprintf(label, "GEN%d", nr + 1);
4030 seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d",
4031 label, on ? " ON" : "OFF",
4032 signal->period, signal->duty, signal->phase,
4033 signal->polarity);
4034
4035 val = ioread32(®->enable);
4036 seq_printf(s, " [%x", val);
4037 val = ioread32(®->status);
4038 seq_printf(s, " %x]", val);
4039
4040 seq_printf(s, " start:%llu\n", signal->start);
4041 }
4042
4043 static void
_frequency_summary_show(struct seq_file * s,int nr,struct frequency_reg __iomem * reg)4044 _frequency_summary_show(struct seq_file *s, int nr,
4045 struct frequency_reg __iomem *reg)
4046 {
4047 char label[16];
4048 bool on;
4049 u32 val;
4050
4051 if (!reg)
4052 return;
4053
4054 sprintf(label, "FREQ%d", nr + 1);
4055 val = ioread32(®->ctrl);
4056 on = val & 1;
4057 val = (val >> 8) & 0xff;
4058 seq_printf(s, "%7s: %s, sec:%u",
4059 label,
4060 on ? " ON" : "OFF",
4061 val);
4062
4063 val = ioread32(®->status);
4064 if (val & FREQ_STATUS_ERROR)
4065 seq_printf(s, ", error");
4066 if (val & FREQ_STATUS_OVERRUN)
4067 seq_printf(s, ", overrun");
4068 if (val & FREQ_STATUS_VALID)
4069 seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK);
4070 seq_printf(s, " reg:%x\n", val);
4071 }
4072
4073 static int
ptp_ocp_summary_show(struct seq_file * s,void * data)4074 ptp_ocp_summary_show(struct seq_file *s, void *data)
4075 {
4076 struct device *dev = s->private;
4077 struct ptp_system_timestamp sts;
4078 struct ts_reg __iomem *ts_reg;
4079 char *buf, *src, *mac_src;
4080 struct timespec64 ts;
4081 struct ptp_ocp *bp;
4082 u16 sma_val[4][2];
4083 u32 ctrl, val;
4084 bool on, map;
4085 int i;
4086
4087 buf = (char *)__get_free_page(GFP_KERNEL);
4088 if (!buf)
4089 return -ENOMEM;
4090
4091 bp = dev_get_drvdata(dev);
4092
4093 seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp));
4094 for (i = 0; i < __PORT_COUNT; i++) {
4095 if (bp->port[i].line != -1)
4096 seq_printf(s, "%7s: /dev/ttyS%d\n", ptp_ocp_tty_port_name(i),
4097 bp->port[i].line);
4098 }
4099
4100 memset(sma_val, 0xff, sizeof(sma_val));
4101 if (bp->sma_map1) {
4102 u32 reg;
4103
4104 reg = ioread32(&bp->sma_map1->gpio1);
4105 sma_val[0][0] = reg & 0xffff;
4106 sma_val[1][0] = reg >> 16;
4107
4108 reg = ioread32(&bp->sma_map1->gpio2);
4109 sma_val[2][1] = reg & 0xffff;
4110 sma_val[3][1] = reg >> 16;
4111
4112 reg = ioread32(&bp->sma_map2->gpio1);
4113 sma_val[2][0] = reg & 0xffff;
4114 sma_val[3][0] = reg >> 16;
4115
4116 reg = ioread32(&bp->sma_map2->gpio2);
4117 sma_val[0][1] = reg & 0xffff;
4118 sma_val[1][1] = reg >> 16;
4119 }
4120
4121 sma1_show(dev, NULL, buf);
4122 seq_printf(s, " sma1: %04x,%04x %s",
4123 sma_val[0][0], sma_val[0][1], buf);
4124
4125 sma2_show(dev, NULL, buf);
4126 seq_printf(s, " sma2: %04x,%04x %s",
4127 sma_val[1][0], sma_val[1][1], buf);
4128
4129 sma3_show(dev, NULL, buf);
4130 seq_printf(s, " sma3: %04x,%04x %s",
4131 sma_val[2][0], sma_val[2][1], buf);
4132
4133 sma4_show(dev, NULL, buf);
4134 seq_printf(s, " sma4: %04x,%04x %s",
4135 sma_val[3][0], sma_val[3][1], buf);
4136
4137 if (bp->ts0) {
4138 ts_reg = bp->ts0->mem;
4139 on = ioread32(&ts_reg->enable);
4140 src = "GNSS1";
4141 seq_printf(s, "%7s: %s, src: %s\n", "TS0",
4142 on ? " ON" : "OFF", src);
4143 }
4144
4145 if (bp->ts1) {
4146 ts_reg = bp->ts1->mem;
4147 on = ioread32(&ts_reg->enable);
4148 gpio_input_map(buf, bp, sma_val, 2, NULL);
4149 seq_printf(s, "%7s: %s, src: %s\n", "TS1",
4150 on ? " ON" : "OFF", buf);
4151 }
4152
4153 if (bp->ts2) {
4154 ts_reg = bp->ts2->mem;
4155 on = ioread32(&ts_reg->enable);
4156 gpio_input_map(buf, bp, sma_val, 3, NULL);
4157 seq_printf(s, "%7s: %s, src: %s\n", "TS2",
4158 on ? " ON" : "OFF", buf);
4159 }
4160
4161 if (bp->ts3) {
4162 ts_reg = bp->ts3->mem;
4163 on = ioread32(&ts_reg->enable);
4164 gpio_input_map(buf, bp, sma_val, 6, NULL);
4165 seq_printf(s, "%7s: %s, src: %s\n", "TS3",
4166 on ? " ON" : "OFF", buf);
4167 }
4168
4169 if (bp->ts4) {
4170 ts_reg = bp->ts4->mem;
4171 on = ioread32(&ts_reg->enable);
4172 gpio_input_map(buf, bp, sma_val, 7, NULL);
4173 seq_printf(s, "%7s: %s, src: %s\n", "TS4",
4174 on ? " ON" : "OFF", buf);
4175 }
4176
4177 if (bp->pps) {
4178 ts_reg = bp->pps->mem;
4179 src = "PHC";
4180 on = ioread32(&ts_reg->enable);
4181 map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP);
4182 seq_printf(s, "%7s: %s, src: %s\n", "TS5",
4183 on && map ? " ON" : "OFF", src);
4184
4185 map = !!(bp->pps_req_map & OCP_REQ_PPS);
4186 seq_printf(s, "%7s: %s, src: %s\n", "PPS",
4187 on && map ? " ON" : "OFF", src);
4188 }
4189
4190 if (bp->fw_cap & OCP_CAP_SIGNAL)
4191 for (i = 0; i < bp->signals_nr; i++)
4192 _signal_summary_show(s, bp, i);
4193
4194 if (bp->fw_cap & OCP_CAP_FREQ)
4195 for (i = 0; i < bp->freq_in_nr; i++)
4196 _frequency_summary_show(s, i, bp->freq_in[i]);
4197
4198 if (bp->irig_out) {
4199 ctrl = ioread32(&bp->irig_out->ctrl);
4200 on = ctrl & IRIG_M_CTRL_ENABLE;
4201 val = ioread32(&bp->irig_out->status);
4202 gpio_output_map(buf, bp, sma_val, 4);
4203 seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG",
4204 on ? " ON" : "OFF", val, (ctrl >> 16), buf);
4205 }
4206
4207 if (bp->irig_in) {
4208 on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE;
4209 val = ioread32(&bp->irig_in->status);
4210 gpio_input_map(buf, bp, sma_val, 4, NULL);
4211 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in",
4212 on ? " ON" : "OFF", val, buf);
4213 }
4214
4215 if (bp->dcf_out) {
4216 on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE;
4217 val = ioread32(&bp->dcf_out->status);
4218 gpio_output_map(buf, bp, sma_val, 5);
4219 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF",
4220 on ? " ON" : "OFF", val, buf);
4221 }
4222
4223 if (bp->dcf_in) {
4224 on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE;
4225 val = ioread32(&bp->dcf_in->status);
4226 gpio_input_map(buf, bp, sma_val, 5, NULL);
4227 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in",
4228 on ? " ON" : "OFF", val, buf);
4229 }
4230
4231 if (bp->nmea_out) {
4232 on = ioread32(&bp->nmea_out->ctrl) & 1;
4233 val = ioread32(&bp->nmea_out->status);
4234 seq_printf(s, "%7s: %s, error: %d\n", "NMEA",
4235 on ? " ON" : "OFF", val);
4236 }
4237
4238 /* compute src for PPS1, used below. */
4239 if (bp->pps_select) {
4240 val = ioread32(&bp->pps_select->gpio1);
4241 src = &buf[80];
4242 mac_src = "GNSS1";
4243 if (val & 0x01) {
4244 gpio_input_map(src, bp, sma_val, 0, NULL);
4245 mac_src = src;
4246 } else if (val & 0x02) {
4247 src = "MAC";
4248 } else if (val & 0x04) {
4249 src = "GNSS1";
4250 } else {
4251 src = "----";
4252 mac_src = src;
4253 }
4254 } else {
4255 src = "?";
4256 mac_src = src;
4257 }
4258 seq_printf(s, "MAC PPS1 src: %s\n", mac_src);
4259
4260 gpio_input_map(buf, bp, sma_val, 1, "GNSS2");
4261 seq_printf(s, "MAC PPS2 src: %s\n", buf);
4262
4263 /* assumes automatic switchover/selection */
4264 val = ioread32(&bp->reg->select);
4265 switch (val >> 16) {
4266 case 0:
4267 sprintf(buf, "----");
4268 break;
4269 case 2:
4270 sprintf(buf, "IRIG");
4271 break;
4272 case 3:
4273 sprintf(buf, "%s via PPS1", src);
4274 break;
4275 case 6:
4276 sprintf(buf, "DCF");
4277 break;
4278 default:
4279 strcpy(buf, "unknown");
4280 break;
4281 }
4282 seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,
4283 bp->sync ? "sync" : "unsynced");
4284
4285 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {
4286 struct timespec64 sys_ts;
4287 s64 pre_ns, post_ns, ns;
4288
4289 pre_ns = timespec64_to_ns(&sts.pre_ts);
4290 post_ns = timespec64_to_ns(&sts.post_ts);
4291 ns = (pre_ns + post_ns) / 2;
4292 ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC;
4293 sys_ts = ns_to_timespec64(ns);
4294
4295 seq_printf(s, "%7s: %ptSp == %ptS TAI\n", "PHC", &ts, &ts);
4296 seq_printf(s, "%7s: %ptSp == %ptS UTC offset %d\n", "SYS",
4297 &sys_ts, &sys_ts, bp->utc_tai_offset);
4298 seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "",
4299 timespec64_to_ns(&ts) - ns,
4300 post_ns - pre_ns);
4301 }
4302
4303 free_page((unsigned long)buf);
4304 return 0;
4305 }
4306 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary);
4307
4308 static int
ptp_ocp_tod_status_show(struct seq_file * s,void * data)4309 ptp_ocp_tod_status_show(struct seq_file *s, void *data)
4310 {
4311 struct device *dev = s->private;
4312 struct ptp_ocp *bp;
4313 u32 val;
4314 int idx;
4315
4316 bp = dev_get_drvdata(dev);
4317
4318 val = ioread32(&bp->tod->ctrl);
4319 if (!(val & TOD_CTRL_ENABLE)) {
4320 seq_printf(s, "TOD Slave disabled\n");
4321 return 0;
4322 }
4323 seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val);
4324
4325 idx = val & TOD_CTRL_PROTOCOL ? 4 : 0;
4326 idx += (val >> 16) & 3;
4327 seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx));
4328
4329 idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;
4330 seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx));
4331
4332 val = ioread32(&bp->tod->version);
4333 seq_printf(s, "TOD Version %d.%d.%d\n",
4334 val >> 24, (val >> 16) & 0xff, val & 0xffff);
4335
4336 val = ioread32(&bp->tod->status);
4337 seq_printf(s, "Status register: 0x%08X\n", val);
4338
4339 val = ioread32(&bp->tod->adj_sec);
4340 idx = (val & ~INT_MAX) ? -1 : 1;
4341 idx *= (val & INT_MAX);
4342 seq_printf(s, "Correction seconds: %d\n", idx);
4343
4344 val = ioread32(&bp->tod->utc_status);
4345 seq_printf(s, "UTC status register: 0x%08X\n", val);
4346 seq_printf(s, "UTC offset: %ld valid:%d\n",
4347 val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0);
4348 seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n",
4349 val & TOD_STATUS_LEAP_VALID ? 1 : 0,
4350 val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0);
4351
4352 val = ioread32(&bp->tod->leap);
4353 seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val);
4354
4355 return 0;
4356 }
4357 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status);
4358
4359 static struct dentry *ptp_ocp_debugfs_root;
4360
4361 static void
ptp_ocp_debugfs_add_device(struct ptp_ocp * bp)4362 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp)
4363 {
4364 struct dentry *d;
4365
4366 d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root);
4367 bp->debug_root = d;
4368 debugfs_create_file("summary", 0444, bp->debug_root,
4369 &bp->dev, &ptp_ocp_summary_fops);
4370 if (bp->tod)
4371 debugfs_create_file("tod_status", 0444, bp->debug_root,
4372 &bp->dev, &ptp_ocp_tod_status_fops);
4373 }
4374
4375 static void
ptp_ocp_debugfs_remove_device(struct ptp_ocp * bp)4376 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp)
4377 {
4378 debugfs_remove_recursive(bp->debug_root);
4379 }
4380
4381 static void
ptp_ocp_debugfs_init(void)4382 ptp_ocp_debugfs_init(void)
4383 {
4384 ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL);
4385 }
4386
4387 static void
ptp_ocp_debugfs_fini(void)4388 ptp_ocp_debugfs_fini(void)
4389 {
4390 debugfs_remove_recursive(ptp_ocp_debugfs_root);
4391 }
4392
4393 static void
ptp_ocp_dev_release(struct device * dev)4394 ptp_ocp_dev_release(struct device *dev)
4395 {
4396 struct ptp_ocp *bp = dev_get_drvdata(dev);
4397
4398 mutex_lock(&ptp_ocp_lock);
4399 idr_remove(&ptp_ocp_idr, bp->id);
4400 mutex_unlock(&ptp_ocp_lock);
4401 }
4402
4403 static int
ptp_ocp_device_init(struct ptp_ocp * bp,struct pci_dev * pdev)4404 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev)
4405 {
4406 int i, err;
4407
4408 mutex_lock(&ptp_ocp_lock);
4409 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL);
4410 mutex_unlock(&ptp_ocp_lock);
4411 if (err < 0) {
4412 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err);
4413 return err;
4414 }
4415 bp->id = err;
4416
4417 bp->ptp_info = ptp_ocp_clock_info;
4418 spin_lock_init(&bp->lock);
4419
4420 for (i = 0; i < __PORT_COUNT; i++)
4421 bp->port[i].line = -1;
4422
4423 bp->pdev = pdev;
4424
4425 device_initialize(&bp->dev);
4426 dev_set_name(&bp->dev, "ocp%d", bp->id);
4427 bp->dev.class = &timecard_class;
4428 bp->dev.parent = &pdev->dev;
4429 bp->dev.release = ptp_ocp_dev_release;
4430 dev_set_drvdata(&bp->dev, bp);
4431
4432 err = device_add(&bp->dev);
4433 if (err) {
4434 dev_err(&bp->dev, "device add failed: %d\n", err);
4435 goto out;
4436 }
4437
4438 pci_set_drvdata(pdev, bp);
4439
4440 return 0;
4441
4442 out:
4443 put_device(&bp->dev);
4444 return err;
4445 }
4446
4447 static void
ptp_ocp_symlink(struct ptp_ocp * bp,struct device * child,const char * link)4448 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link)
4449 {
4450 struct device *dev = &bp->dev;
4451
4452 if (sysfs_create_link(&dev->kobj, &child->kobj, link))
4453 dev_err(dev, "%s symlink failed\n", link);
4454 }
4455
4456 static void
ptp_ocp_link_child(struct ptp_ocp * bp,const char * name,const char * link)4457 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link)
4458 {
4459 struct device *dev, *child;
4460
4461 dev = &bp->pdev->dev;
4462
4463 child = device_find_child_by_name(dev, name);
4464 if (!child) {
4465 dev_err(dev, "Could not find device %s\n", name);
4466 return;
4467 }
4468
4469 ptp_ocp_symlink(bp, child, link);
4470 put_device(child);
4471 }
4472
4473 static int
ptp_ocp_complete(struct ptp_ocp * bp)4474 ptp_ocp_complete(struct ptp_ocp *bp)
4475 {
4476 struct pps_device *pps;
4477 char buf[32];
4478
4479 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp));
4480 ptp_ocp_link_child(bp, buf, "ptp");
4481
4482 pps = pps_lookup_dev(bp->ptp);
4483 if (pps)
4484 ptp_ocp_symlink(bp, &pps->dev, "pps");
4485
4486 ptp_ocp_debugfs_add_device(bp);
4487
4488 return 0;
4489 }
4490
4491 static void
ptp_ocp_phc_info(struct ptp_ocp * bp)4492 ptp_ocp_phc_info(struct ptp_ocp *bp)
4493 {
4494 struct timespec64 ts;
4495 u32 version, select;
4496
4497 version = ioread32(&bp->reg->version);
4498 select = ioread32(&bp->reg->select);
4499 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",
4500 version >> 24, (version >> 16) & 0xff, version & 0xffff,
4501 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),
4502 ptp_clock_index(bp->ptp));
4503
4504 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
4505 dev_info(&bp->pdev->dev, "Time: %ptSp, %s\n",
4506 &ts, bp->sync ? "in-sync" : "UNSYNCED");
4507 }
4508
4509 static void
ptp_ocp_serial_info(struct device * dev,const char * name,int port,int baud)4510 ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud)
4511 {
4512 if (port != -1)
4513 dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud);
4514 }
4515
4516 static void
ptp_ocp_info(struct ptp_ocp * bp)4517 ptp_ocp_info(struct ptp_ocp *bp)
4518 {
4519 static int nmea_baud[] = {
4520 1200, 2400, 4800, 9600, 19200, 38400,
4521 57600, 115200, 230400, 460800, 921600,
4522 1000000, 2000000
4523 };
4524 struct device *dev = &bp->pdev->dev;
4525 u32 reg;
4526 int i;
4527
4528 ptp_ocp_phc_info(bp);
4529
4530 for (i = 0; i < __PORT_COUNT; i++) {
4531 if (i == PORT_NMEA && bp->nmea_out && bp->port[PORT_NMEA].line != -1) {
4532 bp->port[PORT_NMEA].baud = -1;
4533
4534 reg = ioread32(&bp->nmea_out->uart_baud);
4535 if (reg < ARRAY_SIZE(nmea_baud))
4536 bp->port[PORT_NMEA].baud = nmea_baud[reg];
4537 }
4538 ptp_ocp_serial_info(dev, ptp_ocp_tty_port_name(i), bp->port[i].line,
4539 bp->port[i].baud);
4540 }
4541 }
4542
4543 static void
ptp_ocp_detach_sysfs(struct ptp_ocp * bp)4544 ptp_ocp_detach_sysfs(struct ptp_ocp *bp)
4545 {
4546 struct device *dev = &bp->dev;
4547
4548 sysfs_remove_link(&dev->kobj, "ptp");
4549 sysfs_remove_link(&dev->kobj, "pps");
4550 }
4551
4552 static void
ptp_ocp_detach(struct ptp_ocp * bp)4553 ptp_ocp_detach(struct ptp_ocp *bp)
4554 {
4555 int i;
4556
4557 ptp_ocp_debugfs_remove_device(bp);
4558 ptp_ocp_detach_sysfs(bp);
4559 ptp_ocp_attr_group_del(bp);
4560 timer_delete_sync(&bp->watchdog);
4561 ptp_ocp_unregister_ext(bp->ts0);
4562 ptp_ocp_unregister_ext(bp->ts1);
4563 ptp_ocp_unregister_ext(bp->ts2);
4564 ptp_ocp_unregister_ext(bp->ts3);
4565 ptp_ocp_unregister_ext(bp->ts4);
4566 ptp_ocp_unregister_ext(bp->pps);
4567 for (i = 0; i < 4; i++)
4568 ptp_ocp_unregister_ext(bp->signal_out[i]);
4569 for (i = 0; i < __PORT_COUNT; i++)
4570 if (bp->port[i].line != -1)
4571 serial8250_unregister_port(bp->port[i].line);
4572 platform_device_unregister(bp->spi_flash);
4573 platform_device_unregister(bp->i2c_ctrl);
4574 if (bp->i2c_clk)
4575 clk_hw_unregister_fixed_rate(bp->i2c_clk);
4576 if (bp->n_irqs)
4577 pci_free_irq_vectors(bp->pdev);
4578 if (bp->ptp)
4579 ptp_clock_unregister(bp->ptp);
4580 kfree(bp->ptp_info.pin_config);
4581 device_unregister(&bp->dev);
4582 }
4583
4584 static int
ptp_ocp_dpll_lock_status_get(const struct dpll_device * dpll,void * priv,enum dpll_lock_status * status,enum dpll_lock_status_error * status_error,struct netlink_ext_ack * extack)4585 ptp_ocp_dpll_lock_status_get(const struct dpll_device *dpll, void *priv,
4586 enum dpll_lock_status *status,
4587 enum dpll_lock_status_error *status_error,
4588 struct netlink_ext_ack *extack)
4589 {
4590 struct ptp_ocp *bp = priv;
4591
4592 *status = bp->sync ? DPLL_LOCK_STATUS_LOCKED : DPLL_LOCK_STATUS_UNLOCKED;
4593
4594 return 0;
4595 }
4596
ptp_ocp_dpll_state_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack)4597 static int ptp_ocp_dpll_state_get(const struct dpll_pin *pin, void *pin_priv,
4598 const struct dpll_device *dpll, void *priv,
4599 enum dpll_pin_state *state,
4600 struct netlink_ext_ack *extack)
4601 {
4602 struct ptp_ocp *bp = priv;
4603 int idx;
4604
4605 if (bp->pps_select) {
4606 idx = ioread32(&bp->pps_select->gpio1);
4607 *state = (&bp->sma[idx] == pin_priv) ? DPLL_PIN_STATE_CONNECTED :
4608 DPLL_PIN_STATE_SELECTABLE;
4609 return 0;
4610 }
4611 NL_SET_ERR_MSG(extack, "pin selection is not supported on current HW");
4612 return -EINVAL;
4613 }
4614
ptp_ocp_dpll_mode_get(const struct dpll_device * dpll,void * priv,enum dpll_mode * mode,struct netlink_ext_ack * extack)4615 static int ptp_ocp_dpll_mode_get(const struct dpll_device *dpll, void *priv,
4616 enum dpll_mode *mode, struct netlink_ext_ack *extack)
4617 {
4618 *mode = DPLL_MODE_AUTOMATIC;
4619 return 0;
4620 }
4621
ptp_ocp_dpll_direction_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * priv,enum dpll_pin_direction * direction,struct netlink_ext_ack * extack)4622 static int ptp_ocp_dpll_direction_get(const struct dpll_pin *pin,
4623 void *pin_priv,
4624 const struct dpll_device *dpll,
4625 void *priv,
4626 enum dpll_pin_direction *direction,
4627 struct netlink_ext_ack *extack)
4628 {
4629 struct ptp_ocp_sma_connector *sma = pin_priv;
4630
4631 *direction = sma->mode == SMA_MODE_IN ?
4632 DPLL_PIN_DIRECTION_INPUT :
4633 DPLL_PIN_DIRECTION_OUTPUT;
4634 return 0;
4635 }
4636
ptp_ocp_dpll_direction_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_direction direction,struct netlink_ext_ack * extack)4637 static int ptp_ocp_dpll_direction_set(const struct dpll_pin *pin,
4638 void *pin_priv,
4639 const struct dpll_device *dpll,
4640 void *dpll_priv,
4641 enum dpll_pin_direction direction,
4642 struct netlink_ext_ack *extack)
4643 {
4644 struct ptp_ocp_sma_connector *sma = pin_priv;
4645 struct ptp_ocp *bp = dpll_priv;
4646 enum ptp_ocp_sma_mode mode;
4647 int sma_nr = (sma - bp->sma);
4648
4649 if (sma->fixed_dir)
4650 return -EOPNOTSUPP;
4651 mode = direction == DPLL_PIN_DIRECTION_INPUT ?
4652 SMA_MODE_IN : SMA_MODE_OUT;
4653 return ptp_ocp_sma_store_val(bp, 0, mode, sma_nr + 1);
4654 }
4655
ptp_ocp_dpll_frequency_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack)4656 static int ptp_ocp_dpll_frequency_set(const struct dpll_pin *pin,
4657 void *pin_priv,
4658 const struct dpll_device *dpll,
4659 void *dpll_priv, u64 frequency,
4660 struct netlink_ext_ack *extack)
4661 {
4662 struct ptp_ocp_sma_connector *sma = pin_priv;
4663 struct ptp_ocp *bp = dpll_priv;
4664 const struct ocp_selector *tbl;
4665 int sma_nr = (sma - bp->sma);
4666 int i;
4667
4668 if (sma->fixed_fcn)
4669 return -EOPNOTSUPP;
4670
4671 tbl = bp->sma_op->tbl[sma->mode];
4672 for (i = 0; tbl[i].name; i++)
4673 if (tbl[i].frequency == frequency)
4674 return ptp_ocp_sma_store_val(bp, i, sma->mode, sma_nr + 1);
4675 return -EINVAL;
4676 }
4677
ptp_ocp_dpll_frequency_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack)4678 static int ptp_ocp_dpll_frequency_get(const struct dpll_pin *pin,
4679 void *pin_priv,
4680 const struct dpll_device *dpll,
4681 void *dpll_priv, u64 *frequency,
4682 struct netlink_ext_ack *extack)
4683 {
4684 struct ptp_ocp_sma_connector *sma = pin_priv;
4685 struct ptp_ocp *bp = dpll_priv;
4686 const struct ocp_selector *tbl;
4687 int sma_nr = (sma - bp->sma);
4688 u32 val;
4689 int i;
4690
4691 val = bp->sma_op->get(bp, sma_nr + 1);
4692 tbl = bp->sma_op->tbl[sma->mode];
4693 for (i = 0; tbl[i].name; i++)
4694 if (val == tbl[i].value) {
4695 *frequency = tbl[i].frequency;
4696 return 0;
4697 }
4698
4699 return -EINVAL;
4700 }
4701
4702 static const struct dpll_device_ops dpll_ops = {
4703 .lock_status_get = ptp_ocp_dpll_lock_status_get,
4704 .mode_get = ptp_ocp_dpll_mode_get,
4705 };
4706
4707 static const struct dpll_pin_ops dpll_pins_ops = {
4708 .frequency_get = ptp_ocp_dpll_frequency_get,
4709 .frequency_set = ptp_ocp_dpll_frequency_set,
4710 .direction_get = ptp_ocp_dpll_direction_get,
4711 .direction_set = ptp_ocp_dpll_direction_set,
4712 .state_on_dpll_get = ptp_ocp_dpll_state_get,
4713 };
4714
4715 static void
ptp_ocp_sync_work(struct work_struct * work)4716 ptp_ocp_sync_work(struct work_struct *work)
4717 {
4718 struct ptp_ocp *bp;
4719 bool sync;
4720
4721 bp = container_of(work, struct ptp_ocp, sync_work.work);
4722 sync = !!(ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC);
4723
4724 if (bp->sync != sync)
4725 dpll_device_change_ntf(bp->dpll);
4726
4727 bp->sync = sync;
4728
4729 queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
4730 }
4731
4732 static int
ptp_ocp_probe(struct pci_dev * pdev,const struct pci_device_id * id)4733 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
4734 {
4735 struct devlink *devlink;
4736 struct ptp_ocp *bp;
4737 int err, i;
4738 u64 clkid;
4739
4740 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);
4741 if (!devlink) {
4742 dev_err(&pdev->dev, "devlink_alloc failed\n");
4743 return -ENOMEM;
4744 }
4745
4746 err = pci_enable_device(pdev);
4747 if (err) {
4748 dev_err(&pdev->dev, "pci_enable_device\n");
4749 goto out_free;
4750 }
4751
4752 bp = devlink_priv(devlink);
4753 err = ptp_ocp_device_init(bp, pdev);
4754 if (err)
4755 goto out_disable;
4756
4757 INIT_DELAYED_WORK(&bp->sync_work, ptp_ocp_sync_work);
4758
4759 /* compat mode.
4760 * Older FPGA firmware only returns 2 irq's.
4761 * allow this - if not all of the IRQ's are returned, skip the
4762 * extra devices and just register the clock.
4763 */
4764 err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX);
4765 if (err < 0) {
4766 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err);
4767 goto out;
4768 }
4769 bp->n_irqs = err;
4770 pci_set_master(pdev);
4771
4772 err = ptp_ocp_register_resources(bp, id->driver_data);
4773 if (err)
4774 goto out;
4775
4776 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);
4777 if (IS_ERR(bp->ptp)) {
4778 err = PTR_ERR(bp->ptp);
4779 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err);
4780 bp->ptp = NULL;
4781 goto out;
4782 }
4783
4784 err = ptp_ocp_complete(bp);
4785 if (err)
4786 goto out;
4787
4788 ptp_ocp_info(bp);
4789 devlink_register(devlink);
4790
4791 clkid = pci_get_dsn(pdev);
4792 bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE, &bp->tracker);
4793 if (IS_ERR(bp->dpll)) {
4794 err = PTR_ERR(bp->dpll);
4795 dev_err(&pdev->dev, "dpll_device_alloc failed\n");
4796 goto out;
4797 }
4798
4799 err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp);
4800 if (err)
4801 goto out;
4802
4803 for (i = 0; i < OCP_SMA_NUM; i++) {
4804 bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE,
4805 &bp->sma[i].dpll_prop,
4806 &bp->sma[i].tracker);
4807 if (IS_ERR(bp->sma[i].dpll_pin)) {
4808 err = PTR_ERR(bp->sma[i].dpll_pin);
4809 goto out_dpll;
4810 }
4811
4812 err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops,
4813 &bp->sma[i]);
4814 if (err) {
4815 dpll_pin_put(bp->sma[i].dpll_pin, &bp->sma[i].tracker);
4816 goto out_dpll;
4817 }
4818 }
4819 queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
4820
4821 return 0;
4822 out_dpll:
4823 while (i--) {
4824 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
4825 dpll_pin_put(bp->sma[i].dpll_pin, &bp->sma[i].tracker);
4826 }
4827 dpll_device_put(bp->dpll, &bp->tracker);
4828 out:
4829 ptp_ocp_detach(bp);
4830 out_disable:
4831 pci_disable_device(pdev);
4832 out_free:
4833 devlink_free(devlink);
4834 return err;
4835 }
4836
4837 static void
ptp_ocp_remove(struct pci_dev * pdev)4838 ptp_ocp_remove(struct pci_dev *pdev)
4839 {
4840 struct ptp_ocp *bp = pci_get_drvdata(pdev);
4841 struct devlink *devlink = priv_to_devlink(bp);
4842 int i;
4843
4844 cancel_delayed_work_sync(&bp->sync_work);
4845 for (i = 0; i < OCP_SMA_NUM; i++) {
4846 if (bp->sma[i].dpll_pin) {
4847 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
4848 dpll_pin_put(bp->sma[i].dpll_pin, &bp->sma[i].tracker);
4849 }
4850 }
4851 dpll_device_unregister(bp->dpll, &dpll_ops, bp);
4852 dpll_device_put(bp->dpll, &bp->tracker);
4853 devlink_unregister(devlink);
4854 ptp_ocp_detach(bp);
4855 pci_disable_device(pdev);
4856
4857 devlink_free(devlink);
4858 }
4859
4860 static struct pci_driver ptp_ocp_driver = {
4861 .name = KBUILD_MODNAME,
4862 .id_table = ptp_ocp_pcidev_id,
4863 .probe = ptp_ocp_probe,
4864 .remove = ptp_ocp_remove,
4865 };
4866
4867 static int
ptp_ocp_i2c_notifier_call(struct notifier_block * nb,unsigned long action,void * data)4868 ptp_ocp_i2c_notifier_call(struct notifier_block *nb,
4869 unsigned long action, void *data)
4870 {
4871 struct device *dev, *child = data;
4872 struct ptp_ocp *bp;
4873 bool add;
4874
4875 switch (action) {
4876 case BUS_NOTIFY_ADD_DEVICE:
4877 case BUS_NOTIFY_DEL_DEVICE:
4878 add = action == BUS_NOTIFY_ADD_DEVICE;
4879 break;
4880 default:
4881 return 0;
4882 }
4883
4884 if (!i2c_verify_adapter(child))
4885 return 0;
4886
4887 dev = child;
4888 while ((dev = dev->parent))
4889 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
4890 goto found;
4891 return 0;
4892
4893 found:
4894 bp = dev_get_drvdata(dev);
4895 if (add)
4896 ptp_ocp_symlink(bp, child, "i2c");
4897 else
4898 sysfs_remove_link(&bp->dev.kobj, "i2c");
4899
4900 return 0;
4901 }
4902
4903 static struct notifier_block ptp_ocp_i2c_notifier = {
4904 .notifier_call = ptp_ocp_i2c_notifier_call,
4905 };
4906
4907 static int __init
ptp_ocp_init(void)4908 ptp_ocp_init(void)
4909 {
4910 const char *what;
4911 int err;
4912
4913 ptp_ocp_debugfs_init();
4914
4915 what = "timecard class";
4916 err = class_register(&timecard_class);
4917 if (err)
4918 goto out;
4919
4920 what = "i2c notifier";
4921 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4922 if (err)
4923 goto out_notifier;
4924
4925 what = "ptp_ocp driver";
4926 err = pci_register_driver(&ptp_ocp_driver);
4927 if (err)
4928 goto out_register;
4929
4930 return 0;
4931
4932 out_register:
4933 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4934 out_notifier:
4935 class_unregister(&timecard_class);
4936 out:
4937 ptp_ocp_debugfs_fini();
4938 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err);
4939 return err;
4940 }
4941
4942 static void __exit
ptp_ocp_fini(void)4943 ptp_ocp_fini(void)
4944 {
4945 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4946 pci_unregister_driver(&ptp_ocp_driver);
4947 class_unregister(&timecard_class);
4948 ptp_ocp_debugfs_fini();
4949 }
4950
4951 module_init(ptp_ocp_init);
4952 module_exit(ptp_ocp_fini);
4953
4954 MODULE_DESCRIPTION("OpenCompute TimeCard driver");
4955 MODULE_LICENSE("GPL v2");
4956