1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include <linux/debugfs.h>
26 #include <linux/firmware.h>
27 #include <drm/drm_vblank.h>
28
29 #include <drm/drm_file.h>
30 #include <drm/drm_print.h>
31
32 #include "i915_reg.h"
33 #include "intel_crtc.h"
34 #include "intel_de.h"
35 #include "intel_display_power_well.h"
36 #include "intel_display_regs.h"
37 #include "intel_display_rpm.h"
38 #include "intel_display_types.h"
39 #include "intel_display_utils.h"
40 #include "intel_dmc.h"
41 #include "intel_dmc_regs.h"
42 #include "intel_flipq.h"
43 #include "intel_step.h"
44
45 /**
46 * DOC: DMC Firmware Support
47 *
48 * From gen9 onwards we have newly added DMC (Display microcontroller) in display
49 * engine to save and restore the state of display engine when it enter into
50 * low-power state and comes back to normal.
51 */
52
53 #define INTEL_DMC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git"
54
55 enum intel_dmc_id {
56 DMC_FW_MAIN = 0,
57 DMC_FW_PIPEA,
58 DMC_FW_PIPEB,
59 DMC_FW_PIPEC,
60 DMC_FW_PIPED,
61 DMC_FW_MAX
62 };
63
64 struct intel_dmc {
65 struct intel_display *display;
66 struct work_struct work;
67 const char *fw_path;
68 u32 max_fw_size; /* bytes */
69 u32 version;
70 struct {
71 u32 dc5_start;
72 u32 count;
73 } dc6_allowed;
74 struct dmc_fw_info {
75 u32 mmio_count;
76 i915_reg_t mmioaddr[20];
77 u32 mmiodata[20];
78 u32 dmc_offset;
79 u32 start_mmioaddr;
80 u32 dmc_fw_size; /*dwords */
81 u32 *payload;
82 bool present;
83 } dmc_info[DMC_FW_MAX];
84 };
85
86 /* Note: This may be NULL. */
display_to_dmc(struct intel_display * display)87 static struct intel_dmc *display_to_dmc(struct intel_display *display)
88 {
89 return display->dmc.dmc;
90 }
91
dmc_firmware_param(struct intel_display * display)92 static const char *dmc_firmware_param(struct intel_display *display)
93 {
94 const char *p = display->params.dmc_firmware_path;
95
96 return p && *p ? p : NULL;
97 }
98
dmc_firmware_param_disabled(struct intel_display * display)99 static bool dmc_firmware_param_disabled(struct intel_display *display)
100 {
101 const char *p = dmc_firmware_param(display);
102
103 /* Magic path to indicate disabled */
104 return p && !strcmp(p, "/dev/null");
105 }
106
107 #define DMC_VERSION(major, minor) ((major) << 16 | (minor))
108 #define DMC_VERSION_MAJOR(version) ((version) >> 16)
109 #define DMC_VERSION_MINOR(version) ((version) & 0xffff)
110
111 #define DMC_PATH(platform) \
112 "i915/" __stringify(platform) "_dmc.bin"
113
114 /*
115 * New DMC additions should not use this. This is used solely to remain
116 * compatible with systems that have not yet updated DMC blobs to use
117 * unversioned file names.
118 */
119 #define DMC_LEGACY_PATH(platform, major, minor) \
120 "i915/" \
121 __stringify(platform) "_dmc_ver" \
122 __stringify(major) "_" \
123 __stringify(minor) ".bin"
124
125 #define XE2LPD_DMC_MAX_FW_SIZE 0x8000
126 #define XELPDP_DMC_MAX_FW_SIZE 0x7000
127 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000
128 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
129
130 #define XE3P_LPD_DMC_PATH DMC_PATH(xe3p_lpd)
131 MODULE_FIRMWARE(XE3P_LPD_DMC_PATH);
132
133 #define XE3LPD_3002_DMC_PATH DMC_PATH(xe3lpd_3002)
134 MODULE_FIRMWARE(XE3LPD_3002_DMC_PATH);
135
136 #define XE3LPD_DMC_PATH DMC_PATH(xe3lpd)
137 MODULE_FIRMWARE(XE3LPD_DMC_PATH);
138
139 #define XE2LPD_DMC_PATH DMC_PATH(xe2lpd)
140 MODULE_FIRMWARE(XE2LPD_DMC_PATH);
141
142 #define BMG_DMC_PATH DMC_PATH(bmg)
143 MODULE_FIRMWARE(BMG_DMC_PATH);
144
145 #define MTL_DMC_PATH DMC_PATH(mtl)
146 MODULE_FIRMWARE(MTL_DMC_PATH);
147
148 #define DG2_DMC_PATH DMC_LEGACY_PATH(dg2, 2, 08)
149 MODULE_FIRMWARE(DG2_DMC_PATH);
150
151 #define ADLP_DMC_PATH DMC_PATH(adlp)
152 #define ADLP_DMC_FALLBACK_PATH DMC_LEGACY_PATH(adlp, 2, 16)
153 MODULE_FIRMWARE(ADLP_DMC_PATH);
154 MODULE_FIRMWARE(ADLP_DMC_FALLBACK_PATH);
155
156 #define ADLS_DMC_PATH DMC_LEGACY_PATH(adls, 2, 01)
157 MODULE_FIRMWARE(ADLS_DMC_PATH);
158
159 #define DG1_DMC_PATH DMC_LEGACY_PATH(dg1, 2, 02)
160 MODULE_FIRMWARE(DG1_DMC_PATH);
161
162 #define RKL_DMC_PATH DMC_LEGACY_PATH(rkl, 2, 03)
163 MODULE_FIRMWARE(RKL_DMC_PATH);
164
165 #define TGL_DMC_PATH DMC_LEGACY_PATH(tgl, 2, 12)
166 MODULE_FIRMWARE(TGL_DMC_PATH);
167
168 #define ICL_DMC_PATH DMC_LEGACY_PATH(icl, 1, 09)
169 #define ICL_DMC_MAX_FW_SIZE 0x6000
170 MODULE_FIRMWARE(ICL_DMC_PATH);
171
172 #define GLK_DMC_PATH DMC_LEGACY_PATH(glk, 1, 04)
173 #define GLK_DMC_MAX_FW_SIZE 0x4000
174 MODULE_FIRMWARE(GLK_DMC_PATH);
175
176 #define KBL_DMC_PATH DMC_LEGACY_PATH(kbl, 1, 04)
177 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE
178 MODULE_FIRMWARE(KBL_DMC_PATH);
179
180 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27)
181 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE
182 MODULE_FIRMWARE(SKL_DMC_PATH);
183
184 #define BXT_DMC_PATH DMC_LEGACY_PATH(bxt, 1, 07)
185 #define BXT_DMC_MAX_FW_SIZE 0x3000
186 MODULE_FIRMWARE(BXT_DMC_PATH);
187
dmc_firmware_default(struct intel_display * display,u32 * size)188 static const char *dmc_firmware_default(struct intel_display *display, u32 *size)
189 {
190 const char *fw_path = NULL;
191 u32 max_fw_size = 0;
192
193 if (DISPLAY_VERx100(display) == 3500) {
194 fw_path = XE3P_LPD_DMC_PATH;
195 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;
196 } else if (DISPLAY_VERx100(display) == 3002) {
197 fw_path = XE3LPD_3002_DMC_PATH;
198 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;
199 } else if (DISPLAY_VERx100(display) == 3000) {
200 fw_path = XE3LPD_DMC_PATH;
201 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;
202 } else if (DISPLAY_VERx100(display) == 2000) {
203 fw_path = XE2LPD_DMC_PATH;
204 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;
205 } else if (DISPLAY_VERx100(display) == 1401) {
206 fw_path = BMG_DMC_PATH;
207 max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
208 } else if (DISPLAY_VERx100(display) == 1400) {
209 fw_path = MTL_DMC_PATH;
210 max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
211 } else if (display->platform.dg2) {
212 fw_path = DG2_DMC_PATH;
213 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
214 } else if (display->platform.alderlake_p) {
215 fw_path = ADLP_DMC_PATH;
216 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
217 } else if (display->platform.alderlake_s) {
218 fw_path = ADLS_DMC_PATH;
219 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
220 } else if (display->platform.dg1) {
221 fw_path = DG1_DMC_PATH;
222 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
223 } else if (display->platform.rocketlake) {
224 fw_path = RKL_DMC_PATH;
225 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
226 } else if (display->platform.tigerlake) {
227 fw_path = TGL_DMC_PATH;
228 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
229 } else if (DISPLAY_VER(display) == 11) {
230 fw_path = ICL_DMC_PATH;
231 max_fw_size = ICL_DMC_MAX_FW_SIZE;
232 } else if (display->platform.geminilake) {
233 fw_path = GLK_DMC_PATH;
234 max_fw_size = GLK_DMC_MAX_FW_SIZE;
235 } else if (display->platform.kabylake ||
236 display->platform.coffeelake ||
237 display->platform.cometlake) {
238 fw_path = KBL_DMC_PATH;
239 max_fw_size = KBL_DMC_MAX_FW_SIZE;
240 } else if (display->platform.skylake) {
241 fw_path = SKL_DMC_PATH;
242 max_fw_size = SKL_DMC_MAX_FW_SIZE;
243 } else if (display->platform.broxton) {
244 fw_path = BXT_DMC_PATH;
245 max_fw_size = BXT_DMC_MAX_FW_SIZE;
246 }
247
248 *size = max_fw_size;
249
250 return fw_path;
251 }
252
253 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF
254 #define PACKAGE_MAX_FW_INFO_ENTRIES 20
255 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32
256 #define DMC_V1_MAX_MMIO_COUNT 8
257 #define DMC_V3_MAX_MMIO_COUNT 20
258 #define DMC_V1_MMIO_START_RANGE 0x80000
259
260 #define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A))
261
262 struct intel_css_header {
263 /* 0x09 for DMC */
264 u32 module_type;
265
266 /* Includes the DMC specific header in dwords */
267 u32 header_len;
268
269 /* always value would be 0x10000 */
270 u32 header_ver;
271
272 /* Not used */
273 u32 module_id;
274
275 /* Not used */
276 u32 module_vendor;
277
278 /* in YYYYMMDD format */
279 u32 date;
280
281 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
282 u32 size;
283
284 /* Not used */
285 u32 key_size;
286
287 /* Not used */
288 u32 modulus_size;
289
290 /* Not used */
291 u32 exponent_size;
292
293 /* Not used */
294 u32 reserved1[12];
295
296 /* Major Minor */
297 u32 version;
298
299 /* Not used */
300 u32 reserved2[8];
301
302 /* Not used */
303 u32 kernel_header_info;
304 } __packed;
305
306 struct intel_fw_info {
307 u8 reserved1;
308
309 /* reserved on package_header version 1, must be 0 on version 2 */
310 u8 dmc_id;
311
312 /* Stepping (A, B, C, ..., *). * is a wildcard */
313 char stepping;
314
315 /* Sub-stepping (0, 1, ..., *). * is a wildcard */
316 char substepping;
317
318 u32 offset;
319 u32 reserved2;
320 } __packed;
321
322 struct intel_package_header {
323 /* DMC container header length in dwords */
324 u8 header_len;
325
326 /* 0x01, 0x02 */
327 u8 header_ver;
328
329 u8 reserved[10];
330
331 /* Number of valid entries in the FWInfo array below */
332 u32 num_entries;
333 } __packed;
334
335 struct intel_dmc_header_base {
336 /* always value would be 0x40403E3E */
337 u32 signature;
338
339 /* DMC binary header length */
340 u8 header_len;
341
342 /* 0x01 */
343 u8 header_ver;
344
345 /* Reserved */
346 u16 dmcc_ver;
347
348 /* Major, Minor */
349 u32 project;
350
351 /* Firmware program size (excluding header) in dwords */
352 u32 fw_size;
353
354 /* Major Minor version */
355 u32 fw_version;
356 } __packed;
357
358 struct intel_dmc_header_v1 {
359 struct intel_dmc_header_base base;
360
361 /* Number of valid MMIO cycles present. */
362 u32 mmio_count;
363
364 /* MMIO address */
365 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT];
366
367 /* MMIO data */
368 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT];
369
370 /* FW filename */
371 char dfile[32];
372
373 u32 reserved1[2];
374 } __packed;
375
376 struct intel_dmc_header_v3 {
377 struct intel_dmc_header_base base;
378
379 /* DMC RAM start MMIO address */
380 u32 start_mmioaddr;
381
382 u32 reserved[9];
383
384 /* FW filename */
385 char dfile[32];
386
387 /* Number of valid MMIO cycles present. */
388 u32 mmio_count;
389
390 /* MMIO address */
391 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT];
392
393 /* MMIO data */
394 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT];
395 } __packed;
396
397 struct stepping_info {
398 char stepping;
399 char substepping;
400 };
401
402 #define for_each_dmc_id(__dmc_id) \
403 for ((__dmc_id) = DMC_FW_MAIN; (__dmc_id) < DMC_FW_MAX; (__dmc_id)++)
404
is_valid_dmc_id(enum intel_dmc_id dmc_id)405 static bool is_valid_dmc_id(enum intel_dmc_id dmc_id)
406 {
407 return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX;
408 }
409
has_dmc_id_fw(struct intel_display * display,enum intel_dmc_id dmc_id)410 static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id)
411 {
412 struct intel_dmc *dmc = display_to_dmc(display);
413
414 return dmc && dmc->dmc_info[dmc_id].payload;
415 }
416
intel_dmc_has_payload(struct intel_display * display)417 bool intel_dmc_has_payload(struct intel_display *display)
418 {
419 return has_dmc_id_fw(display, DMC_FW_MAIN);
420 }
421
422 static const struct stepping_info *
intel_get_stepping_info(struct intel_display * display,struct stepping_info * si)423 intel_get_stepping_info(struct intel_display *display,
424 struct stepping_info *si)
425 {
426 const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(display));
427
428 si->stepping = step_name[0];
429 si->substepping = step_name[1];
430 return si;
431 }
432
gen9_set_dc_state_debugmask(struct intel_display * display)433 static void gen9_set_dc_state_debugmask(struct intel_display *display)
434 {
435 /* The below bit doesn't need to be cleared ever afterwards */
436 intel_de_rmw(display, DC_STATE_DEBUG, 0,
437 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP);
438 intel_de_posting_read(display, DC_STATE_DEBUG);
439 }
440
disable_event_handler(struct intel_display * display,i915_reg_t ctl_reg,i915_reg_t htp_reg)441 static void disable_event_handler(struct intel_display *display,
442 i915_reg_t ctl_reg, i915_reg_t htp_reg)
443 {
444 intel_de_write(display, ctl_reg,
445 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
446 DMC_EVT_CTL_TYPE_EDGE_0_1) |
447 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
448 DMC_EVENT_FALSE));
449 intel_de_write(display, htp_reg, 0);
450 }
451
disable_all_event_handlers(struct intel_display * display,enum intel_dmc_id dmc_id)452 static void disable_all_event_handlers(struct intel_display *display,
453 enum intel_dmc_id dmc_id)
454 {
455 int handler;
456
457 /* TODO: disable the event handlers on pre-GEN12 platforms as well */
458 if (DISPLAY_VER(display) < 12)
459 return;
460
461 if (!has_dmc_id_fw(display, dmc_id))
462 return;
463
464 for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++)
465 disable_event_handler(display,
466 DMC_EVT_CTL(display, dmc_id, handler),
467 DMC_EVT_HTP(display, dmc_id, handler));
468 }
469
adlp_pipedmc_clock_gating_wa(struct intel_display * display,bool enable)470 static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable)
471 {
472 enum pipe pipe;
473
474 /*
475 * Wa_16015201720:adl-p,dg2
476 * The WA requires clock gating to be disabled all the time
477 * for pipe A and B.
478 * For pipe C and D clock gating needs to be disabled only
479 * during initializing the firmware.
480 */
481 if (enable)
482 for (pipe = PIPE_A; pipe <= PIPE_D; pipe++)
483 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe),
484 0, PIPEDMC_GATING_DIS);
485 else
486 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++)
487 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe),
488 PIPEDMC_GATING_DIS, 0);
489 }
490
mtl_pipedmc_clock_gating_wa(struct intel_display * display)491 static void mtl_pipedmc_clock_gating_wa(struct intel_display *display)
492 {
493 /*
494 * Wa_16015201720
495 * The WA requires clock gating to be disabled all the time
496 * for pipe A and B.
497 */
498 intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0,
499 MTL_PIPEDMC_GATING_DIS(PIPE_A) |
500 MTL_PIPEDMC_GATING_DIS(PIPE_B));
501 }
502
pipedmc_clock_gating_wa(struct intel_display * display,bool enable)503 static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable)
504 {
505 if (display->platform.meteorlake && enable)
506 mtl_pipedmc_clock_gating_wa(display);
507 else if (DISPLAY_VER(display) == 13)
508 adlp_pipedmc_clock_gating_wa(display, enable);
509 }
510
pipedmc_interrupt_mask(struct intel_display * display)511 static u32 pipedmc_interrupt_mask(struct intel_display *display)
512 {
513 /*
514 * FIXME PIPEDMC_ERROR not enabled for now due to LNL pipe B
515 * triggering it during the first DC state transition. Figure
516 * out what is going on...
517 */
518 return PIPEDMC_FLIPQ_PROG_DONE |
519 PIPEDMC_GTT_FAULT |
520 PIPEDMC_ATS_FAULT;
521 }
522
dmc_evt_ctl_disable(u32 dmc_evt_ctl)523 static u32 dmc_evt_ctl_disable(u32 dmc_evt_ctl)
524 {
525 /*
526 * DMC_EVT_CTL_ENABLE cannot be cleared once set. Always
527 * configure it based on the original event definition to
528 * avoid mismatches in assert_dmc_loaded().
529 */
530 return (dmc_evt_ctl & DMC_EVT_CTL_ENABLE) |
531 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
532 DMC_EVT_CTL_TYPE_EDGE_0_1) |
533 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
534 DMC_EVENT_FALSE);
535 }
536
is_dmc_evt_ctl_reg(struct intel_display * display,enum intel_dmc_id dmc_id,i915_reg_t reg)537 static bool is_dmc_evt_ctl_reg(struct intel_display *display,
538 enum intel_dmc_id dmc_id, i915_reg_t reg)
539 {
540 u32 offset = i915_mmio_reg_offset(reg);
541 u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0));
542 u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));
543
544 return offset >= start && offset < end;
545 }
546
is_dmc_evt_htp_reg(struct intel_display * display,enum intel_dmc_id dmc_id,i915_reg_t reg)547 static bool is_dmc_evt_htp_reg(struct intel_display *display,
548 enum intel_dmc_id dmc_id, i915_reg_t reg)
549 {
550 u32 offset = i915_mmio_reg_offset(reg);
551 u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0));
552 u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));
553
554 return offset >= start && offset < end;
555 }
556
is_event_handler(struct intel_display * display,enum intel_dmc_id dmc_id,unsigned int event_id,i915_reg_t reg,u32 data)557 static bool is_event_handler(struct intel_display *display,
558 enum intel_dmc_id dmc_id,
559 unsigned int event_id,
560 i915_reg_t reg, u32 data)
561 {
562 return is_dmc_evt_ctl_reg(display, dmc_id, reg) &&
563 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == event_id;
564 }
565
fixup_dmc_evt(struct intel_display * display,enum intel_dmc_id dmc_id,i915_reg_t reg_ctl,u32 * data_ctl,i915_reg_t reg_htp,u32 * data_htp)566 static bool fixup_dmc_evt(struct intel_display *display,
567 enum intel_dmc_id dmc_id,
568 i915_reg_t reg_ctl, u32 *data_ctl,
569 i915_reg_t reg_htp, u32 *data_htp)
570 {
571 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg_ctl))
572 return false;
573
574 if (!is_dmc_evt_htp_reg(display, dmc_id, reg_htp))
575 return false;
576
577 /* make sure reg_ctl and reg_htp are for the same event */
578 if (i915_mmio_reg_offset(reg_ctl) - i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)) !=
579 i915_mmio_reg_offset(reg_htp) - i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)))
580 return false;
581
582 /*
583 * On ADL-S the HRR event handler is not restored after DC6.
584 * Clear it to zero from the beginning to avoid mismatches later.
585 */
586 if (display->platform.alderlake_s && dmc_id == DMC_FW_MAIN &&
587 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) {
588 *data_ctl = 0;
589 *data_htp = 0;
590 return true;
591 }
592
593 /*
594 * TGL/ADL-S DMC firmware incorrectly uses the undelayed vblank
595 * event for the HRR handler, when it should be using the delayed
596 * vblank event instead. Fixed firmware was never released
597 * so the Windows driver just hacks around it by overriding
598 * the event ID. Do the same.
599 */
600 if ((display->platform.tigerlake || display->platform.alderlake_s) &&
601 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) {
602 *data_ctl &= ~DMC_EVT_CTL_EVENT_ID_MASK;
603 *data_ctl |= REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
604 MAINDMC_EVENT_VBLANK_DELAYED_A);
605 return true;
606 }
607
608 return false;
609 }
610
disable_dmc_evt(struct intel_display * display,enum intel_dmc_id dmc_id,i915_reg_t reg,u32 data)611 static bool disable_dmc_evt(struct intel_display *display,
612 enum intel_dmc_id dmc_id,
613 i915_reg_t reg, u32 data)
614 {
615 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg))
616 return false;
617
618 /* keep all pipe DMC events disabled by default */
619 if (dmc_id != DMC_FW_MAIN)
620 return true;
621
622 /* also disable the flip queue event on the main DMC on TGL */
623 if (display->platform.tigerlake &&
624 is_event_handler(display, dmc_id, MAINDMC_EVENT_CLK_MSEC, reg, data))
625 return true;
626
627 /* also disable the HRR event on the main DMC on TGL/ADLS */
628 if ((display->platform.tigerlake || display->platform.alderlake_s) &&
629 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_DELAYED_A, reg, data))
630 return true;
631
632 return false;
633 }
634
dmc_mmiodata(struct intel_display * display,struct intel_dmc * dmc,enum intel_dmc_id dmc_id,int i)635 static u32 dmc_mmiodata(struct intel_display *display,
636 struct intel_dmc *dmc,
637 enum intel_dmc_id dmc_id, int i)
638 {
639 if (disable_dmc_evt(display, dmc_id,
640 dmc->dmc_info[dmc_id].mmioaddr[i],
641 dmc->dmc_info[dmc_id].mmiodata[i]))
642 return dmc_evt_ctl_disable(dmc->dmc_info[dmc_id].mmiodata[i]);
643 else
644 return dmc->dmc_info[dmc_id].mmiodata[i];
645 }
646
dmc_load_mmio(struct intel_display * display,enum intel_dmc_id dmc_id)647 static void dmc_load_mmio(struct intel_display *display, enum intel_dmc_id dmc_id)
648 {
649 struct intel_dmc *dmc = display_to_dmc(display);
650 int i;
651
652 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {
653 intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i],
654 dmc_mmiodata(display, dmc, dmc_id, i));
655 }
656 }
657
dmc_load_program(struct intel_display * display,enum intel_dmc_id dmc_id)658 static void dmc_load_program(struct intel_display *display, enum intel_dmc_id dmc_id)
659 {
660 struct intel_dmc *dmc = display_to_dmc(display);
661 int i;
662
663 disable_all_event_handlers(display, dmc_id);
664
665 preempt_disable();
666
667 for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) {
668 intel_de_write_fw(display,
669 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i),
670 dmc->dmc_info[dmc_id].payload[i]);
671 }
672
673 preempt_enable();
674
675 dmc_load_mmio(display, dmc_id);
676 }
677
assert_dmc_loaded(struct intel_display * display,enum intel_dmc_id dmc_id)678 static void assert_dmc_loaded(struct intel_display *display,
679 enum intel_dmc_id dmc_id)
680 {
681 struct intel_dmc *dmc = display_to_dmc(display);
682 u32 expected, found;
683 int i;
684
685 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))
686 return;
687
688 found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0));
689 expected = dmc->dmc_info[dmc_id].payload[0];
690
691 drm_WARN(display->drm, found != expected,
692 "DMC %d program storage start incorrect (expected 0x%x, current 0x%x)\n",
693 dmc_id, expected, found);
694
695 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {
696 i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i];
697
698 found = intel_de_read(display, reg);
699 expected = dmc_mmiodata(display, dmc, dmc_id, i);
700
701 drm_WARN(display->drm, found != expected,
702 "DMC %d mmio[%d]/0x%x incorrect (expected 0x%x, current 0x%x)\n",
703 dmc_id, i, i915_mmio_reg_offset(reg), expected, found);
704 }
705 }
706
assert_main_dmc_loaded(struct intel_display * display)707 void assert_main_dmc_loaded(struct intel_display *display)
708 {
709 assert_dmc_loaded(display, DMC_FW_MAIN);
710 }
711
need_pipedmc_load_program(struct intel_display * display)712 static bool need_pipedmc_load_program(struct intel_display *display)
713 {
714 /* On TGL/derivatives pipe DMC state is lost when PG1 is disabled */
715 return DISPLAY_VER(display) == 12;
716 }
717
need_pipedmc_load_mmio(struct intel_display * display,enum pipe pipe)718 static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe)
719 {
720 /*
721 * Xe3_LPD/Xe3p_LPD:
722 * - pipe A/B DMC doesn't need save/restore
723 * - pipe C/D DMC is in PG0, needs manual save/restore
724 */
725 if (IS_DISPLAY_VER(display, 30, 35))
726 return pipe >= PIPE_C;
727
728 /*
729 * FIXME LNL unclear, main DMC firmware has the pipe DMC A/B PG0
730 * save/restore, but so far unable to see the loss of pipe DMC state
731 * in action. Are we just failing to turn off PG0 due to some other
732 * SoC level stuff?
733 */
734 if (DISPLAY_VER(display) == 20)
735 return false;
736
737 /*
738 * FIXME BMG untested, main DMC firmware has the
739 * pipe DMC A/B PG0 save/restore...
740 */
741 if (display->platform.battlemage)
742 return false;
743
744 /*
745 * DG2:
746 * - Pipe DMCs presumably in PG0?
747 * - No DC6, and even DC9 doesn't seem to result
748 * in loss of DMC state for whatever reason
749 */
750 if (display->platform.dg2)
751 return false;
752
753 /*
754 * ADL/MTL:
755 * - pipe A/B DMC is in PG0, saved/restored by the main DMC
756 * - pipe C/D DMC is in PG0, needs manual save/restore
757 */
758 if (IS_DISPLAY_VER(display, 13, 14))
759 return pipe >= PIPE_C;
760
761 return false;
762 }
763
can_enable_pipedmc(const struct intel_crtc_state * crtc_state)764 static bool can_enable_pipedmc(const struct intel_crtc_state *crtc_state)
765 {
766 struct intel_display *display = to_intel_display(crtc_state);
767
768 /*
769 * On TGL/derivatives pipe DMC state is lost when PG1 is disabled.
770 * Do not even enable the pipe DMC when that can happen outside
771 * of driver control (PSR+DC5/6).
772 */
773 if (DISPLAY_VER(display) == 12 && crtc_state->has_psr)
774 return false;
775
776 return true;
777 }
778
intel_dmc_enable_pipe(const struct intel_crtc_state * crtc_state)779 void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state)
780 {
781 struct intel_display *display = to_intel_display(crtc_state);
782 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
783 enum pipe pipe = crtc->pipe;
784 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
785
786 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))
787 return;
788
789 if (!can_enable_pipedmc(crtc_state)) {
790 intel_dmc_disable_pipe(crtc_state);
791 return;
792 }
793
794 if (need_pipedmc_load_program(display))
795 dmc_load_program(display, dmc_id);
796 else if (need_pipedmc_load_mmio(display, pipe))
797 dmc_load_mmio(display, dmc_id);
798
799 assert_dmc_loaded(display, dmc_id);
800
801 if (DISPLAY_VER(display) >= 20) {
802 intel_flipq_reset(display, pipe);
803
804 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display));
805 intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display));
806 }
807
808 if (DISPLAY_VER(display) >= 14)
809 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe));
810 else
811 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE);
812 }
813
intel_dmc_disable_pipe(const struct intel_crtc_state * crtc_state)814 void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state)
815 {
816 struct intel_display *display = to_intel_display(crtc_state);
817 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
818 enum pipe pipe = crtc->pipe;
819 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
820
821 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))
822 return;
823
824 if (DISPLAY_VER(display) >= 14)
825 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0);
826 else
827 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);
828
829 if (DISPLAY_VER(display) >= 20) {
830 intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0);
831 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display));
832
833 intel_flipq_reset(display, pipe);
834 }
835 }
836
dmc_configure_event(struct intel_display * display,enum intel_dmc_id dmc_id,unsigned int event_id,bool enable)837 static void dmc_configure_event(struct intel_display *display,
838 enum intel_dmc_id dmc_id,
839 unsigned int event_id,
840 bool enable)
841 {
842 struct intel_dmc *dmc = display_to_dmc(display);
843 int num_handlers = 0;
844 int i;
845
846 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {
847 i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i];
848 u32 data = dmc->dmc_info[dmc_id].mmiodata[i];
849
850 if (!is_event_handler(display, dmc_id, event_id, reg, data))
851 continue;
852
853 intel_de_write(display, reg, enable ? data : dmc_evt_ctl_disable(data));
854 num_handlers++;
855 }
856
857 drm_WARN_ONCE(display->drm, num_handlers != 1,
858 "DMC %d has %d handlers for event 0x%x\n",
859 dmc_id, num_handlers, event_id);
860 }
861
intel_dmc_configure_dc_balance_event(struct intel_display * display,enum pipe pipe,bool enable)862 void intel_dmc_configure_dc_balance_event(struct intel_display *display,
863 enum pipe pipe, bool enable)
864 {
865 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
866
867 dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER, enable);
868 }
869
870 /**
871 * intel_dmc_block_pkgc() - block PKG C-state
872 * @display: display instance
873 * @pipe: pipe which register use to block
874 * @block: block/unblock
875 *
876 * This interface is target for Wa_16025596647 usage. I.e. to set/clear
877 * PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS bit in PIPEDMC_BLOCK_PKGC_SW register.
878 */
intel_dmc_block_pkgc(struct intel_display * display,enum pipe pipe,bool block)879 void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,
880 bool block)
881 {
882 intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(pipe),
883 PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS, block ?
884 PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS : 0);
885 }
886
887 /**
888 * intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank() - start of PKG
889 * C-state exit
890 * @display: display instance
891 * @pipe: pipe which register use to block
892 * @enable: enable/disable
893 *
894 * This interface is target for Wa_16025596647 usage. I.e. start the package C
895 * exit at the start of the undelayed vblank
896 */
intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display * display,enum pipe pipe,bool enable)897 void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display,
898 enum pipe pipe, bool enable)
899 {
900 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
901
902 dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_VBLANK, enable);
903 }
904
905 /**
906 * intel_dmc_load_program() - write the firmware from memory to register.
907 * @display: display instance
908 *
909 * DMC firmware is read from a .bin file and kept in internal memory one time.
910 * Everytime display comes back from low power state this function is called to
911 * copy the firmware from internal memory to registers.
912 */
intel_dmc_load_program(struct intel_display * display)913 void intel_dmc_load_program(struct intel_display *display)
914 {
915 struct i915_power_domains *power_domains = &display->power.domains;
916 enum intel_dmc_id dmc_id;
917
918 if (!intel_dmc_has_payload(display))
919 return;
920
921 assert_display_rpm_held(display);
922
923 pipedmc_clock_gating_wa(display, true);
924
925 for_each_dmc_id(dmc_id) {
926 dmc_load_program(display, dmc_id);
927 assert_dmc_loaded(display, dmc_id);
928 }
929
930 if (DISPLAY_VER(display) >= 20)
931 intel_de_write(display, DMC_FQ_W2_PTS_CFG_SEL,
932 PIPE_D_DMC_W2_PTS_CONFIG_SELECT(PIPE_D) |
933 PIPE_C_DMC_W2_PTS_CONFIG_SELECT(PIPE_C) |
934 PIPE_B_DMC_W2_PTS_CONFIG_SELECT(PIPE_B) |
935 PIPE_A_DMC_W2_PTS_CONFIG_SELECT(PIPE_A));
936
937 power_domains->dc_state = 0;
938
939 gen9_set_dc_state_debugmask(display);
940
941 pipedmc_clock_gating_wa(display, false);
942 }
943
944 /**
945 * intel_dmc_disable_program() - disable the firmware
946 * @display: display instance
947 *
948 * Disable all event handlers in the firmware, making sure the firmware is
949 * inactive after the display is uninitialized.
950 */
intel_dmc_disable_program(struct intel_display * display)951 void intel_dmc_disable_program(struct intel_display *display)
952 {
953 enum intel_dmc_id dmc_id;
954
955 if (!intel_dmc_has_payload(display))
956 return;
957
958 pipedmc_clock_gating_wa(display, true);
959
960 for_each_dmc_id(dmc_id)
961 disable_all_event_handlers(display, dmc_id);
962
963 pipedmc_clock_gating_wa(display, false);
964 }
965
fw_info_matches_stepping(const struct intel_fw_info * fw_info,const struct stepping_info * si)966 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info,
967 const struct stepping_info *si)
968 {
969 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) ||
970 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) ||
971 /*
972 * If we don't find a more specific one from above two checks, we
973 * then check for the generic one to be sure to work even with
974 * "broken firmware"
975 */
976 (si->stepping == '*' && si->substepping == fw_info->substepping) ||
977 (fw_info->stepping == '*' && fw_info->substepping == '*'))
978 return true;
979
980 return false;
981 }
982
983 /*
984 * Search fw_info table for dmc_offset to find firmware binary: num_entries is
985 * already sanitized.
986 */
dmc_set_fw_offset(struct intel_dmc * dmc,const struct intel_fw_info * fw_info,unsigned int num_entries,const struct stepping_info * si,u8 package_ver)987 static void dmc_set_fw_offset(struct intel_dmc *dmc,
988 const struct intel_fw_info *fw_info,
989 unsigned int num_entries,
990 const struct stepping_info *si,
991 u8 package_ver)
992 {
993 struct intel_display *display = dmc->display;
994 enum intel_dmc_id dmc_id;
995 unsigned int i;
996
997 for (i = 0; i < num_entries; i++) {
998 dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id;
999
1000 if (!is_valid_dmc_id(dmc_id)) {
1001 drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id);
1002 continue;
1003 }
1004
1005 /* More specific versions come first, so we don't even have to
1006 * check for the stepping since we already found a previous FW
1007 * for this id.
1008 */
1009 if (dmc->dmc_info[dmc_id].present)
1010 continue;
1011
1012 if (fw_info_matches_stepping(&fw_info[i], si)) {
1013 dmc->dmc_info[dmc_id].present = true;
1014 dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset;
1015 }
1016 }
1017 }
1018
dmc_mmio_addr_sanity_check(struct intel_dmc * dmc,const u32 * mmioaddr,u32 mmio_count,int header_ver,enum intel_dmc_id dmc_id)1019 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc,
1020 const u32 *mmioaddr, u32 mmio_count,
1021 int header_ver, enum intel_dmc_id dmc_id)
1022 {
1023 struct intel_display *display = dmc->display;
1024 u32 start_range, end_range;
1025 int i;
1026
1027 if (header_ver == 1) {
1028 start_range = DMC_MMIO_START_RANGE;
1029 end_range = DMC_MMIO_END_RANGE;
1030 } else if (dmc_id == DMC_FW_MAIN) {
1031 start_range = TGL_MAIN_MMIO_START;
1032 end_range = TGL_MAIN_MMIO_END;
1033 } else if (DISPLAY_VER(display) >= 13) {
1034 start_range = ADLP_PIPE_MMIO_START;
1035 end_range = ADLP_PIPE_MMIO_END;
1036 } else if (DISPLAY_VER(display) >= 12) {
1037 start_range = TGL_PIPE_MMIO_START(dmc_id);
1038 end_range = TGL_PIPE_MMIO_END(dmc_id);
1039 } else {
1040 drm_warn(display->drm, "Unknown mmio range for sanity check");
1041 return false;
1042 }
1043
1044 for (i = 0; i < mmio_count; i++) {
1045 if (mmioaddr[i] < start_range || mmioaddr[i] > end_range)
1046 return false;
1047 }
1048
1049 return true;
1050 }
1051
parse_dmc_fw_header(struct intel_dmc * dmc,const struct intel_dmc_header_base * dmc_header,size_t rem_size,enum intel_dmc_id dmc_id)1052 static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
1053 const struct intel_dmc_header_base *dmc_header,
1054 size_t rem_size, enum intel_dmc_id dmc_id)
1055 {
1056 struct intel_display *display = dmc->display;
1057 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id];
1058 unsigned int header_len_bytes, dmc_header_size, payload_size, i;
1059 const u32 *mmioaddr, *mmiodata;
1060 u32 mmio_count, mmio_count_max, start_mmioaddr;
1061 u8 *payload;
1062
1063 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
1064 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
1065
1066 /*
1067 * Check if we can access common fields, we will checkc again below
1068 * after we have read the version
1069 */
1070 if (rem_size < sizeof(struct intel_dmc_header_base))
1071 goto error_truncated;
1072
1073 /* Cope with small differences between v1 and v3 */
1074 if (dmc_header->header_ver == 3) {
1075 const struct intel_dmc_header_v3 *v3 =
1076 (const struct intel_dmc_header_v3 *)dmc_header;
1077
1078 if (rem_size < sizeof(struct intel_dmc_header_v3))
1079 goto error_truncated;
1080
1081 mmioaddr = v3->mmioaddr;
1082 mmiodata = v3->mmiodata;
1083 mmio_count = v3->mmio_count;
1084 mmio_count_max = DMC_V3_MAX_MMIO_COUNT;
1085 /* header_len is in dwords */
1086 header_len_bytes = dmc_header->header_len * 4;
1087 start_mmioaddr = v3->start_mmioaddr;
1088 dmc_header_size = sizeof(*v3);
1089 } else if (dmc_header->header_ver == 1) {
1090 const struct intel_dmc_header_v1 *v1 =
1091 (const struct intel_dmc_header_v1 *)dmc_header;
1092
1093 if (rem_size < sizeof(struct intel_dmc_header_v1))
1094 goto error_truncated;
1095
1096 mmioaddr = v1->mmioaddr;
1097 mmiodata = v1->mmiodata;
1098 mmio_count = v1->mmio_count;
1099 mmio_count_max = DMC_V1_MAX_MMIO_COUNT;
1100 header_len_bytes = dmc_header->header_len;
1101 start_mmioaddr = DMC_V1_MMIO_START_RANGE;
1102 dmc_header_size = sizeof(*v1);
1103 } else {
1104 drm_err(display->drm, "Unknown DMC fw header version: %u\n",
1105 dmc_header->header_ver);
1106 return 0;
1107 }
1108
1109 if (header_len_bytes != dmc_header_size) {
1110 drm_err(display->drm, "DMC firmware has wrong dmc header length "
1111 "(%u bytes)\n", header_len_bytes);
1112 return 0;
1113 }
1114
1115 /* Cache the dmc header info. */
1116 if (mmio_count > mmio_count_max) {
1117 drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count);
1118 return 0;
1119 }
1120
1121 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count,
1122 dmc_header->header_ver, dmc_id)) {
1123 drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n");
1124 return 0;
1125 }
1126
1127 drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id);
1128 for (i = 0; i < mmio_count; i++) {
1129 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
1130 dmc_info->mmiodata[i] = mmiodata[i];
1131 }
1132
1133 for (i = 0; i < mmio_count - 1; i++) {
1134 u32 orig_mmiodata[2] = {
1135 dmc_info->mmiodata[i],
1136 dmc_info->mmiodata[i+1],
1137 };
1138
1139 if (!fixup_dmc_evt(display, dmc_id,
1140 dmc_info->mmioaddr[i], &dmc_info->mmiodata[i],
1141 dmc_info->mmioaddr[i+1], &dmc_info->mmiodata[i+1]))
1142 continue;
1143
1144 drm_dbg_kms(display->drm,
1145 " mmio[%d]: 0x%x = 0x%x->0x%x (EVT_CTL)\n",
1146 i, i915_mmio_reg_offset(dmc_info->mmioaddr[i]),
1147 orig_mmiodata[0], dmc_info->mmiodata[i]);
1148 drm_dbg_kms(display->drm,
1149 " mmio[%d]: 0x%x = 0x%x->0x%x (EVT_HTP)\n",
1150 i+1, i915_mmio_reg_offset(dmc_info->mmioaddr[i+1]),
1151 orig_mmiodata[1], dmc_info->mmiodata[i+1]);
1152 }
1153
1154 for (i = 0; i < mmio_count; i++) {
1155 drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n",
1156 i, i915_mmio_reg_offset(dmc_info->mmioaddr[i]), dmc_info->mmiodata[i],
1157 is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" :
1158 is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "",
1159 disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i],
1160 dmc_info->mmiodata[i]) ? " (disabling)" : "");
1161 }
1162 dmc_info->mmio_count = mmio_count;
1163 dmc_info->start_mmioaddr = start_mmioaddr;
1164
1165 rem_size -= header_len_bytes;
1166
1167 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
1168 payload_size = dmc_header->fw_size * 4;
1169 if (rem_size < payload_size)
1170 goto error_truncated;
1171
1172 if (payload_size > dmc->max_fw_size) {
1173 drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size);
1174 return 0;
1175 }
1176 dmc_info->dmc_fw_size = dmc_header->fw_size;
1177
1178 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
1179 if (!dmc_info->payload)
1180 return 0;
1181
1182 payload = (u8 *)(dmc_header) + header_len_bytes;
1183 memcpy(dmc_info->payload, payload, payload_size);
1184
1185 return header_len_bytes + payload_size;
1186
1187 error_truncated:
1188 drm_err(display->drm, "Truncated DMC firmware, refusing.\n");
1189 return 0;
1190 }
1191
1192 static u32
parse_dmc_fw_package(struct intel_dmc * dmc,const struct intel_package_header * package_header,const struct stepping_info * si,size_t rem_size)1193 parse_dmc_fw_package(struct intel_dmc *dmc,
1194 const struct intel_package_header *package_header,
1195 const struct stepping_info *si,
1196 size_t rem_size)
1197 {
1198 struct intel_display *display = dmc->display;
1199 u32 package_size = sizeof(struct intel_package_header);
1200 u32 num_entries, max_entries;
1201 const struct intel_fw_info *fw_info;
1202
1203 if (rem_size < package_size)
1204 goto error_truncated;
1205
1206 if (package_header->header_ver == 1) {
1207 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES;
1208 } else if (package_header->header_ver == 2) {
1209 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
1210 } else {
1211 drm_err(display->drm, "DMC firmware has unknown header version %u\n",
1212 package_header->header_ver);
1213 return 0;
1214 }
1215
1216 /*
1217 * We should always have space for max_entries,
1218 * even if not all are used
1219 */
1220 package_size += max_entries * sizeof(struct intel_fw_info);
1221 if (rem_size < package_size)
1222 goto error_truncated;
1223
1224 if (package_header->header_len * 4 != package_size) {
1225 drm_err(display->drm, "DMC firmware has wrong package header length "
1226 "(%u bytes)\n", package_size);
1227 return 0;
1228 }
1229
1230 num_entries = package_header->num_entries;
1231 if (WARN_ON(num_entries > max_entries))
1232 num_entries = max_entries;
1233
1234 fw_info = (const struct intel_fw_info *)
1235 ((u8 *)package_header + sizeof(*package_header));
1236 dmc_set_fw_offset(dmc, fw_info, num_entries, si,
1237 package_header->header_ver);
1238
1239 /* dmc_offset is in dwords */
1240 return package_size;
1241
1242 error_truncated:
1243 drm_err(display->drm, "Truncated DMC firmware, refusing.\n");
1244 return 0;
1245 }
1246
1247 /* Return number of bytes parsed or 0 on error */
parse_dmc_fw_css(struct intel_dmc * dmc,struct intel_css_header * css_header,size_t rem_size)1248 static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
1249 struct intel_css_header *css_header,
1250 size_t rem_size)
1251 {
1252 struct intel_display *display = dmc->display;
1253
1254 if (rem_size < sizeof(struct intel_css_header)) {
1255 drm_err(display->drm, "Truncated DMC firmware, refusing.\n");
1256 return 0;
1257 }
1258
1259 if (sizeof(struct intel_css_header) !=
1260 (css_header->header_len * 4)) {
1261 drm_err(display->drm, "DMC firmware has wrong CSS header length "
1262 "(%u bytes)\n",
1263 (css_header->header_len * 4));
1264 return 0;
1265 }
1266
1267 dmc->version = css_header->version;
1268
1269 return sizeof(struct intel_css_header);
1270 }
1271
parse_dmc_fw(struct intel_dmc * dmc,const struct firmware * fw)1272 static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw)
1273 {
1274 struct intel_display *display = dmc->display;
1275 struct intel_css_header *css_header;
1276 struct intel_package_header *package_header;
1277 struct intel_dmc_header_base *dmc_header;
1278 struct stepping_info display_info = { '*', '*'};
1279 const struct stepping_info *si = intel_get_stepping_info(display, &display_info);
1280 enum intel_dmc_id dmc_id;
1281 u32 readcount = 0;
1282 u32 r, offset;
1283
1284 if (!fw)
1285 return -EINVAL;
1286
1287 /* Extract CSS Header information */
1288 css_header = (struct intel_css_header *)fw->data;
1289 r = parse_dmc_fw_css(dmc, css_header, fw->size);
1290 if (!r)
1291 return -EINVAL;
1292
1293 readcount += r;
1294
1295 /* Extract Package Header information */
1296 package_header = (struct intel_package_header *)&fw->data[readcount];
1297 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount);
1298 if (!r)
1299 return -EINVAL;
1300
1301 readcount += r;
1302
1303 for_each_dmc_id(dmc_id) {
1304 if (!dmc->dmc_info[dmc_id].present)
1305 continue;
1306
1307 offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4;
1308 if (offset > fw->size) {
1309 drm_err(display->drm, "Reading beyond the fw_size\n");
1310 continue;
1311 }
1312
1313 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset];
1314 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id);
1315 }
1316
1317 if (!intel_dmc_has_payload(display)) {
1318 drm_err(display->drm, "DMC firmware main program not found\n");
1319 return -ENOENT;
1320 }
1321
1322 return 0;
1323 }
1324
intel_dmc_runtime_pm_get(struct intel_display * display)1325 static void intel_dmc_runtime_pm_get(struct intel_display *display)
1326 {
1327 drm_WARN_ON(display->drm, display->dmc.wakeref);
1328 display->dmc.wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT);
1329 }
1330
intel_dmc_runtime_pm_put(struct intel_display * display)1331 static void intel_dmc_runtime_pm_put(struct intel_display *display)
1332 {
1333 struct ref_tracker *wakeref __maybe_unused =
1334 fetch_and_zero(&display->dmc.wakeref);
1335
1336 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);
1337 }
1338
dmc_fallback_path(struct intel_display * display)1339 static const char *dmc_fallback_path(struct intel_display *display)
1340 {
1341 if (display->platform.alderlake_p)
1342 return ADLP_DMC_FALLBACK_PATH;
1343
1344 return NULL;
1345 }
1346
dmc_load_work_fn(struct work_struct * work)1347 static void dmc_load_work_fn(struct work_struct *work)
1348 {
1349 struct intel_dmc *dmc = container_of(work, typeof(*dmc), work);
1350 struct intel_display *display = dmc->display;
1351 const struct firmware *fw = NULL;
1352 const char *fallback_path;
1353 int err;
1354
1355 err = request_firmware(&fw, dmc->fw_path, display->drm->dev);
1356
1357 if (err == -ENOENT && !dmc_firmware_param(display)) {
1358 fallback_path = dmc_fallback_path(display);
1359 if (fallback_path) {
1360 drm_dbg_kms(display->drm, "%s not found, falling back to %s\n",
1361 dmc->fw_path, fallback_path);
1362 err = request_firmware(&fw, fallback_path, display->drm->dev);
1363 if (err == 0)
1364 dmc->fw_path = fallback_path;
1365 }
1366 }
1367
1368 if (err) {
1369 drm_notice(display->drm,
1370 "Failed to load DMC firmware %s (%pe). Disabling runtime power management.\n",
1371 dmc->fw_path, ERR_PTR(err));
1372 drm_notice(display->drm, "DMC firmware homepage: %s",
1373 INTEL_DMC_FIRMWARE_URL);
1374 return;
1375 }
1376
1377 err = parse_dmc_fw(dmc, fw);
1378 if (err) {
1379 drm_notice(display->drm,
1380 "Failed to parse DMC firmware %s (%pe). Disabling runtime power management.\n",
1381 dmc->fw_path, ERR_PTR(err));
1382 goto out;
1383 }
1384
1385 intel_dmc_load_program(display);
1386 intel_dmc_runtime_pm_put(display);
1387
1388 drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n",
1389 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version),
1390 DMC_VERSION_MINOR(dmc->version));
1391
1392 out:
1393 release_firmware(fw);
1394 }
1395
1396 /**
1397 * intel_dmc_init() - initialize the firmware loading.
1398 * @display: display instance
1399 *
1400 * This function is called at the time of loading the display driver to read
1401 * firmware from a .bin file and copied into a internal memory.
1402 */
intel_dmc_init(struct intel_display * display)1403 void intel_dmc_init(struct intel_display *display)
1404 {
1405 struct intel_dmc *dmc;
1406
1407 if (!HAS_DMC(display))
1408 return;
1409
1410 /*
1411 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering
1412 * runtime-suspend.
1413 *
1414 * On error, we return with the rpm wakeref held to prevent runtime
1415 * suspend as runtime suspend *requires* a working DMC for whatever
1416 * reason.
1417 */
1418 intel_dmc_runtime_pm_get(display);
1419
1420 dmc = kzalloc_obj(*dmc);
1421 if (!dmc)
1422 return;
1423
1424 dmc->display = display;
1425
1426 INIT_WORK(&dmc->work, dmc_load_work_fn);
1427
1428 dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size);
1429
1430 if (dmc_firmware_param_disabled(display)) {
1431 drm_info(display->drm, "Disabling DMC firmware and runtime PM\n");
1432 goto out;
1433 }
1434
1435 if (dmc_firmware_param(display))
1436 dmc->fw_path = dmc_firmware_param(display);
1437
1438 if (!dmc->fw_path) {
1439 drm_dbg_kms(display->drm,
1440 "No known DMC firmware for platform, disabling runtime PM\n");
1441 goto out;
1442 }
1443
1444 display->dmc.dmc = dmc;
1445
1446 drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path);
1447 queue_work(display->wq.unordered, &dmc->work);
1448
1449 return;
1450
1451 out:
1452 kfree(dmc);
1453 }
1454
1455 /**
1456 * intel_dmc_suspend() - prepare DMC firmware before system suspend
1457 * @display: display instance
1458 *
1459 * Prepare the DMC firmware before entering system suspend. This includes
1460 * flushing pending work items and releasing any resources acquired during
1461 * init.
1462 */
intel_dmc_suspend(struct intel_display * display)1463 void intel_dmc_suspend(struct intel_display *display)
1464 {
1465 struct intel_dmc *dmc = display_to_dmc(display);
1466
1467 if (!HAS_DMC(display))
1468 return;
1469
1470 if (dmc)
1471 flush_work(&dmc->work);
1472
1473 /* Drop the reference held in case DMC isn't loaded. */
1474 if (!intel_dmc_has_payload(display))
1475 intel_dmc_runtime_pm_put(display);
1476 }
1477
intel_dmc_wait_fw_load(struct intel_display * display)1478 void intel_dmc_wait_fw_load(struct intel_display *display)
1479 {
1480 struct intel_dmc *dmc = display_to_dmc(display);
1481
1482 if (!HAS_DMC(display))
1483 return;
1484
1485 if (dmc)
1486 flush_work(&dmc->work);
1487 }
1488
1489 /**
1490 * intel_dmc_resume() - init DMC firmware during system resume
1491 * @display: display instance
1492 *
1493 * Reinitialize the DMC firmware during system resume, reacquiring any
1494 * resources released in intel_dmc_suspend().
1495 */
intel_dmc_resume(struct intel_display * display)1496 void intel_dmc_resume(struct intel_display *display)
1497 {
1498 if (!HAS_DMC(display))
1499 return;
1500
1501 /*
1502 * Reacquire the reference to keep RPM disabled in case DMC isn't
1503 * loaded.
1504 */
1505 if (!intel_dmc_has_payload(display))
1506 intel_dmc_runtime_pm_get(display);
1507 }
1508
1509 /**
1510 * intel_dmc_fini() - unload the DMC firmware.
1511 * @display: display instance
1512 *
1513 * Firmmware unloading includes freeing the internal memory and reset the
1514 * firmware loading status.
1515 */
intel_dmc_fini(struct intel_display * display)1516 void intel_dmc_fini(struct intel_display *display)
1517 {
1518 struct intel_dmc *dmc = display_to_dmc(display);
1519 enum intel_dmc_id dmc_id;
1520
1521 if (!HAS_DMC(display))
1522 return;
1523
1524 intel_dmc_suspend(display);
1525 drm_WARN_ON(display->drm, display->dmc.wakeref);
1526
1527 if (dmc) {
1528 for_each_dmc_id(dmc_id)
1529 kfree(dmc->dmc_info[dmc_id].payload);
1530
1531 kfree(dmc);
1532 display->dmc.dmc = NULL;
1533 }
1534 }
1535
1536 struct intel_dmc_snapshot {
1537 bool initialized;
1538 bool loaded;
1539 u32 version;
1540 };
1541
intel_dmc_snapshot_capture(struct intel_display * display)1542 struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display)
1543 {
1544 struct intel_dmc *dmc = display_to_dmc(display);
1545 struct intel_dmc_snapshot *snapshot;
1546
1547 if (!HAS_DMC(display))
1548 return NULL;
1549
1550 snapshot = kzalloc_obj(*snapshot, GFP_ATOMIC);
1551 if (!snapshot)
1552 return NULL;
1553
1554 snapshot->initialized = dmc;
1555 snapshot->loaded = intel_dmc_has_payload(display);
1556 if (dmc)
1557 snapshot->version = dmc->version;
1558
1559 return snapshot;
1560 }
1561
intel_dmc_snapshot_print(const struct intel_dmc_snapshot * snapshot,struct drm_printer * p)1562 void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p)
1563 {
1564 if (!snapshot)
1565 return;
1566
1567 drm_printf(p, "DMC initialized: %s\n", str_yes_no(snapshot->initialized));
1568 drm_printf(p, "DMC loaded: %s\n", str_yes_no(snapshot->loaded));
1569 if (snapshot->initialized)
1570 drm_printf(p, "DMC fw version: %d.%d\n",
1571 DMC_VERSION_MAJOR(snapshot->version),
1572 DMC_VERSION_MINOR(snapshot->version));
1573 }
1574
intel_dmc_update_dc6_allowed_count(struct intel_display * display,bool start_tracking)1575 void intel_dmc_update_dc6_allowed_count(struct intel_display *display,
1576 bool start_tracking)
1577 {
1578 struct intel_dmc *dmc = display_to_dmc(display);
1579 u32 dc5_cur_count;
1580
1581 if (DISPLAY_VER(dmc->display) < 14)
1582 return;
1583
1584 dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT);
1585
1586 if (!start_tracking)
1587 dmc->dc6_allowed.count += dc5_cur_count - dmc->dc6_allowed.dc5_start;
1588
1589 dmc->dc6_allowed.dc5_start = dc5_cur_count;
1590 }
1591
intel_dmc_get_dc6_allowed_count(struct intel_display * display,u32 * count)1592 static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count)
1593 {
1594 struct i915_power_domains *power_domains = &display->power.domains;
1595 struct intel_dmc *dmc = display_to_dmc(display);
1596 bool dc6_enabled;
1597
1598 if (DISPLAY_VER(display) < 14)
1599 return false;
1600
1601 mutex_lock(&power_domains->lock);
1602 dc6_enabled = intel_de_read(display, DC_STATE_EN) &
1603 DC_STATE_EN_UPTO_DC6;
1604 if (dc6_enabled)
1605 intel_dmc_update_dc6_allowed_count(display, false);
1606
1607 *count = dmc->dc6_allowed.count;
1608 mutex_unlock(&power_domains->lock);
1609
1610 return true;
1611 }
1612
intel_dmc_debugfs_status_show(struct seq_file * m,void * unused)1613 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
1614 {
1615 struct intel_display *display = m->private;
1616 struct intel_dmc *dmc = display_to_dmc(display);
1617 struct ref_tracker *wakeref;
1618 i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
1619 u32 dc6_allowed_count;
1620
1621 if (!HAS_DMC(display))
1622 return -ENODEV;
1623
1624 wakeref = intel_display_rpm_get(display);
1625
1626 seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc));
1627 seq_printf(m, "fw loaded: %s\n",
1628 str_yes_no(intel_dmc_has_payload(display)));
1629 seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A");
1630 seq_printf(m, "Pipe A fw needed: %s\n",
1631 str_yes_no(DISPLAY_VER(display) >= 12));
1632 seq_printf(m, "Pipe A fw loaded: %s\n",
1633 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA)));
1634 seq_printf(m, "Pipe B fw needed: %s\n",
1635 str_yes_no(display->platform.alderlake_p ||
1636 DISPLAY_VER(display) >= 14));
1637 seq_printf(m, "Pipe B fw loaded: %s\n",
1638 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB)));
1639
1640 if (!intel_dmc_has_payload(display))
1641 goto out;
1642
1643 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version),
1644 DMC_VERSION_MINOR(dmc->version));
1645
1646 if (DISPLAY_VER(display) >= 12) {
1647 i915_reg_t dc3co_reg;
1648
1649 if (display->platform.dgfx || DISPLAY_VER(display) >= 14) {
1650 dc3co_reg = DG1_DMC_DEBUG3;
1651 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
1652 } else {
1653 dc3co_reg = TGL_DMC_DEBUG3;
1654 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
1655 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
1656 }
1657
1658 seq_printf(m, "DC3CO count: %d\n",
1659 intel_de_read(display, dc3co_reg));
1660 } else {
1661 dc5_reg = display->platform.broxton ? BXT_DMC_DC3_DC5_COUNT :
1662 SKL_DMC_DC3_DC5_COUNT;
1663 if (!display->platform.geminilake && !display->platform.broxton)
1664 dc6_reg = SKL_DMC_DC5_DC6_COUNT;
1665 }
1666
1667 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
1668
1669 if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count))
1670 seq_printf(m, "DC5 -> DC6 allowed count: %d\n",
1671 dc6_allowed_count);
1672 else if (i915_mmio_reg_valid(dc6_reg))
1673 seq_printf(m, "DC5 -> DC6 count: %d\n",
1674 intel_de_read(display, dc6_reg));
1675
1676 seq_printf(m, "program base: 0x%08x\n",
1677 intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
1678
1679 out:
1680 seq_printf(m, "ssp base: 0x%08x\n",
1681 intel_de_read(display, DMC_SSP_BASE));
1682 seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL));
1683
1684 intel_display_rpm_put(display, wakeref);
1685
1686 return 0;
1687 }
1688
1689 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status);
1690
intel_dmc_debugfs_register(struct intel_display * display)1691 void intel_dmc_debugfs_register(struct intel_display *display)
1692 {
1693 debugfs_create_file("i915_dmc_info", 0444, display->drm->debugfs_root,
1694 display, &intel_dmc_debugfs_status_fops);
1695 }
1696
intel_pipedmc_irq_handler(struct intel_display * display,enum pipe pipe)1697 void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe)
1698 {
1699 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
1700 u32 tmp = 0, int_vector;
1701
1702 if (DISPLAY_VER(display) >= 20) {
1703 tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe));
1704 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), tmp);
1705
1706 if (tmp & PIPEDMC_FLIPQ_PROG_DONE) {
1707 spin_lock(&display->drm->event_lock);
1708
1709 if (crtc->flipq_event) {
1710 /*
1711 * Update vblank counter/timestamp in case it
1712 * hasn't been done yet for this frame.
1713 */
1714 drm_crtc_accurate_vblank_count(&crtc->base);
1715
1716 drm_crtc_send_vblank_event(&crtc->base, crtc->flipq_event);
1717 crtc->flipq_event = NULL;
1718 }
1719
1720 spin_unlock(&display->drm->event_lock);
1721 }
1722
1723 if (tmp & PIPEDMC_ATS_FAULT)
1724 drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC ATS fault\n",
1725 crtc->base.base.id, crtc->base.name);
1726 if (tmp & PIPEDMC_GTT_FAULT)
1727 drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC GTT fault\n",
1728 crtc->base.base.id, crtc->base.name);
1729 if (tmp & PIPEDMC_ERROR)
1730 drm_err(display->drm, "[CRTC:%d:%s] PIPEDMC error\n",
1731 crtc->base.base.id, crtc->base.name);
1732 }
1733
1734 int_vector = intel_de_read(display, PIPEDMC_STATUS(pipe)) & PIPEDMC_INT_VECTOR_MASK;
1735 if (tmp == 0 && int_vector != 0)
1736 drm_err(display->drm, "[CRTC:%d:%s] PIPEDMC interrupt vector 0x%x\n",
1737 crtc->base.base.id, crtc->base.name, int_vector);
1738 }
1739
intel_pipedmc_enable_event(struct intel_crtc * crtc,enum pipedmc_event_id event)1740 void intel_pipedmc_enable_event(struct intel_crtc *crtc,
1741 enum pipedmc_event_id event)
1742 {
1743 struct intel_display *display = to_intel_display(crtc);
1744 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe);
1745
1746 dmc_configure_event(display, dmc_id, event, true);
1747 }
1748
intel_pipedmc_disable_event(struct intel_crtc * crtc,enum pipedmc_event_id event)1749 void intel_pipedmc_disable_event(struct intel_crtc *crtc,
1750 enum pipedmc_event_id event)
1751 {
1752 struct intel_display *display = to_intel_display(crtc);
1753 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe);
1754
1755 dmc_configure_event(display, dmc_id, event, false);
1756 }
1757
intel_pipedmc_start_mmioaddr(struct intel_crtc * crtc)1758 u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc)
1759 {
1760 struct intel_display *display = to_intel_display(crtc);
1761 struct intel_dmc *dmc = display_to_dmc(display);
1762 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe);
1763
1764 return dmc ? dmc->dmc_info[dmc_id].start_mmioaddr : 0;
1765 }
1766
intel_pipedmc_dcb_enable(struct intel_dsb * dsb,struct intel_crtc * crtc)1767 void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc)
1768 {
1769 struct intel_display *display = to_intel_display(crtc);
1770 enum pipe pipe = crtc->pipe;
1771
1772 intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe),
1773 PIPEDMC_ADAPTIVE_DCB_ENABLE);
1774 }
1775
intel_pipedmc_dcb_disable(struct intel_dsb * dsb,struct intel_crtc * crtc)1776 void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc)
1777 {
1778 struct intel_display *display = to_intel_display(crtc);
1779 enum pipe pipe = crtc->pipe;
1780
1781 intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 0);
1782 }
1783