1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) Ericsson AB 2007-2008 4 * Copyright (C) ST-Ericsson SA 2008-2010 5 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson 6 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson 7 */ 8 9 #include <linux/dma-mapping.h> 10 #include <linux/kernel.h> 11 #include <linux/slab.h> 12 #include <linux/export.h> 13 #include <linux/dmaengine.h> 14 #include <linux/platform_device.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/log2.h> 18 #include <linux/pm.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/err.h> 21 #include <linux/of.h> 22 #include <linux/of_address.h> 23 #include <linux/of_dma.h> 24 #include <linux/amba/bus.h> 25 #include <linux/regulator/consumer.h> 26 27 #include "dmaengine.h" 28 #include "ste_dma40.h" 29 #include "ste_dma40_ll.h" 30 31 /** 32 * struct stedma40_platform_data - Configuration struct for the dma device. 33 * 34 * @disabled_channels: A vector, ending with -1, that marks physical channels 35 * that are for different reasons not available for the driver. 36 * @soft_lli_chans: A vector, that marks physical channels will use LLI by SW 37 * which avoids HW bug that exists in some versions of the controller. 38 * SoftLLI introduces relink overhead that could impact performance for 39 * certain use cases. 40 * @num_of_soft_lli_chans: The number of channels that needs to be configured 41 * to use SoftLLI. 42 * @use_esram_lcla: flag for mapping the lcla into esram region 43 * @num_of_memcpy_chans: The number of channels reserved for memcpy. 44 * @num_of_phy_chans: The number of physical channels implemented in HW. 45 * 0 means reading the number of channels from DMA HW but this is only valid 46 * for 'multiple of 4' channels, like 8. 47 */ 48 struct stedma40_platform_data { 49 int disabled_channels[STEDMA40_MAX_PHYS]; 50 int *soft_lli_chans; 51 int num_of_soft_lli_chans; 52 bool use_esram_lcla; 53 int num_of_memcpy_chans; 54 int num_of_phy_chans; 55 }; 56 57 #define D40_NAME "dma40" 58 59 #define D40_PHY_CHAN -1 60 61 /* For masking out/in 2 bit channel positions */ 62 #define D40_CHAN_POS(chan) (2 * (chan / 2)) 63 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan)) 64 65 /* Maximum iterations taken before giving up suspending a channel */ 66 #define D40_SUSPEND_MAX_IT 500 67 68 /* Milliseconds */ 69 #define DMA40_AUTOSUSPEND_DELAY 100 70 71 /* Hardware requirement on LCLA alignment */ 72 #define LCLA_ALIGNMENT 0x40000 73 74 /* Max number of links per event group */ 75 #define D40_LCLA_LINK_PER_EVENT_GRP 128 76 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP 77 78 /* Max number of logical channels per physical channel */ 79 #define D40_MAX_LOG_CHAN_PER_PHY 32 80 81 /* Attempts before giving up to trying to get pages that are aligned */ 82 #define MAX_LCLA_ALLOC_ATTEMPTS 256 83 84 /* Bit markings for allocation map */ 85 #define D40_ALLOC_FREE BIT(31) 86 #define D40_ALLOC_PHY BIT(30) 87 #define D40_ALLOC_LOG_FREE 0 88 89 #define D40_MEMCPY_MAX_CHANS 8 90 91 /* Reserved event lines for memcpy only. */ 92 #define DB8500_DMA_MEMCPY_EV_0 51 93 #define DB8500_DMA_MEMCPY_EV_1 56 94 #define DB8500_DMA_MEMCPY_EV_2 57 95 #define DB8500_DMA_MEMCPY_EV_3 58 96 #define DB8500_DMA_MEMCPY_EV_4 59 97 #define DB8500_DMA_MEMCPY_EV_5 60 98 99 static int dma40_memcpy_channels[] = { 100 DB8500_DMA_MEMCPY_EV_0, 101 DB8500_DMA_MEMCPY_EV_1, 102 DB8500_DMA_MEMCPY_EV_2, 103 DB8500_DMA_MEMCPY_EV_3, 104 DB8500_DMA_MEMCPY_EV_4, 105 DB8500_DMA_MEMCPY_EV_5, 106 }; 107 108 /* Default configuration for physical memcpy */ 109 static const struct stedma40_chan_cfg dma40_memcpy_conf_phy = { 110 .mode = STEDMA40_MODE_PHYSICAL, 111 .dir = DMA_MEM_TO_MEM, 112 113 .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 114 .src_info.psize = STEDMA40_PSIZE_PHY_1, 115 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, 116 117 .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 118 .dst_info.psize = STEDMA40_PSIZE_PHY_1, 119 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, 120 }; 121 122 /* Default configuration for logical memcpy */ 123 static const struct stedma40_chan_cfg dma40_memcpy_conf_log = { 124 .mode = STEDMA40_MODE_LOGICAL, 125 .dir = DMA_MEM_TO_MEM, 126 127 .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 128 .src_info.psize = STEDMA40_PSIZE_LOG_1, 129 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, 130 131 .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 132 .dst_info.psize = STEDMA40_PSIZE_LOG_1, 133 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, 134 }; 135 136 /** 137 * enum d40_command - The different commands and/or statuses. 138 * 139 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED, 140 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN. 141 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible. 142 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED. 143 */ 144 enum d40_command { 145 D40_DMA_STOP = 0, 146 D40_DMA_RUN = 1, 147 D40_DMA_SUSPEND_REQ = 2, 148 D40_DMA_SUSPENDED = 3 149 }; 150 151 /* 152 * enum d40_events - The different Event Enables for the event lines. 153 * 154 * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan. 155 * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan. 156 * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line. 157 * @D40_ROUND_EVENTLINE: Status check for event line. 158 */ 159 160 enum d40_events { 161 D40_DEACTIVATE_EVENTLINE = 0, 162 D40_ACTIVATE_EVENTLINE = 1, 163 D40_SUSPEND_REQ_EVENTLINE = 2, 164 D40_ROUND_EVENTLINE = 3 165 }; 166 167 /* 168 * These are the registers that has to be saved and later restored 169 * when the DMA hw is powered off. 170 * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works. 171 */ 172 static __maybe_unused u32 d40_backup_regs[] = { 173 D40_DREG_LCPA, 174 D40_DREG_LCLA, 175 D40_DREG_PRMSE, 176 D40_DREG_PRMSO, 177 D40_DREG_PRMOE, 178 D40_DREG_PRMOO, 179 }; 180 181 #define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs) 182 183 /* 184 * since 9540 and 8540 has the same HW revision 185 * use v4a for 9540 or earlier 186 * use v4b for 8540 or later 187 * HW revision: 188 * DB8500ed has revision 0 189 * DB8500v1 has revision 2 190 * DB8500v2 has revision 3 191 * AP9540v1 has revision 4 192 * DB8540v1 has revision 4 193 * TODO: Check if all these registers have to be saved/restored on dma40 v4a 194 */ 195 static u32 d40_backup_regs_v4a[] = { 196 D40_DREG_PSEG1, 197 D40_DREG_PSEG2, 198 D40_DREG_PSEG3, 199 D40_DREG_PSEG4, 200 D40_DREG_PCEG1, 201 D40_DREG_PCEG2, 202 D40_DREG_PCEG3, 203 D40_DREG_PCEG4, 204 D40_DREG_RSEG1, 205 D40_DREG_RSEG2, 206 D40_DREG_RSEG3, 207 D40_DREG_RSEG4, 208 D40_DREG_RCEG1, 209 D40_DREG_RCEG2, 210 D40_DREG_RCEG3, 211 D40_DREG_RCEG4, 212 }; 213 214 #define BACKUP_REGS_SZ_V4A ARRAY_SIZE(d40_backup_regs_v4a) 215 216 static u32 d40_backup_regs_v4b[] = { 217 D40_DREG_CPSEG1, 218 D40_DREG_CPSEG2, 219 D40_DREG_CPSEG3, 220 D40_DREG_CPSEG4, 221 D40_DREG_CPSEG5, 222 D40_DREG_CPCEG1, 223 D40_DREG_CPCEG2, 224 D40_DREG_CPCEG3, 225 D40_DREG_CPCEG4, 226 D40_DREG_CPCEG5, 227 D40_DREG_CRSEG1, 228 D40_DREG_CRSEG2, 229 D40_DREG_CRSEG3, 230 D40_DREG_CRSEG4, 231 D40_DREG_CRSEG5, 232 D40_DREG_CRCEG1, 233 D40_DREG_CRCEG2, 234 D40_DREG_CRCEG3, 235 D40_DREG_CRCEG4, 236 D40_DREG_CRCEG5, 237 }; 238 239 #define BACKUP_REGS_SZ_V4B ARRAY_SIZE(d40_backup_regs_v4b) 240 241 static __maybe_unused u32 d40_backup_regs_chan[] = { 242 D40_CHAN_REG_SSCFG, 243 D40_CHAN_REG_SSELT, 244 D40_CHAN_REG_SSPTR, 245 D40_CHAN_REG_SSLNK, 246 D40_CHAN_REG_SDCFG, 247 D40_CHAN_REG_SDELT, 248 D40_CHAN_REG_SDPTR, 249 D40_CHAN_REG_SDLNK, 250 }; 251 252 #define BACKUP_REGS_SZ_MAX ((BACKUP_REGS_SZ_V4A > BACKUP_REGS_SZ_V4B) ? \ 253 BACKUP_REGS_SZ_V4A : BACKUP_REGS_SZ_V4B) 254 255 /** 256 * struct d40_interrupt_lookup - lookup table for interrupt handler 257 * 258 * @src: Interrupt mask register. 259 * @clr: Interrupt clear register. 260 * @is_error: true if this is an error interrupt. 261 * @offset: start delta in the lookup_log_chans in d40_base. If equals to 262 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead. 263 */ 264 struct d40_interrupt_lookup { 265 u32 src; 266 u32 clr; 267 bool is_error; 268 int offset; 269 }; 270 271 272 static struct d40_interrupt_lookup il_v4a[] = { 273 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0}, 274 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32}, 275 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64}, 276 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96}, 277 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0}, 278 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32}, 279 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64}, 280 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96}, 281 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN}, 282 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN}, 283 }; 284 285 static struct d40_interrupt_lookup il_v4b[] = { 286 {D40_DREG_CLCTIS1, D40_DREG_CLCICR1, false, 0}, 287 {D40_DREG_CLCTIS2, D40_DREG_CLCICR2, false, 32}, 288 {D40_DREG_CLCTIS3, D40_DREG_CLCICR3, false, 64}, 289 {D40_DREG_CLCTIS4, D40_DREG_CLCICR4, false, 96}, 290 {D40_DREG_CLCTIS5, D40_DREG_CLCICR5, false, 128}, 291 {D40_DREG_CLCEIS1, D40_DREG_CLCICR1, true, 0}, 292 {D40_DREG_CLCEIS2, D40_DREG_CLCICR2, true, 32}, 293 {D40_DREG_CLCEIS3, D40_DREG_CLCICR3, true, 64}, 294 {D40_DREG_CLCEIS4, D40_DREG_CLCICR4, true, 96}, 295 {D40_DREG_CLCEIS5, D40_DREG_CLCICR5, true, 128}, 296 {D40_DREG_CPCTIS, D40_DREG_CPCICR, false, D40_PHY_CHAN}, 297 {D40_DREG_CPCEIS, D40_DREG_CPCICR, true, D40_PHY_CHAN}, 298 }; 299 300 /** 301 * struct d40_reg_val - simple lookup struct 302 * 303 * @reg: The register. 304 * @val: The value that belongs to the register in reg. 305 */ 306 struct d40_reg_val { 307 unsigned int reg; 308 unsigned int val; 309 }; 310 311 static __initdata struct d40_reg_val dma_init_reg_v4a[] = { 312 /* Clock every part of the DMA block from start */ 313 { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL}, 314 315 /* Interrupts on all logical channels */ 316 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF}, 317 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF}, 318 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF}, 319 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF}, 320 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF}, 321 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF}, 322 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF}, 323 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF}, 324 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF}, 325 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF}, 326 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF}, 327 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF} 328 }; 329 static __initdata struct d40_reg_val dma_init_reg_v4b[] = { 330 /* Clock every part of the DMA block from start */ 331 { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL}, 332 333 /* Interrupts on all logical channels */ 334 { .reg = D40_DREG_CLCMIS1, .val = 0xFFFFFFFF}, 335 { .reg = D40_DREG_CLCMIS2, .val = 0xFFFFFFFF}, 336 { .reg = D40_DREG_CLCMIS3, .val = 0xFFFFFFFF}, 337 { .reg = D40_DREG_CLCMIS4, .val = 0xFFFFFFFF}, 338 { .reg = D40_DREG_CLCMIS5, .val = 0xFFFFFFFF}, 339 { .reg = D40_DREG_CLCICR1, .val = 0xFFFFFFFF}, 340 { .reg = D40_DREG_CLCICR2, .val = 0xFFFFFFFF}, 341 { .reg = D40_DREG_CLCICR3, .val = 0xFFFFFFFF}, 342 { .reg = D40_DREG_CLCICR4, .val = 0xFFFFFFFF}, 343 { .reg = D40_DREG_CLCICR5, .val = 0xFFFFFFFF}, 344 { .reg = D40_DREG_CLCTIS1, .val = 0xFFFFFFFF}, 345 { .reg = D40_DREG_CLCTIS2, .val = 0xFFFFFFFF}, 346 { .reg = D40_DREG_CLCTIS3, .val = 0xFFFFFFFF}, 347 { .reg = D40_DREG_CLCTIS4, .val = 0xFFFFFFFF}, 348 { .reg = D40_DREG_CLCTIS5, .val = 0xFFFFFFFF} 349 }; 350 351 /** 352 * struct d40_lli_pool - Structure for keeping LLIs in memory 353 * 354 * @base: Pointer to memory area when the pre_alloc_lli's are not large 355 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if 356 * pre_alloc_lli is used. 357 * @dma_addr: DMA address, if mapped 358 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli. 359 * @pre_alloc_lli: Pre allocated area for the most common case of transfers, 360 * one buffer to one buffer. 361 */ 362 struct d40_lli_pool { 363 void *base; 364 int size; 365 dma_addr_t dma_addr; 366 /* Space for dst and src, plus an extra for padding */ 367 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)]; 368 }; 369 370 /** 371 * struct d40_desc - A descriptor is one DMA job. 372 * 373 * @lli_phy: LLI settings for physical channel. Both src and dst= 374 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if 375 * lli_len equals one. 376 * @lli_log: Same as above but for logical channels. 377 * @lli_pool: The pool with two entries pre-allocated. 378 * @lli_len: Number of llis of current descriptor. 379 * @lli_current: Number of transferred llis. 380 * @lcla_alloc: Number of LCLA entries allocated. 381 * @txd: DMA engine struct. Used for among other things for communication 382 * during a transfer. 383 * @node: List entry. 384 * @is_in_client_list: true if the client owns this descriptor. 385 * @cyclic: true if this is a cyclic job 386 * 387 * This descriptor is used for both logical and physical transfers. 388 */ 389 struct d40_desc { 390 /* LLI physical */ 391 struct d40_phy_lli_bidir lli_phy; 392 /* LLI logical */ 393 struct d40_log_lli_bidir lli_log; 394 395 struct d40_lli_pool lli_pool; 396 int lli_len; 397 int lli_current; 398 int lcla_alloc; 399 400 struct dma_async_tx_descriptor txd; 401 struct list_head node; 402 403 bool is_in_client_list; 404 bool cyclic; 405 }; 406 407 /** 408 * struct d40_lcla_pool - LCLA pool settings and data. 409 * 410 * @base: The virtual address of LCLA. 18 bit aligned. 411 * @dma_addr: DMA address, if mapped 412 * @base_unaligned: The original kmalloc pointer, if kmalloc is used. 413 * This pointer is only there for clean-up on error. 414 * @pages: The number of pages needed for all physical channels. 415 * Only used later for clean-up on error 416 * @lock: Lock to protect the content in this struct. 417 * @alloc_map: big map over which LCLA entry is own by which job. 418 */ 419 struct d40_lcla_pool { 420 void *base; 421 dma_addr_t dma_addr; 422 void *base_unaligned; 423 int pages; 424 spinlock_t lock; 425 struct d40_desc **alloc_map; 426 }; 427 428 /** 429 * struct d40_phy_res - struct for handling eventlines mapped to physical 430 * channels. 431 * 432 * @lock: A lock protection this entity. 433 * @reserved: True if used by secure world or otherwise. 434 * @num: The physical channel number of this entity. 435 * @allocated_src: Bit mapped to show which src event line's are mapped to 436 * this physical channel. Can also be free or physically allocated. 437 * @allocated_dst: Same as for src but is dst. 438 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as 439 * event line number. 440 * @use_soft_lli: To mark if the linked lists of channel are managed by SW. 441 */ 442 struct d40_phy_res { 443 spinlock_t lock; 444 bool reserved; 445 int num; 446 u32 allocated_src; 447 u32 allocated_dst; 448 bool use_soft_lli; 449 }; 450 451 struct d40_base; 452 453 /** 454 * struct d40_chan - Struct that describes a channel. 455 * 456 * @lock: A spinlock to protect this struct. 457 * @log_num: The logical number, if any of this channel. 458 * @pending_tx: The number of pending transfers. Used between interrupt handler 459 * and tasklet. 460 * @busy: Set to true when transfer is ongoing on this channel. 461 * @phy_chan: Pointer to physical channel which this instance runs on. If this 462 * point is NULL, then the channel is not allocated. 463 * @chan: DMA engine handle. 464 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a 465 * transfer and call client callback. 466 * @client: Cliented owned descriptor list. 467 * @pending_queue: Submitted jobs, to be issued by issue_pending() 468 * @active: Active descriptor. 469 * @done: Completed jobs 470 * @queue: Queued jobs. 471 * @prepare_queue: Prepared jobs. 472 * @dma_cfg: The client configuration of this dma channel. 473 * @slave_config: DMA slave configuration. 474 * @configured: whether the dma_cfg configuration is valid 475 * @base: Pointer to the device instance struct. 476 * @src_def_cfg: Default cfg register setting for src. 477 * @dst_def_cfg: Default cfg register setting for dst. 478 * @log_def: Default logical channel settings. 479 * @lcpa: Pointer to dst and src lcpa settings. 480 * @runtime_addr: runtime configured address. 481 * @runtime_direction: runtime configured direction. 482 * 483 * This struct can either "be" a logical or a physical channel. 484 */ 485 struct d40_chan { 486 spinlock_t lock; 487 int log_num; 488 int pending_tx; 489 bool busy; 490 struct d40_phy_res *phy_chan; 491 struct dma_chan chan; 492 struct tasklet_struct tasklet; 493 struct list_head client; 494 struct list_head pending_queue; 495 struct list_head active; 496 struct list_head done; 497 struct list_head queue; 498 struct list_head prepare_queue; 499 struct stedma40_chan_cfg dma_cfg; 500 struct dma_slave_config slave_config; 501 bool configured; 502 struct d40_base *base; 503 /* Default register configurations */ 504 u32 src_def_cfg; 505 u32 dst_def_cfg; 506 struct d40_def_lcsp log_def; 507 struct d40_log_lli_full *lcpa; 508 /* Runtime reconfiguration */ 509 dma_addr_t runtime_addr; 510 enum dma_transfer_direction runtime_direction; 511 }; 512 513 /** 514 * struct d40_gen_dmac - generic values to represent u8500/u8540 DMA 515 * controller 516 * 517 * @backup: the pointer to the registers address array for backup 518 * @backup_size: the size of the registers address array for backup 519 * @realtime_en: the realtime enable register 520 * @realtime_clear: the realtime clear register 521 * @high_prio_en: the high priority enable register 522 * @high_prio_clear: the high priority clear register 523 * @interrupt_en: the interrupt enable register 524 * @interrupt_clear: the interrupt clear register 525 * @il: the pointer to struct d40_interrupt_lookup 526 * @il_size: the size of d40_interrupt_lookup array 527 * @init_reg: the pointer to the struct d40_reg_val 528 * @init_reg_size: the size of d40_reg_val array 529 */ 530 struct d40_gen_dmac { 531 u32 *backup; 532 u32 backup_size; 533 u32 realtime_en; 534 u32 realtime_clear; 535 u32 high_prio_en; 536 u32 high_prio_clear; 537 u32 interrupt_en; 538 u32 interrupt_clear; 539 struct d40_interrupt_lookup *il; 540 u32 il_size; 541 struct d40_reg_val *init_reg; 542 u32 init_reg_size; 543 }; 544 545 /** 546 * struct d40_base - The big global struct, one for each probe'd instance. 547 * 548 * @interrupt_lock: Lock used to make sure one interrupt is handle a time. 549 * @execmd_lock: Lock for execute command usage since several channels share 550 * the same physical register. 551 * @dev: The device structure. 552 * @virtbase: The virtual base address of the DMA's register. 553 * @rev: silicon revision detected. 554 * @clk: Pointer to the DMA clock structure. 555 * @irq: The IRQ number. 556 * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem 557 * transfers). 558 * @num_phy_chans: The number of physical channels. Read from HW. This 559 * is the number of available channels for this driver, not counting "Secure 560 * mode" allocated physical channels. 561 * @num_log_chans: The number of logical channels. Calculated from 562 * num_phy_chans. 563 * @dma_both: dma_device channels that can do both memcpy and slave transfers. 564 * @dma_slave: dma_device channels that can do only do slave transfers. 565 * @dma_memcpy: dma_device channels that can do only do memcpy transfers. 566 * @phy_chans: Room for all possible physical channels in system. 567 * @log_chans: Room for all possible logical channels in system. 568 * @lookup_log_chans: Used to map interrupt number to logical channel. Points 569 * to log_chans entries. 570 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points 571 * to phy_chans entries. 572 * @plat_data: Pointer to provided platform_data which is the driver 573 * configuration. 574 * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla. 575 * @phy_res: Vector containing all physical channels. 576 * @lcla_pool: lcla pool settings and data. 577 * @lcpa_base: The virtual mapped address of LCPA. 578 * @phy_lcpa: The physical address of the LCPA. 579 * @lcpa_size: The size of the LCPA area. 580 * @desc_slab: cache for descriptors. 581 * @reg_val_backup: Here the values of some hardware registers are stored 582 * before the DMA is powered off. They are restored when the power is back on. 583 * @reg_val_backup_v4: Backup of registers that only exits on dma40 v3 and 584 * later 585 * @reg_val_backup_chan: Backup data for standard channel parameter registers. 586 * @regs_interrupt: Scratch space for registers during interrupt. 587 * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off. 588 * @gen_dmac: the struct for generic registers values to represent u8500/8540 589 * DMA controller 590 */ 591 struct d40_base { 592 spinlock_t interrupt_lock; 593 spinlock_t execmd_lock; 594 struct device *dev; 595 void __iomem *virtbase; 596 u8 rev:4; 597 struct clk *clk; 598 int irq; 599 int num_memcpy_chans; 600 int num_phy_chans; 601 int num_log_chans; 602 struct dma_device dma_both; 603 struct dma_device dma_slave; 604 struct dma_device dma_memcpy; 605 struct d40_chan *phy_chans; 606 struct d40_chan *log_chans; 607 struct d40_chan **lookup_log_chans; 608 struct d40_chan **lookup_phy_chans; 609 struct stedma40_platform_data *plat_data; 610 struct regulator *lcpa_regulator; 611 /* Physical half channels */ 612 struct d40_phy_res *phy_res; 613 struct d40_lcla_pool lcla_pool; 614 void *lcpa_base; 615 dma_addr_t phy_lcpa; 616 resource_size_t lcpa_size; 617 struct kmem_cache *desc_slab; 618 u32 reg_val_backup[BACKUP_REGS_SZ]; 619 u32 reg_val_backup_v4[BACKUP_REGS_SZ_MAX]; 620 u32 *reg_val_backup_chan; 621 u32 *regs_interrupt; 622 u16 gcc_pwr_off_mask; 623 struct d40_gen_dmac gen_dmac; 624 }; 625 626 static struct device *chan2dev(struct d40_chan *d40c) 627 { 628 return &d40c->chan.dev->device; 629 } 630 631 static bool chan_is_physical(struct d40_chan *chan) 632 { 633 return chan->log_num == D40_PHY_CHAN; 634 } 635 636 static bool chan_is_logical(struct d40_chan *chan) 637 { 638 return !chan_is_physical(chan); 639 } 640 641 static void __iomem *chan_base(struct d40_chan *chan) 642 { 643 return chan->base->virtbase + D40_DREG_PCBASE + 644 chan->phy_chan->num * D40_DREG_PCDELTA; 645 } 646 647 #define d40_err(dev, format, arg...) \ 648 dev_err(dev, "[%s] " format, __func__, ## arg) 649 650 #define chan_err(d40c, format, arg...) \ 651 d40_err(chan2dev(d40c), format, ## arg) 652 653 static int d40_set_runtime_config_write(struct dma_chan *chan, 654 struct dma_slave_config *config, 655 enum dma_transfer_direction direction); 656 657 static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d, 658 int lli_len) 659 { 660 bool is_log = chan_is_logical(d40c); 661 u32 align; 662 void *base; 663 664 if (is_log) 665 align = sizeof(struct d40_log_lli); 666 else 667 align = sizeof(struct d40_phy_lli); 668 669 if (lli_len == 1) { 670 base = d40d->lli_pool.pre_alloc_lli; 671 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli); 672 d40d->lli_pool.base = NULL; 673 } else { 674 d40d->lli_pool.size = lli_len * 2 * align; 675 676 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT); 677 d40d->lli_pool.base = base; 678 679 if (d40d->lli_pool.base == NULL) 680 return -ENOMEM; 681 } 682 683 if (is_log) { 684 d40d->lli_log.src = PTR_ALIGN(base, align); 685 d40d->lli_log.dst = d40d->lli_log.src + lli_len; 686 687 d40d->lli_pool.dma_addr = 0; 688 } else { 689 d40d->lli_phy.src = PTR_ALIGN(base, align); 690 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len; 691 692 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev, 693 d40d->lli_phy.src, 694 d40d->lli_pool.size, 695 DMA_TO_DEVICE); 696 697 if (dma_mapping_error(d40c->base->dev, 698 d40d->lli_pool.dma_addr)) { 699 kfree(d40d->lli_pool.base); 700 d40d->lli_pool.base = NULL; 701 d40d->lli_pool.dma_addr = 0; 702 return -ENOMEM; 703 } 704 } 705 706 return 0; 707 } 708 709 static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d) 710 { 711 if (d40d->lli_pool.dma_addr) 712 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr, 713 d40d->lli_pool.size, DMA_TO_DEVICE); 714 715 kfree(d40d->lli_pool.base); 716 d40d->lli_pool.base = NULL; 717 d40d->lli_pool.size = 0; 718 d40d->lli_log.src = NULL; 719 d40d->lli_log.dst = NULL; 720 d40d->lli_phy.src = NULL; 721 d40d->lli_phy.dst = NULL; 722 } 723 724 static int d40_lcla_alloc_one(struct d40_chan *d40c, 725 struct d40_desc *d40d) 726 { 727 unsigned long flags; 728 int i; 729 int ret = -EINVAL; 730 731 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); 732 733 /* 734 * Allocate both src and dst at the same time, therefore the half 735 * start on 1 since 0 can't be used since zero is used as end marker. 736 */ 737 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) { 738 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i; 739 740 if (!d40c->base->lcla_pool.alloc_map[idx]) { 741 d40c->base->lcla_pool.alloc_map[idx] = d40d; 742 d40d->lcla_alloc++; 743 ret = i; 744 break; 745 } 746 } 747 748 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); 749 750 return ret; 751 } 752 753 static int d40_lcla_free_all(struct d40_chan *d40c, 754 struct d40_desc *d40d) 755 { 756 unsigned long flags; 757 int i; 758 int ret = -EINVAL; 759 760 if (chan_is_physical(d40c)) 761 return 0; 762 763 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); 764 765 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) { 766 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i; 767 768 if (d40c->base->lcla_pool.alloc_map[idx] == d40d) { 769 d40c->base->lcla_pool.alloc_map[idx] = NULL; 770 d40d->lcla_alloc--; 771 if (d40d->lcla_alloc == 0) { 772 ret = 0; 773 break; 774 } 775 } 776 } 777 778 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); 779 780 return ret; 781 782 } 783 784 static void d40_desc_remove(struct d40_desc *d40d) 785 { 786 list_del(&d40d->node); 787 } 788 789 static struct d40_desc *d40_desc_get(struct d40_chan *d40c) 790 { 791 struct d40_desc *desc = NULL; 792 793 if (!list_empty(&d40c->client)) { 794 struct d40_desc *d; 795 struct d40_desc *_d; 796 797 list_for_each_entry_safe(d, _d, &d40c->client, node) { 798 if (async_tx_test_ack(&d->txd)) { 799 d40_desc_remove(d); 800 desc = d; 801 memset(desc, 0, sizeof(*desc)); 802 break; 803 } 804 } 805 } 806 807 if (!desc) 808 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT); 809 810 if (desc) 811 INIT_LIST_HEAD(&desc->node); 812 813 return desc; 814 } 815 816 static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d) 817 { 818 819 d40_pool_lli_free(d40c, d40d); 820 d40_lcla_free_all(d40c, d40d); 821 kmem_cache_free(d40c->base->desc_slab, d40d); 822 } 823 824 static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc) 825 { 826 list_add_tail(&desc->node, &d40c->active); 827 } 828 829 static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc) 830 { 831 struct d40_phy_lli *lli_dst = desc->lli_phy.dst; 832 struct d40_phy_lli *lli_src = desc->lli_phy.src; 833 void __iomem *base = chan_base(chan); 834 835 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG); 836 writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT); 837 writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR); 838 writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK); 839 840 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG); 841 writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT); 842 writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR); 843 writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK); 844 } 845 846 static void d40_desc_done(struct d40_chan *d40c, struct d40_desc *desc) 847 { 848 list_add_tail(&desc->node, &d40c->done); 849 } 850 851 static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc) 852 { 853 struct d40_lcla_pool *pool = &chan->base->lcla_pool; 854 struct d40_log_lli_bidir *lli = &desc->lli_log; 855 int lli_current = desc->lli_current; 856 int lli_len = desc->lli_len; 857 bool cyclic = desc->cyclic; 858 int curr_lcla = -EINVAL; 859 int first_lcla = 0; 860 bool use_esram_lcla = chan->base->plat_data->use_esram_lcla; 861 bool linkback; 862 863 /* 864 * We may have partially running cyclic transfers, in case we did't get 865 * enough LCLA entries. 866 */ 867 linkback = cyclic && lli_current == 0; 868 869 /* 870 * For linkback, we need one LCLA even with only one link, because we 871 * can't link back to the one in LCPA space 872 */ 873 if (linkback || (lli_len - lli_current > 1)) { 874 /* 875 * If the channel is expected to use only soft_lli don't 876 * allocate a lcla. This is to avoid a HW issue that exists 877 * in some controller during a peripheral to memory transfer 878 * that uses linked lists. 879 */ 880 if (!(chan->phy_chan->use_soft_lli && 881 chan->dma_cfg.dir == DMA_DEV_TO_MEM)) 882 curr_lcla = d40_lcla_alloc_one(chan, desc); 883 884 first_lcla = curr_lcla; 885 } 886 887 /* 888 * For linkback, we normally load the LCPA in the loop since we need to 889 * link it to the second LCLA and not the first. However, if we 890 * couldn't even get a first LCLA, then we have to run in LCPA and 891 * reload manually. 892 */ 893 if (!linkback || curr_lcla == -EINVAL) { 894 unsigned int flags = 0; 895 896 if (curr_lcla == -EINVAL) 897 flags |= LLI_TERM_INT; 898 899 d40_log_lli_lcpa_write(chan->lcpa, 900 &lli->dst[lli_current], 901 &lli->src[lli_current], 902 curr_lcla, 903 flags); 904 lli_current++; 905 } 906 907 if (curr_lcla < 0) 908 goto set_current; 909 910 for (; lli_current < lli_len; lli_current++) { 911 unsigned int lcla_offset = chan->phy_chan->num * 1024 + 912 8 * curr_lcla * 2; 913 struct d40_log_lli *lcla = pool->base + lcla_offset; 914 unsigned int flags = 0; 915 int next_lcla; 916 917 if (lli_current + 1 < lli_len) 918 next_lcla = d40_lcla_alloc_one(chan, desc); 919 else 920 next_lcla = linkback ? first_lcla : -EINVAL; 921 922 if (cyclic || next_lcla == -EINVAL) 923 flags |= LLI_TERM_INT; 924 925 if (linkback && curr_lcla == first_lcla) { 926 /* First link goes in both LCPA and LCLA */ 927 d40_log_lli_lcpa_write(chan->lcpa, 928 &lli->dst[lli_current], 929 &lli->src[lli_current], 930 next_lcla, flags); 931 } 932 933 /* 934 * One unused LCLA in the cyclic case if the very first 935 * next_lcla fails... 936 */ 937 d40_log_lli_lcla_write(lcla, 938 &lli->dst[lli_current], 939 &lli->src[lli_current], 940 next_lcla, flags); 941 942 /* 943 * Cache maintenance is not needed if lcla is 944 * mapped in esram 945 */ 946 if (!use_esram_lcla) { 947 dma_sync_single_range_for_device(chan->base->dev, 948 pool->dma_addr, lcla_offset, 949 2 * sizeof(struct d40_log_lli), 950 DMA_TO_DEVICE); 951 } 952 curr_lcla = next_lcla; 953 954 if (curr_lcla == -EINVAL || curr_lcla == first_lcla) { 955 lli_current++; 956 break; 957 } 958 } 959 set_current: 960 desc->lli_current = lli_current; 961 } 962 963 static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d) 964 { 965 if (chan_is_physical(d40c)) { 966 d40_phy_lli_load(d40c, d40d); 967 d40d->lli_current = d40d->lli_len; 968 } else 969 d40_log_lli_to_lcxa(d40c, d40d); 970 } 971 972 static struct d40_desc *d40_first_active_get(struct d40_chan *d40c) 973 { 974 return list_first_entry_or_null(&d40c->active, struct d40_desc, node); 975 } 976 977 /* remove desc from current queue and add it to the pending_queue */ 978 static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc) 979 { 980 d40_desc_remove(desc); 981 desc->is_in_client_list = false; 982 list_add_tail(&desc->node, &d40c->pending_queue); 983 } 984 985 static struct d40_desc *d40_first_pending(struct d40_chan *d40c) 986 { 987 return list_first_entry_or_null(&d40c->pending_queue, struct d40_desc, 988 node); 989 } 990 991 static struct d40_desc *d40_first_queued(struct d40_chan *d40c) 992 { 993 return list_first_entry_or_null(&d40c->queue, struct d40_desc, node); 994 } 995 996 static struct d40_desc *d40_first_done(struct d40_chan *d40c) 997 { 998 return list_first_entry_or_null(&d40c->done, struct d40_desc, node); 999 } 1000 1001 static int d40_psize_2_burst_size(bool is_log, int psize) 1002 { 1003 if (is_log) { 1004 if (psize == STEDMA40_PSIZE_LOG_1) 1005 return 1; 1006 } else { 1007 if (psize == STEDMA40_PSIZE_PHY_1) 1008 return 1; 1009 } 1010 1011 return 2 << psize; 1012 } 1013 1014 /* 1015 * The dma only supports transmitting packages up to 1016 * STEDMA40_MAX_SEG_SIZE * data_width, where data_width is stored in Bytes. 1017 * 1018 * Calculate the total number of dma elements required to send the entire sg list. 1019 */ 1020 static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2) 1021 { 1022 int dmalen; 1023 u32 max_w = max(data_width1, data_width2); 1024 u32 min_w = min(data_width1, data_width2); 1025 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w); 1026 1027 if (seg_max > STEDMA40_MAX_SEG_SIZE) 1028 seg_max -= max_w; 1029 1030 if (!IS_ALIGNED(size, max_w)) 1031 return -EINVAL; 1032 1033 if (size <= seg_max) 1034 dmalen = 1; 1035 else { 1036 dmalen = size / seg_max; 1037 if (dmalen * seg_max < size) 1038 dmalen++; 1039 } 1040 return dmalen; 1041 } 1042 1043 static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len, 1044 u32 data_width1, u32 data_width2) 1045 { 1046 struct scatterlist *sg; 1047 int i; 1048 int len = 0; 1049 int ret; 1050 1051 for_each_sg(sgl, sg, sg_len, i) { 1052 ret = d40_size_2_dmalen(sg_dma_len(sg), 1053 data_width1, data_width2); 1054 if (ret < 0) 1055 return ret; 1056 len += ret; 1057 } 1058 return len; 1059 } 1060 1061 static int __d40_execute_command_phy(struct d40_chan *d40c, 1062 enum d40_command command) 1063 { 1064 u32 status; 1065 int i; 1066 void __iomem *active_reg; 1067 int ret = 0; 1068 unsigned long flags; 1069 u32 wmask; 1070 1071 if (command == D40_DMA_STOP) { 1072 ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ); 1073 if (ret) 1074 return ret; 1075 } 1076 1077 spin_lock_irqsave(&d40c->base->execmd_lock, flags); 1078 1079 if (d40c->phy_chan->num % 2 == 0) 1080 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; 1081 else 1082 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; 1083 1084 if (command == D40_DMA_SUSPEND_REQ) { 1085 status = (readl(active_reg) & 1086 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> 1087 D40_CHAN_POS(d40c->phy_chan->num); 1088 1089 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP) 1090 goto unlock; 1091 } 1092 1093 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num)); 1094 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)), 1095 active_reg); 1096 1097 if (command == D40_DMA_SUSPEND_REQ) { 1098 1099 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) { 1100 status = (readl(active_reg) & 1101 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> 1102 D40_CHAN_POS(d40c->phy_chan->num); 1103 1104 cpu_relax(); 1105 /* 1106 * Reduce the number of bus accesses while 1107 * waiting for the DMA to suspend. 1108 */ 1109 udelay(3); 1110 1111 if (status == D40_DMA_STOP || 1112 status == D40_DMA_SUSPENDED) 1113 break; 1114 } 1115 1116 if (i == D40_SUSPEND_MAX_IT) { 1117 chan_err(d40c, 1118 "unable to suspend the chl %d (log: %d) status %x\n", 1119 d40c->phy_chan->num, d40c->log_num, 1120 status); 1121 dump_stack(); 1122 ret = -EBUSY; 1123 } 1124 1125 } 1126 unlock: 1127 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags); 1128 return ret; 1129 } 1130 1131 static void d40_term_all(struct d40_chan *d40c) 1132 { 1133 struct d40_desc *d40d; 1134 struct d40_desc *_d; 1135 1136 /* Release completed descriptors */ 1137 while ((d40d = d40_first_done(d40c))) { 1138 d40_desc_remove(d40d); 1139 d40_desc_free(d40c, d40d); 1140 } 1141 1142 /* Release active descriptors */ 1143 while ((d40d = d40_first_active_get(d40c))) { 1144 d40_desc_remove(d40d); 1145 d40_desc_free(d40c, d40d); 1146 } 1147 1148 /* Release queued descriptors waiting for transfer */ 1149 while ((d40d = d40_first_queued(d40c))) { 1150 d40_desc_remove(d40d); 1151 d40_desc_free(d40c, d40d); 1152 } 1153 1154 /* Release pending descriptors */ 1155 while ((d40d = d40_first_pending(d40c))) { 1156 d40_desc_remove(d40d); 1157 d40_desc_free(d40c, d40d); 1158 } 1159 1160 /* Release client owned descriptors */ 1161 if (!list_empty(&d40c->client)) 1162 list_for_each_entry_safe(d40d, _d, &d40c->client, node) { 1163 d40_desc_remove(d40d); 1164 d40_desc_free(d40c, d40d); 1165 } 1166 1167 /* Release descriptors in prepare queue */ 1168 if (!list_empty(&d40c->prepare_queue)) 1169 list_for_each_entry_safe(d40d, _d, 1170 &d40c->prepare_queue, node) { 1171 d40_desc_remove(d40d); 1172 d40_desc_free(d40c, d40d); 1173 } 1174 1175 d40c->pending_tx = 0; 1176 } 1177 1178 static void __d40_config_set_event(struct d40_chan *d40c, 1179 enum d40_events event_type, u32 event, 1180 int reg) 1181 { 1182 void __iomem *addr = chan_base(d40c) + reg; 1183 int tries; 1184 u32 status; 1185 1186 switch (event_type) { 1187 1188 case D40_DEACTIVATE_EVENTLINE: 1189 1190 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event)) 1191 | ~D40_EVENTLINE_MASK(event), addr); 1192 break; 1193 1194 case D40_SUSPEND_REQ_EVENTLINE: 1195 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >> 1196 D40_EVENTLINE_POS(event); 1197 1198 if (status == D40_DEACTIVATE_EVENTLINE || 1199 status == D40_SUSPEND_REQ_EVENTLINE) 1200 break; 1201 1202 writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event)) 1203 | ~D40_EVENTLINE_MASK(event), addr); 1204 1205 for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) { 1206 1207 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >> 1208 D40_EVENTLINE_POS(event); 1209 1210 cpu_relax(); 1211 /* 1212 * Reduce the number of bus accesses while 1213 * waiting for the DMA to suspend. 1214 */ 1215 udelay(3); 1216 1217 if (status == D40_DEACTIVATE_EVENTLINE) 1218 break; 1219 } 1220 1221 if (tries == D40_SUSPEND_MAX_IT) { 1222 chan_err(d40c, 1223 "unable to stop the event_line chl %d (log: %d)" 1224 "status %x\n", d40c->phy_chan->num, 1225 d40c->log_num, status); 1226 } 1227 break; 1228 1229 case D40_ACTIVATE_EVENTLINE: 1230 /* 1231 * The hardware sometimes doesn't register the enable when src and dst 1232 * event lines are active on the same logical channel. Retry to ensure 1233 * it does. Usually only one retry is sufficient. 1234 */ 1235 tries = 100; 1236 while (--tries) { 1237 writel((D40_ACTIVATE_EVENTLINE << 1238 D40_EVENTLINE_POS(event)) | 1239 ~D40_EVENTLINE_MASK(event), addr); 1240 1241 if (readl(addr) & D40_EVENTLINE_MASK(event)) 1242 break; 1243 } 1244 1245 if (tries != 99) 1246 dev_dbg(chan2dev(d40c), 1247 "[%s] workaround enable S%cLNK (%d tries)\n", 1248 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D', 1249 100 - tries); 1250 1251 WARN_ON(!tries); 1252 break; 1253 1254 case D40_ROUND_EVENTLINE: 1255 BUG(); 1256 break; 1257 1258 } 1259 } 1260 1261 static void d40_config_set_event(struct d40_chan *d40c, 1262 enum d40_events event_type) 1263 { 1264 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type); 1265 1266 /* Enable event line connected to device (or memcpy) */ 1267 if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) || 1268 (d40c->dma_cfg.dir == DMA_DEV_TO_DEV)) 1269 __d40_config_set_event(d40c, event_type, event, 1270 D40_CHAN_REG_SSLNK); 1271 1272 if (d40c->dma_cfg.dir != DMA_DEV_TO_MEM) 1273 __d40_config_set_event(d40c, event_type, event, 1274 D40_CHAN_REG_SDLNK); 1275 } 1276 1277 static u32 d40_chan_has_events(struct d40_chan *d40c) 1278 { 1279 void __iomem *chanbase = chan_base(d40c); 1280 u32 val; 1281 1282 val = readl(chanbase + D40_CHAN_REG_SSLNK); 1283 val |= readl(chanbase + D40_CHAN_REG_SDLNK); 1284 1285 return val; 1286 } 1287 1288 static int 1289 __d40_execute_command_log(struct d40_chan *d40c, enum d40_command command) 1290 { 1291 unsigned long flags; 1292 int ret = 0; 1293 u32 active_status; 1294 void __iomem *active_reg; 1295 1296 if (d40c->phy_chan->num % 2 == 0) 1297 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; 1298 else 1299 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; 1300 1301 1302 spin_lock_irqsave(&d40c->phy_chan->lock, flags); 1303 1304 switch (command) { 1305 case D40_DMA_STOP: 1306 case D40_DMA_SUSPEND_REQ: 1307 1308 active_status = (readl(active_reg) & 1309 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> 1310 D40_CHAN_POS(d40c->phy_chan->num); 1311 1312 if (active_status == D40_DMA_RUN) 1313 d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE); 1314 else 1315 d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE); 1316 1317 if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP)) 1318 ret = __d40_execute_command_phy(d40c, command); 1319 1320 break; 1321 1322 case D40_DMA_RUN: 1323 1324 d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE); 1325 ret = __d40_execute_command_phy(d40c, command); 1326 break; 1327 1328 case D40_DMA_SUSPENDED: 1329 BUG(); 1330 break; 1331 } 1332 1333 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags); 1334 return ret; 1335 } 1336 1337 static int d40_channel_execute_command(struct d40_chan *d40c, 1338 enum d40_command command) 1339 { 1340 if (chan_is_logical(d40c)) 1341 return __d40_execute_command_log(d40c, command); 1342 else 1343 return __d40_execute_command_phy(d40c, command); 1344 } 1345 1346 static u32 d40_get_prmo(struct d40_chan *d40c) 1347 { 1348 static const unsigned int phy_map[] = { 1349 [STEDMA40_PCHAN_BASIC_MODE] 1350 = D40_DREG_PRMO_PCHAN_BASIC, 1351 [STEDMA40_PCHAN_MODULO_MODE] 1352 = D40_DREG_PRMO_PCHAN_MODULO, 1353 [STEDMA40_PCHAN_DOUBLE_DST_MODE] 1354 = D40_DREG_PRMO_PCHAN_DOUBLE_DST, 1355 }; 1356 static const unsigned int log_map[] = { 1357 [STEDMA40_LCHAN_SRC_PHY_DST_LOG] 1358 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG, 1359 [STEDMA40_LCHAN_SRC_LOG_DST_PHY] 1360 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY, 1361 [STEDMA40_LCHAN_SRC_LOG_DST_LOG] 1362 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG, 1363 }; 1364 1365 if (chan_is_physical(d40c)) 1366 return phy_map[d40c->dma_cfg.mode_opt]; 1367 else 1368 return log_map[d40c->dma_cfg.mode_opt]; 1369 } 1370 1371 static void d40_config_write(struct d40_chan *d40c) 1372 { 1373 u32 addr_base; 1374 u32 var; 1375 1376 /* Odd addresses are even addresses + 4 */ 1377 addr_base = (d40c->phy_chan->num % 2) * 4; 1378 /* Setup channel mode to logical or physical */ 1379 var = ((u32)(chan_is_logical(d40c)) + 1) << 1380 D40_CHAN_POS(d40c->phy_chan->num); 1381 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base); 1382 1383 /* Setup operational mode option register */ 1384 var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num); 1385 1386 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base); 1387 1388 if (chan_is_logical(d40c)) { 1389 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) 1390 & D40_SREG_ELEM_LOG_LIDX_MASK; 1391 void __iomem *chanbase = chan_base(d40c); 1392 1393 /* Set default config for CFG reg */ 1394 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG); 1395 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG); 1396 1397 /* Set LIDX for lcla */ 1398 writel(lidx, chanbase + D40_CHAN_REG_SSELT); 1399 writel(lidx, chanbase + D40_CHAN_REG_SDELT); 1400 1401 /* Clear LNK which will be used by d40_chan_has_events() */ 1402 writel(0, chanbase + D40_CHAN_REG_SSLNK); 1403 writel(0, chanbase + D40_CHAN_REG_SDLNK); 1404 } 1405 } 1406 1407 static u32 d40_residue(struct d40_chan *d40c) 1408 { 1409 u32 num_elt; 1410 1411 if (chan_is_logical(d40c)) 1412 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK) 1413 >> D40_MEM_LCSP2_ECNT_POS; 1414 else { 1415 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT); 1416 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK) 1417 >> D40_SREG_ELEM_PHY_ECNT_POS; 1418 } 1419 1420 return num_elt * d40c->dma_cfg.dst_info.data_width; 1421 } 1422 1423 static bool d40_tx_is_linked(struct d40_chan *d40c) 1424 { 1425 bool is_link; 1426 1427 if (chan_is_logical(d40c)) 1428 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK; 1429 else 1430 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK) 1431 & D40_SREG_LNK_PHYS_LNK_MASK; 1432 1433 return is_link; 1434 } 1435 1436 static int d40_pause(struct dma_chan *chan) 1437 { 1438 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); 1439 int res = 0; 1440 unsigned long flags; 1441 1442 if (d40c->phy_chan == NULL) { 1443 chan_err(d40c, "Channel is not allocated!\n"); 1444 return -EINVAL; 1445 } 1446 1447 if (!d40c->busy) 1448 return 0; 1449 1450 spin_lock_irqsave(&d40c->lock, flags); 1451 pm_runtime_get_sync(d40c->base->dev); 1452 1453 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ); 1454 1455 pm_runtime_put_autosuspend(d40c->base->dev); 1456 spin_unlock_irqrestore(&d40c->lock, flags); 1457 return res; 1458 } 1459 1460 static int d40_resume(struct dma_chan *chan) 1461 { 1462 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); 1463 int res = 0; 1464 unsigned long flags; 1465 1466 if (d40c->phy_chan == NULL) { 1467 chan_err(d40c, "Channel is not allocated!\n"); 1468 return -EINVAL; 1469 } 1470 1471 if (!d40c->busy) 1472 return 0; 1473 1474 spin_lock_irqsave(&d40c->lock, flags); 1475 pm_runtime_get_sync(d40c->base->dev); 1476 1477 /* If bytes left to transfer or linked tx resume job */ 1478 if (d40_residue(d40c) || d40_tx_is_linked(d40c)) 1479 res = d40_channel_execute_command(d40c, D40_DMA_RUN); 1480 1481 pm_runtime_put_autosuspend(d40c->base->dev); 1482 spin_unlock_irqrestore(&d40c->lock, flags); 1483 return res; 1484 } 1485 1486 static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx) 1487 { 1488 struct d40_chan *d40c = container_of(tx->chan, 1489 struct d40_chan, 1490 chan); 1491 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd); 1492 unsigned long flags; 1493 dma_cookie_t cookie; 1494 1495 spin_lock_irqsave(&d40c->lock, flags); 1496 cookie = dma_cookie_assign(tx); 1497 d40_desc_queue(d40c, d40d); 1498 spin_unlock_irqrestore(&d40c->lock, flags); 1499 1500 return cookie; 1501 } 1502 1503 static int d40_start(struct d40_chan *d40c) 1504 { 1505 return d40_channel_execute_command(d40c, D40_DMA_RUN); 1506 } 1507 1508 static struct d40_desc *d40_queue_start(struct d40_chan *d40c) 1509 { 1510 struct d40_desc *d40d; 1511 int err; 1512 1513 /* Start queued jobs, if any */ 1514 d40d = d40_first_queued(d40c); 1515 1516 if (d40d != NULL) { 1517 if (!d40c->busy) { 1518 d40c->busy = true; 1519 pm_runtime_get_sync(d40c->base->dev); 1520 } 1521 1522 /* Remove from queue */ 1523 d40_desc_remove(d40d); 1524 1525 /* Add to active queue */ 1526 d40_desc_submit(d40c, d40d); 1527 1528 /* Initiate DMA job */ 1529 d40_desc_load(d40c, d40d); 1530 1531 /* Start dma job */ 1532 err = d40_start(d40c); 1533 1534 if (err) 1535 return NULL; 1536 } 1537 1538 return d40d; 1539 } 1540 1541 /* called from interrupt context */ 1542 static void dma_tc_handle(struct d40_chan *d40c) 1543 { 1544 struct d40_desc *d40d; 1545 1546 /* Get first active entry from list */ 1547 d40d = d40_first_active_get(d40c); 1548 1549 if (d40d == NULL) 1550 return; 1551 1552 if (d40d->cyclic) { 1553 /* 1554 * If this was a paritially loaded list, we need to reloaded 1555 * it, and only when the list is completed. We need to check 1556 * for done because the interrupt will hit for every link, and 1557 * not just the last one. 1558 */ 1559 if (d40d->lli_current < d40d->lli_len 1560 && !d40_tx_is_linked(d40c) 1561 && !d40_residue(d40c)) { 1562 d40_lcla_free_all(d40c, d40d); 1563 d40_desc_load(d40c, d40d); 1564 (void) d40_start(d40c); 1565 1566 if (d40d->lli_current == d40d->lli_len) 1567 d40d->lli_current = 0; 1568 } 1569 } else { 1570 d40_lcla_free_all(d40c, d40d); 1571 1572 if (d40d->lli_current < d40d->lli_len) { 1573 d40_desc_load(d40c, d40d); 1574 /* Start dma job */ 1575 (void) d40_start(d40c); 1576 return; 1577 } 1578 1579 if (d40_queue_start(d40c) == NULL) { 1580 d40c->busy = false; 1581 1582 pm_runtime_put_autosuspend(d40c->base->dev); 1583 } 1584 1585 d40_desc_remove(d40d); 1586 d40_desc_done(d40c, d40d); 1587 } 1588 1589 d40c->pending_tx++; 1590 tasklet_schedule(&d40c->tasklet); 1591 1592 } 1593 1594 static void dma_tasklet(struct tasklet_struct *t) 1595 { 1596 struct d40_chan *d40c = from_tasklet(d40c, t, tasklet); 1597 struct d40_desc *d40d; 1598 unsigned long flags; 1599 bool callback_active; 1600 struct dmaengine_desc_callback cb; 1601 1602 spin_lock_irqsave(&d40c->lock, flags); 1603 1604 /* Get first entry from the done list */ 1605 d40d = d40_first_done(d40c); 1606 if (d40d == NULL) { 1607 /* Check if we have reached here for cyclic job */ 1608 d40d = d40_first_active_get(d40c); 1609 if (d40d == NULL || !d40d->cyclic) 1610 goto check_pending_tx; 1611 } 1612 1613 if (!d40d->cyclic) 1614 dma_cookie_complete(&d40d->txd); 1615 1616 /* 1617 * If terminating a channel pending_tx is set to zero. 1618 * This prevents any finished active jobs to return to the client. 1619 */ 1620 if (d40c->pending_tx == 0) { 1621 spin_unlock_irqrestore(&d40c->lock, flags); 1622 return; 1623 } 1624 1625 /* Callback to client */ 1626 callback_active = !!(d40d->txd.flags & DMA_PREP_INTERRUPT); 1627 dmaengine_desc_get_callback(&d40d->txd, &cb); 1628 1629 if (!d40d->cyclic) { 1630 if (async_tx_test_ack(&d40d->txd)) { 1631 d40_desc_remove(d40d); 1632 d40_desc_free(d40c, d40d); 1633 } else if (!d40d->is_in_client_list) { 1634 d40_desc_remove(d40d); 1635 d40_lcla_free_all(d40c, d40d); 1636 list_add_tail(&d40d->node, &d40c->client); 1637 d40d->is_in_client_list = true; 1638 } 1639 } 1640 1641 d40c->pending_tx--; 1642 1643 if (d40c->pending_tx) 1644 tasklet_schedule(&d40c->tasklet); 1645 1646 spin_unlock_irqrestore(&d40c->lock, flags); 1647 1648 if (callback_active) 1649 dmaengine_desc_callback_invoke(&cb, NULL); 1650 1651 return; 1652 check_pending_tx: 1653 /* Rescue maneuver if receiving double interrupts */ 1654 if (d40c->pending_tx > 0) 1655 d40c->pending_tx--; 1656 spin_unlock_irqrestore(&d40c->lock, flags); 1657 } 1658 1659 static irqreturn_t d40_handle_interrupt(int irq, void *data) 1660 { 1661 int i; 1662 u32 idx; 1663 u32 row; 1664 long chan = -1; 1665 struct d40_chan *d40c; 1666 struct d40_base *base = data; 1667 u32 *regs = base->regs_interrupt; 1668 struct d40_interrupt_lookup *il = base->gen_dmac.il; 1669 u32 il_size = base->gen_dmac.il_size; 1670 1671 spin_lock(&base->interrupt_lock); 1672 1673 /* Read interrupt status of both logical and physical channels */ 1674 for (i = 0; i < il_size; i++) 1675 regs[i] = readl(base->virtbase + il[i].src); 1676 1677 for (;;) { 1678 1679 chan = find_next_bit((unsigned long *)regs, 1680 BITS_PER_LONG * il_size, chan + 1); 1681 1682 /* No more set bits found? */ 1683 if (chan == BITS_PER_LONG * il_size) 1684 break; 1685 1686 row = chan / BITS_PER_LONG; 1687 idx = chan & (BITS_PER_LONG - 1); 1688 1689 if (il[row].offset == D40_PHY_CHAN) 1690 d40c = base->lookup_phy_chans[idx]; 1691 else 1692 d40c = base->lookup_log_chans[il[row].offset + idx]; 1693 1694 if (!d40c) { 1695 /* 1696 * No error because this can happen if something else 1697 * in the system is using the channel. 1698 */ 1699 continue; 1700 } 1701 1702 /* ACK interrupt */ 1703 writel(BIT(idx), base->virtbase + il[row].clr); 1704 1705 spin_lock(&d40c->lock); 1706 1707 if (!il[row].is_error) 1708 dma_tc_handle(d40c); 1709 else 1710 d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n", 1711 chan, il[row].offset, idx); 1712 1713 spin_unlock(&d40c->lock); 1714 } 1715 1716 spin_unlock(&base->interrupt_lock); 1717 1718 return IRQ_HANDLED; 1719 } 1720 1721 static int d40_validate_conf(struct d40_chan *d40c, 1722 struct stedma40_chan_cfg *conf) 1723 { 1724 int res = 0; 1725 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL; 1726 1727 if (!conf->dir) { 1728 chan_err(d40c, "Invalid direction.\n"); 1729 res = -EINVAL; 1730 } 1731 1732 if ((is_log && conf->dev_type > d40c->base->num_log_chans) || 1733 (!is_log && conf->dev_type > d40c->base->num_phy_chans) || 1734 (conf->dev_type < 0)) { 1735 chan_err(d40c, "Invalid device type (%d)\n", conf->dev_type); 1736 res = -EINVAL; 1737 } 1738 1739 if (conf->dir == DMA_DEV_TO_DEV) { 1740 /* 1741 * DMAC HW supports it. Will be added to this driver, 1742 * in case any dma client requires it. 1743 */ 1744 chan_err(d40c, "periph to periph not supported\n"); 1745 res = -EINVAL; 1746 } 1747 1748 if (d40_psize_2_burst_size(is_log, conf->src_info.psize) * 1749 conf->src_info.data_width != 1750 d40_psize_2_burst_size(is_log, conf->dst_info.psize) * 1751 conf->dst_info.data_width) { 1752 /* 1753 * The DMAC hardware only supports 1754 * src (burst x width) == dst (burst x width) 1755 */ 1756 1757 chan_err(d40c, "src (burst x width) != dst (burst x width)\n"); 1758 res = -EINVAL; 1759 } 1760 1761 return res; 1762 } 1763 1764 static bool d40_alloc_mask_set(struct d40_phy_res *phy, 1765 bool is_src, int log_event_line, bool is_log, 1766 bool *first_user) 1767 { 1768 unsigned long flags; 1769 spin_lock_irqsave(&phy->lock, flags); 1770 1771 *first_user = ((phy->allocated_src | phy->allocated_dst) 1772 == D40_ALLOC_FREE); 1773 1774 if (!is_log) { 1775 /* Physical interrupts are masked per physical full channel */ 1776 if (phy->allocated_src == D40_ALLOC_FREE && 1777 phy->allocated_dst == D40_ALLOC_FREE) { 1778 phy->allocated_dst = D40_ALLOC_PHY; 1779 phy->allocated_src = D40_ALLOC_PHY; 1780 goto found_unlock; 1781 } else 1782 goto not_found_unlock; 1783 } 1784 1785 /* Logical channel */ 1786 if (is_src) { 1787 if (phy->allocated_src == D40_ALLOC_PHY) 1788 goto not_found_unlock; 1789 1790 if (phy->allocated_src == D40_ALLOC_FREE) 1791 phy->allocated_src = D40_ALLOC_LOG_FREE; 1792 1793 if (!(phy->allocated_src & BIT(log_event_line))) { 1794 phy->allocated_src |= BIT(log_event_line); 1795 goto found_unlock; 1796 } else 1797 goto not_found_unlock; 1798 } else { 1799 if (phy->allocated_dst == D40_ALLOC_PHY) 1800 goto not_found_unlock; 1801 1802 if (phy->allocated_dst == D40_ALLOC_FREE) 1803 phy->allocated_dst = D40_ALLOC_LOG_FREE; 1804 1805 if (!(phy->allocated_dst & BIT(log_event_line))) { 1806 phy->allocated_dst |= BIT(log_event_line); 1807 goto found_unlock; 1808 } 1809 } 1810 not_found_unlock: 1811 spin_unlock_irqrestore(&phy->lock, flags); 1812 return false; 1813 found_unlock: 1814 spin_unlock_irqrestore(&phy->lock, flags); 1815 return true; 1816 } 1817 1818 static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src, 1819 int log_event_line) 1820 { 1821 unsigned long flags; 1822 bool is_free = false; 1823 1824 spin_lock_irqsave(&phy->lock, flags); 1825 if (!log_event_line) { 1826 phy->allocated_dst = D40_ALLOC_FREE; 1827 phy->allocated_src = D40_ALLOC_FREE; 1828 is_free = true; 1829 goto unlock; 1830 } 1831 1832 /* Logical channel */ 1833 if (is_src) { 1834 phy->allocated_src &= ~BIT(log_event_line); 1835 if (phy->allocated_src == D40_ALLOC_LOG_FREE) 1836 phy->allocated_src = D40_ALLOC_FREE; 1837 } else { 1838 phy->allocated_dst &= ~BIT(log_event_line); 1839 if (phy->allocated_dst == D40_ALLOC_LOG_FREE) 1840 phy->allocated_dst = D40_ALLOC_FREE; 1841 } 1842 1843 is_free = ((phy->allocated_src | phy->allocated_dst) == 1844 D40_ALLOC_FREE); 1845 unlock: 1846 spin_unlock_irqrestore(&phy->lock, flags); 1847 1848 return is_free; 1849 } 1850 1851 static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user) 1852 { 1853 int dev_type = d40c->dma_cfg.dev_type; 1854 int event_group; 1855 int event_line; 1856 struct d40_phy_res *phys; 1857 int i; 1858 int j; 1859 int log_num; 1860 int num_phy_chans; 1861 bool is_src; 1862 bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL; 1863 1864 phys = d40c->base->phy_res; 1865 num_phy_chans = d40c->base->num_phy_chans; 1866 1867 if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) { 1868 log_num = 2 * dev_type; 1869 is_src = true; 1870 } else if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV || 1871 d40c->dma_cfg.dir == DMA_MEM_TO_MEM) { 1872 /* dst event lines are used for logical memcpy */ 1873 log_num = 2 * dev_type + 1; 1874 is_src = false; 1875 } else 1876 return -EINVAL; 1877 1878 event_group = D40_TYPE_TO_GROUP(dev_type); 1879 event_line = D40_TYPE_TO_EVENT(dev_type); 1880 1881 if (!is_log) { 1882 if (d40c->dma_cfg.dir == DMA_MEM_TO_MEM) { 1883 /* Find physical half channel */ 1884 if (d40c->dma_cfg.use_fixed_channel) { 1885 i = d40c->dma_cfg.phy_channel; 1886 if (d40_alloc_mask_set(&phys[i], is_src, 1887 0, is_log, 1888 first_phy_user)) 1889 goto found_phy; 1890 } else { 1891 for (i = 0; i < num_phy_chans; i++) { 1892 if (d40_alloc_mask_set(&phys[i], is_src, 1893 0, is_log, 1894 first_phy_user)) 1895 goto found_phy; 1896 } 1897 } 1898 } else 1899 for (j = 0; j < d40c->base->num_phy_chans; j += 8) { 1900 int phy_num = j + event_group * 2; 1901 for (i = phy_num; i < phy_num + 2; i++) { 1902 if (d40_alloc_mask_set(&phys[i], 1903 is_src, 1904 0, 1905 is_log, 1906 first_phy_user)) 1907 goto found_phy; 1908 } 1909 } 1910 return -EINVAL; 1911 found_phy: 1912 d40c->phy_chan = &phys[i]; 1913 d40c->log_num = D40_PHY_CHAN; 1914 goto out; 1915 } 1916 if (dev_type == -1) 1917 return -EINVAL; 1918 1919 /* Find logical channel */ 1920 for (j = 0; j < d40c->base->num_phy_chans; j += 8) { 1921 int phy_num = j + event_group * 2; 1922 1923 if (d40c->dma_cfg.use_fixed_channel) { 1924 i = d40c->dma_cfg.phy_channel; 1925 1926 if ((i != phy_num) && (i != phy_num + 1)) { 1927 dev_err(chan2dev(d40c), 1928 "invalid fixed phy channel %d\n", i); 1929 return -EINVAL; 1930 } 1931 1932 if (d40_alloc_mask_set(&phys[i], is_src, event_line, 1933 is_log, first_phy_user)) 1934 goto found_log; 1935 1936 dev_err(chan2dev(d40c), 1937 "could not allocate fixed phy channel %d\n", i); 1938 return -EINVAL; 1939 } 1940 1941 /* 1942 * Spread logical channels across all available physical rather 1943 * than pack every logical channel at the first available phy 1944 * channels. 1945 */ 1946 if (is_src) { 1947 for (i = phy_num; i < phy_num + 2; i++) { 1948 if (d40_alloc_mask_set(&phys[i], is_src, 1949 event_line, is_log, 1950 first_phy_user)) 1951 goto found_log; 1952 } 1953 } else { 1954 for (i = phy_num + 1; i >= phy_num; i--) { 1955 if (d40_alloc_mask_set(&phys[i], is_src, 1956 event_line, is_log, 1957 first_phy_user)) 1958 goto found_log; 1959 } 1960 } 1961 } 1962 return -EINVAL; 1963 1964 found_log: 1965 d40c->phy_chan = &phys[i]; 1966 d40c->log_num = log_num; 1967 out: 1968 1969 if (is_log) 1970 d40c->base->lookup_log_chans[d40c->log_num] = d40c; 1971 else 1972 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c; 1973 1974 return 0; 1975 1976 } 1977 1978 static int d40_config_memcpy(struct d40_chan *d40c) 1979 { 1980 dma_cap_mask_t cap = d40c->chan.device->cap_mask; 1981 1982 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) { 1983 d40c->dma_cfg = dma40_memcpy_conf_log; 1984 d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id]; 1985 1986 d40_log_cfg(&d40c->dma_cfg, 1987 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); 1988 1989 } else if (dma_has_cap(DMA_MEMCPY, cap) && 1990 dma_has_cap(DMA_SLAVE, cap)) { 1991 d40c->dma_cfg = dma40_memcpy_conf_phy; 1992 1993 /* Generate interrupt at end of transfer or relink. */ 1994 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS); 1995 1996 /* Generate interrupt on error. */ 1997 d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS); 1998 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS); 1999 2000 } else { 2001 chan_err(d40c, "No memcpy\n"); 2002 return -EINVAL; 2003 } 2004 2005 return 0; 2006 } 2007 2008 static int d40_free_dma(struct d40_chan *d40c) 2009 { 2010 2011 int res = 0; 2012 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type); 2013 struct d40_phy_res *phy = d40c->phy_chan; 2014 bool is_src; 2015 2016 /* Terminate all queued and active transfers */ 2017 d40_term_all(d40c); 2018 2019 if (phy == NULL) { 2020 chan_err(d40c, "phy == null\n"); 2021 return -EINVAL; 2022 } 2023 2024 if (phy->allocated_src == D40_ALLOC_FREE && 2025 phy->allocated_dst == D40_ALLOC_FREE) { 2026 chan_err(d40c, "channel already free\n"); 2027 return -EINVAL; 2028 } 2029 2030 if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV || 2031 d40c->dma_cfg.dir == DMA_MEM_TO_MEM) 2032 is_src = false; 2033 else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) 2034 is_src = true; 2035 else { 2036 chan_err(d40c, "Unknown direction\n"); 2037 return -EINVAL; 2038 } 2039 2040 pm_runtime_get_sync(d40c->base->dev); 2041 res = d40_channel_execute_command(d40c, D40_DMA_STOP); 2042 if (res) { 2043 chan_err(d40c, "stop failed\n"); 2044 goto mark_last_busy; 2045 } 2046 2047 d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0); 2048 2049 if (chan_is_logical(d40c)) 2050 d40c->base->lookup_log_chans[d40c->log_num] = NULL; 2051 else 2052 d40c->base->lookup_phy_chans[phy->num] = NULL; 2053 2054 if (d40c->busy) 2055 pm_runtime_put_autosuspend(d40c->base->dev); 2056 2057 d40c->busy = false; 2058 d40c->phy_chan = NULL; 2059 d40c->configured = false; 2060 mark_last_busy: 2061 pm_runtime_put_autosuspend(d40c->base->dev); 2062 return res; 2063 } 2064 2065 static bool d40_is_paused(struct d40_chan *d40c) 2066 { 2067 void __iomem *chanbase = chan_base(d40c); 2068 bool is_paused = false; 2069 unsigned long flags; 2070 void __iomem *active_reg; 2071 u32 status; 2072 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type); 2073 2074 spin_lock_irqsave(&d40c->lock, flags); 2075 2076 if (chan_is_physical(d40c)) { 2077 if (d40c->phy_chan->num % 2 == 0) 2078 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; 2079 else 2080 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; 2081 2082 status = (readl(active_reg) & 2083 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> 2084 D40_CHAN_POS(d40c->phy_chan->num); 2085 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP) 2086 is_paused = true; 2087 goto unlock; 2088 } 2089 2090 if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV || 2091 d40c->dma_cfg.dir == DMA_MEM_TO_MEM) { 2092 status = readl(chanbase + D40_CHAN_REG_SDLNK); 2093 } else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) { 2094 status = readl(chanbase + D40_CHAN_REG_SSLNK); 2095 } else { 2096 chan_err(d40c, "Unknown direction\n"); 2097 goto unlock; 2098 } 2099 2100 status = (status & D40_EVENTLINE_MASK(event)) >> 2101 D40_EVENTLINE_POS(event); 2102 2103 if (status != D40_DMA_RUN) 2104 is_paused = true; 2105 unlock: 2106 spin_unlock_irqrestore(&d40c->lock, flags); 2107 return is_paused; 2108 2109 } 2110 2111 static u32 stedma40_residue(struct dma_chan *chan) 2112 { 2113 struct d40_chan *d40c = 2114 container_of(chan, struct d40_chan, chan); 2115 u32 bytes_left; 2116 unsigned long flags; 2117 2118 spin_lock_irqsave(&d40c->lock, flags); 2119 bytes_left = d40_residue(d40c); 2120 spin_unlock_irqrestore(&d40c->lock, flags); 2121 2122 return bytes_left; 2123 } 2124 2125 static int 2126 d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc, 2127 struct scatterlist *sg_src, struct scatterlist *sg_dst, 2128 unsigned int sg_len, dma_addr_t src_dev_addr, 2129 dma_addr_t dst_dev_addr) 2130 { 2131 struct stedma40_chan_cfg *cfg = &chan->dma_cfg; 2132 struct stedma40_half_channel_info *src_info = &cfg->src_info; 2133 struct stedma40_half_channel_info *dst_info = &cfg->dst_info; 2134 int ret; 2135 2136 ret = d40_log_sg_to_lli(sg_src, sg_len, 2137 src_dev_addr, 2138 desc->lli_log.src, 2139 chan->log_def.lcsp1, 2140 src_info->data_width, 2141 dst_info->data_width); 2142 2143 ret = d40_log_sg_to_lli(sg_dst, sg_len, 2144 dst_dev_addr, 2145 desc->lli_log.dst, 2146 chan->log_def.lcsp3, 2147 dst_info->data_width, 2148 src_info->data_width); 2149 2150 return ret < 0 ? ret : 0; 2151 } 2152 2153 static int 2154 d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc, 2155 struct scatterlist *sg_src, struct scatterlist *sg_dst, 2156 unsigned int sg_len, dma_addr_t src_dev_addr, 2157 dma_addr_t dst_dev_addr) 2158 { 2159 struct stedma40_chan_cfg *cfg = &chan->dma_cfg; 2160 struct stedma40_half_channel_info *src_info = &cfg->src_info; 2161 struct stedma40_half_channel_info *dst_info = &cfg->dst_info; 2162 unsigned long flags = 0; 2163 int ret; 2164 2165 if (desc->cyclic) 2166 flags |= LLI_CYCLIC | LLI_TERM_INT; 2167 2168 ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr, 2169 desc->lli_phy.src, 2170 virt_to_phys(desc->lli_phy.src), 2171 chan->src_def_cfg, 2172 src_info, dst_info, flags); 2173 2174 ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr, 2175 desc->lli_phy.dst, 2176 virt_to_phys(desc->lli_phy.dst), 2177 chan->dst_def_cfg, 2178 dst_info, src_info, flags); 2179 2180 dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr, 2181 desc->lli_pool.size, DMA_TO_DEVICE); 2182 2183 return ret < 0 ? ret : 0; 2184 } 2185 2186 static struct d40_desc * 2187 d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg, 2188 unsigned int sg_len, unsigned long dma_flags) 2189 { 2190 struct stedma40_chan_cfg *cfg; 2191 struct d40_desc *desc; 2192 int ret; 2193 2194 desc = d40_desc_get(chan); 2195 if (!desc) 2196 return NULL; 2197 2198 cfg = &chan->dma_cfg; 2199 desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width, 2200 cfg->dst_info.data_width); 2201 if (desc->lli_len < 0) { 2202 chan_err(chan, "Unaligned size\n"); 2203 goto free_desc; 2204 } 2205 2206 ret = d40_pool_lli_alloc(chan, desc, desc->lli_len); 2207 if (ret < 0) { 2208 chan_err(chan, "Could not allocate lli\n"); 2209 goto free_desc; 2210 } 2211 2212 desc->lli_current = 0; 2213 desc->txd.flags = dma_flags; 2214 desc->txd.tx_submit = d40_tx_submit; 2215 2216 dma_async_tx_descriptor_init(&desc->txd, &chan->chan); 2217 2218 return desc; 2219 free_desc: 2220 d40_desc_free(chan, desc); 2221 return NULL; 2222 } 2223 2224 static struct dma_async_tx_descriptor * 2225 d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src, 2226 struct scatterlist *sg_dst, unsigned int sg_len, 2227 enum dma_transfer_direction direction, unsigned long dma_flags) 2228 { 2229 struct d40_chan *chan = container_of(dchan, struct d40_chan, chan); 2230 dma_addr_t src_dev_addr; 2231 dma_addr_t dst_dev_addr; 2232 struct d40_desc *desc; 2233 unsigned long flags; 2234 int ret; 2235 2236 if (!chan->phy_chan) { 2237 chan_err(chan, "Cannot prepare unallocated channel\n"); 2238 return NULL; 2239 } 2240 2241 d40_set_runtime_config_write(dchan, &chan->slave_config, direction); 2242 2243 spin_lock_irqsave(&chan->lock, flags); 2244 2245 desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags); 2246 if (desc == NULL) 2247 goto unlock; 2248 2249 if (sg_next(&sg_src[sg_len - 1]) == sg_src) 2250 desc->cyclic = true; 2251 2252 src_dev_addr = 0; 2253 dst_dev_addr = 0; 2254 if (direction == DMA_DEV_TO_MEM) 2255 src_dev_addr = chan->runtime_addr; 2256 else if (direction == DMA_MEM_TO_DEV) 2257 dst_dev_addr = chan->runtime_addr; 2258 2259 if (chan_is_logical(chan)) 2260 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst, 2261 sg_len, src_dev_addr, dst_dev_addr); 2262 else 2263 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst, 2264 sg_len, src_dev_addr, dst_dev_addr); 2265 2266 if (ret) { 2267 chan_err(chan, "Failed to prepare %s sg job: %d\n", 2268 chan_is_logical(chan) ? "log" : "phy", ret); 2269 goto free_desc; 2270 } 2271 2272 /* 2273 * add descriptor to the prepare queue in order to be able 2274 * to free them later in terminate_all 2275 */ 2276 list_add_tail(&desc->node, &chan->prepare_queue); 2277 2278 spin_unlock_irqrestore(&chan->lock, flags); 2279 2280 return &desc->txd; 2281 free_desc: 2282 d40_desc_free(chan, desc); 2283 unlock: 2284 spin_unlock_irqrestore(&chan->lock, flags); 2285 return NULL; 2286 } 2287 2288 static bool stedma40_filter(struct dma_chan *chan, void *data) 2289 { 2290 struct stedma40_chan_cfg *info = data; 2291 struct d40_chan *d40c = 2292 container_of(chan, struct d40_chan, chan); 2293 int err; 2294 2295 if (data) { 2296 err = d40_validate_conf(d40c, info); 2297 if (!err) 2298 d40c->dma_cfg = *info; 2299 } else 2300 err = d40_config_memcpy(d40c); 2301 2302 if (!err) 2303 d40c->configured = true; 2304 2305 return err == 0; 2306 } 2307 2308 static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src) 2309 { 2310 bool realtime = d40c->dma_cfg.realtime; 2311 bool highprio = d40c->dma_cfg.high_priority; 2312 u32 rtreg; 2313 u32 event = D40_TYPE_TO_EVENT(dev_type); 2314 u32 group = D40_TYPE_TO_GROUP(dev_type); 2315 u32 bit = BIT(event); 2316 u32 prioreg; 2317 struct d40_gen_dmac *dmac = &d40c->base->gen_dmac; 2318 2319 rtreg = realtime ? dmac->realtime_en : dmac->realtime_clear; 2320 /* 2321 * Due to a hardware bug, in some cases a logical channel triggered by 2322 * a high priority destination event line can generate extra packet 2323 * transactions. 2324 * 2325 * The workaround is to not set the high priority level for the 2326 * destination event lines that trigger logical channels. 2327 */ 2328 if (!src && chan_is_logical(d40c)) 2329 highprio = false; 2330 2331 prioreg = highprio ? dmac->high_prio_en : dmac->high_prio_clear; 2332 2333 /* Destination event lines are stored in the upper halfword */ 2334 if (!src) 2335 bit <<= 16; 2336 2337 writel(bit, d40c->base->virtbase + prioreg + group * 4); 2338 writel(bit, d40c->base->virtbase + rtreg + group * 4); 2339 } 2340 2341 static void d40_set_prio_realtime(struct d40_chan *d40c) 2342 { 2343 if (d40c->base->rev < 3) 2344 return; 2345 2346 if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) || 2347 (d40c->dma_cfg.dir == DMA_DEV_TO_DEV)) 2348 __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true); 2349 2350 if ((d40c->dma_cfg.dir == DMA_MEM_TO_DEV) || 2351 (d40c->dma_cfg.dir == DMA_DEV_TO_DEV)) 2352 __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false); 2353 } 2354 2355 #define D40_DT_FLAGS_MODE(flags) ((flags >> 0) & 0x1) 2356 #define D40_DT_FLAGS_DIR(flags) ((flags >> 1) & 0x1) 2357 #define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1) 2358 #define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1) 2359 #define D40_DT_FLAGS_HIGH_PRIO(flags) ((flags >> 4) & 0x1) 2360 2361 static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec, 2362 struct of_dma *ofdma) 2363 { 2364 struct stedma40_chan_cfg cfg; 2365 dma_cap_mask_t cap; 2366 u32 flags; 2367 2368 memset(&cfg, 0, sizeof(struct stedma40_chan_cfg)); 2369 2370 dma_cap_zero(cap); 2371 dma_cap_set(DMA_SLAVE, cap); 2372 2373 cfg.dev_type = dma_spec->args[0]; 2374 flags = dma_spec->args[2]; 2375 2376 switch (D40_DT_FLAGS_MODE(flags)) { 2377 case 0: cfg.mode = STEDMA40_MODE_LOGICAL; break; 2378 case 1: cfg.mode = STEDMA40_MODE_PHYSICAL; break; 2379 } 2380 2381 switch (D40_DT_FLAGS_DIR(flags)) { 2382 case 0: 2383 cfg.dir = DMA_MEM_TO_DEV; 2384 cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags); 2385 break; 2386 case 1: 2387 cfg.dir = DMA_DEV_TO_MEM; 2388 cfg.src_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags); 2389 break; 2390 } 2391 2392 if (D40_DT_FLAGS_FIXED_CHAN(flags)) { 2393 cfg.phy_channel = dma_spec->args[1]; 2394 cfg.use_fixed_channel = true; 2395 } 2396 2397 if (D40_DT_FLAGS_HIGH_PRIO(flags)) 2398 cfg.high_priority = true; 2399 2400 return dma_request_channel(cap, stedma40_filter, &cfg); 2401 } 2402 2403 /* DMA ENGINE functions */ 2404 static int d40_alloc_chan_resources(struct dma_chan *chan) 2405 { 2406 int err; 2407 unsigned long flags; 2408 struct d40_chan *d40c = 2409 container_of(chan, struct d40_chan, chan); 2410 bool is_free_phy; 2411 spin_lock_irqsave(&d40c->lock, flags); 2412 2413 dma_cookie_init(chan); 2414 2415 /* If no dma configuration is set use default configuration (memcpy) */ 2416 if (!d40c->configured) { 2417 err = d40_config_memcpy(d40c); 2418 if (err) { 2419 chan_err(d40c, "Failed to configure memcpy channel\n"); 2420 goto mark_last_busy; 2421 } 2422 } 2423 2424 err = d40_allocate_channel(d40c, &is_free_phy); 2425 if (err) { 2426 chan_err(d40c, "Failed to allocate channel\n"); 2427 d40c->configured = false; 2428 goto mark_last_busy; 2429 } 2430 2431 pm_runtime_get_sync(d40c->base->dev); 2432 2433 d40_set_prio_realtime(d40c); 2434 2435 if (chan_is_logical(d40c)) { 2436 if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) 2437 d40c->lcpa = d40c->base->lcpa_base + 2438 d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE; 2439 else 2440 d40c->lcpa = d40c->base->lcpa_base + 2441 d40c->dma_cfg.dev_type * 2442 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA; 2443 2444 /* Unmask the Global Interrupt Mask. */ 2445 d40c->src_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS); 2446 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS); 2447 } 2448 2449 dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n", 2450 chan_is_logical(d40c) ? "logical" : "physical", 2451 d40c->phy_chan->num, 2452 d40c->dma_cfg.use_fixed_channel ? ", fixed" : ""); 2453 2454 2455 /* 2456 * Only write channel configuration to the DMA if the physical 2457 * resource is free. In case of multiple logical channels 2458 * on the same physical resource, only the first write is necessary. 2459 */ 2460 if (is_free_phy) 2461 d40_config_write(d40c); 2462 mark_last_busy: 2463 pm_runtime_put_autosuspend(d40c->base->dev); 2464 spin_unlock_irqrestore(&d40c->lock, flags); 2465 return err; 2466 } 2467 2468 static void d40_free_chan_resources(struct dma_chan *chan) 2469 { 2470 struct d40_chan *d40c = 2471 container_of(chan, struct d40_chan, chan); 2472 int err; 2473 unsigned long flags; 2474 2475 if (d40c->phy_chan == NULL) { 2476 chan_err(d40c, "Cannot free unallocated channel\n"); 2477 return; 2478 } 2479 2480 spin_lock_irqsave(&d40c->lock, flags); 2481 2482 err = d40_free_dma(d40c); 2483 2484 if (err) 2485 chan_err(d40c, "Failed to free channel\n"); 2486 spin_unlock_irqrestore(&d40c->lock, flags); 2487 } 2488 2489 static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan, 2490 dma_addr_t dst, 2491 dma_addr_t src, 2492 size_t size, 2493 unsigned long dma_flags) 2494 { 2495 struct scatterlist dst_sg; 2496 struct scatterlist src_sg; 2497 2498 sg_init_table(&dst_sg, 1); 2499 sg_init_table(&src_sg, 1); 2500 2501 sg_dma_address(&dst_sg) = dst; 2502 sg_dma_address(&src_sg) = src; 2503 2504 sg_dma_len(&dst_sg) = size; 2505 sg_dma_len(&src_sg) = size; 2506 2507 return d40_prep_sg(chan, &src_sg, &dst_sg, 1, 2508 DMA_MEM_TO_MEM, dma_flags); 2509 } 2510 2511 static struct dma_async_tx_descriptor * 2512 d40_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 2513 unsigned int sg_len, enum dma_transfer_direction direction, 2514 unsigned long dma_flags, void *context) 2515 { 2516 if (!is_slave_direction(direction)) 2517 return NULL; 2518 2519 return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags); 2520 } 2521 2522 static struct dma_async_tx_descriptor * 2523 dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr, 2524 size_t buf_len, size_t period_len, 2525 enum dma_transfer_direction direction, unsigned long flags) 2526 { 2527 unsigned int periods = buf_len / period_len; 2528 struct dma_async_tx_descriptor *txd; 2529 struct scatterlist *sg; 2530 int i; 2531 2532 sg = kzalloc_objs(struct scatterlist, periods + 1, GFP_NOWAIT); 2533 if (!sg) 2534 return NULL; 2535 2536 for (i = 0; i < periods; i++) { 2537 sg_dma_address(&sg[i]) = dma_addr; 2538 sg_dma_len(&sg[i]) = period_len; 2539 dma_addr += period_len; 2540 } 2541 2542 sg_chain(sg, periods + 1, sg); 2543 2544 txd = d40_prep_sg(chan, sg, sg, periods, direction, 2545 DMA_PREP_INTERRUPT); 2546 2547 kfree(sg); 2548 2549 return txd; 2550 } 2551 2552 static enum dma_status d40_tx_status(struct dma_chan *chan, 2553 dma_cookie_t cookie, 2554 struct dma_tx_state *txstate) 2555 { 2556 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); 2557 enum dma_status ret; 2558 2559 if (d40c->phy_chan == NULL) { 2560 chan_err(d40c, "Cannot read status of unallocated channel\n"); 2561 return -EINVAL; 2562 } 2563 2564 ret = dma_cookie_status(chan, cookie, txstate); 2565 if (ret != DMA_COMPLETE && txstate) 2566 dma_set_residue(txstate, stedma40_residue(chan)); 2567 2568 if (d40_is_paused(d40c)) 2569 ret = DMA_PAUSED; 2570 2571 return ret; 2572 } 2573 2574 static void d40_issue_pending(struct dma_chan *chan) 2575 { 2576 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); 2577 unsigned long flags; 2578 2579 if (d40c->phy_chan == NULL) { 2580 chan_err(d40c, "Channel is not allocated!\n"); 2581 return; 2582 } 2583 2584 spin_lock_irqsave(&d40c->lock, flags); 2585 2586 list_splice_tail_init(&d40c->pending_queue, &d40c->queue); 2587 2588 /* Busy means that queued jobs are already being processed */ 2589 if (!d40c->busy) 2590 (void) d40_queue_start(d40c); 2591 2592 spin_unlock_irqrestore(&d40c->lock, flags); 2593 } 2594 2595 static int d40_terminate_all(struct dma_chan *chan) 2596 { 2597 unsigned long flags; 2598 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); 2599 int ret; 2600 2601 if (d40c->phy_chan == NULL) { 2602 chan_err(d40c, "Channel is not allocated!\n"); 2603 return -EINVAL; 2604 } 2605 2606 spin_lock_irqsave(&d40c->lock, flags); 2607 2608 pm_runtime_get_sync(d40c->base->dev); 2609 ret = d40_channel_execute_command(d40c, D40_DMA_STOP); 2610 if (ret) 2611 chan_err(d40c, "Failed to stop channel\n"); 2612 2613 d40_term_all(d40c); 2614 pm_runtime_put_autosuspend(d40c->base->dev); 2615 if (d40c->busy) 2616 pm_runtime_put_autosuspend(d40c->base->dev); 2617 d40c->busy = false; 2618 2619 spin_unlock_irqrestore(&d40c->lock, flags); 2620 return 0; 2621 } 2622 2623 static int 2624 dma40_config_to_halfchannel(struct d40_chan *d40c, 2625 struct stedma40_half_channel_info *info, 2626 u32 maxburst) 2627 { 2628 int psize; 2629 2630 if (chan_is_logical(d40c)) { 2631 if (maxburst >= 16) 2632 psize = STEDMA40_PSIZE_LOG_16; 2633 else if (maxburst >= 8) 2634 psize = STEDMA40_PSIZE_LOG_8; 2635 else if (maxburst >= 4) 2636 psize = STEDMA40_PSIZE_LOG_4; 2637 else 2638 psize = STEDMA40_PSIZE_LOG_1; 2639 } else { 2640 if (maxburst >= 16) 2641 psize = STEDMA40_PSIZE_PHY_16; 2642 else if (maxburst >= 8) 2643 psize = STEDMA40_PSIZE_PHY_8; 2644 else if (maxburst >= 4) 2645 psize = STEDMA40_PSIZE_PHY_4; 2646 else 2647 psize = STEDMA40_PSIZE_PHY_1; 2648 } 2649 2650 info->psize = psize; 2651 info->flow_ctrl = STEDMA40_NO_FLOW_CTRL; 2652 2653 return 0; 2654 } 2655 2656 static int d40_set_runtime_config(struct dma_chan *chan, 2657 struct dma_slave_config *config) 2658 { 2659 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); 2660 2661 memcpy(&d40c->slave_config, config, sizeof(*config)); 2662 2663 return 0; 2664 } 2665 2666 /* Runtime reconfiguration extension */ 2667 static int d40_set_runtime_config_write(struct dma_chan *chan, 2668 struct dma_slave_config *config, 2669 enum dma_transfer_direction direction) 2670 { 2671 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); 2672 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg; 2673 enum dma_slave_buswidth src_addr_width, dst_addr_width; 2674 dma_addr_t config_addr; 2675 u32 src_maxburst, dst_maxburst; 2676 int ret; 2677 2678 if (d40c->phy_chan == NULL) { 2679 chan_err(d40c, "Channel is not allocated!\n"); 2680 return -EINVAL; 2681 } 2682 2683 src_addr_width = config->src_addr_width; 2684 src_maxburst = config->src_maxburst; 2685 dst_addr_width = config->dst_addr_width; 2686 dst_maxburst = config->dst_maxburst; 2687 2688 if (direction == DMA_DEV_TO_MEM) { 2689 config_addr = config->src_addr; 2690 2691 if (cfg->dir != DMA_DEV_TO_MEM) 2692 dev_dbg(d40c->base->dev, 2693 "channel was not configured for peripheral " 2694 "to memory transfer (%d) overriding\n", 2695 cfg->dir); 2696 cfg->dir = DMA_DEV_TO_MEM; 2697 2698 /* Configure the memory side */ 2699 if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 2700 dst_addr_width = src_addr_width; 2701 if (dst_maxburst == 0) 2702 dst_maxburst = src_maxburst; 2703 2704 } else if (direction == DMA_MEM_TO_DEV) { 2705 config_addr = config->dst_addr; 2706 2707 if (cfg->dir != DMA_MEM_TO_DEV) 2708 dev_dbg(d40c->base->dev, 2709 "channel was not configured for memory " 2710 "to peripheral transfer (%d) overriding\n", 2711 cfg->dir); 2712 cfg->dir = DMA_MEM_TO_DEV; 2713 2714 /* Configure the memory side */ 2715 if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 2716 src_addr_width = dst_addr_width; 2717 if (src_maxburst == 0) 2718 src_maxburst = dst_maxburst; 2719 } else { 2720 dev_err(d40c->base->dev, 2721 "unrecognized channel direction %d\n", 2722 direction); 2723 return -EINVAL; 2724 } 2725 2726 if (config_addr <= 0) { 2727 dev_err(d40c->base->dev, "no address supplied\n"); 2728 return -EINVAL; 2729 } 2730 2731 if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) { 2732 dev_err(d40c->base->dev, 2733 "src/dst width/maxburst mismatch: %d*%d != %d*%d\n", 2734 src_maxburst, 2735 src_addr_width, 2736 dst_maxburst, 2737 dst_addr_width); 2738 return -EINVAL; 2739 } 2740 2741 if (src_maxburst > 16) { 2742 src_maxburst = 16; 2743 dst_maxburst = src_maxburst * src_addr_width / dst_addr_width; 2744 } else if (dst_maxburst > 16) { 2745 dst_maxburst = 16; 2746 src_maxburst = dst_maxburst * dst_addr_width / src_addr_width; 2747 } 2748 2749 /* Only valid widths are; 1, 2, 4 and 8. */ 2750 if (src_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED || 2751 src_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES || 2752 dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED || 2753 dst_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES || 2754 !is_power_of_2(src_addr_width) || 2755 !is_power_of_2(dst_addr_width)) 2756 return -EINVAL; 2757 2758 cfg->src_info.data_width = src_addr_width; 2759 cfg->dst_info.data_width = dst_addr_width; 2760 2761 ret = dma40_config_to_halfchannel(d40c, &cfg->src_info, 2762 src_maxburst); 2763 if (ret) 2764 return ret; 2765 2766 ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info, 2767 dst_maxburst); 2768 if (ret) 2769 return ret; 2770 2771 /* Fill in register values */ 2772 if (chan_is_logical(d40c)) 2773 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); 2774 else 2775 d40_phy_cfg(cfg, &d40c->src_def_cfg, &d40c->dst_def_cfg); 2776 2777 /* These settings will take precedence later */ 2778 d40c->runtime_addr = config_addr; 2779 d40c->runtime_direction = direction; 2780 dev_dbg(d40c->base->dev, 2781 "configured channel %s for %s, data width %d/%d, " 2782 "maxburst %d/%d elements, LE, no flow control\n", 2783 dma_chan_name(chan), 2784 (direction == DMA_DEV_TO_MEM) ? "RX" : "TX", 2785 src_addr_width, dst_addr_width, 2786 src_maxburst, dst_maxburst); 2787 2788 return 0; 2789 } 2790 2791 /* Initialization functions */ 2792 2793 static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma, 2794 struct d40_chan *chans, int offset, 2795 int num_chans) 2796 { 2797 int i = 0; 2798 struct d40_chan *d40c; 2799 2800 INIT_LIST_HEAD(&dma->channels); 2801 2802 for (i = offset; i < offset + num_chans; i++) { 2803 d40c = &chans[i]; 2804 d40c->base = base; 2805 d40c->chan.device = dma; 2806 2807 spin_lock_init(&d40c->lock); 2808 2809 d40c->log_num = D40_PHY_CHAN; 2810 2811 INIT_LIST_HEAD(&d40c->done); 2812 INIT_LIST_HEAD(&d40c->active); 2813 INIT_LIST_HEAD(&d40c->queue); 2814 INIT_LIST_HEAD(&d40c->pending_queue); 2815 INIT_LIST_HEAD(&d40c->client); 2816 INIT_LIST_HEAD(&d40c->prepare_queue); 2817 2818 tasklet_setup(&d40c->tasklet, dma_tasklet); 2819 2820 list_add_tail(&d40c->chan.device_node, 2821 &dma->channels); 2822 } 2823 } 2824 2825 static void d40_ops_init(struct d40_base *base, struct dma_device *dev) 2826 { 2827 if (dma_has_cap(DMA_SLAVE, dev->cap_mask)) { 2828 dev->device_prep_slave_sg = d40_prep_slave_sg; 2829 dev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 2830 } 2831 2832 if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) { 2833 dev->device_prep_dma_memcpy = d40_prep_memcpy; 2834 dev->directions = BIT(DMA_MEM_TO_MEM); 2835 /* 2836 * This controller can only access address at even 2837 * 32bit boundaries, i.e. 2^2 2838 */ 2839 dev->copy_align = DMAENGINE_ALIGN_4_BYTES; 2840 } 2841 2842 if (dma_has_cap(DMA_CYCLIC, dev->cap_mask)) 2843 dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic; 2844 2845 dev->device_alloc_chan_resources = d40_alloc_chan_resources; 2846 dev->device_free_chan_resources = d40_free_chan_resources; 2847 dev->device_issue_pending = d40_issue_pending; 2848 dev->device_tx_status = d40_tx_status; 2849 dev->device_config = d40_set_runtime_config; 2850 dev->device_pause = d40_pause; 2851 dev->device_resume = d40_resume; 2852 dev->device_terminate_all = d40_terminate_all; 2853 dev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 2854 dev->dev = base->dev; 2855 } 2856 2857 static int __init d40_dmaengine_init(struct d40_base *base, 2858 int num_reserved_chans) 2859 { 2860 int err ; 2861 2862 d40_chan_init(base, &base->dma_slave, base->log_chans, 2863 0, base->num_log_chans); 2864 2865 dma_cap_zero(base->dma_slave.cap_mask); 2866 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask); 2867 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask); 2868 2869 d40_ops_init(base, &base->dma_slave); 2870 2871 err = dmaenginem_async_device_register(&base->dma_slave); 2872 2873 if (err) { 2874 d40_err(base->dev, "Failed to register slave channels\n"); 2875 goto exit; 2876 } 2877 2878 d40_chan_init(base, &base->dma_memcpy, base->log_chans, 2879 base->num_log_chans, base->num_memcpy_chans); 2880 2881 dma_cap_zero(base->dma_memcpy.cap_mask); 2882 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask); 2883 2884 d40_ops_init(base, &base->dma_memcpy); 2885 2886 err = dmaenginem_async_device_register(&base->dma_memcpy); 2887 2888 if (err) { 2889 d40_err(base->dev, 2890 "Failed to register memcpy only channels\n"); 2891 goto exit; 2892 } 2893 2894 d40_chan_init(base, &base->dma_both, base->phy_chans, 2895 0, num_reserved_chans); 2896 2897 dma_cap_zero(base->dma_both.cap_mask); 2898 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask); 2899 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask); 2900 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask); 2901 2902 d40_ops_init(base, &base->dma_both); 2903 err = dmaenginem_async_device_register(&base->dma_both); 2904 2905 if (err) { 2906 d40_err(base->dev, 2907 "Failed to register logical and physical capable channels\n"); 2908 goto exit; 2909 } 2910 return 0; 2911 exit: 2912 return err; 2913 } 2914 2915 /* Suspend resume functionality */ 2916 #ifdef CONFIG_PM_SLEEP 2917 static int dma40_suspend(struct device *dev) 2918 { 2919 struct d40_base *base = dev_get_drvdata(dev); 2920 int ret; 2921 2922 ret = pm_runtime_force_suspend(dev); 2923 if (ret) 2924 return ret; 2925 2926 if (base->lcpa_regulator) 2927 ret = regulator_disable(base->lcpa_regulator); 2928 return ret; 2929 } 2930 2931 static int dma40_resume(struct device *dev) 2932 { 2933 struct d40_base *base = dev_get_drvdata(dev); 2934 int ret = 0; 2935 2936 if (base->lcpa_regulator) { 2937 ret = regulator_enable(base->lcpa_regulator); 2938 if (ret) 2939 return ret; 2940 } 2941 2942 return pm_runtime_force_resume(dev); 2943 } 2944 #endif 2945 2946 #ifdef CONFIG_PM 2947 static void dma40_backup(void __iomem *baseaddr, u32 *backup, 2948 u32 *regaddr, int num, bool save) 2949 { 2950 int i; 2951 2952 for (i = 0; i < num; i++) { 2953 void __iomem *addr = baseaddr + regaddr[i]; 2954 2955 if (save) 2956 backup[i] = readl_relaxed(addr); 2957 else 2958 writel_relaxed(backup[i], addr); 2959 } 2960 } 2961 2962 static void d40_save_restore_registers(struct d40_base *base, bool save) 2963 { 2964 int i; 2965 2966 /* Save/Restore channel specific registers */ 2967 for (i = 0; i < base->num_phy_chans; i++) { 2968 void __iomem *addr; 2969 int idx; 2970 2971 if (base->phy_res[i].reserved) 2972 continue; 2973 2974 addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA; 2975 idx = i * ARRAY_SIZE(d40_backup_regs_chan); 2976 2977 dma40_backup(addr, &base->reg_val_backup_chan[idx], 2978 d40_backup_regs_chan, 2979 ARRAY_SIZE(d40_backup_regs_chan), 2980 save); 2981 } 2982 2983 /* Save/Restore global registers */ 2984 dma40_backup(base->virtbase, base->reg_val_backup, 2985 d40_backup_regs, ARRAY_SIZE(d40_backup_regs), 2986 save); 2987 2988 /* Save/Restore registers only existing on dma40 v3 and later */ 2989 if (base->gen_dmac.backup) 2990 dma40_backup(base->virtbase, base->reg_val_backup_v4, 2991 base->gen_dmac.backup, 2992 base->gen_dmac.backup_size, 2993 save); 2994 } 2995 2996 static int dma40_runtime_suspend(struct device *dev) 2997 { 2998 struct d40_base *base = dev_get_drvdata(dev); 2999 3000 d40_save_restore_registers(base, true); 3001 3002 /* Don't disable/enable clocks for v1 due to HW bugs */ 3003 if (base->rev != 1) 3004 writel_relaxed(base->gcc_pwr_off_mask, 3005 base->virtbase + D40_DREG_GCC); 3006 3007 return 0; 3008 } 3009 3010 static int dma40_runtime_resume(struct device *dev) 3011 { 3012 struct d40_base *base = dev_get_drvdata(dev); 3013 3014 d40_save_restore_registers(base, false); 3015 3016 writel_relaxed(D40_DREG_GCC_ENABLE_ALL, 3017 base->virtbase + D40_DREG_GCC); 3018 return 0; 3019 } 3020 #endif 3021 3022 static const struct dev_pm_ops dma40_pm_ops = { 3023 SET_LATE_SYSTEM_SLEEP_PM_OPS(dma40_suspend, dma40_resume) 3024 SET_RUNTIME_PM_OPS(dma40_runtime_suspend, 3025 dma40_runtime_resume, 3026 NULL) 3027 }; 3028 3029 /* Initialization functions. */ 3030 3031 static int __init d40_phy_res_init(struct d40_base *base) 3032 { 3033 int i; 3034 int num_phy_chans_avail = 0; 3035 u32 val[2]; 3036 int odd_even_bit = -2; 3037 int gcc = D40_DREG_GCC_ENA; 3038 3039 val[0] = readl(base->virtbase + D40_DREG_PRSME); 3040 val[1] = readl(base->virtbase + D40_DREG_PRSMO); 3041 3042 for (i = 0; i < base->num_phy_chans; i++) { 3043 base->phy_res[i].num = i; 3044 odd_even_bit += 2 * ((i % 2) == 0); 3045 if (((val[i % 2] >> odd_even_bit) & 3) == 1) { 3046 /* Mark security only channels as occupied */ 3047 base->phy_res[i].allocated_src = D40_ALLOC_PHY; 3048 base->phy_res[i].allocated_dst = D40_ALLOC_PHY; 3049 base->phy_res[i].reserved = true; 3050 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i), 3051 D40_DREG_GCC_SRC); 3052 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i), 3053 D40_DREG_GCC_DST); 3054 3055 3056 } else { 3057 base->phy_res[i].allocated_src = D40_ALLOC_FREE; 3058 base->phy_res[i].allocated_dst = D40_ALLOC_FREE; 3059 base->phy_res[i].reserved = false; 3060 num_phy_chans_avail++; 3061 } 3062 spin_lock_init(&base->phy_res[i].lock); 3063 } 3064 3065 /* Mark disabled channels as occupied */ 3066 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) { 3067 int chan = base->plat_data->disabled_channels[i]; 3068 3069 base->phy_res[chan].allocated_src = D40_ALLOC_PHY; 3070 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY; 3071 base->phy_res[chan].reserved = true; 3072 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan), 3073 D40_DREG_GCC_SRC); 3074 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan), 3075 D40_DREG_GCC_DST); 3076 num_phy_chans_avail--; 3077 } 3078 3079 /* Mark soft_lli channels */ 3080 for (i = 0; i < base->plat_data->num_of_soft_lli_chans; i++) { 3081 int chan = base->plat_data->soft_lli_chans[i]; 3082 3083 base->phy_res[chan].use_soft_lli = true; 3084 } 3085 3086 dev_info(base->dev, "%d of %d physical DMA channels available\n", 3087 num_phy_chans_avail, base->num_phy_chans); 3088 3089 /* Verify settings extended vs standard */ 3090 val[0] = readl(base->virtbase + D40_DREG_PRTYP); 3091 3092 for (i = 0; i < base->num_phy_chans; i++) { 3093 3094 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE && 3095 (val[0] & 0x3) != 1) 3096 dev_info(base->dev, 3097 "[%s] INFO: channel %d is misconfigured (%d)\n", 3098 __func__, i, val[0] & 0x3); 3099 3100 val[0] = val[0] >> 2; 3101 } 3102 3103 /* 3104 * To keep things simple, Enable all clocks initially. 3105 * The clocks will get managed later post channel allocation. 3106 * The clocks for the event lines on which reserved channels exists 3107 * are not managed here. 3108 */ 3109 writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC); 3110 base->gcc_pwr_off_mask = gcc; 3111 3112 return num_phy_chans_avail; 3113 } 3114 3115 /* Called from the registered devm action */ 3116 static void d40_drop_kmem_cache_action(void *d) 3117 { 3118 struct kmem_cache *desc_slab = d; 3119 3120 kmem_cache_destroy(desc_slab); 3121 } 3122 3123 static int __init d40_hw_detect_init(struct platform_device *pdev, 3124 struct d40_base **retbase) 3125 { 3126 struct stedma40_platform_data *plat_data = dev_get_platdata(&pdev->dev); 3127 struct device *dev = &pdev->dev; 3128 struct clk *clk; 3129 void __iomem *virtbase; 3130 struct d40_base *base; 3131 int num_log_chans; 3132 int num_phy_chans; 3133 int num_memcpy_chans; 3134 int i; 3135 u32 pid; 3136 u32 cid; 3137 u8 rev; 3138 int ret; 3139 3140 clk = devm_clk_get_enabled(dev, NULL); 3141 if (IS_ERR(clk)) 3142 return PTR_ERR(clk); 3143 3144 /* Get IO for DMAC base address */ 3145 virtbase = devm_platform_ioremap_resource_byname(pdev, "base"); 3146 if (IS_ERR(virtbase)) 3147 return PTR_ERR(virtbase); 3148 3149 /* This is just a regular AMBA PrimeCell ID actually */ 3150 for (pid = 0, i = 0; i < 4; i++) 3151 pid |= (readl(virtbase + SZ_4K - 0x20 + 4 * i) 3152 & 255) << (i * 8); 3153 for (cid = 0, i = 0; i < 4; i++) 3154 cid |= (readl(virtbase + SZ_4K - 0x10 + 4 * i) 3155 & 255) << (i * 8); 3156 3157 if (cid != AMBA_CID) { 3158 d40_err(dev, "Unknown hardware! No PrimeCell ID\n"); 3159 return -EINVAL; 3160 } 3161 if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) { 3162 d40_err(dev, "Unknown designer! Got %x wanted %x\n", 3163 AMBA_MANF_BITS(pid), 3164 AMBA_VENDOR_ST); 3165 return -EINVAL; 3166 } 3167 /* 3168 * HW revision: 3169 * DB8500ed has revision 0 3170 * ? has revision 1 3171 * DB8500v1 has revision 2 3172 * DB8500v2 has revision 3 3173 * AP9540v1 has revision 4 3174 * DB8540v1 has revision 4 3175 */ 3176 rev = AMBA_REV_BITS(pid); 3177 if (rev < 2) { 3178 d40_err(dev, "hardware revision: %d is not supported", rev); 3179 return -EINVAL; 3180 } 3181 3182 /* The number of physical channels on this HW */ 3183 if (plat_data->num_of_phy_chans) 3184 num_phy_chans = plat_data->num_of_phy_chans; 3185 else 3186 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4; 3187 3188 /* The number of channels used for memcpy */ 3189 if (plat_data->num_of_memcpy_chans) 3190 num_memcpy_chans = plat_data->num_of_memcpy_chans; 3191 else 3192 num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels); 3193 3194 num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY; 3195 3196 dev_info(dev, 3197 "hardware rev: %d with %d physical and %d logical channels\n", 3198 rev, num_phy_chans, num_log_chans); 3199 3200 base = devm_kzalloc(dev, 3201 ALIGN(sizeof(struct d40_base), 4) + 3202 (num_phy_chans + num_log_chans + num_memcpy_chans) * 3203 sizeof(struct d40_chan), GFP_KERNEL); 3204 3205 if (!base) 3206 return -ENOMEM; 3207 3208 base->rev = rev; 3209 base->clk = clk; 3210 base->num_memcpy_chans = num_memcpy_chans; 3211 base->num_phy_chans = num_phy_chans; 3212 base->num_log_chans = num_log_chans; 3213 base->virtbase = virtbase; 3214 base->plat_data = plat_data; 3215 base->dev = dev; 3216 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4); 3217 base->log_chans = &base->phy_chans[num_phy_chans]; 3218 3219 if (base->plat_data->num_of_phy_chans == 14) { 3220 base->gen_dmac.backup = d40_backup_regs_v4b; 3221 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B; 3222 base->gen_dmac.interrupt_en = D40_DREG_CPCMIS; 3223 base->gen_dmac.interrupt_clear = D40_DREG_CPCICR; 3224 base->gen_dmac.realtime_en = D40_DREG_CRSEG1; 3225 base->gen_dmac.realtime_clear = D40_DREG_CRCEG1; 3226 base->gen_dmac.high_prio_en = D40_DREG_CPSEG1; 3227 base->gen_dmac.high_prio_clear = D40_DREG_CPCEG1; 3228 base->gen_dmac.il = il_v4b; 3229 base->gen_dmac.il_size = ARRAY_SIZE(il_v4b); 3230 base->gen_dmac.init_reg = dma_init_reg_v4b; 3231 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b); 3232 } else { 3233 if (base->rev >= 3) { 3234 base->gen_dmac.backup = d40_backup_regs_v4a; 3235 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A; 3236 } 3237 base->gen_dmac.interrupt_en = D40_DREG_PCMIS; 3238 base->gen_dmac.interrupt_clear = D40_DREG_PCICR; 3239 base->gen_dmac.realtime_en = D40_DREG_RSEG1; 3240 base->gen_dmac.realtime_clear = D40_DREG_RCEG1; 3241 base->gen_dmac.high_prio_en = D40_DREG_PSEG1; 3242 base->gen_dmac.high_prio_clear = D40_DREG_PCEG1; 3243 base->gen_dmac.il = il_v4a; 3244 base->gen_dmac.il_size = ARRAY_SIZE(il_v4a); 3245 base->gen_dmac.init_reg = dma_init_reg_v4a; 3246 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a); 3247 } 3248 3249 base->phy_res = devm_kcalloc(dev, num_phy_chans, 3250 sizeof(*base->phy_res), 3251 GFP_KERNEL); 3252 if (!base->phy_res) 3253 return -ENOMEM; 3254 3255 base->lookup_phy_chans = devm_kcalloc(dev, num_phy_chans, 3256 sizeof(*base->lookup_phy_chans), 3257 GFP_KERNEL); 3258 if (!base->lookup_phy_chans) 3259 return -ENOMEM; 3260 3261 base->lookup_log_chans = devm_kcalloc(dev, num_log_chans, 3262 sizeof(*base->lookup_log_chans), 3263 GFP_KERNEL); 3264 if (!base->lookup_log_chans) 3265 return -ENOMEM; 3266 3267 base->reg_val_backup_chan = devm_kmalloc_array(dev, base->num_phy_chans, 3268 sizeof(d40_backup_regs_chan), 3269 GFP_KERNEL); 3270 if (!base->reg_val_backup_chan) 3271 return -ENOMEM; 3272 3273 base->lcla_pool.alloc_map = devm_kcalloc(dev, num_phy_chans 3274 * D40_LCLA_LINK_PER_EVENT_GRP, 3275 sizeof(*base->lcla_pool.alloc_map), 3276 GFP_KERNEL); 3277 if (!base->lcla_pool.alloc_map) 3278 return -ENOMEM; 3279 3280 base->regs_interrupt = devm_kmalloc_array(dev, base->gen_dmac.il_size, 3281 sizeof(*base->regs_interrupt), 3282 GFP_KERNEL); 3283 if (!base->regs_interrupt) 3284 return -ENOMEM; 3285 3286 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc), 3287 0, SLAB_HWCACHE_ALIGN, 3288 NULL); 3289 if (!base->desc_slab) 3290 return -ENOMEM; 3291 3292 ret = devm_add_action_or_reset(dev, d40_drop_kmem_cache_action, 3293 base->desc_slab); 3294 if (ret) 3295 return ret; 3296 3297 *retbase = base; 3298 3299 return 0; 3300 } 3301 3302 static void __init d40_hw_init(struct d40_base *base) 3303 { 3304 3305 int i; 3306 u32 prmseo[2] = {0, 0}; 3307 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF}; 3308 u32 pcmis = 0; 3309 u32 pcicr = 0; 3310 struct d40_reg_val *dma_init_reg = base->gen_dmac.init_reg; 3311 u32 reg_size = base->gen_dmac.init_reg_size; 3312 3313 for (i = 0; i < reg_size; i++) 3314 writel(dma_init_reg[i].val, 3315 base->virtbase + dma_init_reg[i].reg); 3316 3317 /* Configure all our dma channels to default settings */ 3318 for (i = 0; i < base->num_phy_chans; i++) { 3319 3320 activeo[i % 2] = activeo[i % 2] << 2; 3321 3322 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src 3323 == D40_ALLOC_PHY) { 3324 activeo[i % 2] |= 3; 3325 continue; 3326 } 3327 3328 /* Enable interrupt # */ 3329 pcmis = (pcmis << 1) | 1; 3330 3331 /* Clear interrupt # */ 3332 pcicr = (pcicr << 1) | 1; 3333 3334 /* Set channel to physical mode */ 3335 prmseo[i % 2] = prmseo[i % 2] << 2; 3336 prmseo[i % 2] |= 1; 3337 3338 } 3339 3340 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE); 3341 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO); 3342 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE); 3343 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO); 3344 3345 /* Write which interrupt to enable */ 3346 writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en); 3347 3348 /* Write which interrupt to clear */ 3349 writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear); 3350 3351 /* These are __initdata and cannot be accessed after init */ 3352 base->gen_dmac.init_reg = NULL; 3353 base->gen_dmac.init_reg_size = 0; 3354 } 3355 3356 static int __init d40_lcla_allocate(struct d40_base *base) 3357 { 3358 struct d40_lcla_pool *pool = &base->lcla_pool; 3359 unsigned long *page_list; 3360 int i, j; 3361 int ret; 3362 3363 /* 3364 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned, 3365 * To full fill this hardware requirement without wasting 256 kb 3366 * we allocate pages until we get an aligned one. 3367 */ 3368 page_list = kmalloc_array(MAX_LCLA_ALLOC_ATTEMPTS, 3369 sizeof(*page_list), 3370 GFP_KERNEL); 3371 if (!page_list) 3372 return -ENOMEM; 3373 3374 /* Calculating how many pages that are required */ 3375 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE; 3376 3377 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) { 3378 page_list[i] = __get_free_pages(GFP_KERNEL, 3379 base->lcla_pool.pages); 3380 if (!page_list[i]) { 3381 3382 d40_err(base->dev, "Failed to allocate %d pages.\n", 3383 base->lcla_pool.pages); 3384 ret = -ENOMEM; 3385 3386 for (j = 0; j < i; j++) 3387 free_pages(page_list[j], base->lcla_pool.pages); 3388 goto free_page_list; 3389 } 3390 3391 if ((virt_to_phys((void *)page_list[i]) & 3392 (LCLA_ALIGNMENT - 1)) == 0) 3393 break; 3394 } 3395 3396 for (j = 0; j < i; j++) 3397 free_pages(page_list[j], base->lcla_pool.pages); 3398 3399 if (i < MAX_LCLA_ALLOC_ATTEMPTS) { 3400 base->lcla_pool.base = (void *)page_list[i]; 3401 } else { 3402 /* 3403 * After many attempts and no success with finding the correct 3404 * alignment, try with allocating a big buffer. 3405 */ 3406 dev_warn(base->dev, 3407 "[%s] Failed to get %d pages @ 18 bit align.\n", 3408 __func__, base->lcla_pool.pages); 3409 base->lcla_pool.base_unaligned = kmalloc(SZ_1K * 3410 base->num_phy_chans + 3411 LCLA_ALIGNMENT, 3412 GFP_KERNEL); 3413 if (!base->lcla_pool.base_unaligned) { 3414 ret = -ENOMEM; 3415 goto free_page_list; 3416 } 3417 3418 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned, 3419 LCLA_ALIGNMENT); 3420 } 3421 3422 pool->dma_addr = dma_map_single(base->dev, pool->base, 3423 SZ_1K * base->num_phy_chans, 3424 DMA_TO_DEVICE); 3425 if (dma_mapping_error(base->dev, pool->dma_addr)) { 3426 pool->dma_addr = 0; 3427 ret = -ENOMEM; 3428 goto free_page_list; 3429 } 3430 3431 writel(virt_to_phys(base->lcla_pool.base), 3432 base->virtbase + D40_DREG_LCLA); 3433 ret = 0; 3434 free_page_list: 3435 kfree(page_list); 3436 return ret; 3437 } 3438 3439 static int __init d40_of_probe(struct device *dev, 3440 struct device_node *np) 3441 { 3442 struct stedma40_platform_data *pdata; 3443 int num_phy = 0, num_memcpy = 0, num_disabled = 0; 3444 const __be32 *list; 3445 3446 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3447 if (!pdata) 3448 return -ENOMEM; 3449 3450 /* If absent this value will be obtained from h/w. */ 3451 of_property_read_u32(np, "dma-channels", &num_phy); 3452 if (num_phy > 0) 3453 pdata->num_of_phy_chans = num_phy; 3454 3455 list = of_get_property(np, "memcpy-channels", &num_memcpy); 3456 num_memcpy /= sizeof(*list); 3457 3458 if (num_memcpy > D40_MEMCPY_MAX_CHANS || num_memcpy <= 0) { 3459 d40_err(dev, 3460 "Invalid number of memcpy channels specified (%d)\n", 3461 num_memcpy); 3462 return -EINVAL; 3463 } 3464 pdata->num_of_memcpy_chans = num_memcpy; 3465 3466 of_property_read_u32_array(np, "memcpy-channels", 3467 dma40_memcpy_channels, 3468 num_memcpy); 3469 3470 list = of_get_property(np, "disabled-channels", &num_disabled); 3471 num_disabled /= sizeof(*list); 3472 3473 if (num_disabled >= STEDMA40_MAX_PHYS || num_disabled < 0) { 3474 d40_err(dev, 3475 "Invalid number of disabled channels specified (%d)\n", 3476 num_disabled); 3477 return -EINVAL; 3478 } 3479 3480 of_property_read_u32_array(np, "disabled-channels", 3481 pdata->disabled_channels, 3482 num_disabled); 3483 pdata->disabled_channels[num_disabled] = -1; 3484 3485 dev->platform_data = pdata; 3486 3487 return 0; 3488 } 3489 3490 static int __init d40_probe(struct platform_device *pdev) 3491 { 3492 struct device *dev = &pdev->dev; 3493 struct device_node *np = pdev->dev.of_node; 3494 struct device_node *np_lcpa; 3495 struct d40_base *base; 3496 struct resource *res; 3497 struct resource res_lcpa; 3498 int num_reserved_chans; 3499 u32 val; 3500 int ret; 3501 3502 if (d40_of_probe(dev, np)) { 3503 ret = -ENOMEM; 3504 goto report_failure; 3505 } 3506 3507 ret = d40_hw_detect_init(pdev, &base); 3508 if (ret) 3509 goto report_failure; 3510 3511 num_reserved_chans = d40_phy_res_init(base); 3512 3513 platform_set_drvdata(pdev, base); 3514 3515 spin_lock_init(&base->interrupt_lock); 3516 spin_lock_init(&base->execmd_lock); 3517 3518 /* Get IO for logical channel parameter address (LCPA) */ 3519 np_lcpa = of_parse_phandle(np, "sram", 0); 3520 if (!np_lcpa) { 3521 dev_err(dev, "no LCPA SRAM node\n"); 3522 ret = -EINVAL; 3523 goto report_failure; 3524 } 3525 /* This is no device so read the address directly from the node */ 3526 ret = of_address_to_resource(np_lcpa, 0, &res_lcpa); 3527 if (ret) { 3528 dev_err(dev, "no LCPA SRAM resource\n"); 3529 goto report_failure; 3530 } 3531 base->lcpa_size = resource_size(&res_lcpa); 3532 base->phy_lcpa = res_lcpa.start; 3533 dev_info(dev, "found LCPA SRAM at %pad, size %pa\n", 3534 &base->phy_lcpa, &base->lcpa_size); 3535 3536 /* We make use of ESRAM memory for this. */ 3537 val = readl(base->virtbase + D40_DREG_LCPA); 3538 if (base->phy_lcpa != val && val != 0) { 3539 dev_warn(dev, 3540 "[%s] Mismatch LCPA dma 0x%x, def %08x\n", 3541 __func__, val, (u32)base->phy_lcpa); 3542 } else 3543 writel(base->phy_lcpa, base->virtbase + D40_DREG_LCPA); 3544 3545 base->lcpa_base = devm_ioremap(dev, base->phy_lcpa, base->lcpa_size); 3546 if (!base->lcpa_base) { 3547 ret = -ENOMEM; 3548 d40_err(dev, "Failed to ioremap LCPA region\n"); 3549 goto report_failure; 3550 } 3551 /* If lcla has to be located in ESRAM we don't need to allocate */ 3552 if (base->plat_data->use_esram_lcla) { 3553 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 3554 "lcla_esram"); 3555 if (!res) { 3556 ret = -ENOENT; 3557 d40_err(dev, 3558 "No \"lcla_esram\" memory resource\n"); 3559 goto report_failure; 3560 } 3561 base->lcla_pool.base = devm_ioremap(dev, res->start, 3562 resource_size(res)); 3563 if (!base->lcla_pool.base) { 3564 ret = -ENOMEM; 3565 d40_err(dev, "Failed to ioremap LCLA region\n"); 3566 goto report_failure; 3567 } 3568 writel(res->start, base->virtbase + D40_DREG_LCLA); 3569 3570 } else { 3571 ret = d40_lcla_allocate(base); 3572 if (ret) { 3573 d40_err(dev, "Failed to allocate LCLA area\n"); 3574 goto destroy_cache; 3575 } 3576 } 3577 3578 spin_lock_init(&base->lcla_pool.lock); 3579 3580 base->irq = platform_get_irq(pdev, 0); 3581 if (base->irq < 0) { 3582 ret = base->irq; 3583 goto destroy_cache; 3584 } 3585 3586 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base); 3587 if (ret) { 3588 d40_err(dev, "No IRQ defined\n"); 3589 goto destroy_cache; 3590 } 3591 3592 if (base->plat_data->use_esram_lcla) { 3593 3594 base->lcpa_regulator = regulator_get(base->dev, "lcla_esram"); 3595 if (IS_ERR(base->lcpa_regulator)) { 3596 d40_err(dev, "Failed to get lcpa_regulator\n"); 3597 ret = PTR_ERR(base->lcpa_regulator); 3598 base->lcpa_regulator = NULL; 3599 goto destroy_cache; 3600 } 3601 3602 ret = regulator_enable(base->lcpa_regulator); 3603 if (ret) { 3604 d40_err(dev, 3605 "Failed to enable lcpa_regulator\n"); 3606 regulator_put(base->lcpa_regulator); 3607 base->lcpa_regulator = NULL; 3608 goto destroy_cache; 3609 } 3610 } 3611 3612 writel_relaxed(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC); 3613 3614 pm_runtime_irq_safe(base->dev); 3615 pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY); 3616 pm_runtime_use_autosuspend(base->dev); 3617 pm_runtime_mark_last_busy(base->dev); 3618 pm_runtime_set_active(base->dev); 3619 pm_runtime_enable(base->dev); 3620 3621 ret = d40_dmaengine_init(base, num_reserved_chans); 3622 if (ret) 3623 goto destroy_cache; 3624 3625 dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE); 3626 3627 d40_hw_init(base); 3628 3629 ret = of_dma_controller_register(np, d40_xlate, NULL); 3630 if (ret) { 3631 dev_err(dev, 3632 "could not register of_dma_controller\n"); 3633 goto destroy_cache; 3634 } 3635 3636 dev_info(base->dev, "initialized\n"); 3637 return 0; 3638 3639 destroy_cache: 3640 if (base->lcla_pool.dma_addr) 3641 dma_unmap_single(base->dev, base->lcla_pool.dma_addr, 3642 SZ_1K * base->num_phy_chans, 3643 DMA_TO_DEVICE); 3644 3645 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base) 3646 free_pages((unsigned long)base->lcla_pool.base, 3647 base->lcla_pool.pages); 3648 3649 kfree(base->lcla_pool.base_unaligned); 3650 3651 if (base->lcpa_regulator) { 3652 regulator_disable(base->lcpa_regulator); 3653 regulator_put(base->lcpa_regulator); 3654 } 3655 pm_runtime_disable(base->dev); 3656 3657 report_failure: 3658 d40_err(dev, "probe failed\n"); 3659 return ret; 3660 } 3661 3662 static const struct of_device_id d40_match[] = { 3663 { .compatible = "stericsson,dma40", }, 3664 {} 3665 }; 3666 3667 static struct platform_driver d40_driver = { 3668 .driver = { 3669 .name = D40_NAME, 3670 .pm = &dma40_pm_ops, 3671 .of_match_table = d40_match, 3672 }, 3673 }; 3674 3675 static int __init stedma40_init(void) 3676 { 3677 return platform_driver_probe(&d40_driver, d40_probe); 3678 } 3679 subsys_initcall(stedma40_init); 3680