1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2013 Imagination Technologies 4 * Author: Paul Burton <paul.burton@mips.com> 5 */ 6 7 #include <linux/cpu.h> 8 #include <linux/delay.h> 9 #include <linux/io.h> 10 #include <linux/memblock.h> 11 #include <linux/sched/task_stack.h> 12 #include <linux/sched/hotplug.h> 13 #include <linux/slab.h> 14 #include <linux/smp.h> 15 #include <linux/types.h> 16 #include <linux/irq.h> 17 18 #include <asm/bcache.h> 19 #include <asm/mips-cps.h> 20 #include <asm/mips_mt.h> 21 #include <asm/mipsregs.h> 22 #include <asm/pm-cps.h> 23 #include <asm/r4kcache.h> 24 #include <asm/regdef.h> 25 #include <asm/smp.h> 26 #include <asm/smp-cps.h> 27 #include <asm/time.h> 28 #include <asm/uasm.h> 29 30 #define BEV_VEC_SIZE 0x500 31 #define BEV_VEC_ALIGN 0x1000 32 33 enum label_id { 34 label_not_nmi = 1, 35 }; 36 37 UASM_L_LA(_not_nmi) 38 39 static u64 core_entry_reg; 40 static phys_addr_t cps_vec_pa; 41 42 struct cluster_boot_config *mips_cps_cluster_bootcfg; 43 44 static void power_up_other_cluster(unsigned int cluster) 45 { 46 u32 stat, seq_state; 47 unsigned int timeout; 48 49 mips_cm_lock_other(cluster, CM_GCR_Cx_OTHER_CORE_CM, 0, 50 CM_GCR_Cx_OTHER_BLOCK_LOCAL); 51 stat = read_cpc_co_stat_conf(); 52 mips_cm_unlock_other(); 53 54 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; 55 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); 56 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U5) 57 return; 58 59 /* Set endianness & power up the CM */ 60 mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); 61 write_cpc_redir_sys_config(IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)); 62 write_cpc_redir_pwrup_ctl(1); 63 mips_cm_unlock_other(); 64 65 /* Wait for the CM to start up */ 66 timeout = 1000; 67 mips_cm_lock_other(cluster, CM_GCR_Cx_OTHER_CORE_CM, 0, 68 CM_GCR_Cx_OTHER_BLOCK_LOCAL); 69 while (1) { 70 stat = read_cpc_co_stat_conf(); 71 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; 72 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); 73 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U5) 74 break; 75 76 if (timeout) { 77 mdelay(1); 78 timeout--; 79 } else { 80 pr_warn("Waiting for cluster %u CM to power up... STAT_CONF=0x%x\n", 81 cluster, stat); 82 mdelay(1000); 83 } 84 } 85 86 mips_cm_unlock_other(); 87 } 88 89 static unsigned __init core_vpe_count(unsigned int cluster, unsigned core) 90 { 91 return min(smp_max_threads, mips_cps_numvps(cluster, core)); 92 } 93 94 static void __init *mips_cps_build_core_entry(void *addr) 95 { 96 extern void (*nmi_handler)(void); 97 u32 *p = addr; 98 u32 val; 99 struct uasm_label labels[2]; 100 struct uasm_reloc relocs[2]; 101 struct uasm_label *l = labels; 102 struct uasm_reloc *r = relocs; 103 104 memset(labels, 0, sizeof(labels)); 105 memset(relocs, 0, sizeof(relocs)); 106 107 uasm_i_mfc0(&p, GPR_K0, C0_STATUS); 108 UASM_i_LA(&p, GPR_T9, ST0_NMI); 109 uasm_i_and(&p, GPR_K0, GPR_K0, GPR_T9); 110 111 uasm_il_bnez(&p, &r, GPR_K0, label_not_nmi); 112 uasm_i_nop(&p); 113 UASM_i_LA(&p, GPR_K0, (long)&nmi_handler); 114 115 uasm_l_not_nmi(&l, p); 116 117 val = CAUSEF_IV; 118 uasm_i_lui(&p, GPR_K0, val >> 16); 119 uasm_i_ori(&p, GPR_K0, GPR_K0, val & 0xffff); 120 uasm_i_mtc0(&p, GPR_K0, C0_CAUSE); 121 val = ST0_CU1 | ST0_CU0 | ST0_BEV | ST0_KX_IF_64; 122 uasm_i_lui(&p, GPR_K0, val >> 16); 123 uasm_i_ori(&p, GPR_K0, GPR_K0, val & 0xffff); 124 uasm_i_mtc0(&p, GPR_K0, C0_STATUS); 125 uasm_i_ehb(&p); 126 uasm_i_ori(&p, GPR_A0, 0, read_c0_config() & CONF_CM_CMASK); 127 UASM_i_LA(&p, GPR_A1, (long)mips_gcr_base); 128 #if defined(KBUILD_64BIT_SYM32) || defined(CONFIG_32BIT) 129 UASM_i_LA(&p, GPR_T9, CKSEG1ADDR(__pa_symbol(mips_cps_core_boot))); 130 #else 131 UASM_i_LA(&p, GPR_T9, TO_UNCAC(__pa_symbol(mips_cps_core_boot))); 132 #endif 133 uasm_i_jr(&p, GPR_T9); 134 uasm_i_nop(&p); 135 136 uasm_resolve_relocs(relocs, labels); 137 138 return p; 139 } 140 141 static bool __init check_64bit_reset(void) 142 { 143 bool cx_64bit_reset = false; 144 145 mips_cm_lock_other(0, 0, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); 146 write_gcr_co_reset64_base(CM_GCR_Cx_RESET64_BASE_BEVEXCBASE); 147 if ((read_gcr_co_reset64_base() & CM_GCR_Cx_RESET64_BASE_BEVEXCBASE) == 148 CM_GCR_Cx_RESET64_BASE_BEVEXCBASE) 149 cx_64bit_reset = true; 150 mips_cm_unlock_other(); 151 152 return cx_64bit_reset; 153 } 154 155 static int __init allocate_cps_vecs(void) 156 { 157 /* Try to allocate in KSEG1 first */ 158 cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN, 159 0x0, CSEGX_SIZE - 1); 160 161 if (cps_vec_pa) 162 core_entry_reg = CKSEG1ADDR(cps_vec_pa) & 163 CM_GCR_Cx_RESET_BASE_BEVEXCBASE; 164 165 if (!cps_vec_pa && mips_cm_is64) { 166 phys_addr_t end; 167 168 if (check_64bit_reset()) { 169 pr_info("VP Local Reset Exception Base support 47 bits address\n"); 170 end = MEMBLOCK_ALLOC_ANYWHERE; 171 } else { 172 end = SZ_4G - 1; 173 } 174 cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN, 0, end); 175 if (cps_vec_pa) { 176 if (check_64bit_reset()) 177 core_entry_reg = (cps_vec_pa & CM_GCR_Cx_RESET64_BASE_BEVEXCBASE) | 178 CM_GCR_Cx_RESET_BASE_MODE; 179 else 180 core_entry_reg = (cps_vec_pa & CM_GCR_Cx_RESET_BASE_BEVEXCBASE) | 181 CM_GCR_Cx_RESET_BASE_MODE; 182 } 183 } 184 185 if (!cps_vec_pa) 186 return -ENOMEM; 187 188 return 0; 189 } 190 191 static void __init setup_cps_vecs(void) 192 { 193 void *cps_vec; 194 195 cps_vec = (void *)CKSEG1ADDR_OR_64BIT(cps_vec_pa); 196 mips_cps_build_core_entry(cps_vec); 197 198 memcpy(cps_vec + 0x200, &excep_tlbfill, 0x80); 199 memcpy(cps_vec + 0x280, &excep_xtlbfill, 0x80); 200 memcpy(cps_vec + 0x300, &excep_cache, 0x80); 201 memcpy(cps_vec + 0x380, &excep_genex, 0x80); 202 memcpy(cps_vec + 0x400, &excep_intex, 0x80); 203 memcpy(cps_vec + 0x480, &excep_ejtag, 0x80); 204 205 /* Make sure no prefetched data in cache */ 206 blast_inv_dcache_range(CKSEG0ADDR_OR_64BIT(cps_vec_pa), CKSEG0ADDR_OR_64BIT(cps_vec_pa) + BEV_VEC_SIZE); 207 bc_inv(CKSEG0ADDR_OR_64BIT(cps_vec_pa), BEV_VEC_SIZE); 208 __sync(); 209 } 210 211 static void __init cps_smp_setup(void) 212 { 213 unsigned int nclusters, ncores, nvpes, core_vpes; 214 int cl, c, v; 215 216 /* Detect & record VPE topology */ 217 nvpes = 0; 218 nclusters = mips_cps_numclusters(); 219 pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE"); 220 for (cl = 0; cl < nclusters; cl++) { 221 if (cl > 0) 222 pr_cont(","); 223 pr_cont("{"); 224 225 if (mips_cm_revision() >= CM_REV_CM3_5) 226 power_up_other_cluster(cl); 227 228 ncores = mips_cps_numcores(cl); 229 for (c = 0; c < ncores; c++) { 230 core_vpes = core_vpe_count(cl, c); 231 232 if (c > 0) 233 pr_cont(","); 234 pr_cont("%u", core_vpes); 235 236 /* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */ 237 if (!cl && !c) 238 smp_num_siblings = core_vpes; 239 cpumask_set_cpu(nvpes, &__cpu_primary_thread_mask); 240 241 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) { 242 cpu_set_cluster(&cpu_data[nvpes + v], cl); 243 cpu_set_core(&cpu_data[nvpes + v], c); 244 cpu_set_vpe_id(&cpu_data[nvpes + v], v); 245 } 246 247 nvpes += core_vpes; 248 } 249 250 pr_cont("}"); 251 } 252 pr_cont(" total %u\n", nvpes); 253 254 /* Indicate present CPUs (CPU being synonymous with VPE) */ 255 for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) { 256 set_cpu_possible(v, true); 257 set_cpu_present(v, true); 258 __cpu_number_map[v] = v; 259 __cpu_logical_map[v] = v; 260 } 261 262 /* Set a coherent default CCA (CWB) */ 263 change_c0_config(CONF_CM_CMASK, 0x5); 264 265 /* Initialise core 0 */ 266 mips_cps_core_init(); 267 268 /* Make core 0 coherent with everything */ 269 write_gcr_cl_coherence(0xff); 270 271 if (allocate_cps_vecs()) 272 pr_err("Failed to allocate CPS vectors\n"); 273 274 if (core_entry_reg && mips_cm_revision() >= CM_REV_CM3) 275 write_gcr_bev_base(core_entry_reg); 276 277 #ifdef CONFIG_MIPS_MT_FPAFF 278 /* If we have an FPU, enroll ourselves in the FPU-full mask */ 279 if (cpu_has_fpu) 280 cpumask_set_cpu(0, &mt_fpu_cpumask); 281 #endif /* CONFIG_MIPS_MT_FPAFF */ 282 } 283 284 unsigned long calibrate_delay_is_known(void) 285 { 286 int first_cpu_cluster = 0; 287 288 /* The calibration has to be done on the primary CPU of the cluster */ 289 if (mips_cps_first_online_in_cluster(&first_cpu_cluster)) 290 return 0; 291 292 return cpu_data[first_cpu_cluster].udelay_val; 293 } 294 295 static void __init cps_prepare_cpus(unsigned int max_cpus) 296 { 297 unsigned int nclusters, ncores, core_vpes, nvpe = 0, c, cl, cca; 298 bool cca_unsuitable, cores_limited; 299 struct cluster_boot_config *cluster_bootcfg; 300 struct core_boot_config *core_bootcfg; 301 302 mips_mt_set_cpuoptions(); 303 304 if (!core_entry_reg) { 305 pr_err("core_entry address unsuitable, disabling smp-cps\n"); 306 goto err_out; 307 } 308 309 /* Detect whether the CCA is unsuited to multi-core SMP */ 310 cca = read_c0_config() & CONF_CM_CMASK; 311 switch (cca) { 312 case 0x4: /* CWBE */ 313 case 0x5: /* CWB */ 314 /* The CCA is coherent, multi-core is fine */ 315 cca_unsuitable = false; 316 break; 317 318 default: 319 /* CCA is not coherent, multi-core is not usable */ 320 cca_unsuitable = true; 321 } 322 323 /* Warn the user if the CCA prevents multi-core */ 324 cores_limited = false; 325 if (cca_unsuitable || cpu_has_dc_aliases) { 326 for_each_present_cpu(c) { 327 if (cpus_are_siblings(smp_processor_id(), c)) 328 continue; 329 330 set_cpu_present(c, false); 331 cores_limited = true; 332 } 333 } 334 if (cores_limited) 335 pr_warn("Using only one core due to %s%s%s\n", 336 cca_unsuitable ? "unsuitable CCA" : "", 337 (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "", 338 cpu_has_dc_aliases ? "dcache aliasing" : ""); 339 340 setup_cps_vecs(); 341 342 /* Allocate cluster boot configuration structs */ 343 nclusters = mips_cps_numclusters(); 344 mips_cps_cluster_bootcfg = kzalloc_objs(*mips_cps_cluster_bootcfg, 345 nclusters, GFP_KERNEL); 346 if (!mips_cps_cluster_bootcfg) 347 goto err_out; 348 349 if (nclusters > 1) 350 mips_cm_update_property(); 351 352 for (cl = 0; cl < nclusters; cl++) { 353 /* Allocate core boot configuration structs */ 354 ncores = mips_cps_numcores(cl); 355 core_bootcfg = kzalloc_objs(*core_bootcfg, ncores, GFP_KERNEL); 356 if (!core_bootcfg) 357 goto err_out; 358 mips_cps_cluster_bootcfg[cl].core_config = core_bootcfg; 359 360 mips_cps_cluster_bootcfg[cl].core_power = 361 kcalloc(BITS_TO_LONGS(ncores), sizeof(unsigned long), 362 GFP_KERNEL); 363 if (!mips_cps_cluster_bootcfg[cl].core_power) 364 goto err_out; 365 366 /* Allocate VPE boot configuration structs */ 367 for (c = 0; c < ncores; c++) { 368 int v; 369 core_vpes = core_vpe_count(cl, c); 370 core_bootcfg[c].vpe_config = kzalloc_objs(*core_bootcfg[c].vpe_config, 371 core_vpes, 372 GFP_KERNEL); 373 for (v = 0; v < core_vpes; v++) 374 cpumask_set_cpu(nvpe++, &mips_cps_cluster_bootcfg[cl].cpumask); 375 if (!core_bootcfg[c].vpe_config) 376 goto err_out; 377 } 378 } 379 380 /* Mark this CPU as powered up & booted */ 381 cl = cpu_cluster(¤t_cpu_data); 382 c = cpu_core(¤t_cpu_data); 383 cluster_bootcfg = &mips_cps_cluster_bootcfg[cl]; 384 cpu_smt_set_num_threads(core_vpes, core_vpes); 385 core_bootcfg = &cluster_bootcfg->core_config[c]; 386 bitmap_set(cluster_bootcfg->core_power, cpu_core(¤t_cpu_data), 1); 387 atomic_set(&core_bootcfg->vpe_mask, 1 << cpu_vpe_id(¤t_cpu_data)); 388 389 return; 390 err_out: 391 /* Clean up allocations */ 392 if (mips_cps_cluster_bootcfg) { 393 for (cl = 0; cl < nclusters; cl++) { 394 cluster_bootcfg = &mips_cps_cluster_bootcfg[cl]; 395 ncores = mips_cps_numcores(cl); 396 for (c = 0; c < ncores; c++) { 397 core_bootcfg = &cluster_bootcfg->core_config[c]; 398 kfree(core_bootcfg->vpe_config); 399 } 400 kfree(mips_cps_cluster_bootcfg[c].core_config); 401 } 402 kfree(mips_cps_cluster_bootcfg); 403 mips_cps_cluster_bootcfg = NULL; 404 } 405 406 /* Effectively disable SMP by declaring CPUs not present */ 407 for_each_possible_cpu(c) { 408 if (c == 0) 409 continue; 410 set_cpu_present(c, false); 411 } 412 } 413 414 static void init_cluster_l2(void) 415 { 416 u32 l2_cfg, l2sm_cop, result; 417 418 while (!mips_cm_is_l2_hci_broken) { 419 l2_cfg = read_gcr_redir_l2_ram_config(); 420 421 /* If HCI is not supported, use the state machine below */ 422 if (!(l2_cfg & CM_GCR_L2_RAM_CONFIG_PRESENT)) 423 break; 424 if (!(l2_cfg & CM_GCR_L2_RAM_CONFIG_HCI_SUPPORTED)) 425 break; 426 427 /* If the HCI_DONE bit is set, we're finished */ 428 if (l2_cfg & CM_GCR_L2_RAM_CONFIG_HCI_DONE) 429 return; 430 } 431 432 l2sm_cop = read_gcr_redir_l2sm_cop(); 433 if (WARN(!(l2sm_cop & CM_GCR_L2SM_COP_PRESENT), 434 "L2 init not supported on this system yet")) 435 return; 436 437 /* Clear L2 tag registers */ 438 write_gcr_redir_l2_tag_state(0); 439 write_gcr_redir_l2_ecc(0); 440 441 /* Ensure the L2 tag writes complete before the state machine starts */ 442 mb(); 443 444 /* Wait for the L2 state machine to be idle */ 445 do { 446 l2sm_cop = read_gcr_redir_l2sm_cop(); 447 } while (l2sm_cop & CM_GCR_L2SM_COP_RUNNING); 448 449 /* Start a store tag operation */ 450 l2sm_cop = CM_GCR_L2SM_COP_TYPE_IDX_STORETAG; 451 l2sm_cop <<= __ffs(CM_GCR_L2SM_COP_TYPE); 452 l2sm_cop |= CM_GCR_L2SM_COP_CMD_START; 453 write_gcr_redir_l2sm_cop(l2sm_cop); 454 455 /* Ensure the state machine starts before we poll for completion */ 456 mb(); 457 458 /* Wait for the operation to be complete */ 459 do { 460 l2sm_cop = read_gcr_redir_l2sm_cop(); 461 result = l2sm_cop & CM_GCR_L2SM_COP_RESULT; 462 result >>= __ffs(CM_GCR_L2SM_COP_RESULT); 463 } while (!result); 464 465 WARN(result != CM_GCR_L2SM_COP_RESULT_DONE_OK, 466 "L2 state machine failed cache init with error %u\n", result); 467 } 468 469 static void boot_core(unsigned int cluster, unsigned int core, 470 unsigned int vpe_id) 471 { 472 struct cluster_boot_config *cluster_cfg; 473 u32 access, stat, seq_state; 474 unsigned int timeout, ncores; 475 476 cluster_cfg = &mips_cps_cluster_bootcfg[cluster]; 477 ncores = mips_cps_numcores(cluster); 478 479 if ((cluster != cpu_cluster(¤t_cpu_data)) && 480 bitmap_empty(cluster_cfg->core_power, ncores)) { 481 power_up_other_cluster(cluster); 482 483 mips_cm_lock_other(cluster, core, 0, 484 CM_GCR_Cx_OTHER_BLOCK_GLOBAL); 485 486 /* Ensure cluster GCRs are where we expect */ 487 write_gcr_redir_base(read_gcr_base()); 488 write_gcr_redir_cpc_base(read_gcr_cpc_base()); 489 write_gcr_redir_gic_base(read_gcr_gic_base()); 490 491 init_cluster_l2(); 492 493 /* Mirror L2 configuration */ 494 write_gcr_redir_l2_only_sync_base(read_gcr_l2_only_sync_base()); 495 write_gcr_redir_l2_pft_control(read_gcr_l2_pft_control()); 496 write_gcr_redir_l2_pft_control_b(read_gcr_l2_pft_control_b()); 497 498 /* Mirror ECC/parity setup */ 499 write_gcr_redir_err_control(read_gcr_err_control()); 500 501 /* Set BEV base */ 502 write_gcr_redir_bev_base(core_entry_reg); 503 504 mips_cm_unlock_other(); 505 } 506 507 if (cluster != cpu_cluster(¤t_cpu_data)) { 508 mips_cm_lock_other(cluster, core, 0, 509 CM_GCR_Cx_OTHER_BLOCK_GLOBAL); 510 511 /* Ensure the core can access the GCRs */ 512 access = read_gcr_redir_access(); 513 access |= BIT(core); 514 write_gcr_redir_access(access); 515 516 mips_cm_unlock_other(); 517 } else { 518 /* Ensure the core can access the GCRs */ 519 access = read_gcr_access(); 520 access |= BIT(core); 521 write_gcr_access(access); 522 } 523 524 /* Select the appropriate core */ 525 mips_cm_lock_other(cluster, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); 526 527 /* Set its reset vector */ 528 if (mips_cm_is64) 529 write_gcr_co_reset64_base(core_entry_reg); 530 else 531 write_gcr_co_reset_base(core_entry_reg); 532 533 /* Ensure its coherency is disabled */ 534 write_gcr_co_coherence(0); 535 536 /* Start it with the legacy memory map and exception base */ 537 write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB); 538 539 /* Ensure the core can access the GCRs */ 540 if (mips_cm_revision() < CM_REV_CM3) 541 set_gcr_access(1 << core); 542 else 543 set_gcr_access_cm3(1 << core); 544 545 if (mips_cpc_present()) { 546 /* Reset the core */ 547 mips_cpc_lock_other(core); 548 549 if (mips_cm_revision() >= CM_REV_CM3) { 550 /* Run only the requested VP following the reset */ 551 write_cpc_co_vp_stop(0xf); 552 write_cpc_co_vp_run(1 << vpe_id); 553 554 /* 555 * Ensure that the VP_RUN register is written before the 556 * core leaves reset. 557 */ 558 wmb(); 559 } 560 561 write_cpc_co_cmd(CPC_Cx_CMD_RESET); 562 563 timeout = 100; 564 while (true) { 565 stat = read_cpc_co_stat_conf(); 566 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; 567 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); 568 569 /* U6 == coherent execution, ie. the core is up */ 570 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6) 571 break; 572 573 /* Delay a little while before we start warning */ 574 if (timeout) { 575 timeout--; 576 mdelay(10); 577 continue; 578 } 579 580 pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n", 581 core, stat); 582 mdelay(1000); 583 } 584 585 mips_cpc_unlock_other(); 586 } else { 587 /* Take the core out of reset */ 588 write_gcr_co_reset_release(0); 589 } 590 591 mips_cm_unlock_other(); 592 593 /* The core is now powered up */ 594 bitmap_set(cluster_cfg->core_power, core, 1); 595 596 /* 597 * Restore CM_PWRUP=0 so that the CM can power down if all the cores in 598 * the cluster do (eg. if they're all removed via hotplug. 599 */ 600 if (mips_cm_revision() >= CM_REV_CM3_5) { 601 mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); 602 write_cpc_redir_pwrup_ctl(0); 603 mips_cm_unlock_other(); 604 } 605 } 606 607 static void remote_vpe_boot(void *dummy) 608 { 609 unsigned int cluster = cpu_cluster(¤t_cpu_data); 610 unsigned core = cpu_core(¤t_cpu_data); 611 struct cluster_boot_config *cluster_cfg = 612 &mips_cps_cluster_bootcfg[cluster]; 613 struct core_boot_config *core_cfg = &cluster_cfg->core_config[core]; 614 615 mips_cps_boot_vpes(core_cfg, cpu_vpe_id(¤t_cpu_data)); 616 } 617 618 static int cps_boot_secondary(int cpu, struct task_struct *idle) 619 { 620 unsigned int cluster = cpu_cluster(&cpu_data[cpu]); 621 unsigned core = cpu_core(&cpu_data[cpu]); 622 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); 623 struct cluster_boot_config *cluster_cfg = 624 &mips_cps_cluster_bootcfg[cluster]; 625 struct core_boot_config *core_cfg = &cluster_cfg->core_config[core]; 626 struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id]; 627 unsigned int remote; 628 int err; 629 630 vpe_cfg->pc = (unsigned long)&smp_bootstrap; 631 vpe_cfg->sp = __KSTK_TOS(idle); 632 vpe_cfg->gp = (unsigned long)task_thread_info(idle); 633 634 atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask); 635 636 preempt_disable(); 637 638 if (!test_bit(core, cluster_cfg->core_power)) { 639 /* Boot a VPE on a powered down core */ 640 boot_core(cluster, core, vpe_id); 641 goto out; 642 } 643 644 if (cpu_has_vp) { 645 mips_cm_lock_other(cluster, core, vpe_id, 646 CM_GCR_Cx_OTHER_BLOCK_LOCAL); 647 if (mips_cm_is64) 648 write_gcr_co_reset64_base(core_entry_reg); 649 else 650 write_gcr_co_reset_base(core_entry_reg); 651 mips_cm_unlock_other(); 652 } 653 654 if (!cpus_are_siblings(cpu, smp_processor_id())) { 655 /* Boot a VPE on another powered up core */ 656 for (remote = 0; remote < NR_CPUS; remote++) { 657 if (!cpus_are_siblings(cpu, remote)) 658 continue; 659 if (cpu_online(remote)) 660 break; 661 } 662 if (remote >= NR_CPUS) { 663 pr_crit("No online CPU in core %u to start CPU%d\n", 664 core, cpu); 665 goto out; 666 } 667 668 err = smp_call_function_single(remote, remote_vpe_boot, 669 NULL, 1); 670 if (err) 671 panic("Failed to call remote CPU\n"); 672 goto out; 673 } 674 675 BUG_ON(!cpu_has_mipsmt && !cpu_has_vp); 676 677 /* Boot a VPE on this core */ 678 mips_cps_boot_vpes(core_cfg, vpe_id); 679 out: 680 preempt_enable(); 681 return 0; 682 } 683 684 static void cps_init_secondary(void) 685 { 686 int core = cpu_core(¤t_cpu_data); 687 688 /* Disable MT - we only want to run 1 TC per VPE */ 689 if (cpu_has_mipsmt) 690 dmt(); 691 692 if (mips_cm_revision() >= CM_REV_CM3) { 693 unsigned int ident = read_gic_vl_ident(); 694 695 /* 696 * Ensure that our calculation of the VP ID matches up with 697 * what the GIC reports, otherwise we'll have configured 698 * interrupts incorrectly. 699 */ 700 BUG_ON(ident != mips_cm_vp_id(smp_processor_id())); 701 } 702 703 if (core > 0 && !read_gcr_cl_coherence()) 704 pr_warn("Core %u is not in coherent domain\n", core); 705 706 if (cpu_has_veic) 707 clear_c0_status(ST0_IM); 708 else 709 change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | 710 STATUSF_IP4 | STATUSF_IP5 | 711 STATUSF_IP6 | STATUSF_IP7); 712 } 713 714 static void cps_smp_finish(void) 715 { 716 write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ)); 717 718 #ifdef CONFIG_MIPS_MT_FPAFF 719 /* If we have an FPU, enroll ourselves in the FPU-full mask */ 720 if (cpu_has_fpu) 721 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask); 722 #endif /* CONFIG_MIPS_MT_FPAFF */ 723 724 local_irq_enable(); 725 } 726 727 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC_CORE) 728 729 enum cpu_death { 730 CPU_DEATH_HALT, 731 CPU_DEATH_POWER, 732 }; 733 734 static void cps_shutdown_this_cpu(enum cpu_death death) 735 { 736 unsigned int cpu, core, vpe_id; 737 738 cpu = smp_processor_id(); 739 core = cpu_core(&cpu_data[cpu]); 740 741 if (death == CPU_DEATH_HALT) { 742 vpe_id = cpu_vpe_id(&cpu_data[cpu]); 743 744 pr_debug("Halting core %d VP%d\n", core, vpe_id); 745 if (cpu_has_mipsmt) { 746 /* Halt this TC */ 747 write_c0_tchalt(TCHALT_H); 748 instruction_hazard(); 749 } else if (cpu_has_vp) { 750 write_cpc_cl_vp_stop(1 << vpe_id); 751 752 /* Ensure that the VP_STOP register is written */ 753 wmb(); 754 } 755 } else { 756 if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) { 757 pr_debug("Gating power to core %d\n", core); 758 /* Power down the core */ 759 cps_pm_enter_state(CPS_PM_POWER_GATED); 760 } 761 } 762 } 763 764 #ifdef CONFIG_KEXEC_CORE 765 766 static void cps_kexec_nonboot_cpu(void) 767 { 768 if (cpu_has_mipsmt || cpu_has_vp) 769 cps_shutdown_this_cpu(CPU_DEATH_HALT); 770 else 771 cps_shutdown_this_cpu(CPU_DEATH_POWER); 772 } 773 774 #endif /* CONFIG_KEXEC_CORE */ 775 776 #endif /* CONFIG_HOTPLUG_CPU || CONFIG_KEXEC_CORE */ 777 778 #ifdef CONFIG_HOTPLUG_CPU 779 780 static int cps_cpu_disable(void) 781 { 782 unsigned cpu = smp_processor_id(); 783 struct cluster_boot_config *cluster_cfg; 784 struct core_boot_config *core_cfg; 785 786 if (!cps_pm_support_state(CPS_PM_POWER_GATED)) 787 return -EINVAL; 788 789 cluster_cfg = &mips_cps_cluster_bootcfg[cpu_cluster(¤t_cpu_data)]; 790 core_cfg = &cluster_cfg->core_config[cpu_core(¤t_cpu_data)]; 791 atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask); 792 smp_mb__after_atomic(); 793 set_cpu_online(cpu, false); 794 calculate_cpu_foreign_map(); 795 irq_migrate_all_off_this_cpu(); 796 797 return 0; 798 } 799 800 static unsigned cpu_death_sibling; 801 static enum cpu_death cpu_death; 802 803 void play_dead(void) 804 { 805 unsigned int cpu; 806 807 local_irq_disable(); 808 idle_task_exit(); 809 cpu = smp_processor_id(); 810 cpu_death = CPU_DEATH_POWER; 811 812 pr_debug("CPU%d going offline\n", cpu); 813 814 if (cpu_has_mipsmt || cpu_has_vp) { 815 /* Look for another online VPE within the core */ 816 for_each_online_cpu(cpu_death_sibling) { 817 if (!cpus_are_siblings(cpu, cpu_death_sibling)) 818 continue; 819 820 /* 821 * There is an online VPE within the core. Just halt 822 * this TC and leave the core alone. 823 */ 824 cpu_death = CPU_DEATH_HALT; 825 break; 826 } 827 } 828 829 cpuhp_ap_report_dead(); 830 831 cps_shutdown_this_cpu(cpu_death); 832 833 /* This should never be reached */ 834 panic("Failed to offline CPU %u", cpu); 835 } 836 837 static void wait_for_sibling_halt(void *ptr_cpu) 838 { 839 unsigned cpu = (unsigned long)ptr_cpu; 840 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); 841 unsigned halted; 842 unsigned long flags; 843 844 do { 845 local_irq_save(flags); 846 settc(vpe_id); 847 halted = read_tc_c0_tchalt(); 848 local_irq_restore(flags); 849 } while (!(halted & TCHALT_H)); 850 } 851 852 static void cps_cpu_die(unsigned int cpu) { } 853 854 static void cps_cleanup_dead_cpu(unsigned cpu) 855 { 856 unsigned int cluster = cpu_cluster(&cpu_data[cpu]); 857 unsigned core = cpu_core(&cpu_data[cpu]); 858 unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]); 859 ktime_t fail_time; 860 unsigned stat; 861 int err; 862 struct cluster_boot_config *cluster_cfg; 863 864 cluster_cfg = &mips_cps_cluster_bootcfg[cluster]; 865 866 /* 867 * Now wait for the CPU to actually offline. Without doing this that 868 * offlining may race with one or more of: 869 * 870 * - Onlining the CPU again. 871 * - Powering down the core if another VPE within it is offlined. 872 * - A sibling VPE entering a non-coherent state. 873 * 874 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing 875 * with which we could race, so do nothing. 876 */ 877 if (cpu_death == CPU_DEATH_POWER) { 878 /* 879 * Wait for the core to enter a powered down or clock gated 880 * state, the latter happening when a JTAG probe is connected 881 * in which case the CPC will refuse to power down the core. 882 */ 883 fail_time = ktime_add_ms(ktime_get(), 2000); 884 do { 885 mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); 886 mips_cpc_lock_other(core); 887 stat = read_cpc_co_stat_conf(); 888 stat &= CPC_Cx_STAT_CONF_SEQSTATE; 889 stat >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); 890 mips_cpc_unlock_other(); 891 mips_cm_unlock_other(); 892 893 if (stat == CPC_Cx_STAT_CONF_SEQSTATE_D0 || 894 stat == CPC_Cx_STAT_CONF_SEQSTATE_D2 || 895 stat == CPC_Cx_STAT_CONF_SEQSTATE_U2) 896 break; 897 898 /* 899 * The core ought to have powered down, but didn't & 900 * now we don't really know what state it's in. It's 901 * likely that its _pwr_up pin has been wired to logic 902 * 1 & it powered back up as soon as we powered it 903 * down... 904 * 905 * The best we can do is warn the user & continue in 906 * the hope that the core is doing nothing harmful & 907 * might behave properly if we online it later. 908 */ 909 if (WARN(ktime_after(ktime_get(), fail_time), 910 "CPU%u hasn't powered down, seq. state %u\n", 911 cpu, stat)) 912 break; 913 } while (1); 914 915 /* Indicate the core is powered off */ 916 bitmap_clear(cluster_cfg->core_power, core, 1); 917 } else if (cpu_has_mipsmt) { 918 /* 919 * Have a CPU with access to the offlined CPUs registers wait 920 * for its TC to halt. 921 */ 922 err = smp_call_function_single(cpu_death_sibling, 923 wait_for_sibling_halt, 924 (void *)(unsigned long)cpu, 1); 925 if (err) 926 panic("Failed to call remote sibling CPU\n"); 927 } else if (cpu_has_vp) { 928 do { 929 mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL); 930 stat = read_cpc_co_vp_running(); 931 mips_cm_unlock_other(); 932 } while (stat & (1 << vpe_id)); 933 } 934 } 935 936 #endif /* CONFIG_HOTPLUG_CPU */ 937 938 static const struct plat_smp_ops cps_smp_ops = { 939 .smp_setup = cps_smp_setup, 940 .prepare_cpus = cps_prepare_cpus, 941 .boot_secondary = cps_boot_secondary, 942 .init_secondary = cps_init_secondary, 943 .smp_finish = cps_smp_finish, 944 .send_ipi_single = mips_smp_send_ipi_single, 945 .send_ipi_mask = mips_smp_send_ipi_mask, 946 #ifdef CONFIG_HOTPLUG_CPU 947 .cpu_disable = cps_cpu_disable, 948 .cpu_die = cps_cpu_die, 949 .cleanup_dead_cpu = cps_cleanup_dead_cpu, 950 #endif 951 #ifdef CONFIG_KEXEC_CORE 952 .kexec_nonboot_cpu = cps_kexec_nonboot_cpu, 953 #endif 954 }; 955 956 bool mips_cps_smp_in_use(void) 957 { 958 extern const struct plat_smp_ops *mp_ops; 959 return mp_ops == &cps_smp_ops; 960 } 961 962 int register_cps_smp_ops(void) 963 { 964 if (!mips_cm_present()) { 965 pr_warn("MIPS CPS SMP unable to proceed without a CM\n"); 966 return -ENODEV; 967 } 968 969 /* check we have a GIC - we need one for IPIs */ 970 if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX)) { 971 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n"); 972 return -ENODEV; 973 } 974 975 register_smp_ops(&cps_smp_ops); 976 return 0; 977 } 978