1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2018 Intel Corporation
7 //
8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10 // Rander Wang <rander.wang@intel.com>
11 // Keyon Jie <yang.jie@linux.intel.com>
12 //
13
14 /*
15 * Hardware interface for audio DSP on Cannonlake.
16 */
17
18 #include <sound/sof/ext_manifest4.h>
19 #include <sound/sof/ipc4/header.h>
20 #include <trace/events/sof_intel.h>
21 #include "../ipc4-priv.h"
22 #include "../ops.h"
23 #include "hda.h"
24 #include "hda-ipc.h"
25 #include "../sof-audio.h"
26
27 static const struct snd_sof_debugfs_map cnl_dsp_debugfs[] = {
28 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
29 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
30 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
31 };
32
33 static void cnl_ipc_host_done(struct snd_sof_dev *sdev);
34 static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev);
35
cnl_ipc4_irq_thread(int irq,void * context)36 irqreturn_t cnl_ipc4_irq_thread(int irq, void *context)
37 {
38 struct sof_ipc4_msg notification_data = {{ 0 }};
39 struct snd_sof_dev *sdev = context;
40 bool ack_received = false;
41 bool ipc_irq = false;
42 u32 hipcida, hipctdr;
43
44 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
45 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
46 if (hipcida & CNL_DSP_REG_HIPCIDA_DONE) {
47 /* DSP received the message */
48 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
49 CNL_DSP_REG_HIPCCTL,
50 CNL_DSP_REG_HIPCCTL_DONE, 0);
51 cnl_ipc_dsp_done(sdev);
52
53 ipc_irq = true;
54 ack_received = true;
55 }
56
57 if (hipctdr & CNL_DSP_REG_HIPCTDR_BUSY) {
58 /* Message from DSP (reply or notification) */
59 u32 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
60 CNL_DSP_REG_HIPCTDD);
61 u32 primary = hipctdr & CNL_DSP_REG_HIPCTDR_MSG_MASK;
62 u32 extension = hipctdd & CNL_DSP_REG_HIPCTDD_MSG_MASK;
63
64 if (primary & SOF_IPC4_MSG_DIR_MASK) {
65 /* Reply received */
66 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) {
67 struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data;
68
69 data->primary = primary;
70 data->extension = extension;
71
72 guard(spinlock_irq)(&sdev->ipc_lock);
73 snd_sof_ipc_get_reply(sdev);
74 cnl_ipc_host_done(sdev);
75 snd_sof_ipc_reply(sdev, data->primary);
76 } else {
77 dev_dbg_ratelimited(sdev->dev,
78 "IPC reply before FW_READY: %#x|%#x\n",
79 primary, extension);
80 }
81 } else {
82 /* Notification received */
83 notification_data.primary = primary;
84 notification_data.extension = extension;
85
86 sdev->ipc->msg.rx_data = ¬ification_data;
87 snd_sof_ipc_msgs_rx(sdev);
88 sdev->ipc->msg.rx_data = NULL;
89
90 /* Let DSP know that we have finished processing the message */
91 cnl_ipc_host_done(sdev);
92 }
93
94 ipc_irq = true;
95 }
96
97 if (!ipc_irq)
98 /* This interrupt is not shared so no need to return IRQ_NONE. */
99 dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n");
100
101 if (ack_received) {
102 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
103
104 if (hdev->delayed_ipc_tx_msg)
105 cnl_ipc4_send_msg(sdev, hdev->delayed_ipc_tx_msg);
106 }
107
108 return IRQ_HANDLED;
109 }
110 EXPORT_SYMBOL_NS(cnl_ipc4_irq_thread, "SND_SOC_SOF_INTEL_CNL");
111
cnl_ipc_irq_thread(int irq,void * context)112 irqreturn_t cnl_ipc_irq_thread(int irq, void *context)
113 {
114 struct snd_sof_dev *sdev = context;
115 u32 hipci;
116 u32 hipcida;
117 u32 hipctdr;
118 u32 hipctdd;
119 u32 msg;
120 u32 msg_ext;
121 bool ipc_irq = false;
122
123 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
124 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
125 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDD);
126 hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR);
127
128 /* reply message from DSP */
129 if (hipcida & CNL_DSP_REG_HIPCIDA_DONE) {
130 msg_ext = hipci & CNL_DSP_REG_HIPCIDR_MSG_MASK;
131 msg = hipcida & CNL_DSP_REG_HIPCIDA_MSG_MASK;
132
133 trace_sof_intel_ipc_firmware_response(sdev, msg, msg_ext);
134
135 /* mask Done interrupt */
136 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
137 CNL_DSP_REG_HIPCCTL,
138 CNL_DSP_REG_HIPCCTL_DONE, 0);
139
140 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) {
141 /* handle immediate reply from DSP core */
142 guard(spinlock_irq)(&sdev->ipc_lock);
143 hda_dsp_ipc_get_reply(sdev);
144 snd_sof_ipc_reply(sdev, msg);
145 cnl_ipc_dsp_done(sdev);
146 } else {
147 dev_dbg_ratelimited(sdev->dev, "IPC reply before FW_READY: %#x\n",
148 msg);
149 }
150
151 ipc_irq = true;
152 }
153
154 /* new message from DSP */
155 if (hipctdr & CNL_DSP_REG_HIPCTDR_BUSY) {
156 msg = hipctdr & CNL_DSP_REG_HIPCTDR_MSG_MASK;
157 msg_ext = hipctdd & CNL_DSP_REG_HIPCTDD_MSG_MASK;
158
159 trace_sof_intel_ipc_firmware_initiated(sdev, msg, msg_ext);
160
161 /* handle messages from DSP */
162 if ((hipctdr & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
163 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
164 bool non_recoverable = true;
165
166 /*
167 * This is a PANIC message!
168 *
169 * If it is arriving during firmware boot and it is not
170 * the last boot attempt then change the non_recoverable
171 * to false as the DSP might be able to boot in the next
172 * iteration(s)
173 */
174 if (sdev->fw_state == SOF_FW_BOOT_IN_PROGRESS &&
175 hda->boot_iteration < HDA_FW_BOOT_ATTEMPTS)
176 non_recoverable = false;
177
178 snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext),
179 non_recoverable);
180 } else {
181 snd_sof_ipc_msgs_rx(sdev);
182 }
183
184 cnl_ipc_host_done(sdev);
185
186 ipc_irq = true;
187 }
188
189 if (!ipc_irq) {
190 /*
191 * This interrupt is not shared so no need to return IRQ_NONE.
192 */
193 dev_dbg_ratelimited(sdev->dev,
194 "nothing to do in IPC IRQ thread\n");
195 }
196
197 return IRQ_HANDLED;
198 }
199 EXPORT_SYMBOL_NS(cnl_ipc_irq_thread, "SND_SOC_SOF_INTEL_CNL");
200
cnl_ipc_host_done(struct snd_sof_dev * sdev)201 static void cnl_ipc_host_done(struct snd_sof_dev *sdev)
202 {
203 /*
204 * clear busy interrupt to tell dsp controller this
205 * interrupt has been accepted, not trigger it again
206 */
207 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
208 CNL_DSP_REG_HIPCTDR,
209 CNL_DSP_REG_HIPCTDR_BUSY,
210 CNL_DSP_REG_HIPCTDR_BUSY);
211 /*
212 * set done bit to ack dsp the msg has been
213 * processed and send reply msg to dsp
214 */
215 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
216 CNL_DSP_REG_HIPCTDA,
217 CNL_DSP_REG_HIPCTDA_DONE,
218 CNL_DSP_REG_HIPCTDA_DONE);
219 }
220
cnl_ipc_dsp_done(struct snd_sof_dev * sdev)221 static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev)
222 {
223 /*
224 * set DONE bit - tell DSP we have received the reply msg
225 * from DSP, and processed it, don't send more reply to host
226 */
227 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
228 CNL_DSP_REG_HIPCIDA,
229 CNL_DSP_REG_HIPCIDA_DONE,
230 CNL_DSP_REG_HIPCIDA_DONE);
231
232 /* unmask Done interrupt */
233 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
234 CNL_DSP_REG_HIPCCTL,
235 CNL_DSP_REG_HIPCCTL_DONE,
236 CNL_DSP_REG_HIPCCTL_DONE);
237 }
238
cnl_compact_ipc_compress(struct snd_sof_ipc_msg * msg,u32 * dr,u32 * dd)239 static bool cnl_compact_ipc_compress(struct snd_sof_ipc_msg *msg,
240 u32 *dr, u32 *dd)
241 {
242 struct sof_ipc_pm_gate *pm_gate = msg->msg_data;
243
244 if (pm_gate->hdr.cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE)) {
245 /* send the compact message via the primary register */
246 *dr = HDA_IPC_MSG_COMPACT | HDA_IPC_PM_GATE;
247
248 /* send payload via the extended data register */
249 *dd = pm_gate->flags;
250
251 return true;
252 }
253
254 return false;
255 }
256
cnl_ipc4_send_msg(struct snd_sof_dev * sdev,struct snd_sof_ipc_msg * msg)257 int cnl_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
258 {
259 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
260 struct sof_ipc4_msg *msg_data = msg->msg_data;
261
262 if (hda_ipc4_tx_is_busy(sdev)) {
263 hdev->delayed_ipc_tx_msg = msg;
264 return 0;
265 }
266
267 hdev->delayed_ipc_tx_msg = NULL;
268
269 /* send the message via mailbox */
270 if (msg_data->data_size)
271 sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr,
272 msg_data->data_size);
273
274 snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDD, msg_data->extension);
275 snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
276 msg_data->primary | CNL_DSP_REG_HIPCIDR_BUSY);
277
278 hda_dsp_ipc4_schedule_d0i3_work(hdev, msg);
279
280 return 0;
281 }
282 EXPORT_SYMBOL_NS(cnl_ipc4_send_msg, "SND_SOC_SOF_INTEL_CNL");
283
cnl_ipc_send_msg(struct snd_sof_dev * sdev,struct snd_sof_ipc_msg * msg)284 int cnl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
285 {
286 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
287 struct sof_ipc_cmd_hdr *hdr;
288 u32 dr = 0;
289 u32 dd = 0;
290
291 /*
292 * Currently the only compact IPC supported is the PM_GATE
293 * IPC which is used for transitioning the DSP between the
294 * D0I0 and D0I3 states. And these are sent only during the
295 * set_power_state() op. Therefore, there will never be a case
296 * that a compact IPC results in the DSP exiting D0I3 without
297 * the host and FW being in sync.
298 */
299 if (cnl_compact_ipc_compress(msg, &dr, &dd)) {
300 /* send the message via IPC registers */
301 snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDD,
302 dd);
303 snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
304 CNL_DSP_REG_HIPCIDR_BUSY | dr);
305 return 0;
306 }
307
308 /* send the message via mailbox */
309 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
310 msg->msg_size);
311 snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
312 CNL_DSP_REG_HIPCIDR_BUSY);
313
314 hdr = msg->msg_data;
315
316 /*
317 * Use mod_delayed_work() to schedule the delayed work
318 * to avoid scheduling multiple workqueue items when
319 * IPCs are sent at a high-rate. mod_delayed_work()
320 * modifies the timer if the work is pending.
321 * Also, a new delayed work should not be queued after the
322 * CTX_SAVE IPC, which is sent before the DSP enters D3.
323 */
324 if (hdr->cmd != (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CTX_SAVE))
325 mod_delayed_work(system_dfl_wq, &hdev->d0i3_work,
326 msecs_to_jiffies(SOF_HDA_D0I3_WORK_DELAY_MS));
327
328 return 0;
329 }
330 EXPORT_SYMBOL_NS(cnl_ipc_send_msg, "SND_SOC_SOF_INTEL_CNL");
331
cnl_ipc_dump(struct snd_sof_dev * sdev)332 void cnl_ipc_dump(struct snd_sof_dev *sdev)
333 {
334 u32 hipcctl;
335 u32 hipcida;
336 u32 hipctdr;
337
338 hda_ipc_irq_dump(sdev);
339
340 /* read IPC status */
341 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
342 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL);
343 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
344
345 /* dump the IPC regs */
346 /* TODO: parse the raw msg */
347 dev_err(sdev->dev,
348 "error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
349 hipcida, hipctdr, hipcctl);
350 }
351 EXPORT_SYMBOL_NS(cnl_ipc_dump, "SND_SOC_SOF_INTEL_CNL");
352
cnl_ipc4_dump(struct snd_sof_dev * sdev)353 void cnl_ipc4_dump(struct snd_sof_dev *sdev)
354 {
355 u32 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl;
356
357 hda_ipc_irq_dump(sdev);
358
359 hipcidr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR);
360 hipcidd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDD);
361 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
362 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
363 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDD);
364 hipctda = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDA);
365 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL);
366
367 /* dump the IPC regs */
368 /* TODO: parse the raw msg */
369 dev_err(sdev->dev,
370 "Host IPC initiator: %#x|%#x|%#x, target: %#x|%#x|%#x, ctl: %#x\n",
371 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl);
372 }
373 EXPORT_SYMBOL_NS(cnl_ipc4_dump, "SND_SOC_SOF_INTEL_CNL");
374
375 /* cannonlake ops */
376 struct snd_sof_dsp_ops sof_cnl_ops;
377 EXPORT_SYMBOL_NS(sof_cnl_ops, "SND_SOC_SOF_INTEL_CNL");
378
sof_cnl_ops_init(struct snd_sof_dev * sdev)379 int sof_cnl_ops_init(struct snd_sof_dev *sdev)
380 {
381 /* common defaults */
382 memcpy(&sof_cnl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
383
384 /* probe/remove/shutdown */
385 sof_cnl_ops.shutdown = hda_dsp_shutdown;
386
387 /* ipc */
388 if (sdev->pdata->ipc_type == SOF_IPC_TYPE_3) {
389 /* doorbell */
390 sof_cnl_ops.irq_thread = cnl_ipc_irq_thread;
391
392 /* ipc */
393 sof_cnl_ops.send_msg = cnl_ipc_send_msg;
394
395 /* debug */
396 sof_cnl_ops.ipc_dump = cnl_ipc_dump;
397
398 sof_cnl_ops.set_power_state = hda_dsp_set_power_state_ipc3;
399 }
400
401 if (sdev->pdata->ipc_type == SOF_IPC_TYPE_4) {
402 struct sof_ipc4_fw_data *ipc4_data;
403
404 sdev->private = kzalloc_obj(*ipc4_data);
405 if (!sdev->private)
406 return -ENOMEM;
407
408 ipc4_data = sdev->private;
409 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
410
411 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_1_8;
412
413 /* External library loading support */
414 ipc4_data->load_library = hda_dsp_ipc4_load_library;
415
416 /* doorbell */
417 sof_cnl_ops.irq_thread = cnl_ipc4_irq_thread;
418
419 /* ipc */
420 sof_cnl_ops.send_msg = cnl_ipc4_send_msg;
421
422 /* debug */
423 sof_cnl_ops.ipc_dump = cnl_ipc4_dump;
424
425 sof_cnl_ops.set_power_state = hda_dsp_set_power_state_ipc4;
426 }
427
428 /* set DAI driver ops */
429 hda_set_dai_drv_ops(sdev, &sof_cnl_ops);
430
431 /* debug */
432 sof_cnl_ops.debug_map = cnl_dsp_debugfs;
433 sof_cnl_ops.debug_map_count = ARRAY_SIZE(cnl_dsp_debugfs);
434
435 /* pre/post fw run */
436 sof_cnl_ops.post_fw_run = hda_dsp_post_fw_run;
437
438 /* firmware run */
439 sof_cnl_ops.run = hda_dsp_cl_boot_firmware;
440
441 /* dsp core get/put */
442 sof_cnl_ops.core_get = hda_dsp_core_get;
443
444 return 0;
445 };
446 EXPORT_SYMBOL_NS(sof_cnl_ops_init, "SND_SOC_SOF_INTEL_CNL");
447
448 const struct sof_intel_dsp_desc cnl_chip_info = {
449 /* Cannonlake */
450 .cores_num = 4,
451 .init_core_mask = 1,
452 .host_managed_cores_mask = GENMASK(3, 0),
453 .ipc_req = CNL_DSP_REG_HIPCIDR,
454 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
455 .ipc_ack = CNL_DSP_REG_HIPCIDA,
456 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
457 .ipc_ctl = CNL_DSP_REG_HIPCCTL,
458 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
459 .rom_init_timeout = 300,
460 .ssp_count = CNL_SSP_COUNT,
461 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
462 .sdw_shim_base = SDW_SHIM_BASE,
463 .sdw_alh_base = SDW_ALH_BASE,
464 .d0i3_offset = SOF_HDA_VS_D0I3C,
465 .read_sdw_lcount = hda_sdw_check_lcount_common,
466 .enable_sdw_irq = hda_common_enable_sdw_irq,
467 .check_sdw_irq = hda_common_check_sdw_irq,
468 .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
469 .sdw_process_wakeen = hda_sdw_process_wakeen_common,
470 .check_ipc_irq = hda_dsp_check_ipc_irq,
471 .cl_init = cl_dsp_init,
472 .power_down_dsp = hda_power_down_dsp,
473 .disable_interrupts = hda_dsp_disable_interrupts,
474 .hw_ip_version = SOF_INTEL_CAVS_1_8,
475 .platform = "cnl",
476 };
477
478 /*
479 * JasperLake is technically derived from IceLake, and should be in
480 * described in icl.c. However since JasperLake was designed with
481 * two cores, it cannot support the IceLake-specific power-up sequences
482 * which rely on core3. To simplify, JasperLake uses the CannonLake ops and
483 * is described in cnl.c
484 */
485 const struct sof_intel_dsp_desc jsl_chip_info = {
486 /* Jasperlake */
487 .cores_num = 2,
488 .init_core_mask = 1,
489 .host_managed_cores_mask = GENMASK(1, 0),
490 .ipc_req = CNL_DSP_REG_HIPCIDR,
491 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
492 .ipc_ack = CNL_DSP_REG_HIPCIDA,
493 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
494 .ipc_ctl = CNL_DSP_REG_HIPCCTL,
495 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
496 .rom_init_timeout = 300,
497 .ssp_count = ICL_SSP_COUNT,
498 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
499 .sdw_shim_base = SDW_SHIM_BASE,
500 .sdw_alh_base = SDW_ALH_BASE,
501 .d0i3_offset = SOF_HDA_VS_D0I3C,
502 .read_sdw_lcount = hda_sdw_check_lcount_common,
503 .enable_sdw_irq = hda_common_enable_sdw_irq,
504 .check_sdw_irq = hda_common_check_sdw_irq,
505 .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
506 .sdw_process_wakeen = hda_sdw_process_wakeen_common,
507 .check_ipc_irq = hda_dsp_check_ipc_irq,
508 .cl_init = cl_dsp_init,
509 .power_down_dsp = hda_power_down_dsp,
510 .disable_interrupts = hda_dsp_disable_interrupts,
511 .hw_ip_version = SOF_INTEL_CAVS_2_0,
512 .platform = "jsl",
513 };
514 EXPORT_SYMBOL_NS(jsl_chip_info, "SND_SOC_SOF_INTEL_CNL");
515