1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 */
5
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/types.h>
9 #include <linux/fs.h>
10 #include <linux/hex.h>
11 #include <linux/uaccess.h>
12 #include <linux/string.h>
13 #include <linux/pci.h>
14 #include <linux/io.h>
15 #include <linux/delay.h>
16 #include <linux/mutex.h>
17 #include <linux/if_ether.h>
18 #include <linux/ctype.h>
19 #include <linux/dmi.h>
20 #include <linux/of.h>
21
22 #define PHUB_STATUS 0x00 /* Status Register offset */
23 #define PHUB_CONTROL 0x04 /* Control Register offset */
24 #define PHUB_TIMEOUT 0x05 /* Time out value for Status Register */
25 #define PCH_PHUB_ROM_WRITE_ENABLE 0x01 /* Enabling for writing ROM */
26 #define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */
27 #define PCH_PHUB_MAC_START_ADDR_EG20T 0x14 /* MAC data area start address
28 offset */
29 #define PCH_PHUB_MAC_START_ADDR_ML7223 0x20C /* MAC data area start address
30 offset */
31 #define PCH_PHUB_ROM_START_ADDR_EG20T 0x80 /* ROM data area start address offset
32 (Intel EG20T PCH)*/
33 #define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address
34 offset(LAPIS Semicon ML7213)
35 */
36 #define PCH_PHUB_ROM_START_ADDR_ML7223 0x400 /* ROM data area start address
37 offset(LAPIS Semicon ML7223)
38 */
39
40 /* MAX number of INT_REDUCE_CONTROL registers */
41 #define MAX_NUM_INT_REDUCE_CONTROL_REG 128
42 #define PCI_DEVICE_ID_PCH1_PHUB 0x8801
43 #define PCH_MINOR_NOS 1
44 #define CLKCFG_CAN_50MHZ 0x12000000
45 #define CLKCFG_CANCLK_MASK 0xFF000000
46 #define CLKCFG_UART_MASK 0xFFFFFF
47
48 /* CM-iTC */
49 #define CLKCFG_UART_48MHZ (1 << 16)
50 #define CLKCFG_UART_25MHZ (2 << 16)
51 #define CLKCFG_BAUDDIV (2 << 20)
52 #define CLKCFG_PLL2VCO (8 << 9)
53 #define CLKCFG_UARTCLKSEL (1 << 18)
54
55 /* Macros for ML7213 */
56 #define PCI_DEVICE_ID_ROHM_ML7213_PHUB 0x801A
57
58 /* Macros for ML7223 */
59 #define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */
60 #define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */
61
62 /* Macros for ML7831 */
63 #define PCI_DEVICE_ID_ROHM_ML7831_PHUB 0x8801
64
65 /* SROM ACCESS Macro */
66 #define PCH_WORD_ADDR_MASK (~((1 << 2) - 1))
67
68 /* Registers address offset */
69 #define PCH_PHUB_ID_REG 0x0000
70 #define PCH_PHUB_QUEUE_PRI_VAL_REG 0x0004
71 #define PCH_PHUB_RC_QUEUE_MAXSIZE_REG 0x0008
72 #define PCH_PHUB_BRI_QUEUE_MAXSIZE_REG 0x000C
73 #define PCH_PHUB_COMP_RESP_TIMEOUT_REG 0x0010
74 #define PCH_PHUB_BUS_SLAVE_CONTROL_REG 0x0014
75 #define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG 0x0018
76 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG0 0x0020
77 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG1 0x0024
78 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG2 0x0028
79 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG3 0x002C
80 #define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE 0x0040
81 #define CLKCFG_REG_OFFSET 0x500
82 #define FUNCSEL_REG_OFFSET 0x508
83
84 #define PCH_PHUB_OROM_SIZE 15360
85
86 /**
87 * struct pch_phub_reg - PHUB register structure
88 * @phub_id_reg: PHUB_ID register val
89 * @q_pri_val_reg: QUEUE_PRI_VAL register val
90 * @rc_q_maxsize_reg: RC_QUEUE_MAXSIZE register val
91 * @bri_q_maxsize_reg: BRI_QUEUE_MAXSIZE register val
92 * @comp_resp_timeout_reg: COMP_RESP_TIMEOUT register val
93 * @bus_slave_control_reg: BUS_SLAVE_CONTROL_REG register val
94 * @deadlock_avoid_type_reg: DEADLOCK_AVOID_TYPE register val
95 * @intpin_reg_wpermit_reg0: INTPIN_REG_WPERMIT register 0 val
96 * @intpin_reg_wpermit_reg1: INTPIN_REG_WPERMIT register 1 val
97 * @intpin_reg_wpermit_reg2: INTPIN_REG_WPERMIT register 2 val
98 * @intpin_reg_wpermit_reg3: INTPIN_REG_WPERMIT register 3 val
99 * @int_reduce_control_reg: INT_REDUCE_CONTROL registers val
100 * @clkcfg_reg: CLK CFG register val
101 * @funcsel_reg: Function select register value
102 * @pch_phub_base_address: Register base address
103 * @pch_phub_extrom_base_address: external rom base address
104 * @pch_mac_start_address: MAC address area start address
105 * @pch_opt_rom_start_address: Option ROM start address
106 * @ioh_type: Save IOH type
107 * @pdev: pointer to pci device struct
108 */
109 struct pch_phub_reg {
110 u32 phub_id_reg;
111 u32 q_pri_val_reg;
112 u32 rc_q_maxsize_reg;
113 u32 bri_q_maxsize_reg;
114 u32 comp_resp_timeout_reg;
115 u32 bus_slave_control_reg;
116 u32 deadlock_avoid_type_reg;
117 u32 intpin_reg_wpermit_reg0;
118 u32 intpin_reg_wpermit_reg1;
119 u32 intpin_reg_wpermit_reg2;
120 u32 intpin_reg_wpermit_reg3;
121 u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG];
122 u32 clkcfg_reg;
123 u32 funcsel_reg;
124 void __iomem *pch_phub_base_address;
125 void __iomem *pch_phub_extrom_base_address;
126 u32 pch_mac_start_address;
127 u32 pch_opt_rom_start_address;
128 int ioh_type;
129 struct pci_dev *pdev;
130 };
131
132 /* SROM SPEC for MAC address assignment offset */
133 static const int pch_phub_mac_offset[ETH_ALEN] = {0x3, 0x2, 0x1, 0x0, 0xb, 0xa};
134
135 static DEFINE_MUTEX(pch_phub_mutex);
136
137 /**
138 * pch_phub_read_modify_write_reg() - Reading modifying and writing register
139 * @chip: Pointer to the PHUB register structure
140 * @reg_addr_offset: Register offset address value.
141 * @data: Writing value.
142 * @mask: Mask value.
143 */
pch_phub_read_modify_write_reg(struct pch_phub_reg * chip,unsigned int reg_addr_offset,unsigned int data,unsigned int mask)144 static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip,
145 unsigned int reg_addr_offset,
146 unsigned int data, unsigned int mask)
147 {
148 void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset;
149 iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr);
150 }
151
152 /* pch_phub_save_reg_conf - saves register configuration */
pch_phub_save_reg_conf(struct pci_dev * pdev)153 static void __maybe_unused pch_phub_save_reg_conf(struct pci_dev *pdev)
154 {
155 unsigned int i;
156 struct pch_phub_reg *chip = pci_get_drvdata(pdev);
157
158 void __iomem *p = chip->pch_phub_base_address;
159
160 chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG);
161 chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG);
162 chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
163 chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
164 chip->comp_resp_timeout_reg =
165 ioread32(p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
166 chip->bus_slave_control_reg =
167 ioread32(p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
168 chip->deadlock_avoid_type_reg =
169 ioread32(p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
170 chip->intpin_reg_wpermit_reg0 =
171 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
172 chip->intpin_reg_wpermit_reg1 =
173 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
174 chip->intpin_reg_wpermit_reg2 =
175 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
176 chip->intpin_reg_wpermit_reg3 =
177 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
178 dev_dbg(&pdev->dev, "%s : "
179 "chip->phub_id_reg=%x, "
180 "chip->q_pri_val_reg=%x, "
181 "chip->rc_q_maxsize_reg=%x, "
182 "chip->bri_q_maxsize_reg=%x, "
183 "chip->comp_resp_timeout_reg=%x, "
184 "chip->bus_slave_control_reg=%x, "
185 "chip->deadlock_avoid_type_reg=%x, "
186 "chip->intpin_reg_wpermit_reg0=%x, "
187 "chip->intpin_reg_wpermit_reg1=%x, "
188 "chip->intpin_reg_wpermit_reg2=%x, "
189 "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
190 chip->phub_id_reg,
191 chip->q_pri_val_reg,
192 chip->rc_q_maxsize_reg,
193 chip->bri_q_maxsize_reg,
194 chip->comp_resp_timeout_reg,
195 chip->bus_slave_control_reg,
196 chip->deadlock_avoid_type_reg,
197 chip->intpin_reg_wpermit_reg0,
198 chip->intpin_reg_wpermit_reg1,
199 chip->intpin_reg_wpermit_reg2,
200 chip->intpin_reg_wpermit_reg3);
201 for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
202 chip->int_reduce_control_reg[i] =
203 ioread32(p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
204 dev_dbg(&pdev->dev, "%s : "
205 "chip->int_reduce_control_reg[%d]=%x\n",
206 __func__, i, chip->int_reduce_control_reg[i]);
207 }
208 chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET);
209 if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
210 chip->funcsel_reg = ioread32(p + FUNCSEL_REG_OFFSET);
211 }
212
213 /* pch_phub_restore_reg_conf - restore register configuration */
pch_phub_restore_reg_conf(struct pci_dev * pdev)214 static void __maybe_unused pch_phub_restore_reg_conf(struct pci_dev *pdev)
215 {
216 unsigned int i;
217 struct pch_phub_reg *chip = pci_get_drvdata(pdev);
218 void __iomem *p;
219 p = chip->pch_phub_base_address;
220
221 iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG);
222 iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG);
223 iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
224 iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
225 iowrite32(chip->comp_resp_timeout_reg,
226 p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
227 iowrite32(chip->bus_slave_control_reg,
228 p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
229 iowrite32(chip->deadlock_avoid_type_reg,
230 p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
231 iowrite32(chip->intpin_reg_wpermit_reg0,
232 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
233 iowrite32(chip->intpin_reg_wpermit_reg1,
234 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
235 iowrite32(chip->intpin_reg_wpermit_reg2,
236 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
237 iowrite32(chip->intpin_reg_wpermit_reg3,
238 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
239 dev_dbg(&pdev->dev, "%s : "
240 "chip->phub_id_reg=%x, "
241 "chip->q_pri_val_reg=%x, "
242 "chip->rc_q_maxsize_reg=%x, "
243 "chip->bri_q_maxsize_reg=%x, "
244 "chip->comp_resp_timeout_reg=%x, "
245 "chip->bus_slave_control_reg=%x, "
246 "chip->deadlock_avoid_type_reg=%x, "
247 "chip->intpin_reg_wpermit_reg0=%x, "
248 "chip->intpin_reg_wpermit_reg1=%x, "
249 "chip->intpin_reg_wpermit_reg2=%x, "
250 "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
251 chip->phub_id_reg,
252 chip->q_pri_val_reg,
253 chip->rc_q_maxsize_reg,
254 chip->bri_q_maxsize_reg,
255 chip->comp_resp_timeout_reg,
256 chip->bus_slave_control_reg,
257 chip->deadlock_avoid_type_reg,
258 chip->intpin_reg_wpermit_reg0,
259 chip->intpin_reg_wpermit_reg1,
260 chip->intpin_reg_wpermit_reg2,
261 chip->intpin_reg_wpermit_reg3);
262 for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
263 iowrite32(chip->int_reduce_control_reg[i],
264 p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
265 dev_dbg(&pdev->dev, "%s : "
266 "chip->int_reduce_control_reg[%d]=%x\n",
267 __func__, i, chip->int_reduce_control_reg[i]);
268 }
269
270 iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET);
271 if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
272 iowrite32(chip->funcsel_reg, p + FUNCSEL_REG_OFFSET);
273 }
274
275 /**
276 * pch_phub_read_serial_rom() - Reading Serial ROM
277 * @chip: Pointer to the PHUB register structure
278 * @offset_address: Serial ROM offset address to read.
279 * @data: Read buffer for specified Serial ROM value.
280 */
pch_phub_read_serial_rom(struct pch_phub_reg * chip,unsigned int offset_address,u8 * data)281 static void pch_phub_read_serial_rom(struct pch_phub_reg *chip,
282 unsigned int offset_address, u8 *data)
283 {
284 void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
285 offset_address;
286
287 *data = ioread8(mem_addr);
288 }
289
290 /**
291 * pch_phub_write_serial_rom() - Writing Serial ROM
292 * @chip: Pointer to the PHUB register structure
293 * @offset_address: Serial ROM offset address.
294 * @data: Serial ROM value to write.
295 */
pch_phub_write_serial_rom(struct pch_phub_reg * chip,unsigned int offset_address,u8 data)296 static int pch_phub_write_serial_rom(struct pch_phub_reg *chip,
297 unsigned int offset_address, u8 data)
298 {
299 void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
300 (offset_address & PCH_WORD_ADDR_MASK);
301 int i;
302 unsigned int word_data;
303 unsigned int pos;
304 unsigned int mask;
305 pos = (offset_address % 4) * 8;
306 mask = ~(0xFF << pos);
307
308 iowrite32(PCH_PHUB_ROM_WRITE_ENABLE,
309 chip->pch_phub_extrom_base_address + PHUB_CONTROL);
310
311 word_data = ioread32(mem_addr);
312 iowrite32((word_data & mask) | (u32)data << pos, mem_addr);
313
314 i = 0;
315 while (ioread8(chip->pch_phub_extrom_base_address +
316 PHUB_STATUS) != 0x00) {
317 msleep(1);
318 if (i == PHUB_TIMEOUT)
319 return -ETIMEDOUT;
320 i++;
321 }
322
323 iowrite32(PCH_PHUB_ROM_WRITE_DISABLE,
324 chip->pch_phub_extrom_base_address + PHUB_CONTROL);
325
326 return 0;
327 }
328
329 /**
330 * pch_phub_read_serial_rom_val() - Read Serial ROM value
331 * @chip: Pointer to the PHUB register structure
332 * @offset_address: Serial ROM address offset value.
333 * @data: Serial ROM value to read.
334 */
pch_phub_read_serial_rom_val(struct pch_phub_reg * chip,unsigned int offset_address,u8 * data)335 static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip,
336 unsigned int offset_address, u8 *data)
337 {
338 unsigned int mem_addr;
339
340 mem_addr = chip->pch_mac_start_address +
341 pch_phub_mac_offset[offset_address];
342
343 pch_phub_read_serial_rom(chip, mem_addr, data);
344 }
345
346 /**
347 * pch_phub_write_serial_rom_val() - writing Serial ROM value
348 * @chip: Pointer to the PHUB register structure
349 * @offset_address: Serial ROM address offset value.
350 * @data: Serial ROM value.
351 */
pch_phub_write_serial_rom_val(struct pch_phub_reg * chip,unsigned int offset_address,u8 data)352 static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip,
353 unsigned int offset_address, u8 data)
354 {
355 int retval;
356 unsigned int mem_addr;
357
358 mem_addr = chip->pch_mac_start_address +
359 pch_phub_mac_offset[offset_address];
360
361 retval = pch_phub_write_serial_rom(chip, mem_addr, data);
362
363 return retval;
364 }
365
366 /* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration
367 * for Gigabit Ethernet MAC address
368 */
pch_phub_gbe_serial_rom_conf(struct pch_phub_reg * chip)369 static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip)
370 {
371 int retval;
372
373 retval = pch_phub_write_serial_rom(chip, 0x0b, 0xbc);
374 retval |= pch_phub_write_serial_rom(chip, 0x0a, 0x10);
375 retval |= pch_phub_write_serial_rom(chip, 0x09, 0x01);
376 retval |= pch_phub_write_serial_rom(chip, 0x08, 0x02);
377
378 retval |= pch_phub_write_serial_rom(chip, 0x0f, 0x00);
379 retval |= pch_phub_write_serial_rom(chip, 0x0e, 0x00);
380 retval |= pch_phub_write_serial_rom(chip, 0x0d, 0x00);
381 retval |= pch_phub_write_serial_rom(chip, 0x0c, 0x80);
382
383 retval |= pch_phub_write_serial_rom(chip, 0x13, 0xbc);
384 retval |= pch_phub_write_serial_rom(chip, 0x12, 0x10);
385 retval |= pch_phub_write_serial_rom(chip, 0x11, 0x01);
386 retval |= pch_phub_write_serial_rom(chip, 0x10, 0x18);
387
388 retval |= pch_phub_write_serial_rom(chip, 0x1b, 0xbc);
389 retval |= pch_phub_write_serial_rom(chip, 0x1a, 0x10);
390 retval |= pch_phub_write_serial_rom(chip, 0x19, 0x01);
391 retval |= pch_phub_write_serial_rom(chip, 0x18, 0x19);
392
393 retval |= pch_phub_write_serial_rom(chip, 0x23, 0xbc);
394 retval |= pch_phub_write_serial_rom(chip, 0x22, 0x10);
395 retval |= pch_phub_write_serial_rom(chip, 0x21, 0x01);
396 retval |= pch_phub_write_serial_rom(chip, 0x20, 0x3a);
397
398 retval |= pch_phub_write_serial_rom(chip, 0x27, 0x01);
399 retval |= pch_phub_write_serial_rom(chip, 0x26, 0x00);
400 retval |= pch_phub_write_serial_rom(chip, 0x25, 0x00);
401 retval |= pch_phub_write_serial_rom(chip, 0x24, 0x00);
402
403 return retval;
404 }
405
406 /* pch_phub_gbe_serial_rom_conf_mp - makes SerialROM header format configuration
407 * for Gigabit Ethernet MAC address
408 */
pch_phub_gbe_serial_rom_conf_mp(struct pch_phub_reg * chip)409 static int pch_phub_gbe_serial_rom_conf_mp(struct pch_phub_reg *chip)
410 {
411 int retval;
412 u32 offset_addr;
413
414 offset_addr = 0x200;
415 retval = pch_phub_write_serial_rom(chip, 0x03 + offset_addr, 0xbc);
416 retval |= pch_phub_write_serial_rom(chip, 0x02 + offset_addr, 0x00);
417 retval |= pch_phub_write_serial_rom(chip, 0x01 + offset_addr, 0x40);
418 retval |= pch_phub_write_serial_rom(chip, 0x00 + offset_addr, 0x02);
419
420 retval |= pch_phub_write_serial_rom(chip, 0x07 + offset_addr, 0x00);
421 retval |= pch_phub_write_serial_rom(chip, 0x06 + offset_addr, 0x00);
422 retval |= pch_phub_write_serial_rom(chip, 0x05 + offset_addr, 0x00);
423 retval |= pch_phub_write_serial_rom(chip, 0x04 + offset_addr, 0x80);
424
425 retval |= pch_phub_write_serial_rom(chip, 0x0b + offset_addr, 0xbc);
426 retval |= pch_phub_write_serial_rom(chip, 0x0a + offset_addr, 0x00);
427 retval |= pch_phub_write_serial_rom(chip, 0x09 + offset_addr, 0x40);
428 retval |= pch_phub_write_serial_rom(chip, 0x08 + offset_addr, 0x18);
429
430 retval |= pch_phub_write_serial_rom(chip, 0x13 + offset_addr, 0xbc);
431 retval |= pch_phub_write_serial_rom(chip, 0x12 + offset_addr, 0x00);
432 retval |= pch_phub_write_serial_rom(chip, 0x11 + offset_addr, 0x40);
433 retval |= pch_phub_write_serial_rom(chip, 0x10 + offset_addr, 0x19);
434
435 retval |= pch_phub_write_serial_rom(chip, 0x1b + offset_addr, 0xbc);
436 retval |= pch_phub_write_serial_rom(chip, 0x1a + offset_addr, 0x00);
437 retval |= pch_phub_write_serial_rom(chip, 0x19 + offset_addr, 0x40);
438 retval |= pch_phub_write_serial_rom(chip, 0x18 + offset_addr, 0x3a);
439
440 retval |= pch_phub_write_serial_rom(chip, 0x1f + offset_addr, 0x01);
441 retval |= pch_phub_write_serial_rom(chip, 0x1e + offset_addr, 0x00);
442 retval |= pch_phub_write_serial_rom(chip, 0x1d + offset_addr, 0x00);
443 retval |= pch_phub_write_serial_rom(chip, 0x1c + offset_addr, 0x00);
444
445 return retval;
446 }
447
448 /**
449 * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address
450 * @chip: Pointer to the PHUB register structure
451 * @data: Buffer of the Gigabit Ethernet MAC address value.
452 */
pch_phub_read_gbe_mac_addr(struct pch_phub_reg * chip,u8 * data)453 static void pch_phub_read_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
454 {
455 int i;
456 for (i = 0; i < ETH_ALEN; i++)
457 pch_phub_read_serial_rom_val(chip, i, &data[i]);
458 }
459
460 /**
461 * pch_phub_write_gbe_mac_addr() - Write MAC address
462 * @chip: Pointer to the PHUB register structure
463 * @data: Gigabit Ethernet MAC address value.
464 */
pch_phub_write_gbe_mac_addr(struct pch_phub_reg * chip,u8 * data)465 static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
466 {
467 int retval;
468 int i;
469
470 if ((chip->ioh_type == 1) || (chip->ioh_type == 5)) /* EG20T or ML7831*/
471 retval = pch_phub_gbe_serial_rom_conf(chip);
472 else /* ML7223 */
473 retval = pch_phub_gbe_serial_rom_conf_mp(chip);
474 if (retval)
475 return retval;
476
477 for (i = 0; i < ETH_ALEN; i++) {
478 retval = pch_phub_write_serial_rom_val(chip, i, data[i]);
479 if (retval)
480 return retval;
481 }
482
483 return retval;
484 }
485
pch_phub_bin_read(struct file * filp,struct kobject * kobj,const struct bin_attribute * attr,char * buf,loff_t off,size_t count)486 static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj,
487 const struct bin_attribute *attr, char *buf,
488 loff_t off, size_t count)
489 {
490 unsigned int rom_signature;
491 unsigned char rom_length;
492 unsigned int tmp;
493 unsigned int addr_offset;
494 unsigned int orom_size;
495 int ret;
496 int err;
497 ssize_t rom_size;
498
499 struct pch_phub_reg *chip = dev_get_drvdata(kobj_to_dev(kobj));
500
501 ret = mutex_lock_interruptible(&pch_phub_mutex);
502 if (ret) {
503 err = -ERESTARTSYS;
504 goto return_err_nomutex;
505 }
506
507 /* Get Rom signature */
508 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
509 if (!chip->pch_phub_extrom_base_address) {
510 err = -ENODATA;
511 goto exrom_map_err;
512 }
513
514 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address,
515 (unsigned char *)&rom_signature);
516 rom_signature &= 0xff;
517 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1,
518 (unsigned char *)&tmp);
519 rom_signature |= (tmp & 0xff) << 8;
520 if (rom_signature == 0xAA55) {
521 pch_phub_read_serial_rom(chip,
522 chip->pch_opt_rom_start_address + 2,
523 &rom_length);
524 orom_size = rom_length * 512;
525 if (orom_size < off) {
526 addr_offset = 0;
527 goto return_ok;
528 }
529 if (orom_size < count) {
530 addr_offset = 0;
531 goto return_ok;
532 }
533
534 for (addr_offset = 0; addr_offset < count; addr_offset++) {
535 pch_phub_read_serial_rom(chip,
536 chip->pch_opt_rom_start_address + addr_offset + off,
537 &buf[addr_offset]);
538 }
539 } else {
540 err = -ENODATA;
541 goto return_err;
542 }
543 return_ok:
544 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
545 mutex_unlock(&pch_phub_mutex);
546 return addr_offset;
547
548 return_err:
549 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
550 exrom_map_err:
551 mutex_unlock(&pch_phub_mutex);
552 return_err_nomutex:
553 return err;
554 }
555
pch_phub_bin_write(struct file * filp,struct kobject * kobj,const struct bin_attribute * attr,char * buf,loff_t off,size_t count)556 static ssize_t pch_phub_bin_write(struct file *filp, struct kobject *kobj,
557 const struct bin_attribute *attr,
558 char *buf, loff_t off, size_t count)
559 {
560 int err;
561 unsigned int addr_offset;
562 int ret;
563 ssize_t rom_size;
564 struct pch_phub_reg *chip = dev_get_drvdata(kobj_to_dev(kobj));
565
566 ret = mutex_lock_interruptible(&pch_phub_mutex);
567 if (ret)
568 return -ERESTARTSYS;
569
570 if (off > PCH_PHUB_OROM_SIZE) {
571 addr_offset = 0;
572 goto return_ok;
573 }
574 if (count > PCH_PHUB_OROM_SIZE) {
575 addr_offset = 0;
576 goto return_ok;
577 }
578
579 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
580 if (!chip->pch_phub_extrom_base_address) {
581 err = -ENOMEM;
582 goto exrom_map_err;
583 }
584
585 for (addr_offset = 0; addr_offset < count; addr_offset++) {
586 if (PCH_PHUB_OROM_SIZE < off + addr_offset)
587 goto return_ok;
588
589 ret = pch_phub_write_serial_rom(chip,
590 chip->pch_opt_rom_start_address + addr_offset + off,
591 buf[addr_offset]);
592 if (ret) {
593 err = ret;
594 goto return_err;
595 }
596 }
597
598 return_ok:
599 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
600 mutex_unlock(&pch_phub_mutex);
601 return addr_offset;
602
603 return_err:
604 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
605
606 exrom_map_err:
607 mutex_unlock(&pch_phub_mutex);
608 return err;
609 }
610
show_pch_mac(struct device * dev,struct device_attribute * attr,char * buf)611 static ssize_t show_pch_mac(struct device *dev, struct device_attribute *attr,
612 char *buf)
613 {
614 u8 mac[8];
615 struct pch_phub_reg *chip = dev_get_drvdata(dev);
616 ssize_t rom_size;
617
618 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
619 if (!chip->pch_phub_extrom_base_address)
620 return -ENOMEM;
621
622 pch_phub_read_gbe_mac_addr(chip, mac);
623 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
624
625 return sprintf(buf, "%pM\n", mac);
626 }
627
store_pch_mac(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)628 static ssize_t store_pch_mac(struct device *dev, struct device_attribute *attr,
629 const char *buf, size_t count)
630 {
631 u8 mac[ETH_ALEN];
632 ssize_t rom_size;
633 struct pch_phub_reg *chip = dev_get_drvdata(dev);
634 int ret;
635
636 if (!mac_pton(buf, mac))
637 return -EINVAL;
638
639 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
640 if (!chip->pch_phub_extrom_base_address)
641 return -ENOMEM;
642
643 ret = pch_phub_write_gbe_mac_addr(chip, mac);
644 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
645 if (ret)
646 return ret;
647
648 return count;
649 }
650
651 static DEVICE_ATTR(pch_mac, S_IRUGO | S_IWUSR, show_pch_mac, store_pch_mac);
652
653 static const struct bin_attribute pch_bin_attr = {
654 .attr = {
655 .name = "pch_firmware",
656 .mode = S_IRUGO | S_IWUSR,
657 },
658 .size = PCH_PHUB_OROM_SIZE + 1,
659 .read = pch_phub_bin_read,
660 .write = pch_phub_bin_write,
661 };
662
pch_phub_probe(struct pci_dev * pdev,const struct pci_device_id * id)663 static int pch_phub_probe(struct pci_dev *pdev,
664 const struct pci_device_id *id)
665 {
666 int ret;
667 struct pch_phub_reg *chip;
668
669 chip = kzalloc_obj(struct pch_phub_reg);
670 if (chip == NULL)
671 return -ENOMEM;
672
673 ret = pci_enable_device(pdev);
674 if (ret) {
675 dev_err(&pdev->dev,
676 "%s : pci_enable_device FAILED(ret=%d)", __func__, ret);
677 goto err_pci_enable_dev;
678 }
679 dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__,
680 ret);
681
682 ret = pci_request_regions(pdev, KBUILD_MODNAME);
683 if (ret) {
684 dev_err(&pdev->dev,
685 "%s : pci_request_regions FAILED(ret=%d)", __func__, ret);
686 goto err_req_regions;
687 }
688 dev_dbg(&pdev->dev, "%s : "
689 "pci_request_regions returns %d\n", __func__, ret);
690
691 chip->pch_phub_base_address = pci_iomap(pdev, 1, 0);
692
693
694 if (chip->pch_phub_base_address == NULL) {
695 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
696 ret = -ENOMEM;
697 goto err_pci_iomap;
698 }
699 dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value "
700 "in pch_phub_base_address variable is %p\n", __func__,
701 chip->pch_phub_base_address);
702
703 chip->pdev = pdev; /* Save pci device struct */
704
705 if (id->driver_data == 1) { /* EG20T PCH */
706 const char *board_name;
707 unsigned int prefetch = 0x000affaa;
708
709 if (pdev->dev.of_node)
710 of_property_read_u32(pdev->dev.of_node,
711 "intel,eg20t-prefetch",
712 &prefetch);
713
714 ret = sysfs_create_file(&pdev->dev.kobj,
715 &dev_attr_pch_mac.attr);
716 if (ret)
717 goto err_sysfs_create;
718
719 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
720 if (ret)
721 goto exit_bin_attr;
722
723 pch_phub_read_modify_write_reg(chip,
724 (unsigned int)CLKCFG_REG_OFFSET,
725 CLKCFG_CAN_50MHZ,
726 CLKCFG_CANCLK_MASK);
727
728 /* quirk for CM-iTC board */
729 board_name = dmi_get_system_info(DMI_BOARD_NAME);
730 if (board_name && strstr(board_name, "CM-iTC"))
731 pch_phub_read_modify_write_reg(chip,
732 (unsigned int)CLKCFG_REG_OFFSET,
733 CLKCFG_UART_48MHZ | CLKCFG_BAUDDIV |
734 CLKCFG_PLL2VCO | CLKCFG_UARTCLKSEL,
735 CLKCFG_UART_MASK);
736
737 /* set the prefech value */
738 iowrite32(prefetch, chip->pch_phub_base_address + 0x14);
739 /* set the interrupt delay value */
740 iowrite32(0x25, chip->pch_phub_base_address + 0x44);
741 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
742 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
743
744 /* quirk for MIPS Boston platform */
745 if (pdev->dev.of_node) {
746 if (of_machine_is_compatible("img,boston")) {
747 pch_phub_read_modify_write_reg(chip,
748 (unsigned int)CLKCFG_REG_OFFSET,
749 CLKCFG_UART_25MHZ,
750 CLKCFG_UART_MASK);
751 }
752 }
753 } else if (id->driver_data == 2) { /* ML7213 IOH */
754 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
755 if (ret)
756 goto err_sysfs_create;
757 /* set the prefech value
758 * Device2(USB OHCI #1/ USB EHCI #1/ USB Device):a
759 * Device4(SDIO #0,1,2):f
760 * Device6(SATA 2):f
761 * Device8(USB OHCI #0/ USB EHCI #0):a
762 */
763 iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14);
764 chip->pch_opt_rom_start_address =\
765 PCH_PHUB_ROM_START_ADDR_ML7213;
766 } else if (id->driver_data == 3) { /* ML7223 IOH Bus-m*/
767 /* set the prefech value
768 * Device8(GbE)
769 */
770 iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14);
771 /* set the interrupt delay value */
772 iowrite32(0x25, chip->pch_phub_base_address + 0x140);
773 chip->pch_opt_rom_start_address =\
774 PCH_PHUB_ROM_START_ADDR_ML7223;
775 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
776 } else if (id->driver_data == 4) { /* ML7223 IOH Bus-n*/
777 ret = sysfs_create_file(&pdev->dev.kobj,
778 &dev_attr_pch_mac.attr);
779 if (ret)
780 goto err_sysfs_create;
781 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
782 if (ret)
783 goto exit_bin_attr;
784 /* set the prefech value
785 * Device2(USB OHCI #0,1,2,3/ USB EHCI #0):a
786 * Device4(SDIO #0,1):f
787 * Device6(SATA 2):f
788 */
789 iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14);
790 chip->pch_opt_rom_start_address =\
791 PCH_PHUB_ROM_START_ADDR_ML7223;
792 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
793 } else if (id->driver_data == 5) { /* ML7831 */
794 ret = sysfs_create_file(&pdev->dev.kobj,
795 &dev_attr_pch_mac.attr);
796 if (ret)
797 goto err_sysfs_create;
798
799 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
800 if (ret)
801 goto exit_bin_attr;
802
803 /* set the prefech value */
804 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
805 /* set the interrupt delay value */
806 iowrite32(0x25, chip->pch_phub_base_address + 0x44);
807 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
808 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
809 }
810
811 chip->ioh_type = id->driver_data;
812 pci_set_drvdata(pdev, chip);
813
814 return 0;
815 exit_bin_attr:
816 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
817
818 err_sysfs_create:
819 pci_iounmap(pdev, chip->pch_phub_base_address);
820 err_pci_iomap:
821 pci_release_regions(pdev);
822 err_req_regions:
823 pci_disable_device(pdev);
824 err_pci_enable_dev:
825 kfree(chip);
826 dev_err(&pdev->dev, "%s returns %d\n", __func__, ret);
827 return ret;
828 }
829
pch_phub_remove(struct pci_dev * pdev)830 static void pch_phub_remove(struct pci_dev *pdev)
831 {
832 struct pch_phub_reg *chip = pci_get_drvdata(pdev);
833
834 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
835 sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr);
836 pci_iounmap(pdev, chip->pch_phub_base_address);
837 pci_release_regions(pdev);
838 pci_disable_device(pdev);
839 kfree(chip);
840 }
841
pch_phub_suspend(struct device * dev_d)842 static int __maybe_unused pch_phub_suspend(struct device *dev_d)
843 {
844 device_wakeup_disable(dev_d);
845
846 return 0;
847 }
848
pch_phub_resume(struct device * dev_d)849 static int __maybe_unused pch_phub_resume(struct device *dev_d)
850 {
851 device_wakeup_disable(dev_d);
852
853 return 0;
854 }
855
856 static const struct pci_device_id pch_phub_pcidev_id[] = {
857 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB), 1, },
858 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), 2, },
859 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_mPHUB), 3, },
860 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_nPHUB), 4, },
861 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7831_PHUB), 5, },
862 { }
863 };
864 MODULE_DEVICE_TABLE(pci, pch_phub_pcidev_id);
865
866 static SIMPLE_DEV_PM_OPS(pch_phub_pm_ops, pch_phub_suspend, pch_phub_resume);
867
868 static struct pci_driver pch_phub_driver = {
869 .name = "pch_phub",
870 .id_table = pch_phub_pcidev_id,
871 .probe = pch_phub_probe,
872 .remove = pch_phub_remove,
873 .driver.pm = &pch_phub_pm_ops,
874 };
875
876 module_pci_driver(pch_phub_driver);
877
878 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor IOH(ML7213/ML7223) PHUB");
879 MODULE_LICENSE("GPL");
880