xref: /linux/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml (revision 69050f8d6d075dc01af7a5f2f550a8067510366f) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: PDC interrupt controller
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description: |
13  Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
14  Power Domain Controller (PDC) that is on always-on domain. In addition to
15  providing power control for the power domains, the hardware also has an
16  interrupt controller that can be used to help detect edge low interrupts as
17  well detect interrupts when the GIC is non-operational.
18
19  GIC is parent interrupt controller at the highest level. Platform interrupt
20  controller PDC is next in hierarchy, followed by others. Drivers requiring
21  wakeup capabilities of their device interrupts routed through the PDC, must
22  specify PDC as their interrupt controller and request the PDC port associated
23  with the GIC interrupt. See example below.
24
25properties:
26  compatible:
27    items:
28      - enum:
29          - qcom,glymur-pdc
30          - qcom,kaanapali-pdc
31          - qcom,milos-pdc
32          - qcom,qcs615-pdc
33          - qcom,qcs8300-pdc
34          - qcom,qdu1000-pdc
35          - qcom,sa8255p-pdc
36          - qcom,sa8775p-pdc
37          - qcom,sar2130p-pdc
38          - qcom,sc7180-pdc
39          - qcom,sc7280-pdc
40          - qcom,sc8180x-pdc
41          - qcom,sc8280xp-pdc
42          - qcom,sdm670-pdc
43          - qcom,sdm845-pdc
44          - qcom,sdx55-pdc
45          - qcom,sdx65-pdc
46          - qcom,sdx75-pdc
47          - qcom,sm4450-pdc
48          - qcom,sm6350-pdc
49          - qcom,sm8150-pdc
50          - qcom,sm8250-pdc
51          - qcom,sm8350-pdc
52          - qcom,sm8450-pdc
53          - qcom,sm8550-pdc
54          - qcom,sm8650-pdc
55          - qcom,sm8750-pdc
56          - qcom,x1e80100-pdc
57      - const: qcom,pdc
58
59  reg:
60    minItems: 1
61    items:
62      - description: PDC base register region
63      - description: Edge or Level config register for SPI interrupts
64
65  '#interrupt-cells':
66    const: 2
67
68  interrupt-controller: true
69
70  qcom,pdc-ranges:
71    $ref: /schemas/types.yaml#/definitions/uint32-matrix
72    minItems: 1
73    maxItems: 128 # no hard limit
74    items:
75      items:
76        - description: starting PDC port
77        - description: GIC hwirq number for the PDC port
78        - description: number of interrupts in sequence
79    description: |
80      Specifies the PDC pin offset and the number of PDC ports.
81      The tuples indicates the valid mapping of valid PDC ports
82      and their hwirq mapping.
83
84required:
85  - compatible
86  - reg
87  - '#interrupt-cells'
88  - interrupt-controller
89  - qcom,pdc-ranges
90
91additionalProperties: false
92
93examples:
94  - |
95    #include <dt-bindings/interrupt-controller/irq.h>
96
97    pdc: interrupt-controller@b220000 {
98        compatible = "qcom,sdm845-pdc", "qcom,pdc";
99        reg = <0xb220000 0x30000>;
100        qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
101        #interrupt-cells = <2>;
102        interrupt-parent = <&intc>;
103        interrupt-controller;
104    };
105
106    wake-device {
107        interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
108    };
109