1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ps3vram - Use extra PS3 video ram as block device. 4 * 5 * Copyright 2009 Sony Corporation 6 * 7 * Based on the MTD ps3vram driver, which is 8 * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com> 9 * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr> 10 */ 11 12 #include <linux/blkdev.h> 13 #include <linux/delay.h> 14 #include <linux/module.h> 15 #include <linux/proc_fs.h> 16 #include <linux/seq_file.h> 17 #include <linux/slab.h> 18 19 #include <asm/cell-regs.h> 20 #include <asm/firmware.h> 21 #include <asm/lv1call.h> 22 #include <asm/ps3.h> 23 #include <asm/ps3gpu.h> 24 25 26 #define DEVICE_NAME "ps3vram" 27 28 29 #define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */ 30 #define XDR_IOIF 0x0c000000 31 32 #define FIFO_BASE XDR_IOIF 33 #define FIFO_SIZE (64 * 1024) 34 35 #define DMA_PAGE_SIZE (4 * 1024) 36 37 #define CACHE_PAGE_SIZE (256 * 1024) 38 #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE) 39 40 #define CACHE_OFFSET CACHE_PAGE_SIZE 41 #define FIFO_OFFSET 0 42 43 #define CTRL_PUT 0x10 44 #define CTRL_GET 0x11 45 #define CTRL_TOP 0x15 46 47 #define UPLOAD_SUBCH 1 48 #define DOWNLOAD_SUBCH 2 49 50 #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c 51 #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 52 53 #define CACHE_PAGE_PRESENT 1 54 #define CACHE_PAGE_DIRTY 2 55 56 struct ps3vram_tag { 57 unsigned int address; 58 unsigned int flags; 59 }; 60 61 struct ps3vram_cache { 62 unsigned int page_count; 63 unsigned int page_size; 64 struct ps3vram_tag *tags; 65 unsigned int hit; 66 unsigned int miss; 67 }; 68 69 struct ps3vram_priv { 70 struct gendisk *gendisk; 71 72 u64 size; 73 74 u64 memory_handle; 75 u64 context_handle; 76 u32 __iomem *ctrl; 77 void __iomem *reports; 78 u8 *xdr_buf; 79 80 u32 *fifo_base; 81 u32 *fifo_ptr; 82 83 struct ps3vram_cache cache; 84 85 spinlock_t lock; /* protecting list of bios */ 86 struct bio_list list; 87 }; 88 89 90 static int ps3vram_major; 91 92 #define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */ 93 #define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */ 94 #define DMA_NOTIFIER_SIZE 0x40 95 #define NOTIFIER 7 /* notifier used for completion report */ 96 97 static char *size = "256M"; 98 module_param(size, charp, 0); 99 MODULE_PARM_DESC(size, "memory size"); 100 101 static u32 __iomem *ps3vram_get_notifier(void __iomem *reports, int notifier) 102 { 103 return reports + DMA_NOTIFIER_OFFSET_BASE + 104 DMA_NOTIFIER_SIZE * notifier; 105 } 106 107 static void ps3vram_notifier_reset(struct ps3_system_bus_device *dev) 108 { 109 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 110 u32 __iomem *notify = ps3vram_get_notifier(priv->reports, NOTIFIER); 111 int i; 112 113 for (i = 0; i < 4; i++) 114 iowrite32be(0xffffffff, notify + i); 115 } 116 117 static int ps3vram_notifier_wait(struct ps3_system_bus_device *dev, 118 unsigned int timeout_ms) 119 { 120 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 121 u32 __iomem *notify = ps3vram_get_notifier(priv->reports, NOTIFIER); 122 unsigned long timeout; 123 124 for (timeout = 20; timeout; timeout--) { 125 if (!ioread32be(notify + 3)) 126 return 0; 127 udelay(10); 128 } 129 130 timeout = jiffies + msecs_to_jiffies(timeout_ms); 131 132 do { 133 if (!ioread32be(notify + 3)) 134 return 0; 135 msleep(1); 136 } while (time_before(jiffies, timeout)); 137 138 return -ETIMEDOUT; 139 } 140 141 static void ps3vram_init_ring(struct ps3_system_bus_device *dev) 142 { 143 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 144 145 iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_PUT); 146 iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_GET); 147 } 148 149 static int ps3vram_wait_ring(struct ps3_system_bus_device *dev, 150 unsigned int timeout_ms) 151 { 152 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 153 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 154 155 do { 156 if (ioread32be(priv->ctrl + CTRL_PUT) == ioread32be(priv->ctrl + CTRL_GET)) 157 return 0; 158 msleep(1); 159 } while (time_before(jiffies, timeout)); 160 161 dev_warn(&dev->core, "FIFO timeout (%08x/%08x/%08x)\n", 162 ioread32be(priv->ctrl + CTRL_PUT), ioread32be(priv->ctrl + CTRL_GET), 163 ioread32be(priv->ctrl + CTRL_TOP)); 164 165 return -ETIMEDOUT; 166 } 167 168 static void ps3vram_out_ring(struct ps3vram_priv *priv, u32 data) 169 { 170 *(priv->fifo_ptr)++ = data; 171 } 172 173 static void ps3vram_begin_ring(struct ps3vram_priv *priv, u32 chan, u32 tag, 174 u32 size) 175 { 176 ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag); 177 } 178 179 static void ps3vram_rewind_ring(struct ps3_system_bus_device *dev) 180 { 181 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 182 int status; 183 184 ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET)); 185 186 iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_PUT); 187 188 /* asking the HV for a blit will kick the FIFO */ 189 status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0); 190 if (status) 191 dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n", 192 __func__, status); 193 194 priv->fifo_ptr = priv->fifo_base; 195 } 196 197 static void ps3vram_fire_ring(struct ps3_system_bus_device *dev) 198 { 199 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 200 int status; 201 202 mutex_lock(&ps3_gpu_mutex); 203 204 iowrite32be(FIFO_BASE + FIFO_OFFSET + (priv->fifo_ptr - priv->fifo_base) 205 * sizeof(u32), priv->ctrl + CTRL_PUT); 206 207 /* asking the HV for a blit will kick the FIFO */ 208 status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0); 209 if (status) 210 dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n", 211 __func__, status); 212 213 if ((priv->fifo_ptr - priv->fifo_base) * sizeof(u32) > 214 FIFO_SIZE - 1024) { 215 dev_dbg(&dev->core, "FIFO full, rewinding\n"); 216 ps3vram_wait_ring(dev, 200); 217 ps3vram_rewind_ring(dev); 218 } 219 220 mutex_unlock(&ps3_gpu_mutex); 221 } 222 223 static void ps3vram_bind(struct ps3_system_bus_device *dev) 224 { 225 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 226 227 ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1); 228 ps3vram_out_ring(priv, 0x31337303); 229 ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3); 230 ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER); 231 ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */ 232 ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */ 233 234 ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1); 235 ps3vram_out_ring(priv, 0x3137c0de); 236 ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3); 237 ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER); 238 ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */ 239 ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */ 240 241 ps3vram_fire_ring(dev); 242 } 243 244 static int ps3vram_upload(struct ps3_system_bus_device *dev, 245 unsigned int src_offset, unsigned int dst_offset, 246 int len, int count) 247 { 248 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 249 250 ps3vram_begin_ring(priv, UPLOAD_SUBCH, 251 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); 252 ps3vram_out_ring(priv, XDR_IOIF + src_offset); 253 ps3vram_out_ring(priv, dst_offset); 254 ps3vram_out_ring(priv, len); 255 ps3vram_out_ring(priv, len); 256 ps3vram_out_ring(priv, len); 257 ps3vram_out_ring(priv, count); 258 ps3vram_out_ring(priv, (1 << 8) | 1); 259 ps3vram_out_ring(priv, 0); 260 261 ps3vram_notifier_reset(dev); 262 ps3vram_begin_ring(priv, UPLOAD_SUBCH, 263 NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1); 264 ps3vram_out_ring(priv, 0); 265 ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1); 266 ps3vram_out_ring(priv, 0); 267 ps3vram_fire_ring(dev); 268 if (ps3vram_notifier_wait(dev, 200) < 0) { 269 dev_warn(&dev->core, "%s: Notifier timeout\n", __func__); 270 return -1; 271 } 272 273 return 0; 274 } 275 276 static int ps3vram_download(struct ps3_system_bus_device *dev, 277 unsigned int src_offset, unsigned int dst_offset, 278 int len, int count) 279 { 280 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 281 282 ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 283 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); 284 ps3vram_out_ring(priv, src_offset); 285 ps3vram_out_ring(priv, XDR_IOIF + dst_offset); 286 ps3vram_out_ring(priv, len); 287 ps3vram_out_ring(priv, len); 288 ps3vram_out_ring(priv, len); 289 ps3vram_out_ring(priv, count); 290 ps3vram_out_ring(priv, (1 << 8) | 1); 291 ps3vram_out_ring(priv, 0); 292 293 ps3vram_notifier_reset(dev); 294 ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 295 NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1); 296 ps3vram_out_ring(priv, 0); 297 ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1); 298 ps3vram_out_ring(priv, 0); 299 ps3vram_fire_ring(dev); 300 if (ps3vram_notifier_wait(dev, 200) < 0) { 301 dev_warn(&dev->core, "%s: Notifier timeout\n", __func__); 302 return -1; 303 } 304 305 return 0; 306 } 307 308 static void ps3vram_cache_evict(struct ps3_system_bus_device *dev, int entry) 309 { 310 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 311 struct ps3vram_cache *cache = &priv->cache; 312 313 if (!(cache->tags[entry].flags & CACHE_PAGE_DIRTY)) 314 return; 315 316 dev_dbg(&dev->core, "Flushing %d: 0x%08x\n", entry, 317 cache->tags[entry].address); 318 if (ps3vram_upload(dev, CACHE_OFFSET + entry * cache->page_size, 319 cache->tags[entry].address, DMA_PAGE_SIZE, 320 cache->page_size / DMA_PAGE_SIZE) < 0) { 321 dev_err(&dev->core, 322 "Failed to upload from 0x%x to " "0x%x size 0x%x\n", 323 entry * cache->page_size, cache->tags[entry].address, 324 cache->page_size); 325 } 326 cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY; 327 } 328 329 static void ps3vram_cache_load(struct ps3_system_bus_device *dev, int entry, 330 unsigned int address) 331 { 332 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 333 struct ps3vram_cache *cache = &priv->cache; 334 335 dev_dbg(&dev->core, "Fetching %d: 0x%08x\n", entry, address); 336 if (ps3vram_download(dev, address, 337 CACHE_OFFSET + entry * cache->page_size, 338 DMA_PAGE_SIZE, 339 cache->page_size / DMA_PAGE_SIZE) < 0) { 340 dev_err(&dev->core, 341 "Failed to download from 0x%x to 0x%x size 0x%x\n", 342 address, entry * cache->page_size, cache->page_size); 343 } 344 345 cache->tags[entry].address = address; 346 cache->tags[entry].flags |= CACHE_PAGE_PRESENT; 347 } 348 349 350 static void ps3vram_cache_flush(struct ps3_system_bus_device *dev) 351 { 352 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 353 struct ps3vram_cache *cache = &priv->cache; 354 int i; 355 356 dev_dbg(&dev->core, "FLUSH\n"); 357 for (i = 0; i < cache->page_count; i++) { 358 ps3vram_cache_evict(dev, i); 359 cache->tags[i].flags = 0; 360 } 361 } 362 363 static unsigned int ps3vram_cache_match(struct ps3_system_bus_device *dev, 364 loff_t address) 365 { 366 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 367 struct ps3vram_cache *cache = &priv->cache; 368 unsigned int base; 369 unsigned int offset; 370 int i; 371 static int counter; 372 373 offset = (unsigned int) (address & (cache->page_size - 1)); 374 base = (unsigned int) (address - offset); 375 376 /* fully associative check */ 377 for (i = 0; i < cache->page_count; i++) { 378 if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) && 379 cache->tags[i].address == base) { 380 cache->hit++; 381 dev_dbg(&dev->core, "Found entry %d: 0x%08x\n", i, 382 cache->tags[i].address); 383 return i; 384 } 385 } 386 387 /* choose a random entry */ 388 i = (jiffies + (counter++)) % cache->page_count; 389 dev_dbg(&dev->core, "Using entry %d\n", i); 390 391 ps3vram_cache_evict(dev, i); 392 ps3vram_cache_load(dev, i, base); 393 394 cache->miss++; 395 return i; 396 } 397 398 static int ps3vram_cache_init(struct ps3_system_bus_device *dev) 399 { 400 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 401 402 priv->cache.page_count = CACHE_PAGE_COUNT; 403 priv->cache.page_size = CACHE_PAGE_SIZE; 404 priv->cache.tags = kzalloc_objs(struct ps3vram_tag, CACHE_PAGE_COUNT, 405 GFP_KERNEL); 406 if (!priv->cache.tags) 407 return -ENOMEM; 408 409 dev_info(&dev->core, "Created ram cache: %d entries, %d KiB each\n", 410 CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024); 411 412 return 0; 413 } 414 415 static void ps3vram_cache_cleanup(struct ps3_system_bus_device *dev) 416 { 417 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 418 419 ps3vram_cache_flush(dev); 420 kfree(priv->cache.tags); 421 } 422 423 static blk_status_t ps3vram_read(struct ps3_system_bus_device *dev, loff_t from, 424 size_t len, size_t *retlen, u_char *buf) 425 { 426 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 427 unsigned int cached, count; 428 429 dev_dbg(&dev->core, "%s: from=0x%08x len=0x%zx\n", __func__, 430 (unsigned int)from, len); 431 432 if (from >= priv->size) 433 return BLK_STS_IOERR; 434 435 if (len > priv->size - from) 436 len = priv->size - from; 437 438 /* Copy from vram to buf */ 439 count = len; 440 while (count) { 441 unsigned int offset, avail; 442 unsigned int entry; 443 444 offset = (unsigned int) (from & (priv->cache.page_size - 1)); 445 avail = priv->cache.page_size - offset; 446 447 entry = ps3vram_cache_match(dev, from); 448 cached = CACHE_OFFSET + entry * priv->cache.page_size + offset; 449 450 dev_dbg(&dev->core, "%s: from=%08x cached=%08x offset=%08x " 451 "avail=%08x count=%08x\n", __func__, 452 (unsigned int)from, cached, offset, avail, count); 453 454 if (avail > count) 455 avail = count; 456 memcpy(buf, priv->xdr_buf + cached, avail); 457 458 buf += avail; 459 count -= avail; 460 from += avail; 461 } 462 463 *retlen = len; 464 return 0; 465 } 466 467 static blk_status_t ps3vram_write(struct ps3_system_bus_device *dev, loff_t to, 468 size_t len, size_t *retlen, const u_char *buf) 469 { 470 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 471 unsigned int cached, count; 472 473 if (to >= priv->size) 474 return BLK_STS_IOERR; 475 476 if (len > priv->size - to) 477 len = priv->size - to; 478 479 /* Copy from buf to vram */ 480 count = len; 481 while (count) { 482 unsigned int offset, avail; 483 unsigned int entry; 484 485 offset = (unsigned int) (to & (priv->cache.page_size - 1)); 486 avail = priv->cache.page_size - offset; 487 488 entry = ps3vram_cache_match(dev, to); 489 cached = CACHE_OFFSET + entry * priv->cache.page_size + offset; 490 491 dev_dbg(&dev->core, "%s: to=%08x cached=%08x offset=%08x " 492 "avail=%08x count=%08x\n", __func__, (unsigned int)to, 493 cached, offset, avail, count); 494 495 if (avail > count) 496 avail = count; 497 memcpy(priv->xdr_buf + cached, buf, avail); 498 499 priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY; 500 501 buf += avail; 502 count -= avail; 503 to += avail; 504 } 505 506 *retlen = len; 507 return 0; 508 } 509 510 static int ps3vram_proc_show(struct seq_file *m, void *v) 511 { 512 struct ps3vram_priv *priv = m->private; 513 514 seq_printf(m, "hit:%u\nmiss:%u\n", priv->cache.hit, priv->cache.miss); 515 return 0; 516 } 517 518 static void ps3vram_proc_init(struct ps3_system_bus_device *dev) 519 { 520 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 521 struct proc_dir_entry *pde; 522 523 pde = proc_create_single_data(DEVICE_NAME, 0444, NULL, 524 ps3vram_proc_show, priv); 525 if (!pde) 526 dev_warn(&dev->core, "failed to create /proc entry\n"); 527 } 528 529 static struct bio *ps3vram_do_bio(struct ps3_system_bus_device *dev, 530 struct bio *bio) 531 { 532 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 533 int write = bio_data_dir(bio) == WRITE; 534 const char *op = write ? "write" : "read"; 535 loff_t offset = bio->bi_iter.bi_sector << 9; 536 blk_status_t error = 0; 537 struct bio_vec bvec; 538 struct bvec_iter iter; 539 struct bio *next; 540 541 bio_for_each_segment(bvec, bio, iter) { 542 /* PS3 is ppc64, so we don't handle highmem */ 543 char *ptr = bvec_virt(&bvec); 544 size_t len = bvec.bv_len, retlen; 545 546 dev_dbg(&dev->core, " %s %zu bytes at offset %llu\n", op, 547 len, offset); 548 if (write) 549 error = ps3vram_write(dev, offset, len, &retlen, ptr); 550 else 551 error = ps3vram_read(dev, offset, len, &retlen, ptr); 552 553 if (error) { 554 dev_err(&dev->core, "%s failed\n", op); 555 goto out; 556 } 557 558 if (retlen != len) { 559 dev_err(&dev->core, "Short %s\n", op); 560 error = BLK_STS_IOERR; 561 goto out; 562 } 563 564 offset += len; 565 } 566 567 dev_dbg(&dev->core, "%s completed\n", op); 568 569 out: 570 spin_lock_irq(&priv->lock); 571 bio_list_pop(&priv->list); 572 next = bio_list_peek(&priv->list); 573 spin_unlock_irq(&priv->lock); 574 575 bio->bi_status = error; 576 bio_endio(bio); 577 return next; 578 } 579 580 static void ps3vram_submit_bio(struct bio *bio) 581 { 582 struct ps3_system_bus_device *dev = bio->bi_bdev->bd_disk->private_data; 583 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 584 int busy; 585 586 dev_dbg(&dev->core, "%s\n", __func__); 587 588 spin_lock_irq(&priv->lock); 589 busy = !bio_list_empty(&priv->list); 590 bio_list_add(&priv->list, bio); 591 spin_unlock_irq(&priv->lock); 592 593 if (busy) 594 return; 595 596 do { 597 bio = ps3vram_do_bio(dev, bio); 598 } while (bio); 599 } 600 601 static const struct block_device_operations ps3vram_fops = { 602 .owner = THIS_MODULE, 603 .submit_bio = ps3vram_submit_bio, 604 }; 605 606 static int ps3vram_probe(struct ps3_system_bus_device *dev) 607 { 608 struct ps3vram_priv *priv; 609 int error, status; 610 struct gendisk *gendisk; 611 u64 ddr_size, ddr_lpar, ctrl_lpar, info_lpar, reports_lpar, 612 reports_size, xdr_lpar; 613 char *rest; 614 615 priv = kzalloc_obj(*priv, GFP_KERNEL); 616 if (!priv) { 617 error = -ENOMEM; 618 goto fail; 619 } 620 621 spin_lock_init(&priv->lock); 622 bio_list_init(&priv->list); 623 ps3_system_bus_set_drvdata(dev, priv); 624 625 /* Allocate XDR buffer (1MiB aligned) */ 626 priv->xdr_buf = (void *)__get_free_pages(GFP_KERNEL, 627 get_order(XDR_BUF_SIZE)); 628 if (priv->xdr_buf == NULL) { 629 dev_err(&dev->core, "Could not allocate XDR buffer\n"); 630 error = -ENOMEM; 631 goto fail_free_priv; 632 } 633 634 /* Put FIFO at begginning of XDR buffer */ 635 priv->fifo_base = (u32 *) (priv->xdr_buf + FIFO_OFFSET); 636 priv->fifo_ptr = priv->fifo_base; 637 638 /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */ 639 if (ps3_open_hv_device(dev)) { 640 dev_err(&dev->core, "ps3_open_hv_device failed\n"); 641 error = -EAGAIN; 642 goto out_free_xdr_buf; 643 } 644 645 /* Request memory */ 646 status = -1; 647 ddr_size = ALIGN(memparse(size, &rest), 1024*1024); 648 if (!ddr_size) { 649 dev_err(&dev->core, "Specified size is too small\n"); 650 error = -EINVAL; 651 goto out_close_gpu; 652 } 653 654 while (ddr_size > 0) { 655 status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0, 656 &priv->memory_handle, 657 &ddr_lpar); 658 if (!status) 659 break; 660 ddr_size -= 1024*1024; 661 } 662 if (status) { 663 dev_err(&dev->core, "lv1_gpu_memory_allocate failed %d\n", 664 status); 665 error = -ENOMEM; 666 goto out_close_gpu; 667 } 668 669 /* Request context */ 670 status = lv1_gpu_context_allocate(priv->memory_handle, 0, 671 &priv->context_handle, &ctrl_lpar, 672 &info_lpar, &reports_lpar, 673 &reports_size); 674 if (status) { 675 dev_err(&dev->core, "lv1_gpu_context_allocate failed %d\n", 676 status); 677 error = -ENOMEM; 678 goto out_free_memory; 679 } 680 681 /* Map XDR buffer to RSX */ 682 xdr_lpar = ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)); 683 status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, 684 xdr_lpar, XDR_BUF_SIZE, 685 CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | 686 CBE_IOPTE_M); 687 if (status) { 688 dev_err(&dev->core, "lv1_gpu_context_iomap failed %d\n", 689 status); 690 error = -ENOMEM; 691 goto out_free_context; 692 } 693 694 priv->ctrl = ioremap(ctrl_lpar, 64 * 1024); 695 if (!priv->ctrl) { 696 dev_err(&dev->core, "ioremap CTRL failed\n"); 697 error = -ENOMEM; 698 goto out_unmap_context; 699 } 700 701 priv->reports = ioremap(reports_lpar, reports_size); 702 if (!priv->reports) { 703 dev_err(&dev->core, "ioremap REPORTS failed\n"); 704 error = -ENOMEM; 705 goto out_unmap_ctrl; 706 } 707 708 mutex_lock(&ps3_gpu_mutex); 709 ps3vram_init_ring(dev); 710 mutex_unlock(&ps3_gpu_mutex); 711 712 priv->size = ddr_size; 713 714 ps3vram_bind(dev); 715 716 mutex_lock(&ps3_gpu_mutex); 717 error = ps3vram_wait_ring(dev, 100); 718 mutex_unlock(&ps3_gpu_mutex); 719 if (error < 0) { 720 dev_err(&dev->core, "Failed to initialize channels\n"); 721 error = -ETIMEDOUT; 722 goto out_unmap_reports; 723 } 724 725 error = ps3vram_cache_init(dev); 726 if (error < 0) { 727 goto out_unmap_reports; 728 } 729 730 ps3vram_proc_init(dev); 731 732 gendisk = blk_alloc_disk(NULL, NUMA_NO_NODE); 733 if (IS_ERR(gendisk)) { 734 dev_err(&dev->core, "blk_alloc_disk failed\n"); 735 error = PTR_ERR(gendisk); 736 goto out_cache_cleanup; 737 } 738 739 priv->gendisk = gendisk; 740 gendisk->major = ps3vram_major; 741 gendisk->minors = 1; 742 gendisk->flags |= GENHD_FL_NO_PART; 743 gendisk->fops = &ps3vram_fops; 744 gendisk->private_data = dev; 745 strscpy(gendisk->disk_name, DEVICE_NAME, sizeof(gendisk->disk_name)); 746 set_capacity(gendisk, priv->size >> 9); 747 748 dev_info(&dev->core, "%s: Using %llu MiB of GPU memory\n", 749 gendisk->disk_name, get_capacity(gendisk) >> 11); 750 751 error = device_add_disk(&dev->core, gendisk, NULL); 752 if (error) 753 goto out_cleanup_disk; 754 755 return 0; 756 757 out_cleanup_disk: 758 put_disk(gendisk); 759 out_cache_cleanup: 760 remove_proc_entry(DEVICE_NAME, NULL); 761 ps3vram_cache_cleanup(dev); 762 out_unmap_reports: 763 iounmap(priv->reports); 764 out_unmap_ctrl: 765 iounmap(priv->ctrl); 766 out_unmap_context: 767 lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, xdr_lpar, 768 XDR_BUF_SIZE, CBE_IOPTE_M); 769 out_free_context: 770 lv1_gpu_context_free(priv->context_handle); 771 out_free_memory: 772 lv1_gpu_memory_free(priv->memory_handle); 773 out_close_gpu: 774 ps3_close_hv_device(dev); 775 out_free_xdr_buf: 776 free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE)); 777 fail_free_priv: 778 kfree(priv); 779 ps3_system_bus_set_drvdata(dev, NULL); 780 fail: 781 return error; 782 } 783 784 static void ps3vram_remove(struct ps3_system_bus_device *dev) 785 { 786 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); 787 788 del_gendisk(priv->gendisk); 789 put_disk(priv->gendisk); 790 remove_proc_entry(DEVICE_NAME, NULL); 791 ps3vram_cache_cleanup(dev); 792 iounmap(priv->reports); 793 iounmap(priv->ctrl); 794 lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, 795 ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)), 796 XDR_BUF_SIZE, CBE_IOPTE_M); 797 lv1_gpu_context_free(priv->context_handle); 798 lv1_gpu_memory_free(priv->memory_handle); 799 ps3_close_hv_device(dev); 800 free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE)); 801 kfree(priv); 802 ps3_system_bus_set_drvdata(dev, NULL); 803 } 804 805 static struct ps3_system_bus_driver ps3vram = { 806 .match_id = PS3_MATCH_ID_GPU, 807 .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK, 808 .core.name = DEVICE_NAME, 809 .core.owner = THIS_MODULE, 810 .probe = ps3vram_probe, 811 .remove = ps3vram_remove, 812 .shutdown = ps3vram_remove, 813 }; 814 815 816 static int __init ps3vram_init(void) 817 { 818 int error; 819 820 if (!firmware_has_feature(FW_FEATURE_PS3_LV1)) 821 return -ENODEV; 822 823 error = register_blkdev(0, DEVICE_NAME); 824 if (error <= 0) { 825 pr_err("%s: register_blkdev failed %d\n", DEVICE_NAME, error); 826 return error; 827 } 828 ps3vram_major = error; 829 830 pr_info("%s: registered block device major %d\n", DEVICE_NAME, 831 ps3vram_major); 832 833 error = ps3_system_bus_driver_register(&ps3vram); 834 if (error) 835 unregister_blkdev(ps3vram_major, DEVICE_NAME); 836 837 return error; 838 } 839 840 static void __exit ps3vram_exit(void) 841 { 842 ps3_system_bus_driver_unregister(&ps3vram); 843 unregister_blkdev(ps3vram_major, DEVICE_NAME); 844 } 845 846 module_init(ps3vram_init); 847 module_exit(ps3vram_exit); 848 849 MODULE_LICENSE("GPL"); 850 MODULE_DESCRIPTION("PS3 Video RAM Storage Driver"); 851 MODULE_AUTHOR("Sony Corporation"); 852 MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK); 853