xref: /linux/tools/testing/selftests/kvm/include/x86/svm.h (revision 69050f8d6d075dc01af7a5f2f550a8067510366f) 
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef SELFTEST_KVM_SVM_H
3 #define SELFTEST_KVM_SVM_H
4 
5 enum {
6 	INTERCEPT_INTR,
7 	INTERCEPT_NMI,
8 	INTERCEPT_SMI,
9 	INTERCEPT_INIT,
10 	INTERCEPT_VINTR,
11 	INTERCEPT_SELECTIVE_CR0,
12 	INTERCEPT_STORE_IDTR,
13 	INTERCEPT_STORE_GDTR,
14 	INTERCEPT_STORE_LDTR,
15 	INTERCEPT_STORE_TR,
16 	INTERCEPT_LOAD_IDTR,
17 	INTERCEPT_LOAD_GDTR,
18 	INTERCEPT_LOAD_LDTR,
19 	INTERCEPT_LOAD_TR,
20 	INTERCEPT_RDTSC,
21 	INTERCEPT_RDPMC,
22 	INTERCEPT_PUSHF,
23 	INTERCEPT_POPF,
24 	INTERCEPT_CPUID,
25 	INTERCEPT_RSM,
26 	INTERCEPT_IRET,
27 	INTERCEPT_INTn,
28 	INTERCEPT_INVD,
29 	INTERCEPT_PAUSE,
30 	INTERCEPT_HLT,
31 	INTERCEPT_INVLPG,
32 	INTERCEPT_INVLPGA,
33 	INTERCEPT_IOIO_PROT,
34 	INTERCEPT_MSR_PROT,
35 	INTERCEPT_TASK_SWITCH,
36 	INTERCEPT_FERR_FREEZE,
37 	INTERCEPT_SHUTDOWN,
38 	INTERCEPT_VMRUN,
39 	INTERCEPT_VMMCALL,
40 	INTERCEPT_VMLOAD,
41 	INTERCEPT_VMSAVE,
42 	INTERCEPT_STGI,
43 	INTERCEPT_CLGI,
44 	INTERCEPT_SKINIT,
45 	INTERCEPT_RDTSCP,
46 	INTERCEPT_ICEBP,
47 	INTERCEPT_WBINVD,
48 	INTERCEPT_MONITOR,
49 	INTERCEPT_MWAIT,
50 	INTERCEPT_MWAIT_COND,
51 	INTERCEPT_XSETBV,
52 	INTERCEPT_RDPRU,
53 };
54 
55 struct hv_vmcb_enlightenments {
56 	struct __packed hv_enlightenments_control {
57 		u32 nested_flush_hypercall:1;
58 		u32 msr_bitmap:1;
59 		u32 enlightened_npt_tlb: 1;
60 		u32 reserved:29;
61 	} __packed hv_enlightenments_control;
62 	u32 hv_vp_id;
63 	u64 hv_vm_id;
64 	u64 partition_assist_page;
65 	u64 reserved;
66 } __packed;
67 
68 /*
69  * Hyper-V uses the software reserved clean bit in VMCB
70  */
71 #define HV_VMCB_NESTED_ENLIGHTENMENTS (1U << 31)
72 
73 /* Synthetic VM-Exit */
74 #define HV_SVM_EXITCODE_ENL			0xf0000000
75 #define HV_SVM_ENL_EXITCODE_TRAP_AFTER_FLUSH	(1)
76 
77 struct __attribute__ ((__packed__)) vmcb_control_area {
78 	u32 intercept_cr;
79 	u32 intercept_dr;
80 	u32 intercept_exceptions;
81 	u64 intercept;
82 	u8 reserved_1[40];
83 	u16 pause_filter_thresh;
84 	u16 pause_filter_count;
85 	u64 iopm_base_pa;
86 	u64 msrpm_base_pa;
87 	u64 tsc_offset;
88 	u32 asid;
89 	u8 tlb_ctl;
90 	u8 reserved_2[3];
91 	u32 int_ctl;
92 	u32 int_vector;
93 	u32 int_state;
94 	u8 reserved_3[4];
95 	u64 exit_code;
96 	u64 exit_info_1;
97 	u64 exit_info_2;
98 	u32 exit_int_info;
99 	u32 exit_int_info_err;
100 	u64 nested_ctl;
101 	u64 avic_vapic_bar;
102 	u8 reserved_4[8];
103 	u32 event_inj;
104 	u32 event_inj_err;
105 	u64 nested_cr3;
106 	u64 virt_ext;
107 	u32 clean;
108 	u32 reserved_5;
109 	u64 next_rip;
110 	u8 insn_len;
111 	u8 insn_bytes[15];
112 	u64 avic_backing_page;	/* Offset 0xe0 */
113 	u8 reserved_6[8];	/* Offset 0xe8 */
114 	u64 avic_logical_id;	/* Offset 0xf0 */
115 	u64 avic_physical_id;	/* Offset 0xf8 */
116 	u8 reserved_7[8];
117 	u64 vmsa_pa;		/* Used for an SEV-ES guest */
118 	u8 reserved_8[720];
119 	/*
120 	 * Offset 0x3e0, 32 bytes reserved
121 	 * for use by hypervisor/software.
122 	 */
123 	union {
124 		struct hv_vmcb_enlightenments hv_enlightenments;
125 		u8 reserved_sw[32];
126 	};
127 };
128 
129 
130 #define TLB_CONTROL_DO_NOTHING 0
131 #define TLB_CONTROL_FLUSH_ALL_ASID 1
132 #define TLB_CONTROL_FLUSH_ASID 3
133 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
134 
135 #define V_TPR_MASK 0x0f
136 
137 #define V_IRQ_SHIFT 8
138 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
139 
140 #define V_GIF_SHIFT 9
141 #define V_GIF_MASK (1 << V_GIF_SHIFT)
142 
143 #define V_INTR_PRIO_SHIFT 16
144 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
145 
146 #define V_IGN_TPR_SHIFT 20
147 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
148 
149 #define V_INTR_MASKING_SHIFT 24
150 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
151 
152 #define V_GIF_ENABLE_SHIFT 25
153 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
154 
155 #define AVIC_ENABLE_SHIFT 31
156 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
157 
158 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
159 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
160 
161 #define SVM_INTERRUPT_SHADOW_MASK 1
162 
163 #define SVM_IOIO_STR_SHIFT 2
164 #define SVM_IOIO_REP_SHIFT 3
165 #define SVM_IOIO_SIZE_SHIFT 4
166 #define SVM_IOIO_ASIZE_SHIFT 7
167 
168 #define SVM_IOIO_TYPE_MASK 1
169 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
170 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
171 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
172 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
173 
174 #define SVM_VM_CR_VALID_MASK	0x001fULL
175 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
176 #define SVM_VM_CR_SVM_DIS_MASK  0x0010ULL
177 
178 #define SVM_NESTED_CTL_NP_ENABLE	BIT(0)
179 #define SVM_NESTED_CTL_SEV_ENABLE	BIT(1)
180 
181 struct __attribute__ ((__packed__)) vmcb_seg {
182 	u16 selector;
183 	u16 attrib;
184 	u32 limit;
185 	u64 base;
186 };
187 
188 struct __attribute__ ((__packed__)) vmcb_save_area {
189 	struct vmcb_seg es;
190 	struct vmcb_seg cs;
191 	struct vmcb_seg ss;
192 	struct vmcb_seg ds;
193 	struct vmcb_seg fs;
194 	struct vmcb_seg gs;
195 	struct vmcb_seg gdtr;
196 	struct vmcb_seg ldtr;
197 	struct vmcb_seg idtr;
198 	struct vmcb_seg tr;
199 	u8 reserved_1[43];
200 	u8 cpl;
201 	u8 reserved_2[4];
202 	u64 efer;
203 	u8 reserved_3[112];
204 	u64 cr4;
205 	u64 cr3;
206 	u64 cr0;
207 	u64 dr7;
208 	u64 dr6;
209 	u64 rflags;
210 	u64 rip;
211 	u8 reserved_4[88];
212 	u64 rsp;
213 	u8 reserved_5[24];
214 	u64 rax;
215 	u64 star;
216 	u64 lstar;
217 	u64 cstar;
218 	u64 sfmask;
219 	u64 kernel_gs_base;
220 	u64 sysenter_cs;
221 	u64 sysenter_esp;
222 	u64 sysenter_eip;
223 	u64 cr2;
224 	u8 reserved_6[32];
225 	u64 g_pat;
226 	u64 dbgctl;
227 	u64 br_from;
228 	u64 br_to;
229 	u64 last_excp_from;
230 	u64 last_excp_to;
231 };
232 
233 struct __attribute__ ((__packed__)) vmcb {
234 	struct vmcb_control_area control;
235 	struct vmcb_save_area save;
236 };
237 
238 #define SVM_VM_CR_SVM_DISABLE 4
239 
240 #define SVM_SELECTOR_S_SHIFT 4
241 #define SVM_SELECTOR_DPL_SHIFT 5
242 #define SVM_SELECTOR_P_SHIFT 7
243 #define SVM_SELECTOR_AVL_SHIFT 8
244 #define SVM_SELECTOR_L_SHIFT 9
245 #define SVM_SELECTOR_DB_SHIFT 10
246 #define SVM_SELECTOR_G_SHIFT 11
247 
248 #define SVM_SELECTOR_TYPE_MASK (0xf)
249 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
250 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
251 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
252 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
253 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
254 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
255 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
256 
257 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
258 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
259 #define SVM_SELECTOR_CODE_MASK (1 << 3)
260 
261 #define INTERCEPT_CR0_READ	0
262 #define INTERCEPT_CR3_READ	3
263 #define INTERCEPT_CR4_READ	4
264 #define INTERCEPT_CR8_READ	8
265 #define INTERCEPT_CR0_WRITE	(16 + 0)
266 #define INTERCEPT_CR3_WRITE	(16 + 3)
267 #define INTERCEPT_CR4_WRITE	(16 + 4)
268 #define INTERCEPT_CR8_WRITE	(16 + 8)
269 
270 #define INTERCEPT_DR0_READ	0
271 #define INTERCEPT_DR1_READ	1
272 #define INTERCEPT_DR2_READ	2
273 #define INTERCEPT_DR3_READ	3
274 #define INTERCEPT_DR4_READ	4
275 #define INTERCEPT_DR5_READ	5
276 #define INTERCEPT_DR6_READ	6
277 #define INTERCEPT_DR7_READ	7
278 #define INTERCEPT_DR0_WRITE	(16 + 0)
279 #define INTERCEPT_DR1_WRITE	(16 + 1)
280 #define INTERCEPT_DR2_WRITE	(16 + 2)
281 #define INTERCEPT_DR3_WRITE	(16 + 3)
282 #define INTERCEPT_DR4_WRITE	(16 + 4)
283 #define INTERCEPT_DR5_WRITE	(16 + 5)
284 #define INTERCEPT_DR6_WRITE	(16 + 6)
285 #define INTERCEPT_DR7_WRITE	(16 + 7)
286 
287 #define SVM_EVTINJ_VEC_MASK 0xff
288 
289 #define SVM_EVTINJ_TYPE_SHIFT 8
290 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
291 
292 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
293 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
294 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
295 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
296 
297 #define SVM_EVTINJ_VALID (1 << 31)
298 #define SVM_EVTINJ_VALID_ERR (1 << 11)
299 
300 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
301 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
302 
303 #define	SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
304 #define	SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
305 #define	SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
306 #define	SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
307 
308 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
309 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
310 
311 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
312 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
313 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
314 
315 #define SVM_EXITINFO_REG_MASK 0x0F
316 
317 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
318 
319 #endif /* SELFTEST_KVM_SVM_H */
320