1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 /** 30 * DOC: Interrupt Handling 31 * 32 * Interrupts generated within GPU hardware raise interrupt requests that are 33 * passed to amdgpu IRQ handler which is responsible for detecting source and 34 * type of the interrupt and dispatching matching handlers. If handling an 35 * interrupt requires calling kernel functions that may sleep processing is 36 * dispatched to work handlers. 37 * 38 * If MSI functionality is not disabled by module parameter then MSI 39 * support will be enabled. 40 * 41 * For GPU interrupt sources that may be driven by another driver, IRQ domain 42 * support is used (with mapping between virtual and hardware IRQs). 43 */ 44 45 #include <linux/irq.h> 46 #include <linux/pci.h> 47 48 #include <drm/drm_vblank.h> 49 #include <drm/amdgpu_drm.h> 50 #include <drm/drm_drv.h> 51 #include "amdgpu.h" 52 #include "amdgpu_ih.h" 53 #include "atom.h" 54 #include "amdgpu_connectors.h" 55 #include "amdgpu_trace.h" 56 #include "amdgpu_amdkfd.h" 57 #include "amdgpu_ras.h" 58 59 #include <linux/pm_runtime.h> 60 61 #ifdef CONFIG_DRM_AMD_DC 62 #include "amdgpu_dm_irq.h" 63 #endif 64 65 #define AMDGPU_WAIT_IDLE_TIMEOUT 200 66 67 const char *soc15_ih_clientid_name[] = { 68 "IH", 69 "SDMA2 or ACP", 70 "ATHUB", 71 "BIF", 72 "SDMA3 or DCE", 73 "SDMA4 or ISP", 74 "VMC1 or PCIE0", 75 "RLC", 76 "SDMA0", 77 "SDMA1", 78 "SE0SH", 79 "SE1SH", 80 "SE2SH", 81 "SE3SH", 82 "VCN1 or UVD1", 83 "THM", 84 "VCN or UVD", 85 "SDMA5 or VCE0", 86 "VMC", 87 "SDMA6 or XDMA", 88 "GRBM_CP", 89 "ATS", 90 "ROM_SMUIO", 91 "DF", 92 "SDMA7 or VCE1", 93 "PWR", 94 "reserved", 95 "UTCL2", 96 "EA", 97 "UTCL2LOG", 98 "MP0", 99 "MP1" 100 }; 101 102 const char *soc_v1_0_ih_clientid_name[] = { 103 "IH", 104 "Reserved", 105 "ATHUB", 106 "BIF", 107 "Reserved", 108 "Reserved", 109 "Reserved", 110 "RLC", 111 "Reserved", 112 "Reserved", 113 "GFX", 114 "IMU", 115 "Reserved", 116 "Reserved", 117 "VCN1 or UVD1", 118 "THM", 119 "VCN or UVD", 120 "Reserved", 121 "VMC", 122 "Reserved", 123 "GRBM_CP", 124 "GC_AID", 125 "ROM_SMUIO", 126 "DF", 127 "Reserved", 128 "PWR", 129 "LSDMA", 130 "GC_UTCL2", 131 "nHT", 132 "Reserved", 133 "MP0", 134 "MP1", 135 }; 136 137 const int node_id_to_phys_map[NODEID_MAX] = { 138 [AID0_NODEID] = 0, 139 [XCD0_NODEID] = 0, 140 [XCD1_NODEID] = 1, 141 [AID1_NODEID] = 1, 142 [XCD2_NODEID] = 2, 143 [XCD3_NODEID] = 3, 144 [AID2_NODEID] = 2, 145 [XCD4_NODEID] = 4, 146 [XCD5_NODEID] = 5, 147 [AID3_NODEID] = 3, 148 [XCD6_NODEID] = 6, 149 [XCD7_NODEID] = 7, 150 }; 151 152 /** 153 * amdgpu_irq_disable_all - disable *all* interrupts 154 * 155 * @adev: amdgpu device pointer 156 * 157 * Disable all types of interrupts from all sources. 158 */ 159 void amdgpu_irq_disable_all(struct amdgpu_device *adev) 160 { 161 unsigned long irqflags; 162 unsigned int i, j, k; 163 int r; 164 165 spin_lock_irqsave(&adev->irq.lock, irqflags); 166 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 167 if (!adev->irq.client[i].sources) 168 continue; 169 170 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 171 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 172 173 if (!src || !src->funcs->set || !src->num_types) 174 continue; 175 176 for (k = 0; k < src->num_types; ++k) { 177 r = src->funcs->set(adev, src, k, 178 AMDGPU_IRQ_STATE_DISABLE); 179 if (r) 180 dev_err(adev->dev, 181 "error disabling interrupt (%d)\n", 182 r); 183 } 184 } 185 } 186 spin_unlock_irqrestore(&adev->irq.lock, irqflags); 187 } 188 189 /** 190 * amdgpu_irq_handler - IRQ handler 191 * 192 * @irq: IRQ number (unused) 193 * @arg: pointer to DRM device 194 * 195 * IRQ handler for amdgpu driver (all ASICs). 196 * 197 * Returns: 198 * result of handling the IRQ, as defined by &irqreturn_t 199 */ 200 static irqreturn_t amdgpu_irq_handler(int irq, void *arg) 201 { 202 struct drm_device *dev = (struct drm_device *) arg; 203 struct amdgpu_device *adev = drm_to_adev(dev); 204 irqreturn_t ret; 205 206 ret = amdgpu_ih_process(adev, &adev->irq.ih); 207 if (ret == IRQ_HANDLED) 208 pm_runtime_mark_last_busy(dev->dev); 209 210 amdgpu_ras_interrupt_fatal_error_handler(adev); 211 212 return ret; 213 } 214 215 /** 216 * amdgpu_irq_handle_ih1 - kick of processing for IH1 217 * 218 * @work: work structure in struct amdgpu_irq 219 * 220 * Kick of processing IH ring 1. 221 */ 222 static void amdgpu_irq_handle_ih1(struct work_struct *work) 223 { 224 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 225 irq.ih1_work); 226 227 amdgpu_ih_process(adev, &adev->irq.ih1); 228 } 229 230 /** 231 * amdgpu_irq_handle_ih2 - kick of processing for IH2 232 * 233 * @work: work structure in struct amdgpu_irq 234 * 235 * Kick of processing IH ring 2. 236 */ 237 static void amdgpu_irq_handle_ih2(struct work_struct *work) 238 { 239 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 240 irq.ih2_work); 241 242 amdgpu_ih_process(adev, &adev->irq.ih2); 243 } 244 245 /** 246 * amdgpu_irq_handle_ih_soft - kick of processing for ih_soft 247 * 248 * @work: work structure in struct amdgpu_irq 249 * 250 * Kick of processing IH soft ring. 251 */ 252 static void amdgpu_irq_handle_ih_soft(struct work_struct *work) 253 { 254 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 255 irq.ih_soft_work); 256 257 amdgpu_ih_process(adev, &adev->irq.ih_soft); 258 } 259 260 /** 261 * amdgpu_msi_ok - check whether MSI functionality is enabled 262 * 263 * @adev: amdgpu device pointer (unused) 264 * 265 * Checks whether MSI functionality has been disabled via module parameter 266 * (all ASICs). 267 * 268 * Returns: 269 * *true* if MSIs are allowed to be enabled or *false* otherwise 270 */ 271 static bool amdgpu_msi_ok(struct amdgpu_device *adev) 272 { 273 if (amdgpu_msi == 1) 274 return true; 275 else if (amdgpu_msi == 0) 276 return false; 277 278 return true; 279 } 280 281 void amdgpu_restore_msix(struct amdgpu_device *adev) 282 { 283 u16 ctrl; 284 285 pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 286 if (!(ctrl & PCI_MSIX_FLAGS_ENABLE)) 287 return; 288 289 /* VF FLR */ 290 ctrl &= ~PCI_MSIX_FLAGS_ENABLE; 291 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl); 292 ctrl |= PCI_MSIX_FLAGS_ENABLE; 293 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl); 294 } 295 296 /** 297 * amdgpu_irq_init - initialize interrupt handling 298 * 299 * @adev: amdgpu device pointer 300 * 301 * Sets up work functions for hotplug and reset interrupts, enables MSI 302 * functionality, initializes vblank, hotplug and reset interrupt handling. 303 * 304 * Returns: 305 * 0 on success or error code on failure 306 */ 307 int amdgpu_irq_init(struct amdgpu_device *adev) 308 { 309 unsigned int irq, flags; 310 int r; 311 312 spin_lock_init(&adev->irq.lock); 313 314 /* Enable MSI if not disabled by module parameter */ 315 adev->irq.msi_enabled = false; 316 317 if (!amdgpu_msi_ok(adev)) 318 flags = PCI_IRQ_INTX; 319 else 320 flags = PCI_IRQ_ALL_TYPES; 321 322 /* we only need one vector */ 323 r = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags); 324 if (r < 0) { 325 dev_err(adev->dev, "Failed to alloc msi vectors\n"); 326 return r; 327 } 328 329 if (amdgpu_msi_ok(adev)) { 330 adev->irq.msi_enabled = true; 331 dev_dbg(adev->dev, "using MSI/MSI-X.\n"); 332 } 333 334 INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1); 335 INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2); 336 INIT_WORK(&adev->irq.ih_soft_work, amdgpu_irq_handle_ih_soft); 337 338 /* Use vector 0 for MSI-X. */ 339 r = pci_irq_vector(adev->pdev, 0); 340 if (r < 0) 341 goto free_vectors; 342 irq = r; 343 344 /* PCI devices require shared interrupts. */ 345 r = request_irq(irq, amdgpu_irq_handler, IRQF_SHARED, adev_to_drm(adev)->driver->name, 346 adev_to_drm(adev)); 347 if (r) 348 goto free_vectors; 349 350 adev->irq.installed = true; 351 adev->irq.irq = irq; 352 adev_to_drm(adev)->max_vblank_count = 0x00ffffff; 353 354 dev_dbg(adev->dev, "irq initialized.\n"); 355 return 0; 356 357 free_vectors: 358 if (adev->irq.msi_enabled) 359 pci_free_irq_vectors(adev->pdev); 360 361 adev->irq.msi_enabled = false; 362 return r; 363 } 364 365 void amdgpu_irq_fini_hw(struct amdgpu_device *adev) 366 { 367 if (adev->irq.installed) { 368 free_irq(adev->irq.irq, adev_to_drm(adev)); 369 adev->irq.installed = false; 370 if (adev->irq.msi_enabled) 371 pci_free_irq_vectors(adev->pdev); 372 } 373 374 amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); 375 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 376 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 377 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 378 } 379 380 /** 381 * amdgpu_irq_fini_sw - shut down interrupt handling 382 * 383 * @adev: amdgpu device pointer 384 * 385 * Tears down work functions for hotplug and reset interrupts, disables MSI 386 * functionality, shuts down vblank, hotplug and reset interrupt handling, 387 * turns off interrupts from all sources (all ASICs). 388 */ 389 void amdgpu_irq_fini_sw(struct amdgpu_device *adev) 390 { 391 unsigned int i, j; 392 393 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 394 if (!adev->irq.client[i].sources) 395 continue; 396 397 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 398 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 399 400 if (!src) 401 continue; 402 403 kfree(src->enabled_types); 404 src->enabled_types = NULL; 405 } 406 kfree(adev->irq.client[i].sources); 407 adev->irq.client[i].sources = NULL; 408 } 409 } 410 411 /** 412 * amdgpu_irq_add_id - register IRQ source 413 * 414 * @adev: amdgpu device pointer 415 * @client_id: client id 416 * @src_id: source id 417 * @source: IRQ source pointer 418 * 419 * Registers IRQ source on a client. 420 * 421 * Returns: 422 * 0 on success or error code otherwise 423 */ 424 int amdgpu_irq_add_id(struct amdgpu_device *adev, 425 unsigned int client_id, unsigned int src_id, 426 struct amdgpu_irq_src *source) 427 { 428 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) 429 return -EINVAL; 430 431 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) 432 return -EINVAL; 433 434 if (!source->funcs) 435 return -EINVAL; 436 437 if (!adev->irq.client[client_id].sources) { 438 adev->irq.client[client_id].sources = 439 kzalloc_objs(struct amdgpu_irq_src *, 440 AMDGPU_MAX_IRQ_SRC_ID, GFP_KERNEL); 441 if (!adev->irq.client[client_id].sources) 442 return -ENOMEM; 443 } 444 445 if (adev->irq.client[client_id].sources[src_id] != NULL) 446 return -EINVAL; 447 448 if (source->num_types && !source->enabled_types) { 449 atomic_t *types; 450 451 types = kzalloc_objs(atomic_t, source->num_types, GFP_KERNEL); 452 if (!types) 453 return -ENOMEM; 454 455 source->enabled_types = types; 456 } 457 458 adev->irq.client[client_id].sources[src_id] = source; 459 return 0; 460 } 461 462 /** 463 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks 464 * 465 * @adev: amdgpu device pointer 466 * @ih: interrupt ring instance 467 * 468 * Dispatches IRQ to IP blocks. 469 */ 470 void amdgpu_irq_dispatch(struct amdgpu_device *adev, 471 struct amdgpu_ih_ring *ih) 472 { 473 u32 ring_index = ih->rptr >> 2; 474 struct amdgpu_iv_entry entry; 475 unsigned int client_id, src_id; 476 struct amdgpu_irq_src *src; 477 bool handled = false; 478 int r; 479 480 entry.ih = ih; 481 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index]; 482 483 /* 484 * timestamp is not supported on some legacy SOCs (cik, cz, iceland, 485 * si and tonga), so initialize timestamp and timestamp_src to 0 486 */ 487 entry.timestamp = 0; 488 entry.timestamp_src = 0; 489 490 amdgpu_ih_decode_iv(adev, &entry); 491 492 trace_amdgpu_iv(ih - &adev->irq.ih, &entry); 493 494 client_id = entry.client_id; 495 src_id = entry.src_id; 496 497 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) { 498 dev_dbg(adev->dev, "Invalid client_id in IV: %d\n", client_id); 499 500 } else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) { 501 dev_dbg(adev->dev, "Invalid src_id in IV: %d\n", src_id); 502 503 } else if (((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) || 504 (client_id == SOC15_IH_CLIENTID_ISP)) && 505 adev->irq.virq[src_id]) { 506 generic_handle_domain_irq(adev->irq.domain, src_id); 507 508 } else if (!adev->irq.client[client_id].sources) { 509 dev_dbg(adev->dev, 510 "Unregistered interrupt client_id: %d src_id: %d\n", 511 client_id, src_id); 512 513 } else if ((src = adev->irq.client[client_id].sources[src_id])) { 514 r = src->funcs->process(adev, src, &entry); 515 if (r < 0) 516 dev_err(adev->dev, "error processing interrupt (%d)\n", 517 r); 518 else if (r) 519 handled = true; 520 521 } else { 522 dev_dbg(adev->dev, 523 "Unregistered interrupt src_id: %d of client_id:%d\n", 524 src_id, client_id); 525 } 526 527 /* Send it to amdkfd as well if it isn't already handled */ 528 if (!handled) 529 amdgpu_amdkfd_interrupt(adev, entry.iv_entry); 530 531 if (amdgpu_ih_ts_after(ih->processed_timestamp, entry.timestamp)) 532 ih->processed_timestamp = entry.timestamp; 533 } 534 535 /** 536 * amdgpu_irq_delegate - delegate IV to soft IH ring 537 * 538 * @adev: amdgpu device pointer 539 * @entry: IV entry 540 * @num_dw: size of IV 541 * 542 * Delegate the IV to the soft IH ring and schedule processing of it. Used 543 * if the hardware delegation to IH1 or IH2 doesn't work for some reason. 544 */ 545 void amdgpu_irq_delegate(struct amdgpu_device *adev, 546 struct amdgpu_iv_entry *entry, 547 unsigned int num_dw) 548 { 549 amdgpu_ih_ring_write(adev, &adev->irq.ih_soft, entry->iv_entry, num_dw); 550 schedule_work(&adev->irq.ih_soft_work); 551 } 552 553 /** 554 * amdgpu_irq_update - update hardware interrupt state 555 * 556 * @adev: amdgpu device pointer 557 * @src: interrupt source pointer 558 * @type: type of interrupt 559 * 560 * Updates interrupt state for the specific source (all ASICs). 561 */ 562 int amdgpu_irq_update(struct amdgpu_device *adev, 563 struct amdgpu_irq_src *src, unsigned int type) 564 { 565 unsigned long irqflags; 566 enum amdgpu_interrupt_state state; 567 int r; 568 569 spin_lock_irqsave(&adev->irq.lock, irqflags); 570 571 /* We need to determine after taking the lock, otherwise 572 * we might disable just enabled interrupts again 573 */ 574 if (amdgpu_irq_enabled(adev, src, type)) 575 state = AMDGPU_IRQ_STATE_ENABLE; 576 else 577 state = AMDGPU_IRQ_STATE_DISABLE; 578 579 r = src->funcs->set(adev, src, type, state); 580 spin_unlock_irqrestore(&adev->irq.lock, irqflags); 581 return r; 582 } 583 584 /** 585 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources 586 * 587 * @adev: amdgpu device pointer 588 * 589 * Updates state of all types of interrupts on all sources on resume after 590 * reset. 591 */ 592 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev) 593 { 594 int i, j, k; 595 596 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) 597 amdgpu_restore_msix(adev); 598 599 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 600 if (!adev->irq.client[i].sources) 601 continue; 602 603 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 604 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 605 606 if (!src || !src->funcs || !src->funcs->set) 607 continue; 608 for (k = 0; k < src->num_types; k++) 609 amdgpu_irq_update(adev, src, k); 610 } 611 } 612 } 613 614 /** 615 * amdgpu_irq_get - enable interrupt 616 * 617 * @adev: amdgpu device pointer 618 * @src: interrupt source pointer 619 * @type: type of interrupt 620 * 621 * Enables specified type of interrupt on the specified source (all ASICs). 622 * 623 * Returns: 624 * 0 on success or error code otherwise 625 */ 626 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 627 unsigned int type) 628 { 629 if (!adev->irq.installed) 630 return -ENOENT; 631 632 if (type >= src->num_types) 633 return -EINVAL; 634 635 if (!src->enabled_types || !src->funcs->set) 636 return -EINVAL; 637 638 if (atomic_inc_return(&src->enabled_types[type]) == 1) 639 return amdgpu_irq_update(adev, src, type); 640 641 return 0; 642 } 643 644 /** 645 * amdgpu_irq_put - disable interrupt 646 * 647 * @adev: amdgpu device pointer 648 * @src: interrupt source pointer 649 * @type: type of interrupt 650 * 651 * Enables specified type of interrupt on the specified source (all ASICs). 652 * 653 * Returns: 654 * 0 on success or error code otherwise 655 */ 656 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 657 unsigned int type) 658 { 659 /* When the threshold is reached,the interrupt source may not be enabled.return -EINVAL */ 660 if (amdgpu_ras_is_rma(adev) && !amdgpu_irq_enabled(adev, src, type)) 661 return -EINVAL; 662 663 if (!adev->irq.installed) 664 return -ENOENT; 665 666 if (type >= src->num_types) 667 return -EINVAL; 668 669 if (!src->enabled_types || !src->funcs->set) 670 return -EINVAL; 671 672 if (WARN_ON(!amdgpu_irq_enabled(adev, src, type))) 673 return -EINVAL; 674 675 if (atomic_dec_and_test(&src->enabled_types[type])) 676 return amdgpu_irq_update(adev, src, type); 677 678 return 0; 679 } 680 681 /** 682 * amdgpu_irq_enabled - check whether interrupt is enabled or not 683 * 684 * @adev: amdgpu device pointer 685 * @src: interrupt source pointer 686 * @type: type of interrupt 687 * 688 * Checks whether the given type of interrupt is enabled on the given source. 689 * 690 * Returns: 691 * *true* if interrupt is enabled, *false* if interrupt is disabled or on 692 * invalid parameters 693 */ 694 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 695 unsigned int type) 696 { 697 if (!adev->irq.installed) 698 return false; 699 700 if (type >= src->num_types) 701 return false; 702 703 if (!src->enabled_types || !src->funcs->set) 704 return false; 705 706 return !!atomic_read(&src->enabled_types[type]); 707 } 708 709 /* XXX: Generic IRQ handling */ 710 static void amdgpu_irq_mask(struct irq_data *irqd) 711 { 712 /* XXX */ 713 } 714 715 static void amdgpu_irq_unmask(struct irq_data *irqd) 716 { 717 /* XXX */ 718 } 719 720 /* amdgpu hardware interrupt chip descriptor */ 721 static struct irq_chip amdgpu_irq_chip = { 722 .name = "amdgpu-ih", 723 .irq_mask = amdgpu_irq_mask, 724 .irq_unmask = amdgpu_irq_unmask, 725 }; 726 727 /** 728 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers 729 * 730 * @d: amdgpu IRQ domain pointer (unused) 731 * @irq: virtual IRQ number 732 * @hwirq: hardware irq number 733 * 734 * Current implementation assigns simple interrupt handler to the given virtual 735 * IRQ. 736 * 737 * Returns: 738 * 0 on success or error code otherwise 739 */ 740 static int amdgpu_irqdomain_map(struct irq_domain *d, 741 unsigned int irq, irq_hw_number_t hwirq) 742 { 743 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID) 744 return -EPERM; 745 746 irq_set_chip_and_handler(irq, 747 &amdgpu_irq_chip, handle_simple_irq); 748 return 0; 749 } 750 751 /* Implementation of methods for amdgpu IRQ domain */ 752 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = { 753 .map = amdgpu_irqdomain_map, 754 }; 755 756 /** 757 * amdgpu_irq_add_domain - create a linear IRQ domain 758 * 759 * @adev: amdgpu device pointer 760 * 761 * Creates an IRQ domain for GPU interrupt sources 762 * that may be driven by another driver (e.g., ACP). 763 * 764 * Returns: 765 * 0 on success or error code otherwise 766 */ 767 int amdgpu_irq_add_domain(struct amdgpu_device *adev) 768 { 769 adev->irq.domain = irq_domain_create_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID, 770 &amdgpu_hw_irqdomain_ops, adev); 771 if (!adev->irq.domain) { 772 dev_err(adev->dev, "GPU irq add domain failed\n"); 773 return -ENODEV; 774 } 775 776 return 0; 777 } 778 779 /** 780 * amdgpu_irq_remove_domain - remove the IRQ domain 781 * 782 * @adev: amdgpu device pointer 783 * 784 * Removes the IRQ domain for GPU interrupt sources 785 * that may be driven by another driver (e.g., ACP). 786 */ 787 void amdgpu_irq_remove_domain(struct amdgpu_device *adev) 788 { 789 if (adev->irq.domain) { 790 irq_domain_remove(adev->irq.domain); 791 adev->irq.domain = NULL; 792 } 793 } 794 795 /** 796 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs 797 * 798 * @adev: amdgpu device pointer 799 * @src_id: IH source id 800 * 801 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ 802 * Use this for components that generate a GPU interrupt, but are driven 803 * by a different driver (e.g., ACP). 804 * 805 * Returns: 806 * Linux IRQ 807 */ 808 unsigned int amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned int src_id) 809 { 810 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id); 811 812 return adev->irq.virq[src_id]; 813 } 814