1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module 3 * 4 * This driver supports the memory controllers found on the Intel 5 * processor family Sandy Bridge. 6 * 7 * Copyright (c) 2011 by: 8 * Mauro Carvalho Chehab 9 */ 10 11 #include <linux/module.h> 12 #include <linux/init.h> 13 #include <linux/pci.h> 14 #include <linux/pci_ids.h> 15 #include <linux/slab.h> 16 #include <linux/delay.h> 17 #include <linux/edac.h> 18 #include <linux/mmzone.h> 19 #include <linux/smp.h> 20 #include <linux/bitmap.h> 21 #include <linux/math64.h> 22 #include <linux/mod_devicetable.h> 23 #include <asm/cpu_device_id.h> 24 #include <asm/intel-family.h> 25 #include <asm/processor.h> 26 #include <asm/mce.h> 27 28 #include "edac_module.h" 29 30 /* Static vars */ 31 static LIST_HEAD(sbridge_edac_list); 32 static char sb_msg[256]; 33 static char sb_msg_full[512]; 34 35 /* 36 * Alter this version for the module when modifications are made 37 */ 38 #define SBRIDGE_REVISION " Ver: 1.1.2 " 39 #define EDAC_MOD_STR "sb_edac" 40 41 /* 42 * Debug macros 43 */ 44 #define sbridge_printk(level, fmt, arg...) \ 45 edac_printk(level, "sbridge", fmt, ##arg) 46 47 #define sbridge_mc_printk(mci, level, fmt, arg...) \ 48 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg) 49 50 /* 51 * Get a bit field at register value <v>, from bit <lo> to bit <hi> 52 */ 53 #define GET_BITFIELD(v, lo, hi) \ 54 (((v) & GENMASK_ULL(hi, lo)) >> (lo)) 55 56 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */ 57 static const u32 sbridge_dram_rule[] = { 58 0x80, 0x88, 0x90, 0x98, 0xa0, 59 0xa8, 0xb0, 0xb8, 0xc0, 0xc8, 60 }; 61 62 static const u32 ibridge_dram_rule[] = { 63 0x60, 0x68, 0x70, 0x78, 0x80, 64 0x88, 0x90, 0x98, 0xa0, 0xa8, 65 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, 66 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, 67 }; 68 69 static const u32 knl_dram_rule[] = { 70 0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */ 71 0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */ 72 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */ 73 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */ 74 0x100, 0x108, 0x110, 0x118, /* 20-23 */ 75 }; 76 77 #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0) 78 #define A7MODE(reg) GET_BITFIELD(reg, 26, 26) 79 80 static char *show_dram_attr(u32 attr) 81 { 82 switch (attr) { 83 case 0: 84 return "DRAM"; 85 case 1: 86 return "MMCFG"; 87 case 2: 88 return "NXM"; 89 default: 90 return "unknown"; 91 } 92 } 93 94 static const u32 sbridge_interleave_list[] = { 95 0x84, 0x8c, 0x94, 0x9c, 0xa4, 96 0xac, 0xb4, 0xbc, 0xc4, 0xcc, 97 }; 98 99 static const u32 ibridge_interleave_list[] = { 100 0x64, 0x6c, 0x74, 0x7c, 0x84, 101 0x8c, 0x94, 0x9c, 0xa4, 0xac, 102 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, 103 0xdc, 0xe4, 0xec, 0xf4, 0xfc, 104 }; 105 106 static const u32 knl_interleave_list[] = { 107 0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */ 108 0x8c, 0x94, 0x9c, 0xa4, 0xac, /* 5-9 */ 109 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, /* 10-14 */ 110 0xdc, 0xe4, 0xec, 0xf4, 0xfc, /* 15-19 */ 111 0x104, 0x10c, 0x114, 0x11c, /* 20-23 */ 112 }; 113 #define MAX_INTERLEAVE \ 114 (MAX_T(unsigned int, ARRAY_SIZE(sbridge_interleave_list), \ 115 MAX_T(unsigned int, ARRAY_SIZE(ibridge_interleave_list), \ 116 ARRAY_SIZE(knl_interleave_list)))) 117 118 struct interleave_pkg { 119 unsigned char start; 120 unsigned char end; 121 }; 122 123 static const struct interleave_pkg sbridge_interleave_pkg[] = { 124 { 0, 2 }, 125 { 3, 5 }, 126 { 8, 10 }, 127 { 11, 13 }, 128 { 16, 18 }, 129 { 19, 21 }, 130 { 24, 26 }, 131 { 27, 29 }, 132 }; 133 134 static const struct interleave_pkg ibridge_interleave_pkg[] = { 135 { 0, 3 }, 136 { 4, 7 }, 137 { 8, 11 }, 138 { 12, 15 }, 139 { 16, 19 }, 140 { 20, 23 }, 141 { 24, 27 }, 142 { 28, 31 }, 143 }; 144 145 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg, 146 int interleave) 147 { 148 return GET_BITFIELD(reg, table[interleave].start, 149 table[interleave].end); 150 } 151 152 /* Devices 12 Function 7 */ 153 154 #define TOLM 0x80 155 #define TOHM 0x84 156 #define HASWELL_TOLM 0xd0 157 #define HASWELL_TOHM_0 0xd4 158 #define HASWELL_TOHM_1 0xd8 159 #define KNL_TOLM 0xd0 160 #define KNL_TOHM_0 0xd4 161 #define KNL_TOHM_1 0xd8 162 163 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff) 164 #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff) 165 166 /* Device 13 Function 6 */ 167 168 #define SAD_TARGET 0xf0 169 170 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11) 171 172 #define SOURCE_ID_KNL(reg) GET_BITFIELD(reg, 12, 14) 173 174 #define SAD_CONTROL 0xf4 175 176 /* Device 14 function 0 */ 177 178 static const u32 tad_dram_rule[] = { 179 0x40, 0x44, 0x48, 0x4c, 180 0x50, 0x54, 0x58, 0x5c, 181 0x60, 0x64, 0x68, 0x6c, 182 }; 183 #define MAX_TAD ARRAY_SIZE(tad_dram_rule) 184 185 #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff) 186 #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11) 187 #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9) 188 #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7) 189 #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5) 190 #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3) 191 #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1) 192 193 /* Device 15, function 0 */ 194 195 #define MCMTR 0x7c 196 #define KNL_MCMTR 0x624 197 198 #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2) 199 #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1) 200 #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0) 201 202 /* Device 15, function 1 */ 203 204 #define RASENABLES 0xac 205 #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0) 206 207 /* Device 15, functions 2-5 */ 208 209 static const int mtr_regs[] = { 210 0x80, 0x84, 0x88, 211 }; 212 213 static const int knl_mtr_reg = 0xb60; 214 215 #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19) 216 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14) 217 #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13) 218 #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4) 219 #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1) 220 221 static const u32 tad_ch_nilv_offset[] = { 222 0x90, 0x94, 0x98, 0x9c, 223 0xa0, 0xa4, 0xa8, 0xac, 224 0xb0, 0xb4, 0xb8, 0xbc, 225 }; 226 #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29) 227 #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26) 228 229 static const u32 rir_way_limit[] = { 230 0x108, 0x10c, 0x110, 0x114, 0x118, 231 }; 232 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit) 233 234 #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31) 235 #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29) 236 237 #define MAX_RIR_WAY 8 238 239 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = { 240 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c }, 241 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c }, 242 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c }, 243 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c }, 244 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc }, 245 }; 246 247 #define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \ 248 GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19)) 249 250 #define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \ 251 GET_BITFIELD(reg, 2, 15) : GET_BITFIELD(reg, 2, 14)) 252 253 /* Device 16, functions 2-7 */ 254 255 /* 256 * FIXME: Implement the error count reads directly 257 */ 258 259 #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31) 260 #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30) 261 #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15) 262 #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14) 263 264 #if 0 /* Currently unused*/ 265 static const u32 correrrcnt[] = { 266 0x104, 0x108, 0x10c, 0x110, 267 }; 268 269 static const u32 correrrthrsld[] = { 270 0x11c, 0x120, 0x124, 0x128, 271 }; 272 #endif 273 274 #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30) 275 #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14) 276 277 278 /* Device 17, function 0 */ 279 280 #define SB_RANK_CFG_A 0x0328 281 282 #define IB_RANK_CFG_A 0x0320 283 284 /* 285 * sbridge structs 286 */ 287 288 #define NUM_CHANNELS 6 /* Max channels per MC */ 289 #define MAX_DIMMS 3 /* Max DIMMS per channel */ 290 #define KNL_MAX_CHAS 38 /* KNL max num. of Cache Home Agents */ 291 #define KNL_MAX_CHANNELS 6 /* KNL max num. of PCI channels */ 292 #define KNL_MAX_EDCS 8 /* Embedded DRAM controllers */ 293 #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */ 294 295 enum type { 296 SANDY_BRIDGE, 297 IVY_BRIDGE, 298 HASWELL, 299 BROADWELL, 300 KNIGHTS_LANDING, 301 }; 302 303 enum domain { 304 IMC0 = 0, 305 IMC1, 306 SOCK, 307 }; 308 309 enum mirroring_mode { 310 NON_MIRRORING, 311 ADDR_RANGE_MIRRORING, 312 FULL_MIRRORING, 313 }; 314 315 struct sbridge_pvt; 316 struct sbridge_info { 317 enum type type; 318 u32 mcmtr; 319 u32 rankcfgr; 320 u64 (*get_tolm)(struct sbridge_pvt *pvt); 321 u64 (*get_tohm)(struct sbridge_pvt *pvt); 322 u64 (*rir_limit)(u32 reg); 323 u64 (*sad_limit)(u32 reg); 324 u32 (*interleave_mode)(u32 reg); 325 u32 (*dram_attr)(u32 reg); 326 const u32 *dram_rule; 327 const u32 *interleave_list; 328 const struct interleave_pkg *interleave_pkg; 329 u8 max_sad; 330 u8 (*get_node_id)(struct sbridge_pvt *pvt); 331 u8 (*get_ha)(u8 bank); 332 enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt); 333 enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr); 334 struct pci_dev *pci_vtd; 335 }; 336 337 struct sbridge_channel { 338 u32 ranks; 339 u32 dimms; 340 struct dimm { 341 u32 rowbits; 342 u32 colbits; 343 u32 bank_xor_enable; 344 u32 amap_fine; 345 } dimm[MAX_DIMMS]; 346 }; 347 348 struct pci_id_descr { 349 int dev_id; 350 int optional; 351 enum domain dom; 352 }; 353 354 struct pci_id_table { 355 const struct pci_id_descr *descr; 356 int n_devs_per_imc; 357 int n_devs_per_sock; 358 int n_imcs_per_sock; 359 enum type type; 360 }; 361 362 struct sbridge_dev { 363 struct list_head list; 364 int seg; 365 u8 bus, mc; 366 u8 node_id, source_id; 367 struct pci_dev **pdev; 368 enum domain dom; 369 int n_devs; 370 int i_devs; 371 struct mem_ctl_info *mci; 372 }; 373 374 struct knl_pvt { 375 struct pci_dev *pci_cha[KNL_MAX_CHAS]; 376 struct pci_dev *pci_channel[KNL_MAX_CHANNELS]; 377 struct pci_dev *pci_mc0; 378 struct pci_dev *pci_mc1; 379 struct pci_dev *pci_mc0_misc; 380 struct pci_dev *pci_mc1_misc; 381 struct pci_dev *pci_mc_info; /* tolm, tohm */ 382 }; 383 384 struct sbridge_pvt { 385 /* Devices per socket */ 386 struct pci_dev *pci_ddrio; 387 struct pci_dev *pci_sad0, *pci_sad1; 388 struct pci_dev *pci_br0, *pci_br1; 389 /* Devices per memory controller */ 390 struct pci_dev *pci_ha, *pci_ta, *pci_ras; 391 struct pci_dev *pci_tad[NUM_CHANNELS]; 392 393 struct sbridge_dev *sbridge_dev; 394 395 struct sbridge_info info; 396 struct sbridge_channel channel[NUM_CHANNELS]; 397 398 /* Memory type detection */ 399 bool is_cur_addr_mirrored, is_lockstep, is_close_pg; 400 bool is_chan_hash; 401 enum mirroring_mode mirror_mode; 402 403 /* Memory description */ 404 u64 tolm, tohm; 405 struct knl_pvt knl; 406 }; 407 408 #define PCI_DESCR(device_id, opt, domain) \ 409 .dev_id = (device_id), \ 410 .optional = opt, \ 411 .dom = domain 412 413 static const struct pci_id_descr pci_dev_descr_sbridge[] = { 414 /* Processor Home Agent */ 415 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0, IMC0) }, 416 417 /* Memory controller */ 418 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0, IMC0) }, 419 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0, IMC0) }, 420 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0, IMC0) }, 421 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0, IMC0) }, 422 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0, IMC0) }, 423 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0, IMC0) }, 424 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1, SOCK) }, 425 426 /* System Address Decoder */ 427 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0, SOCK) }, 428 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0, SOCK) }, 429 430 /* Broadcast Registers */ 431 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0, SOCK) }, 432 }; 433 434 #define PCI_ID_TABLE_ENTRY(A, N, M, T) { \ 435 .descr = A, \ 436 .n_devs_per_imc = N, \ 437 .n_devs_per_sock = ARRAY_SIZE(A), \ 438 .n_imcs_per_sock = M, \ 439 .type = T \ 440 } 441 442 static const struct pci_id_table pci_dev_descr_sbridge_table[] = { 443 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge, ARRAY_SIZE(pci_dev_descr_sbridge), 1, SANDY_BRIDGE), 444 { NULL, } 445 }; 446 447 /* This changes depending if 1HA or 2HA: 448 * 1HA: 449 * 0x0eb8 (17.0) is DDRIO0 450 * 2HA: 451 * 0x0ebc (17.4) is DDRIO0 452 */ 453 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8 454 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc 455 456 /* pci ids */ 457 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0 458 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8 459 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71 460 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa 461 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab 462 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac 463 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead 464 #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8 465 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9 466 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca 467 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60 468 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68 469 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79 470 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a 471 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b 472 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2 0x0e6c 473 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3 0x0e6d 474 475 static const struct pci_id_descr pci_dev_descr_ibridge[] = { 476 /* Processor Home Agent */ 477 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0, IMC0) }, 478 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1, IMC1) }, 479 480 /* Memory controller */ 481 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0, IMC0) }, 482 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0, IMC0) }, 483 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0, IMC0) }, 484 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0, IMC0) }, 485 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0, IMC0) }, 486 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0, IMC0) }, 487 488 /* Optional, mode 2HA */ 489 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1, IMC1) }, 490 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1, IMC1) }, 491 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1, IMC1) }, 492 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1, IMC1) }, 493 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1, IMC1) }, 494 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1, IMC1) }, 495 496 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1, SOCK) }, 497 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1, SOCK) }, 498 499 /* System Address Decoder */ 500 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0, SOCK) }, 501 502 /* Broadcast Registers */ 503 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1, SOCK) }, 504 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0, SOCK) }, 505 506 }; 507 508 static const struct pci_id_table pci_dev_descr_ibridge_table[] = { 509 PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge, 12, 2, IVY_BRIDGE), 510 { NULL, } 511 }; 512 513 /* Haswell support */ 514 /* EN processor: 515 * - 1 IMC 516 * - 3 DDR3 channels, 2 DPC per channel 517 * EP processor: 518 * - 1 or 2 IMC 519 * - 4 DDR4 channels, 3 DPC per channel 520 * EP 4S processor: 521 * - 2 IMC 522 * - 4 DDR4 channels, 3 DPC per channel 523 * EX processor: 524 * - 2 IMC 525 * - each IMC interfaces with a SMI 2 channel 526 * - each SMI channel interfaces with a scalable memory buffer 527 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC 528 */ 529 #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */ 530 #define HASWELL_HASYSDEFEATURE2 0x84 531 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28 532 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0 533 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60 534 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8 535 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM 0x2f71 536 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68 537 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM 0x2f79 538 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc 539 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd 540 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa 541 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab 542 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac 543 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad 544 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a 545 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b 546 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c 547 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d 548 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd 549 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf 550 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9 551 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb 552 static const struct pci_id_descr pci_dev_descr_haswell[] = { 553 /* first item must be the HA */ 554 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0, IMC0) }, 555 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1, IMC1) }, 556 557 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0, IMC0) }, 558 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM, 0, IMC0) }, 559 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0, IMC0) }, 560 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0, IMC0) }, 561 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1, IMC0) }, 562 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1, IMC0) }, 563 564 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1, IMC1) }, 565 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM, 1, IMC1) }, 566 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1, IMC1) }, 567 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1, IMC1) }, 568 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1, IMC1) }, 569 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1, IMC1) }, 570 571 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0, SOCK) }, 572 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0, SOCK) }, 573 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1, SOCK) }, 574 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1, SOCK) }, 575 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1, SOCK) }, 576 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1, SOCK) }, 577 }; 578 579 static const struct pci_id_table pci_dev_descr_haswell_table[] = { 580 PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell, 13, 2, HASWELL), 581 { NULL, } 582 }; 583 584 /* Knight's Landing Support */ 585 /* 586 * KNL's memory channels are swizzled between memory controllers. 587 * MC0 is mapped to CH3,4,5 and MC1 is mapped to CH0,1,2 588 */ 589 #define knl_channel_remap(mc, chan) ((mc) ? (chan) : (chan) + 3) 590 591 /* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */ 592 #define PCI_DEVICE_ID_INTEL_KNL_IMC_MC 0x7840 593 /* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */ 594 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN 0x7843 595 /* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */ 596 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TA 0x7844 597 /* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */ 598 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0 0x782a 599 /* SAD target - 1-29-1 (1 of these) */ 600 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1 0x782b 601 /* Caching / Home Agent */ 602 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHA 0x782c 603 /* Device with TOLM and TOHM, 0-5-0 (1 of these) */ 604 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM 0x7810 605 606 /* 607 * KNL differs from SB, IB, and Haswell in that it has multiple 608 * instances of the same device with the same device ID, so we handle that 609 * by creating as many copies in the table as we expect to find. 610 * (Like device ID must be grouped together.) 611 */ 612 613 static const struct pci_id_descr pci_dev_descr_knl[] = { 614 [0 ... 1] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_MC, 0, IMC0)}, 615 [2 ... 7] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN, 0, IMC0) }, 616 [8] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TA, 0, IMC0) }, 617 [9] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM, 0, IMC0) }, 618 [10] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0, 0, SOCK) }, 619 [11] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1, 0, SOCK) }, 620 [12 ... 49] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHA, 0, SOCK) }, 621 }; 622 623 static const struct pci_id_table pci_dev_descr_knl_table[] = { 624 PCI_ID_TABLE_ENTRY(pci_dev_descr_knl, ARRAY_SIZE(pci_dev_descr_knl), 1, KNIGHTS_LANDING), 625 { NULL, } 626 }; 627 628 /* 629 * Broadwell support 630 * 631 * DE processor: 632 * - 1 IMC 633 * - 2 DDR3 channels, 2 DPC per channel 634 * EP processor: 635 * - 1 or 2 IMC 636 * - 4 DDR4 channels, 3 DPC per channel 637 * EP 4S processor: 638 * - 2 IMC 639 * - 4 DDR4 channels, 3 DPC per channel 640 * EX processor: 641 * - 2 IMC 642 * - each IMC interfaces with a SMI 2 channel 643 * - each SMI channel interfaces with a scalable memory buffer 644 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC 645 */ 646 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28 647 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0x6fa0 648 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1 0x6f60 649 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0x6fa8 650 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM 0x6f71 651 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA 0x6f68 652 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM 0x6f79 653 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc 654 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd 655 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa 656 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab 657 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac 658 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad 659 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a 660 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b 661 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c 662 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d 663 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf 664 665 static const struct pci_id_descr pci_dev_descr_broadwell[] = { 666 /* first item must be the HA */ 667 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0, IMC0) }, 668 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1, IMC1) }, 669 670 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0, IMC0) }, 671 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM, 0, IMC0) }, 672 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0, IMC0) }, 673 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0, IMC0) }, 674 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1, IMC0) }, 675 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1, IMC0) }, 676 677 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1, IMC1) }, 678 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM, 1, IMC1) }, 679 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1, IMC1) }, 680 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1, IMC1) }, 681 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1, IMC1) }, 682 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1, IMC1) }, 683 684 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0, SOCK) }, 685 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0, SOCK) }, 686 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1, SOCK) }, 687 }; 688 689 static const struct pci_id_table pci_dev_descr_broadwell_table[] = { 690 PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell, 10, 2, BROADWELL), 691 { NULL, } 692 }; 693 694 695 /**************************************************************************** 696 Ancillary status routines 697 ****************************************************************************/ 698 699 static inline int numrank(enum type type, u32 mtr) 700 { 701 int ranks = (1 << RANK_CNT_BITS(mtr)); 702 int max = 4; 703 704 if (type == HASWELL || type == BROADWELL || type == KNIGHTS_LANDING) 705 max = 8; 706 707 if (ranks > max) { 708 edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n", 709 ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr); 710 return -EINVAL; 711 } 712 713 return ranks; 714 } 715 716 static inline int numrow(u32 mtr) 717 { 718 int rows = (RANK_WIDTH_BITS(mtr) + 12); 719 720 if (rows < 13 || rows > 18) { 721 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n", 722 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr); 723 return -EINVAL; 724 } 725 726 return 1 << rows; 727 } 728 729 static inline int numcol(u32 mtr) 730 { 731 int cols = (COL_WIDTH_BITS(mtr) + 10); 732 733 if (cols > 12) { 734 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n", 735 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr); 736 return -EINVAL; 737 } 738 739 return 1 << cols; 740 } 741 742 static struct sbridge_dev *get_sbridge_dev(int seg, u8 bus, enum domain dom, 743 int multi_bus, 744 struct sbridge_dev *prev) 745 { 746 struct sbridge_dev *sbridge_dev; 747 748 /* 749 * If we have devices scattered across several busses that pertain 750 * to the same memory controller, we'll lump them all together. 751 */ 752 if (multi_bus) { 753 return list_first_entry_or_null(&sbridge_edac_list, 754 struct sbridge_dev, list); 755 } 756 757 sbridge_dev = list_entry(prev ? prev->list.next 758 : sbridge_edac_list.next, struct sbridge_dev, list); 759 760 list_for_each_entry_from(sbridge_dev, &sbridge_edac_list, list) { 761 if ((sbridge_dev->seg == seg) && (sbridge_dev->bus == bus) && 762 (dom == SOCK || dom == sbridge_dev->dom)) 763 return sbridge_dev; 764 } 765 766 return NULL; 767 } 768 769 static struct sbridge_dev *alloc_sbridge_dev(int seg, u8 bus, enum domain dom, 770 const struct pci_id_table *table) 771 { 772 struct sbridge_dev *sbridge_dev; 773 774 sbridge_dev = kzalloc_obj(*sbridge_dev); 775 if (!sbridge_dev) 776 return NULL; 777 778 sbridge_dev->pdev = kzalloc_objs(*sbridge_dev->pdev, 779 table->n_devs_per_imc, GFP_KERNEL); 780 if (!sbridge_dev->pdev) { 781 kfree(sbridge_dev); 782 return NULL; 783 } 784 785 sbridge_dev->seg = seg; 786 sbridge_dev->bus = bus; 787 sbridge_dev->dom = dom; 788 sbridge_dev->n_devs = table->n_devs_per_imc; 789 list_add_tail(&sbridge_dev->list, &sbridge_edac_list); 790 791 return sbridge_dev; 792 } 793 794 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev) 795 { 796 list_del(&sbridge_dev->list); 797 kfree(sbridge_dev->pdev); 798 kfree(sbridge_dev); 799 } 800 801 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt) 802 { 803 u32 reg; 804 805 /* Address range is 32:28 */ 806 pci_read_config_dword(pvt->pci_sad1, TOLM, ®); 807 return GET_TOLM(reg); 808 } 809 810 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt) 811 { 812 u32 reg; 813 814 pci_read_config_dword(pvt->pci_sad1, TOHM, ®); 815 return GET_TOHM(reg); 816 } 817 818 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt) 819 { 820 u32 reg; 821 822 pci_read_config_dword(pvt->pci_br1, TOLM, ®); 823 824 return GET_TOLM(reg); 825 } 826 827 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt) 828 { 829 u32 reg; 830 831 pci_read_config_dword(pvt->pci_br1, TOHM, ®); 832 833 return GET_TOHM(reg); 834 } 835 836 static u64 rir_limit(u32 reg) 837 { 838 return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff; 839 } 840 841 static u64 sad_limit(u32 reg) 842 { 843 return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff; 844 } 845 846 static u32 interleave_mode(u32 reg) 847 { 848 return GET_BITFIELD(reg, 1, 1); 849 } 850 851 static u32 dram_attr(u32 reg) 852 { 853 return GET_BITFIELD(reg, 2, 3); 854 } 855 856 static u64 knl_sad_limit(u32 reg) 857 { 858 return (GET_BITFIELD(reg, 7, 26) << 26) | 0x3ffffff; 859 } 860 861 static u32 knl_interleave_mode(u32 reg) 862 { 863 return GET_BITFIELD(reg, 1, 2); 864 } 865 866 static const char * const knl_intlv_mode[] = { 867 "[8:6]", "[10:8]", "[14:12]", "[32:30]" 868 }; 869 870 static const char *get_intlv_mode_str(u32 reg, enum type t) 871 { 872 if (t == KNIGHTS_LANDING) 873 return knl_intlv_mode[knl_interleave_mode(reg)]; 874 else 875 return interleave_mode(reg) ? "[8:6]" : "[8:6]XOR[18:16]"; 876 } 877 878 static u32 dram_attr_knl(u32 reg) 879 { 880 return GET_BITFIELD(reg, 3, 4); 881 } 882 883 884 static enum mem_type get_memory_type(struct sbridge_pvt *pvt) 885 { 886 u32 reg; 887 enum mem_type mtype; 888 889 if (pvt->pci_ddrio) { 890 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr, 891 ®); 892 if (GET_BITFIELD(reg, 11, 11)) 893 /* FIXME: Can also be LRDIMM */ 894 mtype = MEM_RDDR3; 895 else 896 mtype = MEM_DDR3; 897 } else 898 mtype = MEM_UNKNOWN; 899 900 return mtype; 901 } 902 903 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt) 904 { 905 u32 reg; 906 bool registered = false; 907 enum mem_type mtype = MEM_UNKNOWN; 908 909 if (!pvt->pci_ddrio) 910 goto out; 911 912 pci_read_config_dword(pvt->pci_ddrio, 913 HASWELL_DDRCRCLKCONTROLS, ®); 914 /* Is_Rdimm */ 915 if (GET_BITFIELD(reg, 16, 16)) 916 registered = true; 917 918 pci_read_config_dword(pvt->pci_ta, MCMTR, ®); 919 if (GET_BITFIELD(reg, 14, 14)) { 920 if (registered) 921 mtype = MEM_RDDR4; 922 else 923 mtype = MEM_DDR4; 924 } else { 925 if (registered) 926 mtype = MEM_RDDR3; 927 else 928 mtype = MEM_DDR3; 929 } 930 931 out: 932 return mtype; 933 } 934 935 static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr) 936 { 937 /* for KNL value is fixed */ 938 return DEV_X16; 939 } 940 941 static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr) 942 { 943 /* there's no way to figure out */ 944 return DEV_UNKNOWN; 945 } 946 947 static enum dev_type __ibridge_get_width(u32 mtr) 948 { 949 enum dev_type type = DEV_UNKNOWN; 950 951 switch (mtr) { 952 case 2: 953 type = DEV_X16; 954 break; 955 case 1: 956 type = DEV_X8; 957 break; 958 case 0: 959 type = DEV_X4; 960 break; 961 } 962 963 return type; 964 } 965 966 static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr) 967 { 968 /* 969 * ddr3_width on the documentation but also valid for DDR4 on 970 * Haswell 971 */ 972 return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8)); 973 } 974 975 static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr) 976 { 977 /* ddr3_width on the documentation but also valid for DDR4 */ 978 return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9)); 979 } 980 981 static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt) 982 { 983 /* DDR4 RDIMMS and LRDIMMS are supported */ 984 return MEM_RDDR4; 985 } 986 987 static u8 get_node_id(struct sbridge_pvt *pvt) 988 { 989 u32 reg; 990 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®); 991 return GET_BITFIELD(reg, 0, 2); 992 } 993 994 static u8 haswell_get_node_id(struct sbridge_pvt *pvt) 995 { 996 u32 reg; 997 998 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); 999 return GET_BITFIELD(reg, 0, 3); 1000 } 1001 1002 static u8 knl_get_node_id(struct sbridge_pvt *pvt) 1003 { 1004 u32 reg; 1005 1006 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); 1007 return GET_BITFIELD(reg, 0, 2); 1008 } 1009 1010 /* 1011 * Use the reporting bank number to determine which memory 1012 * controller (also known as "ha" for "home agent"). Sandy 1013 * Bridge only has one memory controller per socket, so the 1014 * answer is always zero. 1015 */ 1016 static u8 sbridge_get_ha(u8 bank) 1017 { 1018 return 0; 1019 } 1020 1021 /* 1022 * On Ivy Bridge, Haswell and Broadwell the error may be in a 1023 * home agent bank (7, 8), or one of the per-channel memory 1024 * controller banks (9 .. 16). 1025 */ 1026 static u8 ibridge_get_ha(u8 bank) 1027 { 1028 switch (bank) { 1029 case 7 ... 8: 1030 return bank - 7; 1031 case 9 ... 16: 1032 return (bank - 9) / 4; 1033 default: 1034 return 0xff; 1035 } 1036 } 1037 1038 /* Not used, but included for safety/symmetry */ 1039 static u8 knl_get_ha(u8 bank) 1040 { 1041 return 0xff; 1042 } 1043 1044 static u64 haswell_get_tolm(struct sbridge_pvt *pvt) 1045 { 1046 u32 reg; 1047 1048 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®); 1049 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff; 1050 } 1051 1052 static u64 haswell_get_tohm(struct sbridge_pvt *pvt) 1053 { 1054 u64 rc; 1055 u32 reg; 1056 1057 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®); 1058 rc = GET_BITFIELD(reg, 26, 31); 1059 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®); 1060 rc = ((reg << 6) | rc) << 26; 1061 1062 return rc | 0x3ffffff; 1063 } 1064 1065 static u64 knl_get_tolm(struct sbridge_pvt *pvt) 1066 { 1067 u32 reg; 1068 1069 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, ®); 1070 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff; 1071 } 1072 1073 static u64 knl_get_tohm(struct sbridge_pvt *pvt) 1074 { 1075 u64 rc; 1076 u32 reg_lo, reg_hi; 1077 1078 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, ®_lo); 1079 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, ®_hi); 1080 rc = ((u64)reg_hi << 32) | reg_lo; 1081 return rc | 0x3ffffff; 1082 } 1083 1084 1085 static u64 haswell_rir_limit(u32 reg) 1086 { 1087 return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1; 1088 } 1089 1090 static inline u8 sad_pkg_socket(u8 pkg) 1091 { 1092 /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */ 1093 return ((pkg >> 3) << 2) | (pkg & 0x3); 1094 } 1095 1096 static inline u8 sad_pkg_ha(u8 pkg) 1097 { 1098 return (pkg >> 2) & 0x1; 1099 } 1100 1101 static int haswell_chan_hash(int idx, u64 addr) 1102 { 1103 int i; 1104 1105 /* 1106 * XOR even bits from 12:26 to bit0 of idx, 1107 * odd bits from 13:27 to bit1 1108 */ 1109 for (i = 12; i < 28; i += 2) 1110 idx ^= (addr >> i) & 3; 1111 1112 return idx; 1113 } 1114 1115 /* Low bits of TAD limit, and some metadata. */ 1116 static const u32 knl_tad_dram_limit_lo[] = { 1117 0x400, 0x500, 0x600, 0x700, 1118 0x800, 0x900, 0xa00, 0xb00, 1119 }; 1120 1121 /* Low bits of TAD offset. */ 1122 static const u32 knl_tad_dram_offset_lo[] = { 1123 0x404, 0x504, 0x604, 0x704, 1124 0x804, 0x904, 0xa04, 0xb04, 1125 }; 1126 1127 /* High 16 bits of TAD limit and offset. */ 1128 static const u32 knl_tad_dram_hi[] = { 1129 0x408, 0x508, 0x608, 0x708, 1130 0x808, 0x908, 0xa08, 0xb08, 1131 }; 1132 1133 /* Number of ways a tad entry is interleaved. */ 1134 static const u32 knl_tad_ways[] = { 1135 8, 6, 4, 3, 2, 1, 1136 }; 1137 1138 /* 1139 * Retrieve the n'th Target Address Decode table entry 1140 * from the memory controller's TAD table. 1141 * 1142 * @pvt: driver private data 1143 * @entry: which entry you want to retrieve 1144 * @mc: which memory controller (0 or 1) 1145 * @offset: output tad range offset 1146 * @limit: output address of first byte above tad range 1147 * @ways: output number of interleave ways 1148 * 1149 * The offset value has curious semantics. It's a sort of running total 1150 * of the sizes of all the memory regions that aren't mapped in this 1151 * tad table. 1152 */ 1153 static int knl_get_tad(const struct sbridge_pvt *pvt, 1154 const int entry, 1155 const int mc, 1156 u64 *offset, 1157 u64 *limit, 1158 int *ways) 1159 { 1160 u32 reg_limit_lo, reg_offset_lo, reg_hi; 1161 struct pci_dev *pci_mc; 1162 int way_id; 1163 1164 switch (mc) { 1165 case 0: 1166 pci_mc = pvt->knl.pci_mc0; 1167 break; 1168 case 1: 1169 pci_mc = pvt->knl.pci_mc1; 1170 break; 1171 default: 1172 WARN_ON(1); 1173 return -EINVAL; 1174 } 1175 1176 pci_read_config_dword(pci_mc, 1177 knl_tad_dram_limit_lo[entry], ®_limit_lo); 1178 pci_read_config_dword(pci_mc, 1179 knl_tad_dram_offset_lo[entry], ®_offset_lo); 1180 pci_read_config_dword(pci_mc, 1181 knl_tad_dram_hi[entry], ®_hi); 1182 1183 /* Is this TAD entry enabled? */ 1184 if (!GET_BITFIELD(reg_limit_lo, 0, 0)) 1185 return -ENODEV; 1186 1187 way_id = GET_BITFIELD(reg_limit_lo, 3, 5); 1188 1189 if (way_id < ARRAY_SIZE(knl_tad_ways)) { 1190 *ways = knl_tad_ways[way_id]; 1191 } else { 1192 *ways = 0; 1193 sbridge_printk(KERN_ERR, 1194 "Unexpected value %d in mc_tad_limit_lo wayness field\n", 1195 way_id); 1196 return -ENODEV; 1197 } 1198 1199 /* 1200 * The least significant 6 bits of base and limit are truncated. 1201 * For limit, we fill the missing bits with 1s. 1202 */ 1203 *offset = ((u64) GET_BITFIELD(reg_offset_lo, 6, 31) << 6) | 1204 ((u64) GET_BITFIELD(reg_hi, 0, 15) << 32); 1205 *limit = ((u64) GET_BITFIELD(reg_limit_lo, 6, 31) << 6) | 63 | 1206 ((u64) GET_BITFIELD(reg_hi, 16, 31) << 32); 1207 1208 return 0; 1209 } 1210 1211 /* Determine which memory controller is responsible for a given channel. */ 1212 static int knl_channel_mc(int channel) 1213 { 1214 WARN_ON(channel < 0 || channel >= 6); 1215 1216 return channel < 3 ? 1 : 0; 1217 } 1218 1219 /* 1220 * Get the Nth entry from EDC_ROUTE_TABLE register. 1221 * (This is the per-tile mapping of logical interleave targets to 1222 * physical EDC modules.) 1223 * 1224 * entry 0: 0:2 1225 * 1: 3:5 1226 * 2: 6:8 1227 * 3: 9:11 1228 * 4: 12:14 1229 * 5: 15:17 1230 * 6: 18:20 1231 * 7: 21:23 1232 * reserved: 24:31 1233 */ 1234 static u32 knl_get_edc_route(int entry, u32 reg) 1235 { 1236 WARN_ON(entry >= KNL_MAX_EDCS); 1237 return GET_BITFIELD(reg, entry*3, (entry*3)+2); 1238 } 1239 1240 /* 1241 * Get the Nth entry from MC_ROUTE_TABLE register. 1242 * (This is the per-tile mapping of logical interleave targets to 1243 * physical DRAM channels modules.) 1244 * 1245 * entry 0: mc 0:2 channel 18:19 1246 * 1: mc 3:5 channel 20:21 1247 * 2: mc 6:8 channel 22:23 1248 * 3: mc 9:11 channel 24:25 1249 * 4: mc 12:14 channel 26:27 1250 * 5: mc 15:17 channel 28:29 1251 * reserved: 30:31 1252 * 1253 * Though we have 3 bits to identify the MC, we should only see 1254 * the values 0 or 1. 1255 */ 1256 1257 static u32 knl_get_mc_route(int entry, u32 reg) 1258 { 1259 int mc, chan; 1260 1261 WARN_ON(entry >= KNL_MAX_CHANNELS); 1262 1263 mc = GET_BITFIELD(reg, entry*3, (entry*3)+2); 1264 chan = GET_BITFIELD(reg, (entry*2) + 18, (entry*2) + 18 + 1); 1265 1266 return knl_channel_remap(mc, chan); 1267 } 1268 1269 /* 1270 * Render the EDC_ROUTE register in human-readable form. 1271 * Output string s should be at least KNL_MAX_EDCS*2 bytes. 1272 */ 1273 static void knl_show_edc_route(u32 reg, char *s) 1274 { 1275 int i; 1276 1277 for (i = 0; i < KNL_MAX_EDCS; i++) { 1278 s[i*2] = knl_get_edc_route(i, reg) + '0'; 1279 s[i*2+1] = '-'; 1280 } 1281 1282 s[KNL_MAX_EDCS*2 - 1] = '\0'; 1283 } 1284 1285 /* 1286 * Render the MC_ROUTE register in human-readable form. 1287 * Output string s should be at least KNL_MAX_CHANNELS*2 bytes. 1288 */ 1289 static void knl_show_mc_route(u32 reg, char *s) 1290 { 1291 int i; 1292 1293 for (i = 0; i < KNL_MAX_CHANNELS; i++) { 1294 s[i*2] = knl_get_mc_route(i, reg) + '0'; 1295 s[i*2+1] = '-'; 1296 } 1297 1298 s[KNL_MAX_CHANNELS*2 - 1] = '\0'; 1299 } 1300 1301 #define KNL_EDC_ROUTE 0xb8 1302 #define KNL_MC_ROUTE 0xb4 1303 1304 /* Is this dram rule backed by regular DRAM in flat mode? */ 1305 #define KNL_EDRAM(reg) GET_BITFIELD(reg, 29, 29) 1306 1307 /* Is this dram rule cached? */ 1308 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28) 1309 1310 /* Is this rule backed by edc ? */ 1311 #define KNL_EDRAM_ONLY(reg) GET_BITFIELD(reg, 29, 29) 1312 1313 /* Is this rule backed by DRAM, cacheable in EDRAM? */ 1314 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28) 1315 1316 /* Is this rule mod3? */ 1317 #define KNL_MOD3(reg) GET_BITFIELD(reg, 27, 27) 1318 1319 /* 1320 * Figure out how big our RAM modules are. 1321 * 1322 * The DIMMMTR register in KNL doesn't tell us the size of the DIMMs, so we 1323 * have to figure this out from the SAD rules, interleave lists, route tables, 1324 * and TAD rules. 1325 * 1326 * SAD rules can have holes in them (e.g. the 3G-4G hole), so we have to 1327 * inspect the TAD rules to figure out how large the SAD regions really are. 1328 * 1329 * When we know the real size of a SAD region and how many ways it's 1330 * interleaved, we know the individual contribution of each channel to 1331 * TAD is size/ways. 1332 * 1333 * Finally, we have to check whether each channel participates in each SAD 1334 * region. 1335 * 1336 * Fortunately, KNL only supports one DIMM per channel, so once we know how 1337 * much memory the channel uses, we know the DIMM is at least that large. 1338 * (The BIOS might possibly choose not to map all available memory, in which 1339 * case we will underreport the size of the DIMM.) 1340 * 1341 * In theory, we could try to determine the EDC sizes as well, but that would 1342 * only work in flat mode, not in cache mode. 1343 * 1344 * @mc_sizes: Output sizes of channels (must have space for KNL_MAX_CHANNELS 1345 * elements) 1346 */ 1347 static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes) 1348 { 1349 u64 sad_base, sad_limit = 0; 1350 u64 tad_base, tad_size, tad_limit, tad_deadspace, tad_livespace; 1351 int sad_rule = 0; 1352 int tad_rule = 0; 1353 int intrlv_ways, tad_ways; 1354 u32 first_pkg, pkg; 1355 int i; 1356 u64 sad_actual_size[2]; /* sad size accounting for holes, per mc */ 1357 u32 dram_rule, interleave_reg; 1358 u32 mc_route_reg[KNL_MAX_CHAS]; 1359 u32 edc_route_reg[KNL_MAX_CHAS]; 1360 int edram_only; 1361 char edc_route_string[KNL_MAX_EDCS*2]; 1362 char mc_route_string[KNL_MAX_CHANNELS*2]; 1363 int cur_reg_start; 1364 int mc; 1365 int channel; 1366 int participants[KNL_MAX_CHANNELS]; 1367 1368 for (i = 0; i < KNL_MAX_CHANNELS; i++) 1369 mc_sizes[i] = 0; 1370 1371 /* Read the EDC route table in each CHA. */ 1372 cur_reg_start = 0; 1373 for (i = 0; i < KNL_MAX_CHAS; i++) { 1374 pci_read_config_dword(pvt->knl.pci_cha[i], 1375 KNL_EDC_ROUTE, &edc_route_reg[i]); 1376 1377 if (i > 0 && edc_route_reg[i] != edc_route_reg[i-1]) { 1378 knl_show_edc_route(edc_route_reg[i-1], 1379 edc_route_string); 1380 if (cur_reg_start == i-1) 1381 edac_dbg(0, "edc route table for CHA %d: %s\n", 1382 cur_reg_start, edc_route_string); 1383 else 1384 edac_dbg(0, "edc route table for CHA %d-%d: %s\n", 1385 cur_reg_start, i-1, edc_route_string); 1386 cur_reg_start = i; 1387 } 1388 } 1389 knl_show_edc_route(edc_route_reg[i-1], edc_route_string); 1390 if (cur_reg_start == i-1) 1391 edac_dbg(0, "edc route table for CHA %d: %s\n", 1392 cur_reg_start, edc_route_string); 1393 else 1394 edac_dbg(0, "edc route table for CHA %d-%d: %s\n", 1395 cur_reg_start, i-1, edc_route_string); 1396 1397 /* Read the MC route table in each CHA. */ 1398 cur_reg_start = 0; 1399 for (i = 0; i < KNL_MAX_CHAS; i++) { 1400 pci_read_config_dword(pvt->knl.pci_cha[i], 1401 KNL_MC_ROUTE, &mc_route_reg[i]); 1402 1403 if (i > 0 && mc_route_reg[i] != mc_route_reg[i-1]) { 1404 knl_show_mc_route(mc_route_reg[i-1], mc_route_string); 1405 if (cur_reg_start == i-1) 1406 edac_dbg(0, "mc route table for CHA %d: %s\n", 1407 cur_reg_start, mc_route_string); 1408 else 1409 edac_dbg(0, "mc route table for CHA %d-%d: %s\n", 1410 cur_reg_start, i-1, mc_route_string); 1411 cur_reg_start = i; 1412 } 1413 } 1414 knl_show_mc_route(mc_route_reg[i-1], mc_route_string); 1415 if (cur_reg_start == i-1) 1416 edac_dbg(0, "mc route table for CHA %d: %s\n", 1417 cur_reg_start, mc_route_string); 1418 else 1419 edac_dbg(0, "mc route table for CHA %d-%d: %s\n", 1420 cur_reg_start, i-1, mc_route_string); 1421 1422 /* Process DRAM rules */ 1423 for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) { 1424 /* previous limit becomes the new base */ 1425 sad_base = sad_limit; 1426 1427 pci_read_config_dword(pvt->pci_sad0, 1428 pvt->info.dram_rule[sad_rule], &dram_rule); 1429 1430 if (!DRAM_RULE_ENABLE(dram_rule)) 1431 break; 1432 1433 edram_only = KNL_EDRAM_ONLY(dram_rule); 1434 1435 sad_limit = pvt->info.sad_limit(dram_rule)+1; 1436 1437 pci_read_config_dword(pvt->pci_sad0, 1438 pvt->info.interleave_list[sad_rule], &interleave_reg); 1439 1440 /* 1441 * Find out how many ways this dram rule is interleaved. 1442 * We stop when we see the first channel again. 1443 */ 1444 first_pkg = sad_pkg(pvt->info.interleave_pkg, 1445 interleave_reg, 0); 1446 for (intrlv_ways = 1; intrlv_ways < 8; intrlv_ways++) { 1447 pkg = sad_pkg(pvt->info.interleave_pkg, 1448 interleave_reg, intrlv_ways); 1449 1450 if ((pkg & 0x8) == 0) { 1451 /* 1452 * 0 bit means memory is non-local, 1453 * which KNL doesn't support 1454 */ 1455 edac_dbg(0, "Unexpected interleave target %d\n", 1456 pkg); 1457 return -1; 1458 } 1459 1460 if (pkg == first_pkg) 1461 break; 1462 } 1463 if (KNL_MOD3(dram_rule)) 1464 intrlv_ways *= 3; 1465 1466 edac_dbg(3, "dram rule %d (base 0x%llx, limit 0x%llx), %d way interleave%s\n", 1467 sad_rule, 1468 sad_base, 1469 sad_limit, 1470 intrlv_ways, 1471 edram_only ? ", EDRAM" : ""); 1472 1473 /* 1474 * Find out how big the SAD region really is by iterating 1475 * over TAD tables (SAD regions may contain holes). 1476 * Each memory controller might have a different TAD table, so 1477 * we have to look at both. 1478 * 1479 * Livespace is the memory that's mapped in this TAD table, 1480 * deadspace is the holes (this could be the MMIO hole, or it 1481 * could be memory that's mapped by the other TAD table but 1482 * not this one). 1483 */ 1484 for (mc = 0; mc < 2; mc++) { 1485 sad_actual_size[mc] = 0; 1486 tad_livespace = 0; 1487 for (tad_rule = 0; 1488 tad_rule < ARRAY_SIZE( 1489 knl_tad_dram_limit_lo); 1490 tad_rule++) { 1491 if (knl_get_tad(pvt, 1492 tad_rule, 1493 mc, 1494 &tad_deadspace, 1495 &tad_limit, 1496 &tad_ways)) 1497 break; 1498 1499 tad_size = (tad_limit+1) - 1500 (tad_livespace + tad_deadspace); 1501 tad_livespace += tad_size; 1502 tad_base = (tad_limit+1) - tad_size; 1503 1504 if (tad_base < sad_base) { 1505 if (tad_limit > sad_base) 1506 edac_dbg(0, "TAD region overlaps lower SAD boundary -- TAD tables may be configured incorrectly.\n"); 1507 } else if (tad_base < sad_limit) { 1508 if (tad_limit+1 > sad_limit) { 1509 edac_dbg(0, "TAD region overlaps upper SAD boundary -- TAD tables may be configured incorrectly.\n"); 1510 } else { 1511 /* TAD region is completely inside SAD region */ 1512 edac_dbg(3, "TAD region %d 0x%llx - 0x%llx (%lld bytes) table%d\n", 1513 tad_rule, tad_base, 1514 tad_limit, tad_size, 1515 mc); 1516 sad_actual_size[mc] += tad_size; 1517 } 1518 } 1519 } 1520 } 1521 1522 for (mc = 0; mc < 2; mc++) { 1523 edac_dbg(3, " total TAD DRAM footprint in table%d : 0x%llx (%lld bytes)\n", 1524 mc, sad_actual_size[mc], sad_actual_size[mc]); 1525 } 1526 1527 /* Ignore EDRAM rule */ 1528 if (edram_only) 1529 continue; 1530 1531 /* Figure out which channels participate in interleave. */ 1532 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) 1533 participants[channel] = 0; 1534 1535 /* For each channel, does at least one CHA have 1536 * this channel mapped to the given target? 1537 */ 1538 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) { 1539 int target; 1540 int cha; 1541 1542 for (target = 0; target < KNL_MAX_CHANNELS; target++) { 1543 for (cha = 0; cha < KNL_MAX_CHAS; cha++) { 1544 if (knl_get_mc_route(target, 1545 mc_route_reg[cha]) == channel 1546 && !participants[channel]) { 1547 participants[channel] = 1; 1548 break; 1549 } 1550 } 1551 } 1552 } 1553 1554 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) { 1555 mc = knl_channel_mc(channel); 1556 if (participants[channel]) { 1557 edac_dbg(4, "mc channel %d contributes %lld bytes via sad entry %d\n", 1558 channel, 1559 sad_actual_size[mc]/intrlv_ways, 1560 sad_rule); 1561 mc_sizes[channel] += 1562 sad_actual_size[mc]/intrlv_ways; 1563 } 1564 } 1565 } 1566 1567 return 0; 1568 } 1569 1570 static void get_source_id(struct mem_ctl_info *mci) 1571 { 1572 struct sbridge_pvt *pvt = mci->pvt_info; 1573 u32 reg; 1574 1575 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL || 1576 pvt->info.type == KNIGHTS_LANDING) 1577 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®); 1578 else 1579 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®); 1580 1581 if (pvt->info.type == KNIGHTS_LANDING) 1582 pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg); 1583 else 1584 pvt->sbridge_dev->source_id = SOURCE_ID(reg); 1585 } 1586 1587 static int __populate_dimms(struct mem_ctl_info *mci, 1588 u64 knl_mc_sizes[KNL_MAX_CHANNELS], 1589 enum edac_type mode) 1590 { 1591 struct sbridge_pvt *pvt = mci->pvt_info; 1592 int channels = pvt->info.type == KNIGHTS_LANDING ? KNL_MAX_CHANNELS 1593 : NUM_CHANNELS; 1594 unsigned int i, j, banks, ranks, rows, cols, npages; 1595 struct dimm_info *dimm; 1596 enum mem_type mtype; 1597 u64 size; 1598 1599 mtype = pvt->info.get_memory_type(pvt); 1600 if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4) 1601 edac_dbg(0, "Memory is registered\n"); 1602 else if (mtype == MEM_UNKNOWN) 1603 edac_dbg(0, "Cannot determine memory type\n"); 1604 else 1605 edac_dbg(0, "Memory is unregistered\n"); 1606 1607 if (mtype == MEM_DDR4 || mtype == MEM_RDDR4) 1608 banks = 16; 1609 else 1610 banks = 8; 1611 1612 for (i = 0; i < channels; i++) { 1613 u32 mtr, amap = 0; 1614 1615 int max_dimms_per_channel; 1616 1617 if (pvt->info.type == KNIGHTS_LANDING) { 1618 max_dimms_per_channel = 1; 1619 if (!pvt->knl.pci_channel[i]) 1620 continue; 1621 } else { 1622 max_dimms_per_channel = ARRAY_SIZE(mtr_regs); 1623 if (!pvt->pci_tad[i]) 1624 continue; 1625 pci_read_config_dword(pvt->pci_tad[i], 0x8c, &amap); 1626 } 1627 1628 for (j = 0; j < max_dimms_per_channel; j++) { 1629 dimm = edac_get_dimm(mci, i, j, 0); 1630 if (pvt->info.type == KNIGHTS_LANDING) { 1631 pci_read_config_dword(pvt->knl.pci_channel[i], 1632 knl_mtr_reg, &mtr); 1633 } else { 1634 pci_read_config_dword(pvt->pci_tad[i], 1635 mtr_regs[j], &mtr); 1636 } 1637 edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr); 1638 1639 if (IS_DIMM_PRESENT(mtr)) { 1640 if (!IS_ECC_ENABLED(pvt->info.mcmtr)) { 1641 sbridge_printk(KERN_ERR, "CPU SrcID #%d, Ha #%d, Channel #%d has DIMMs, but ECC is disabled\n", 1642 pvt->sbridge_dev->source_id, 1643 pvt->sbridge_dev->dom, i); 1644 return -ENODEV; 1645 } 1646 pvt->channel[i].dimms++; 1647 1648 ranks = numrank(pvt->info.type, mtr); 1649 1650 if (pvt->info.type == KNIGHTS_LANDING) { 1651 /* For DDR4, this is fixed. */ 1652 cols = 1 << 10; 1653 rows = knl_mc_sizes[i] / 1654 ((u64) cols * ranks * banks * 8); 1655 } else { 1656 rows = numrow(mtr); 1657 cols = numcol(mtr); 1658 } 1659 1660 size = ((u64)rows * cols * banks * ranks) >> (20 - 3); 1661 npages = MiB_TO_PAGES(size); 1662 1663 edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n", 1664 pvt->sbridge_dev->mc, pvt->sbridge_dev->dom, i, j, 1665 size, npages, 1666 banks, ranks, rows, cols); 1667 1668 dimm->nr_pages = npages; 1669 dimm->grain = 32; 1670 dimm->dtype = pvt->info.get_width(pvt, mtr); 1671 dimm->mtype = mtype; 1672 dimm->edac_mode = mode; 1673 pvt->channel[i].dimm[j].rowbits = order_base_2(rows); 1674 pvt->channel[i].dimm[j].colbits = order_base_2(cols); 1675 pvt->channel[i].dimm[j].bank_xor_enable = 1676 GET_BITFIELD(pvt->info.mcmtr, 9, 9); 1677 pvt->channel[i].dimm[j].amap_fine = GET_BITFIELD(amap, 0, 0); 1678 snprintf(dimm->label, sizeof(dimm->label), 1679 "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u", 1680 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom, i, j); 1681 } 1682 } 1683 } 1684 1685 return 0; 1686 } 1687 1688 static int get_dimm_config(struct mem_ctl_info *mci) 1689 { 1690 struct sbridge_pvt *pvt = mci->pvt_info; 1691 u64 knl_mc_sizes[KNL_MAX_CHANNELS]; 1692 enum edac_type mode; 1693 u32 reg; 1694 1695 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt); 1696 edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n", 1697 pvt->sbridge_dev->mc, 1698 pvt->sbridge_dev->node_id, 1699 pvt->sbridge_dev->source_id); 1700 1701 /* KNL doesn't support mirroring or lockstep, 1702 * and is always closed page 1703 */ 1704 if (pvt->info.type == KNIGHTS_LANDING) { 1705 mode = EDAC_S4ECD4ED; 1706 pvt->mirror_mode = NON_MIRRORING; 1707 pvt->is_cur_addr_mirrored = false; 1708 1709 if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0) 1710 return -1; 1711 if (pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr)) { 1712 edac_dbg(0, "Failed to read KNL_MCMTR register\n"); 1713 return -ENODEV; 1714 } 1715 } else { 1716 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { 1717 if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®)) { 1718 edac_dbg(0, "Failed to read HASWELL_HASYSDEFEATURE2 register\n"); 1719 return -ENODEV; 1720 } 1721 pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21); 1722 if (GET_BITFIELD(reg, 28, 28)) { 1723 pvt->mirror_mode = ADDR_RANGE_MIRRORING; 1724 edac_dbg(0, "Address range partial memory mirroring is enabled\n"); 1725 goto next; 1726 } 1727 } 1728 if (pci_read_config_dword(pvt->pci_ras, RASENABLES, ®)) { 1729 edac_dbg(0, "Failed to read RASENABLES register\n"); 1730 return -ENODEV; 1731 } 1732 if (IS_MIRROR_ENABLED(reg)) { 1733 pvt->mirror_mode = FULL_MIRRORING; 1734 edac_dbg(0, "Full memory mirroring is enabled\n"); 1735 } else { 1736 pvt->mirror_mode = NON_MIRRORING; 1737 edac_dbg(0, "Memory mirroring is disabled\n"); 1738 } 1739 1740 next: 1741 if (pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr)) { 1742 edac_dbg(0, "Failed to read MCMTR register\n"); 1743 return -ENODEV; 1744 } 1745 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { 1746 edac_dbg(0, "Lockstep is enabled\n"); 1747 mode = EDAC_S8ECD8ED; 1748 pvt->is_lockstep = true; 1749 } else { 1750 edac_dbg(0, "Lockstep is disabled\n"); 1751 mode = EDAC_S4ECD4ED; 1752 pvt->is_lockstep = false; 1753 } 1754 if (IS_CLOSE_PG(pvt->info.mcmtr)) { 1755 edac_dbg(0, "address map is on closed page mode\n"); 1756 pvt->is_close_pg = true; 1757 } else { 1758 edac_dbg(0, "address map is on open page mode\n"); 1759 pvt->is_close_pg = false; 1760 } 1761 } 1762 1763 return __populate_dimms(mci, knl_mc_sizes, mode); 1764 } 1765 1766 static void get_memory_layout(const struct mem_ctl_info *mci) 1767 { 1768 struct sbridge_pvt *pvt = mci->pvt_info; 1769 int i, j, k, n_sads, n_tads, sad_interl; 1770 u32 reg; 1771 u64 limit, prv = 0; 1772 u64 tmp_mb; 1773 u32 gb, mb; 1774 u32 rir_way; 1775 1776 /* 1777 * Step 1) Get TOLM/TOHM ranges 1778 */ 1779 1780 pvt->tolm = pvt->info.get_tolm(pvt); 1781 tmp_mb = (1 + pvt->tolm) >> 20; 1782 1783 gb = div_u64_rem(tmp_mb, 1024, &mb); 1784 edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n", 1785 gb, (mb*1000)/1024, (u64)pvt->tolm); 1786 1787 /* Address range is already 45:25 */ 1788 pvt->tohm = pvt->info.get_tohm(pvt); 1789 tmp_mb = (1 + pvt->tohm) >> 20; 1790 1791 gb = div_u64_rem(tmp_mb, 1024, &mb); 1792 edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n", 1793 gb, (mb*1000)/1024, (u64)pvt->tohm); 1794 1795 /* 1796 * Step 2) Get SAD range and SAD Interleave list 1797 * TAD registers contain the interleave wayness. However, it 1798 * seems simpler to just discover it indirectly, with the 1799 * algorithm bellow. 1800 */ 1801 prv = 0; 1802 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { 1803 /* SAD_LIMIT Address range is 45:26 */ 1804 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], 1805 ®); 1806 limit = pvt->info.sad_limit(reg); 1807 1808 if (!DRAM_RULE_ENABLE(reg)) 1809 continue; 1810 1811 if (limit <= prv) 1812 break; 1813 1814 tmp_mb = (limit + 1) >> 20; 1815 gb = div_u64_rem(tmp_mb, 1024, &mb); 1816 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n", 1817 n_sads, 1818 show_dram_attr(pvt->info.dram_attr(reg)), 1819 gb, (mb*1000)/1024, 1820 ((u64)tmp_mb) << 20L, 1821 get_intlv_mode_str(reg, pvt->info.type), 1822 reg); 1823 prv = limit; 1824 1825 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], 1826 ®); 1827 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); 1828 for (j = 0; j < 8; j++) { 1829 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j); 1830 if (j > 0 && sad_interl == pkg) 1831 break; 1832 1833 edac_dbg(0, "SAD#%d, interleave #%d: %d\n", 1834 n_sads, j, pkg); 1835 } 1836 } 1837 1838 if (pvt->info.type == KNIGHTS_LANDING) 1839 return; 1840 1841 /* 1842 * Step 3) Get TAD range 1843 */ 1844 prv = 0; 1845 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { 1846 pci_read_config_dword(pvt->pci_ha, tad_dram_rule[n_tads], ®); 1847 limit = TAD_LIMIT(reg); 1848 if (limit <= prv) 1849 break; 1850 tmp_mb = (limit + 1) >> 20; 1851 1852 gb = div_u64_rem(tmp_mb, 1024, &mb); 1853 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n", 1854 n_tads, gb, (mb*1000)/1024, 1855 ((u64)tmp_mb) << 20L, 1856 (u32)(1 << TAD_SOCK(reg)), 1857 (u32)TAD_CH(reg) + 1, 1858 (u32)TAD_TGT0(reg), 1859 (u32)TAD_TGT1(reg), 1860 (u32)TAD_TGT2(reg), 1861 (u32)TAD_TGT3(reg), 1862 reg); 1863 prv = limit; 1864 } 1865 1866 /* 1867 * Step 4) Get TAD offsets, per each channel 1868 */ 1869 for (i = 0; i < NUM_CHANNELS; i++) { 1870 if (!pvt->channel[i].dimms) 1871 continue; 1872 for (j = 0; j < n_tads; j++) { 1873 pci_read_config_dword(pvt->pci_tad[i], 1874 tad_ch_nilv_offset[j], 1875 ®); 1876 tmp_mb = TAD_OFFSET(reg) >> 20; 1877 gb = div_u64_rem(tmp_mb, 1024, &mb); 1878 edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n", 1879 i, j, 1880 gb, (mb*1000)/1024, 1881 ((u64)tmp_mb) << 20L, 1882 reg); 1883 } 1884 } 1885 1886 /* 1887 * Step 6) Get RIR Wayness/Limit, per each channel 1888 */ 1889 for (i = 0; i < NUM_CHANNELS; i++) { 1890 if (!pvt->channel[i].dimms) 1891 continue; 1892 for (j = 0; j < MAX_RIR_RANGES; j++) { 1893 pci_read_config_dword(pvt->pci_tad[i], 1894 rir_way_limit[j], 1895 ®); 1896 1897 if (!IS_RIR_VALID(reg)) 1898 continue; 1899 1900 tmp_mb = pvt->info.rir_limit(reg) >> 20; 1901 rir_way = 1 << RIR_WAY(reg); 1902 gb = div_u64_rem(tmp_mb, 1024, &mb); 1903 edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n", 1904 i, j, 1905 gb, (mb*1000)/1024, 1906 ((u64)tmp_mb) << 20L, 1907 rir_way, 1908 reg); 1909 1910 for (k = 0; k < rir_way; k++) { 1911 pci_read_config_dword(pvt->pci_tad[i], 1912 rir_offset[j][k], 1913 ®); 1914 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6; 1915 1916 gb = div_u64_rem(tmp_mb, 1024, &mb); 1917 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n", 1918 i, j, k, 1919 gb, (mb*1000)/1024, 1920 ((u64)tmp_mb) << 20L, 1921 (u32)RIR_RNK_TGT(pvt->info.type, reg), 1922 reg); 1923 } 1924 } 1925 } 1926 } 1927 1928 static struct mem_ctl_info *get_mci_for_node_id(u8 node_id, u8 ha) 1929 { 1930 struct sbridge_dev *sbridge_dev; 1931 1932 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { 1933 if (sbridge_dev->node_id == node_id && sbridge_dev->dom == ha) 1934 return sbridge_dev->mci; 1935 } 1936 return NULL; 1937 } 1938 1939 static u8 sb_close_row[] = { 1940 15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33 1941 }; 1942 1943 static u8 sb_close_column[] = { 1944 3, 4, 5, 14, 19, 23, 24, 25, 26, 27 1945 }; 1946 1947 static u8 sb_open_row[] = { 1948 14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33 1949 }; 1950 1951 static u8 sb_open_column[] = { 1952 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 1953 }; 1954 1955 static u8 sb_open_fine_column[] = { 1956 3, 4, 5, 7, 8, 9, 10, 11, 12, 13 1957 }; 1958 1959 static int sb_bits(u64 addr, int nbits, u8 *bits) 1960 { 1961 int i, res = 0; 1962 1963 for (i = 0; i < nbits; i++) 1964 res |= ((addr >> bits[i]) & 1) << i; 1965 return res; 1966 } 1967 1968 static int sb_bank_bits(u64 addr, int b0, int b1, int do_xor, int x0, int x1) 1969 { 1970 int ret = GET_BITFIELD(addr, b0, b0) | (GET_BITFIELD(addr, b1, b1) << 1); 1971 1972 if (do_xor) 1973 ret ^= GET_BITFIELD(addr, x0, x0) | (GET_BITFIELD(addr, x1, x1) << 1); 1974 1975 return ret; 1976 } 1977 1978 static bool sb_decode_ddr4(struct mem_ctl_info *mci, int ch, u8 rank, 1979 u64 rank_addr, char *msg) 1980 { 1981 int dimmno = 0; 1982 int row, col, bank_address, bank_group; 1983 struct sbridge_pvt *pvt; 1984 u32 bg0 = 0, rowbits = 0, colbits = 0; 1985 u32 amap_fine = 0, bank_xor_enable = 0; 1986 1987 dimmno = (rank < 12) ? rank / 4 : 2; 1988 pvt = mci->pvt_info; 1989 amap_fine = pvt->channel[ch].dimm[dimmno].amap_fine; 1990 bg0 = amap_fine ? 6 : 13; 1991 rowbits = pvt->channel[ch].dimm[dimmno].rowbits; 1992 colbits = pvt->channel[ch].dimm[dimmno].colbits; 1993 bank_xor_enable = pvt->channel[ch].dimm[dimmno].bank_xor_enable; 1994 1995 if (pvt->is_lockstep) { 1996 pr_warn_once("LockStep row/column decode is not supported yet!\n"); 1997 msg[0] = '\0'; 1998 return false; 1999 } 2000 2001 if (pvt->is_close_pg) { 2002 row = sb_bits(rank_addr, rowbits, sb_close_row); 2003 col = sb_bits(rank_addr, colbits, sb_close_column); 2004 col |= 0x400; /* C10 is autoprecharge, always set */ 2005 bank_address = sb_bank_bits(rank_addr, 8, 9, bank_xor_enable, 22, 28); 2006 bank_group = sb_bank_bits(rank_addr, 6, 7, bank_xor_enable, 20, 21); 2007 } else { 2008 row = sb_bits(rank_addr, rowbits, sb_open_row); 2009 if (amap_fine) 2010 col = sb_bits(rank_addr, colbits, sb_open_fine_column); 2011 else 2012 col = sb_bits(rank_addr, colbits, sb_open_column); 2013 bank_address = sb_bank_bits(rank_addr, 18, 19, bank_xor_enable, 22, 23); 2014 bank_group = sb_bank_bits(rank_addr, bg0, 17, bank_xor_enable, 20, 21); 2015 } 2016 2017 row &= (1u << rowbits) - 1; 2018 2019 sprintf(msg, "row:0x%x col:0x%x bank_addr:%d bank_group:%d", 2020 row, col, bank_address, bank_group); 2021 return true; 2022 } 2023 2024 static bool sb_decode_ddr3(struct mem_ctl_info *mci, int ch, u8 rank, 2025 u64 rank_addr, char *msg) 2026 { 2027 pr_warn_once("DDR3 row/column decode not support yet!\n"); 2028 msg[0] = '\0'; 2029 return false; 2030 } 2031 2032 static int get_memory_error_data(struct mem_ctl_info *mci, 2033 u64 addr, 2034 u8 *socket, u8 *ha, 2035 long *channel_mask, 2036 u8 *rank, 2037 char **area_type, char *msg) 2038 { 2039 struct mem_ctl_info *new_mci; 2040 struct sbridge_pvt *pvt = mci->pvt_info; 2041 struct pci_dev *pci_ha; 2042 int n_rir, n_sads, n_tads, sad_way, sck_xch; 2043 int sad_interl, idx, base_ch; 2044 int interleave_mode, shiftup = 0; 2045 unsigned int sad_interleave[MAX_INTERLEAVE]; 2046 u32 reg, dram_rule; 2047 u8 ch_way, sck_way, pkg, sad_ha = 0, rankid = 0; 2048 u32 tad_offset; 2049 u32 rir_way; 2050 u32 mb, gb; 2051 u64 ch_addr, offset, limit = 0, prv = 0; 2052 u64 rank_addr; 2053 enum mem_type mtype; 2054 2055 /* 2056 * Step 0) Check if the address is at special memory ranges 2057 * The check bellow is probably enough to fill all cases where 2058 * the error is not inside a memory, except for the legacy 2059 * range (e. g. VGA addresses). It is unlikely, however, that the 2060 * memory controller would generate an error on that range. 2061 */ 2062 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) { 2063 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr); 2064 return -EINVAL; 2065 } 2066 if (addr >= (u64)pvt->tohm) { 2067 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr); 2068 return -EINVAL; 2069 } 2070 2071 /* 2072 * Step 1) Get socket 2073 */ 2074 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { 2075 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], 2076 ®); 2077 2078 if (!DRAM_RULE_ENABLE(reg)) 2079 continue; 2080 2081 limit = pvt->info.sad_limit(reg); 2082 if (limit <= prv) { 2083 sprintf(msg, "Can't discover the memory socket"); 2084 return -EINVAL; 2085 } 2086 if (addr <= limit) 2087 break; 2088 prv = limit; 2089 } 2090 if (n_sads == pvt->info.max_sad) { 2091 sprintf(msg, "Can't discover the memory socket"); 2092 return -EINVAL; 2093 } 2094 dram_rule = reg; 2095 *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule)); 2096 interleave_mode = pvt->info.interleave_mode(dram_rule); 2097 2098 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], 2099 ®); 2100 2101 if (pvt->info.type == SANDY_BRIDGE) { 2102 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); 2103 for (sad_way = 0; sad_way < 8; sad_way++) { 2104 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way); 2105 if (sad_way > 0 && sad_interl == pkg) 2106 break; 2107 sad_interleave[sad_way] = pkg; 2108 edac_dbg(0, "SAD interleave #%d: %d\n", 2109 sad_way, sad_interleave[sad_way]); 2110 } 2111 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n", 2112 pvt->sbridge_dev->mc, 2113 n_sads, 2114 addr, 2115 limit, 2116 sad_way + 7, 2117 !interleave_mode ? "" : "XOR[18:16]"); 2118 if (interleave_mode) 2119 idx = ((addr >> 6) ^ (addr >> 16)) & 7; 2120 else 2121 idx = (addr >> 6) & 7; 2122 switch (sad_way) { 2123 case 1: 2124 idx = 0; 2125 break; 2126 case 2: 2127 idx = idx & 1; 2128 break; 2129 case 4: 2130 idx = idx & 3; 2131 break; 2132 case 8: 2133 break; 2134 default: 2135 sprintf(msg, "Can't discover socket interleave"); 2136 return -EINVAL; 2137 } 2138 *socket = sad_interleave[idx]; 2139 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n", 2140 idx, sad_way, *socket); 2141 } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { 2142 int bits, a7mode = A7MODE(dram_rule); 2143 2144 if (a7mode) { 2145 /* A7 mode swaps P9 with P6 */ 2146 bits = GET_BITFIELD(addr, 7, 8) << 1; 2147 bits |= GET_BITFIELD(addr, 9, 9); 2148 } else 2149 bits = GET_BITFIELD(addr, 6, 8); 2150 2151 if (interleave_mode == 0) { 2152 /* interleave mode will XOR {8,7,6} with {18,17,16} */ 2153 idx = GET_BITFIELD(addr, 16, 18); 2154 idx ^= bits; 2155 } else 2156 idx = bits; 2157 2158 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); 2159 *socket = sad_pkg_socket(pkg); 2160 sad_ha = sad_pkg_ha(pkg); 2161 2162 if (a7mode) { 2163 /* MCChanShiftUpEnable */ 2164 pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®); 2165 shiftup = GET_BITFIELD(reg, 22, 22); 2166 } 2167 2168 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n", 2169 idx, *socket, sad_ha, shiftup); 2170 } else { 2171 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */ 2172 idx = (addr >> 6) & 7; 2173 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); 2174 *socket = sad_pkg_socket(pkg); 2175 sad_ha = sad_pkg_ha(pkg); 2176 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n", 2177 idx, *socket, sad_ha); 2178 } 2179 2180 *ha = sad_ha; 2181 2182 /* 2183 * Move to the proper node structure, in order to access the 2184 * right PCI registers 2185 */ 2186 new_mci = get_mci_for_node_id(*socket, sad_ha); 2187 if (!new_mci) { 2188 sprintf(msg, "Struct for socket #%u wasn't initialized", 2189 *socket); 2190 return -EINVAL; 2191 } 2192 mci = new_mci; 2193 pvt = mci->pvt_info; 2194 2195 /* 2196 * Step 2) Get memory channel 2197 */ 2198 prv = 0; 2199 pci_ha = pvt->pci_ha; 2200 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { 2201 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], ®); 2202 limit = TAD_LIMIT(reg); 2203 if (limit <= prv) { 2204 sprintf(msg, "Can't discover the memory channel"); 2205 return -EINVAL; 2206 } 2207 if (addr <= limit) 2208 break; 2209 prv = limit; 2210 } 2211 if (n_tads == MAX_TAD) { 2212 sprintf(msg, "Can't discover the memory channel"); 2213 return -EINVAL; 2214 } 2215 2216 ch_way = TAD_CH(reg) + 1; 2217 sck_way = TAD_SOCK(reg); 2218 2219 if (ch_way == 3) 2220 idx = addr >> 6; 2221 else { 2222 idx = (addr >> (6 + sck_way + shiftup)) & 0x3; 2223 if (pvt->is_chan_hash) 2224 idx = haswell_chan_hash(idx, addr); 2225 } 2226 idx = idx % ch_way; 2227 2228 /* 2229 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ??? 2230 */ 2231 switch (idx) { 2232 case 0: 2233 base_ch = TAD_TGT0(reg); 2234 break; 2235 case 1: 2236 base_ch = TAD_TGT1(reg); 2237 break; 2238 case 2: 2239 base_ch = TAD_TGT2(reg); 2240 break; 2241 case 3: 2242 base_ch = TAD_TGT3(reg); 2243 break; 2244 default: 2245 sprintf(msg, "Can't discover the TAD target"); 2246 return -EINVAL; 2247 } 2248 *channel_mask = 1 << base_ch; 2249 2250 pci_read_config_dword(pvt->pci_tad[base_ch], tad_ch_nilv_offset[n_tads], &tad_offset); 2251 2252 if (pvt->mirror_mode == FULL_MIRRORING || 2253 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && n_tads == 0)) { 2254 *channel_mask |= 1 << ((base_ch + 2) % 4); 2255 switch(ch_way) { 2256 case 2: 2257 case 4: 2258 sck_xch = (1 << sck_way) * (ch_way >> 1); 2259 break; 2260 default: 2261 sprintf(msg, "Invalid mirror set. Can't decode addr"); 2262 return -EINVAL; 2263 } 2264 2265 pvt->is_cur_addr_mirrored = true; 2266 } else { 2267 sck_xch = (1 << sck_way) * ch_way; 2268 pvt->is_cur_addr_mirrored = false; 2269 } 2270 2271 if (pvt->is_lockstep) 2272 *channel_mask |= 1 << ((base_ch + 1) % 4); 2273 2274 offset = TAD_OFFSET(tad_offset); 2275 2276 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n", 2277 n_tads, 2278 addr, 2279 limit, 2280 sck_way, 2281 ch_way, 2282 offset, 2283 idx, 2284 base_ch, 2285 *channel_mask); 2286 2287 /* Calculate channel address */ 2288 /* Remove the TAD offset */ 2289 2290 if (offset > addr) { 2291 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!", 2292 offset, addr); 2293 return -EINVAL; 2294 } 2295 2296 ch_addr = addr - offset; 2297 ch_addr >>= (6 + shiftup); 2298 ch_addr /= sck_xch; 2299 ch_addr <<= (6 + shiftup); 2300 ch_addr |= addr & ((1 << (6 + shiftup)) - 1); 2301 2302 /* 2303 * Step 3) Decode rank 2304 */ 2305 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) { 2306 pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], ®); 2307 2308 if (!IS_RIR_VALID(reg)) 2309 continue; 2310 2311 limit = pvt->info.rir_limit(reg); 2312 gb = div_u64_rem(limit >> 20, 1024, &mb); 2313 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n", 2314 n_rir, 2315 gb, (mb*1000)/1024, 2316 limit, 2317 1 << RIR_WAY(reg)); 2318 if (ch_addr <= limit) 2319 break; 2320 } 2321 if (n_rir == MAX_RIR_RANGES) { 2322 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx", 2323 ch_addr); 2324 return -EINVAL; 2325 } 2326 rir_way = RIR_WAY(reg); 2327 2328 if (pvt->is_close_pg) 2329 idx = (ch_addr >> 6); 2330 else 2331 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */ 2332 idx %= 1 << rir_way; 2333 2334 pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], ®); 2335 *rank = RIR_RNK_TGT(pvt->info.type, reg); 2336 2337 if (pvt->info.type == BROADWELL) { 2338 if (pvt->is_close_pg) 2339 shiftup = 6; 2340 else 2341 shiftup = 13; 2342 2343 rank_addr = ch_addr >> shiftup; 2344 rank_addr /= (1 << rir_way); 2345 rank_addr <<= shiftup; 2346 rank_addr |= ch_addr & GENMASK_ULL(shiftup - 1, 0); 2347 rank_addr -= RIR_OFFSET(pvt->info.type, reg); 2348 2349 mtype = pvt->info.get_memory_type(pvt); 2350 rankid = *rank; 2351 if (mtype == MEM_DDR4 || mtype == MEM_RDDR4) 2352 sb_decode_ddr4(mci, base_ch, rankid, rank_addr, msg); 2353 else 2354 sb_decode_ddr3(mci, base_ch, rankid, rank_addr, msg); 2355 } else { 2356 msg[0] = '\0'; 2357 } 2358 2359 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", 2360 n_rir, 2361 ch_addr, 2362 limit, 2363 rir_way, 2364 idx); 2365 2366 return 0; 2367 } 2368 2369 static int get_memory_error_data_from_mce(struct mem_ctl_info *mci, 2370 const struct mce *m, u8 *socket, 2371 u8 *ha, long *channel_mask, 2372 char *msg) 2373 { 2374 u32 reg, channel = GET_BITFIELD(m->status, 0, 3); 2375 struct mem_ctl_info *new_mci; 2376 struct sbridge_pvt *pvt; 2377 struct pci_dev *pci_ha; 2378 bool tad0; 2379 2380 if (channel >= NUM_CHANNELS) { 2381 sprintf(msg, "Invalid channel 0x%x", channel); 2382 return -EINVAL; 2383 } 2384 2385 pvt = mci->pvt_info; 2386 if (!pvt->info.get_ha) { 2387 sprintf(msg, "No get_ha()"); 2388 return -EINVAL; 2389 } 2390 *ha = pvt->info.get_ha(m->bank); 2391 if (*ha != 0 && *ha != 1) { 2392 sprintf(msg, "Impossible bank %d", m->bank); 2393 return -EINVAL; 2394 } 2395 2396 *socket = m->socketid; 2397 new_mci = get_mci_for_node_id(*socket, *ha); 2398 if (!new_mci) { 2399 strcpy(msg, "mci socket got corrupted!"); 2400 return -EINVAL; 2401 } 2402 2403 pvt = new_mci->pvt_info; 2404 pci_ha = pvt->pci_ha; 2405 pci_read_config_dword(pci_ha, tad_dram_rule[0], ®); 2406 tad0 = m->addr <= TAD_LIMIT(reg); 2407 2408 *channel_mask = 1 << channel; 2409 if (pvt->mirror_mode == FULL_MIRRORING || 2410 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && tad0)) { 2411 *channel_mask |= 1 << ((channel + 2) % 4); 2412 pvt->is_cur_addr_mirrored = true; 2413 } else { 2414 pvt->is_cur_addr_mirrored = false; 2415 } 2416 2417 if (pvt->is_lockstep) 2418 *channel_mask |= 1 << ((channel + 1) % 4); 2419 2420 return 0; 2421 } 2422 2423 /**************************************************************************** 2424 Device initialization routines: put/get, init/exit 2425 ****************************************************************************/ 2426 2427 /* 2428 * sbridge_put_all_devices 'put' all the devices that we have 2429 * reserved via 'get' 2430 */ 2431 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev) 2432 { 2433 int i; 2434 2435 edac_dbg(0, "\n"); 2436 for (i = 0; i < sbridge_dev->n_devs; i++) { 2437 struct pci_dev *pdev = sbridge_dev->pdev[i]; 2438 if (!pdev) 2439 continue; 2440 edac_dbg(0, "Removing dev %02x:%02x.%d\n", 2441 pdev->bus->number, 2442 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 2443 pci_dev_put(pdev); 2444 } 2445 } 2446 2447 static void sbridge_put_all_devices(void) 2448 { 2449 struct sbridge_dev *sbridge_dev, *tmp; 2450 2451 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) { 2452 sbridge_put_devices(sbridge_dev); 2453 free_sbridge_dev(sbridge_dev); 2454 } 2455 } 2456 2457 static int sbridge_get_onedevice(struct pci_dev **prev, 2458 u8 *num_mc, 2459 const struct pci_id_table *table, 2460 const unsigned devno, 2461 const int multi_bus) 2462 { 2463 struct sbridge_dev *sbridge_dev = NULL; 2464 const struct pci_id_descr *dev_descr = &table->descr[devno]; 2465 struct pci_dev *pdev = NULL; 2466 int seg = 0; 2467 u8 bus = 0; 2468 int i = 0; 2469 2470 sbridge_printk(KERN_DEBUG, 2471 "Seeking for: PCI ID %04x:%04x\n", 2472 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 2473 2474 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 2475 dev_descr->dev_id, *prev); 2476 2477 if (!pdev) { 2478 if (*prev) { 2479 *prev = pdev; 2480 return 0; 2481 } 2482 2483 if (dev_descr->optional) 2484 return 0; 2485 2486 /* if the HA wasn't found */ 2487 if (devno == 0) 2488 return -ENODEV; 2489 2490 sbridge_printk(KERN_INFO, 2491 "Device not found: %04x:%04x\n", 2492 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 2493 2494 /* End of list, leave */ 2495 return -ENODEV; 2496 } 2497 seg = pci_domain_nr(pdev->bus); 2498 bus = pdev->bus->number; 2499 2500 next_imc: 2501 sbridge_dev = get_sbridge_dev(seg, bus, dev_descr->dom, 2502 multi_bus, sbridge_dev); 2503 if (!sbridge_dev) { 2504 /* If the HA1 wasn't found, don't create EDAC second memory controller */ 2505 if (dev_descr->dom == IMC1 && devno != 1) { 2506 edac_dbg(0, "Skip IMC1: %04x:%04x (since HA1 was absent)\n", 2507 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 2508 pci_dev_put(pdev); 2509 return 0; 2510 } 2511 2512 if (dev_descr->dom == SOCK) 2513 goto out_imc; 2514 2515 sbridge_dev = alloc_sbridge_dev(seg, bus, dev_descr->dom, table); 2516 if (!sbridge_dev) { 2517 pci_dev_put(pdev); 2518 return -ENOMEM; 2519 } 2520 (*num_mc)++; 2521 } 2522 2523 if (sbridge_dev->pdev[sbridge_dev->i_devs]) { 2524 sbridge_printk(KERN_ERR, 2525 "Duplicated device for %04x:%04x\n", 2526 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 2527 pci_dev_put(pdev); 2528 return -ENODEV; 2529 } 2530 2531 sbridge_dev->pdev[sbridge_dev->i_devs++] = pdev; 2532 2533 /* pdev belongs to more than one IMC, do extra gets */ 2534 if (++i > 1) 2535 pci_dev_get(pdev); 2536 2537 if (dev_descr->dom == SOCK && i < table->n_imcs_per_sock) 2538 goto next_imc; 2539 2540 out_imc: 2541 /* Be sure that the device is enabled */ 2542 if (unlikely(pci_enable_device(pdev) < 0)) { 2543 sbridge_printk(KERN_ERR, 2544 "Couldn't enable %04x:%04x\n", 2545 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 2546 return -ENODEV; 2547 } 2548 2549 edac_dbg(0, "Detected %04x:%04x\n", 2550 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 2551 2552 /* 2553 * As stated on drivers/pci/search.c, the reference count for 2554 * @from is always decremented if it is not %NULL. So, as we need 2555 * to get all devices up to null, we need to do a get for the device 2556 */ 2557 pci_dev_get(pdev); 2558 2559 *prev = pdev; 2560 2561 return 0; 2562 } 2563 2564 /* 2565 * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's 2566 * devices we want to reference for this driver. 2567 * @num_mc: pointer to the memory controllers count, to be incremented in case 2568 * of success. 2569 * @table: model specific table 2570 * 2571 * returns 0 in case of success or error code 2572 */ 2573 static int sbridge_get_all_devices(u8 *num_mc, 2574 const struct pci_id_table *table) 2575 { 2576 int i, rc; 2577 struct pci_dev *pdev = NULL; 2578 int allow_dups = 0; 2579 int multi_bus = 0; 2580 2581 if (table->type == KNIGHTS_LANDING) 2582 allow_dups = multi_bus = 1; 2583 while (table && table->descr) { 2584 for (i = 0; i < table->n_devs_per_sock; i++) { 2585 if (!allow_dups || i == 0 || 2586 table->descr[i].dev_id != 2587 table->descr[i-1].dev_id) { 2588 pdev = NULL; 2589 } 2590 do { 2591 rc = sbridge_get_onedevice(&pdev, num_mc, 2592 table, i, multi_bus); 2593 if (rc < 0) { 2594 if (i == 0) { 2595 i = table->n_devs_per_sock; 2596 break; 2597 } 2598 sbridge_put_all_devices(); 2599 return -ENODEV; 2600 } 2601 } while (pdev && !allow_dups); 2602 } 2603 table++; 2604 } 2605 2606 return 0; 2607 } 2608 2609 /* 2610 * Device IDs for {SBRIDGE,IBRIDGE,HASWELL,BROADWELL}_IMC_HA0_TAD0 are in 2611 * the format: XXXa. So we can convert from a device to the corresponding 2612 * channel like this 2613 */ 2614 #define TAD_DEV_TO_CHAN(dev) (((dev) & 0xf) - 0xa) 2615 2616 static int sbridge_mci_bind_devs(struct mem_ctl_info *mci, 2617 struct sbridge_dev *sbridge_dev) 2618 { 2619 struct sbridge_pvt *pvt = mci->pvt_info; 2620 struct pci_dev *pdev; 2621 u8 saw_chan_mask = 0; 2622 int i; 2623 2624 for (i = 0; i < sbridge_dev->n_devs; i++) { 2625 pdev = sbridge_dev->pdev[i]; 2626 if (!pdev) 2627 continue; 2628 2629 switch (pdev->device) { 2630 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0: 2631 pvt->pci_sad0 = pdev; 2632 break; 2633 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1: 2634 pvt->pci_sad1 = pdev; 2635 break; 2636 case PCI_DEVICE_ID_INTEL_SBRIDGE_BR: 2637 pvt->pci_br0 = pdev; 2638 break; 2639 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0: 2640 pvt->pci_ha = pdev; 2641 break; 2642 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA: 2643 pvt->pci_ta = pdev; 2644 break; 2645 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS: 2646 pvt->pci_ras = pdev; 2647 break; 2648 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0: 2649 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1: 2650 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2: 2651 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3: 2652 { 2653 int id = TAD_DEV_TO_CHAN(pdev->device); 2654 pvt->pci_tad[id] = pdev; 2655 saw_chan_mask |= 1 << id; 2656 } 2657 break; 2658 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO: 2659 pvt->pci_ddrio = pdev; 2660 break; 2661 default: 2662 goto error; 2663 } 2664 2665 edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n", 2666 pdev->vendor, pdev->device, 2667 sbridge_dev->bus, 2668 pdev); 2669 } 2670 2671 /* Check if everything were registered */ 2672 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha || 2673 !pvt->pci_ras || !pvt->pci_ta) 2674 goto enodev; 2675 2676 if (saw_chan_mask != 0x0f) 2677 goto enodev; 2678 return 0; 2679 2680 enodev: 2681 sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); 2682 return -ENODEV; 2683 2684 error: 2685 sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n", 2686 PCI_VENDOR_ID_INTEL, pdev->device); 2687 return -EINVAL; 2688 } 2689 2690 static int ibridge_mci_bind_devs(struct mem_ctl_info *mci, 2691 struct sbridge_dev *sbridge_dev) 2692 { 2693 struct sbridge_pvt *pvt = mci->pvt_info; 2694 struct pci_dev *pdev; 2695 u8 saw_chan_mask = 0; 2696 int i; 2697 2698 for (i = 0; i < sbridge_dev->n_devs; i++) { 2699 pdev = sbridge_dev->pdev[i]; 2700 if (!pdev) 2701 continue; 2702 2703 switch (pdev->device) { 2704 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0: 2705 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1: 2706 pvt->pci_ha = pdev; 2707 break; 2708 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA: 2709 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA: 2710 pvt->pci_ta = pdev; 2711 break; 2712 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS: 2713 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS: 2714 pvt->pci_ras = pdev; 2715 break; 2716 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0: 2717 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1: 2718 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2: 2719 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3: 2720 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0: 2721 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1: 2722 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2: 2723 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3: 2724 { 2725 int id = TAD_DEV_TO_CHAN(pdev->device); 2726 pvt->pci_tad[id] = pdev; 2727 saw_chan_mask |= 1 << id; 2728 } 2729 break; 2730 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0: 2731 pvt->pci_ddrio = pdev; 2732 break; 2733 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0: 2734 pvt->pci_ddrio = pdev; 2735 break; 2736 case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD: 2737 pvt->pci_sad0 = pdev; 2738 break; 2739 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0: 2740 pvt->pci_br0 = pdev; 2741 break; 2742 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1: 2743 pvt->pci_br1 = pdev; 2744 break; 2745 default: 2746 goto error; 2747 } 2748 2749 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", 2750 sbridge_dev->bus, 2751 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2752 pdev); 2753 } 2754 2755 /* Check if everything were registered */ 2756 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_br0 || 2757 !pvt->pci_br1 || !pvt->pci_ras || !pvt->pci_ta) 2758 goto enodev; 2759 2760 if (saw_chan_mask != 0x0f && /* -EN/-EX */ 2761 saw_chan_mask != 0x03) /* -EP */ 2762 goto enodev; 2763 return 0; 2764 2765 enodev: 2766 sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); 2767 return -ENODEV; 2768 2769 error: 2770 sbridge_printk(KERN_ERR, 2771 "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL, 2772 pdev->device); 2773 return -EINVAL; 2774 } 2775 2776 static int haswell_mci_bind_devs(struct mem_ctl_info *mci, 2777 struct sbridge_dev *sbridge_dev) 2778 { 2779 struct sbridge_pvt *pvt = mci->pvt_info; 2780 struct pci_dev *pdev; 2781 u8 saw_chan_mask = 0; 2782 int i; 2783 2784 /* there's only one device per system; not tied to any bus */ 2785 if (pvt->info.pci_vtd == NULL) 2786 /* result will be checked later */ 2787 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, 2788 PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC, 2789 NULL); 2790 2791 for (i = 0; i < sbridge_dev->n_devs; i++) { 2792 pdev = sbridge_dev->pdev[i]; 2793 if (!pdev) 2794 continue; 2795 2796 switch (pdev->device) { 2797 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0: 2798 pvt->pci_sad0 = pdev; 2799 break; 2800 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1: 2801 pvt->pci_sad1 = pdev; 2802 break; 2803 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0: 2804 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1: 2805 pvt->pci_ha = pdev; 2806 break; 2807 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA: 2808 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA: 2809 pvt->pci_ta = pdev; 2810 break; 2811 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM: 2812 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM: 2813 pvt->pci_ras = pdev; 2814 break; 2815 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0: 2816 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1: 2817 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2: 2818 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3: 2819 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0: 2820 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1: 2821 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2: 2822 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3: 2823 { 2824 int id = TAD_DEV_TO_CHAN(pdev->device); 2825 pvt->pci_tad[id] = pdev; 2826 saw_chan_mask |= 1 << id; 2827 } 2828 break; 2829 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0: 2830 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1: 2831 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2: 2832 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3: 2833 if (!pvt->pci_ddrio) 2834 pvt->pci_ddrio = pdev; 2835 break; 2836 default: 2837 break; 2838 } 2839 2840 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", 2841 sbridge_dev->bus, 2842 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2843 pdev); 2844 } 2845 2846 /* Check if everything were registered */ 2847 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 || 2848 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) 2849 goto enodev; 2850 2851 if (saw_chan_mask != 0x0f && /* -EN/-EX */ 2852 saw_chan_mask != 0x03) /* -EP */ 2853 goto enodev; 2854 return 0; 2855 2856 enodev: 2857 sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); 2858 return -ENODEV; 2859 } 2860 2861 static int broadwell_mci_bind_devs(struct mem_ctl_info *mci, 2862 struct sbridge_dev *sbridge_dev) 2863 { 2864 struct sbridge_pvt *pvt = mci->pvt_info; 2865 struct pci_dev *pdev; 2866 u8 saw_chan_mask = 0; 2867 int i; 2868 2869 /* there's only one device per system; not tied to any bus */ 2870 if (pvt->info.pci_vtd == NULL) 2871 /* result will be checked later */ 2872 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, 2873 PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC, 2874 NULL); 2875 2876 for (i = 0; i < sbridge_dev->n_devs; i++) { 2877 pdev = sbridge_dev->pdev[i]; 2878 if (!pdev) 2879 continue; 2880 2881 switch (pdev->device) { 2882 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0: 2883 pvt->pci_sad0 = pdev; 2884 break; 2885 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1: 2886 pvt->pci_sad1 = pdev; 2887 break; 2888 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0: 2889 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1: 2890 pvt->pci_ha = pdev; 2891 break; 2892 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA: 2893 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA: 2894 pvt->pci_ta = pdev; 2895 break; 2896 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM: 2897 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM: 2898 pvt->pci_ras = pdev; 2899 break; 2900 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0: 2901 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1: 2902 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2: 2903 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3: 2904 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0: 2905 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1: 2906 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2: 2907 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3: 2908 { 2909 int id = TAD_DEV_TO_CHAN(pdev->device); 2910 pvt->pci_tad[id] = pdev; 2911 saw_chan_mask |= 1 << id; 2912 } 2913 break; 2914 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0: 2915 pvt->pci_ddrio = pdev; 2916 break; 2917 default: 2918 break; 2919 } 2920 2921 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", 2922 sbridge_dev->bus, 2923 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2924 pdev); 2925 } 2926 2927 /* Check if everything were registered */ 2928 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 || 2929 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) 2930 goto enodev; 2931 2932 if (saw_chan_mask != 0x0f && /* -EN/-EX */ 2933 saw_chan_mask != 0x03) /* -EP */ 2934 goto enodev; 2935 return 0; 2936 2937 enodev: 2938 sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); 2939 return -ENODEV; 2940 } 2941 2942 static int knl_mci_bind_devs(struct mem_ctl_info *mci, 2943 struct sbridge_dev *sbridge_dev) 2944 { 2945 struct sbridge_pvt *pvt = mci->pvt_info; 2946 struct pci_dev *pdev; 2947 int dev, func; 2948 2949 int i; 2950 int devidx; 2951 2952 for (i = 0; i < sbridge_dev->n_devs; i++) { 2953 pdev = sbridge_dev->pdev[i]; 2954 if (!pdev) 2955 continue; 2956 2957 /* Extract PCI device and function. */ 2958 dev = (pdev->devfn >> 3) & 0x1f; 2959 func = pdev->devfn & 0x7; 2960 2961 switch (pdev->device) { 2962 case PCI_DEVICE_ID_INTEL_KNL_IMC_MC: 2963 if (dev == 8) 2964 pvt->knl.pci_mc0 = pdev; 2965 else if (dev == 9) 2966 pvt->knl.pci_mc1 = pdev; 2967 else { 2968 sbridge_printk(KERN_ERR, 2969 "Memory controller in unexpected place! (dev %d, fn %d)\n", 2970 dev, func); 2971 continue; 2972 } 2973 break; 2974 2975 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0: 2976 pvt->pci_sad0 = pdev; 2977 break; 2978 2979 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1: 2980 pvt->pci_sad1 = pdev; 2981 break; 2982 2983 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHA: 2984 /* There are one of these per tile, and range from 2985 * 1.14.0 to 1.18.5. 2986 */ 2987 devidx = ((dev-14)*8)+func; 2988 2989 if (devidx < 0 || devidx >= KNL_MAX_CHAS) { 2990 sbridge_printk(KERN_ERR, 2991 "Caching and Home Agent in unexpected place! (dev %d, fn %d)\n", 2992 dev, func); 2993 continue; 2994 } 2995 2996 WARN_ON(pvt->knl.pci_cha[devidx] != NULL); 2997 2998 pvt->knl.pci_cha[devidx] = pdev; 2999 break; 3000 3001 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN: 3002 devidx = -1; 3003 3004 /* 3005 * MC0 channels 0-2 are device 9 function 2-4, 3006 * MC1 channels 3-5 are device 8 function 2-4. 3007 */ 3008 3009 if (dev == 9) 3010 devidx = func-2; 3011 else if (dev == 8) 3012 devidx = 3 + (func-2); 3013 3014 if (devidx < 0 || devidx >= KNL_MAX_CHANNELS) { 3015 sbridge_printk(KERN_ERR, 3016 "DRAM Channel Registers in unexpected place! (dev %d, fn %d)\n", 3017 dev, func); 3018 continue; 3019 } 3020 3021 WARN_ON(pvt->knl.pci_channel[devidx] != NULL); 3022 pvt->knl.pci_channel[devidx] = pdev; 3023 break; 3024 3025 case PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM: 3026 pvt->knl.pci_mc_info = pdev; 3027 break; 3028 3029 case PCI_DEVICE_ID_INTEL_KNL_IMC_TA: 3030 pvt->pci_ta = pdev; 3031 break; 3032 3033 default: 3034 sbridge_printk(KERN_ERR, "Unexpected device %d\n", 3035 pdev->device); 3036 break; 3037 } 3038 } 3039 3040 if (!pvt->knl.pci_mc0 || !pvt->knl.pci_mc1 || 3041 !pvt->pci_sad0 || !pvt->pci_sad1 || 3042 !pvt->pci_ta) { 3043 goto enodev; 3044 } 3045 3046 for (i = 0; i < KNL_MAX_CHANNELS; i++) { 3047 if (!pvt->knl.pci_channel[i]) { 3048 sbridge_printk(KERN_ERR, "Missing channel %d\n", i); 3049 goto enodev; 3050 } 3051 } 3052 3053 for (i = 0; i < KNL_MAX_CHAS; i++) { 3054 if (!pvt->knl.pci_cha[i]) { 3055 sbridge_printk(KERN_ERR, "Missing CHA %d\n", i); 3056 goto enodev; 3057 } 3058 } 3059 3060 return 0; 3061 3062 enodev: 3063 sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); 3064 return -ENODEV; 3065 } 3066 3067 /**************************************************************************** 3068 Error check routines 3069 ****************************************************************************/ 3070 3071 /* 3072 * While Sandy Bridge has error count registers, SMI BIOS read values from 3073 * and resets the counters. So, they are not reliable for the OS to read 3074 * from them. So, we have no option but to just trust on whatever MCE is 3075 * telling us about the errors. 3076 */ 3077 static void sbridge_mce_output_error(struct mem_ctl_info *mci, 3078 const struct mce *m) 3079 { 3080 struct mem_ctl_info *new_mci; 3081 struct sbridge_pvt *pvt = mci->pvt_info; 3082 enum hw_event_mc_err_type tp_event; 3083 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); 3084 bool overflow = GET_BITFIELD(m->status, 62, 62); 3085 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); 3086 bool recoverable; 3087 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); 3088 u32 mscod = GET_BITFIELD(m->status, 16, 31); 3089 u32 errcode = GET_BITFIELD(m->status, 0, 15); 3090 u32 channel = GET_BITFIELD(m->status, 0, 3); 3091 u32 optypenum = GET_BITFIELD(m->status, 4, 6); 3092 /* 3093 * Bits 5-0 of MCi_MISC give the least significant bit that is valid. 3094 * A value 6 is for cache line aligned address, a value 12 is for page 3095 * aligned address reported by patrol scrubber. 3096 */ 3097 u32 lsb = GET_BITFIELD(m->misc, 0, 5); 3098 char *optype, *area_type = "DRAM"; 3099 long channel_mask, first_channel; 3100 u8 rank = 0xff, socket, ha; 3101 int rc, dimm; 3102 3103 if (pvt->info.type != SANDY_BRIDGE) 3104 recoverable = true; 3105 else 3106 recoverable = GET_BITFIELD(m->status, 56, 56); 3107 3108 if (uncorrected_error) { 3109 core_err_cnt = 1; 3110 if (ripv) { 3111 tp_event = HW_EVENT_ERR_UNCORRECTED; 3112 } else { 3113 tp_event = HW_EVENT_ERR_FATAL; 3114 } 3115 } else { 3116 tp_event = HW_EVENT_ERR_CORRECTED; 3117 } 3118 3119 /* 3120 * According with Table 15-9 of the Intel Architecture spec vol 3A, 3121 * memory errors should fit in this mask: 3122 * 000f 0000 1mmm cccc (binary) 3123 * where: 3124 * f = Correction Report Filtering Bit. If 1, subsequent errors 3125 * won't be shown 3126 * mmm = error type 3127 * cccc = channel 3128 * If the mask doesn't match, report an error to the parsing logic 3129 */ 3130 switch (optypenum) { 3131 case 0: 3132 optype = "generic undef request error"; 3133 break; 3134 case 1: 3135 optype = "memory read error"; 3136 break; 3137 case 2: 3138 optype = "memory write error"; 3139 break; 3140 case 3: 3141 optype = "addr/cmd error"; 3142 break; 3143 case 4: 3144 optype = "memory scrubbing error"; 3145 break; 3146 default: 3147 optype = "reserved"; 3148 break; 3149 } 3150 3151 if (pvt->info.type == KNIGHTS_LANDING) { 3152 if (channel == 14) { 3153 edac_dbg(0, "%s%s err_code:%04x:%04x EDRAM bank %d\n", 3154 overflow ? " OVERFLOW" : "", 3155 (uncorrected_error && recoverable) 3156 ? " recoverable" : "", 3157 mscod, errcode, 3158 m->bank); 3159 } else { 3160 char A = *("A"); 3161 3162 /* 3163 * Reported channel is in range 0-2, so we can't map it 3164 * back to mc. To figure out mc we check machine check 3165 * bank register that reported this error. 3166 * bank15 means mc0 and bank16 means mc1. 3167 */ 3168 channel = knl_channel_remap(m->bank == 16, channel); 3169 channel_mask = 1 << channel; 3170 3171 snprintf(sb_msg, sizeof(sb_msg), 3172 "%s%s err_code:%04x:%04x channel:%d (DIMM_%c)", 3173 overflow ? " OVERFLOW" : "", 3174 (uncorrected_error && recoverable) 3175 ? " recoverable" : " ", 3176 mscod, errcode, channel, A + channel); 3177 edac_mc_handle_error(tp_event, mci, core_err_cnt, 3178 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, 3179 channel, 0, -1, 3180 optype, sb_msg); 3181 } 3182 return; 3183 } else if (lsb < 12) { 3184 rc = get_memory_error_data(mci, m->addr, &socket, &ha, 3185 &channel_mask, &rank, 3186 &area_type, sb_msg); 3187 } else { 3188 rc = get_memory_error_data_from_mce(mci, m, &socket, &ha, 3189 &channel_mask, sb_msg); 3190 } 3191 3192 if (rc < 0) 3193 goto err_parsing; 3194 new_mci = get_mci_for_node_id(socket, ha); 3195 if (!new_mci) { 3196 strscpy(sb_msg, "Error: socket got corrupted!"); 3197 goto err_parsing; 3198 } 3199 mci = new_mci; 3200 pvt = mci->pvt_info; 3201 3202 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS); 3203 3204 if (rank == 0xff) 3205 dimm = -1; 3206 else if (rank < 4) 3207 dimm = 0; 3208 else if (rank < 8) 3209 dimm = 1; 3210 else 3211 dimm = 2; 3212 3213 /* 3214 * FIXME: On some memory configurations (mirror, lockstep), the 3215 * Memory Controller can't point the error to a single DIMM. The 3216 * EDAC core should be handling the channel mask, in order to point 3217 * to the group of dimm's where the error may be happening. 3218 */ 3219 if (!pvt->is_lockstep && !pvt->is_cur_addr_mirrored && !pvt->is_close_pg) 3220 channel = first_channel; 3221 snprintf(sb_msg_full, sizeof(sb_msg_full), 3222 "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d %s", 3223 overflow ? " OVERFLOW" : "", 3224 (uncorrected_error && recoverable) ? " recoverable" : "", 3225 area_type, 3226 mscod, errcode, 3227 socket, ha, 3228 channel_mask, 3229 rank, sb_msg); 3230 3231 edac_dbg(0, "%s\n", sb_msg_full); 3232 3233 /* FIXME: need support for channel mask */ 3234 3235 if (channel == CHANNEL_UNSPECIFIED) 3236 channel = -1; 3237 3238 /* Call the helper to output message */ 3239 edac_mc_handle_error(tp_event, mci, core_err_cnt, 3240 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, 3241 channel, dimm, -1, 3242 optype, sb_msg_full); 3243 return; 3244 err_parsing: 3245 edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0, 3246 -1, -1, -1, 3247 sb_msg, ""); 3248 3249 } 3250 3251 /* 3252 * Check that logging is enabled and that this is the right type 3253 * of error for us to handle. 3254 */ 3255 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val, 3256 void *data) 3257 { 3258 struct mce *mce = (struct mce *)data; 3259 struct mem_ctl_info *mci; 3260 char *type; 3261 3262 if (mce->kflags & MCE_HANDLED_CEC) 3263 return NOTIFY_DONE; 3264 3265 /* 3266 * Just let mcelog handle it if the error is 3267 * outside the memory controller. A memory error 3268 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0. 3269 * bit 12 has an special meaning. 3270 */ 3271 if ((mce->status & 0xefff) >> 7 != 1) 3272 return NOTIFY_DONE; 3273 3274 /* Check ADDRV bit in STATUS */ 3275 if (!GET_BITFIELD(mce->status, 58, 58)) 3276 return NOTIFY_DONE; 3277 3278 /* Check MISCV bit in STATUS */ 3279 if (!GET_BITFIELD(mce->status, 59, 59)) 3280 return NOTIFY_DONE; 3281 3282 /* Check address type in MISC (physical address only) */ 3283 if (GET_BITFIELD(mce->misc, 6, 8) != 2) 3284 return NOTIFY_DONE; 3285 3286 mci = get_mci_for_node_id(mce->socketid, IMC0); 3287 if (!mci) 3288 return NOTIFY_DONE; 3289 3290 if (mce->mcgstatus & MCG_STATUS_MCIP) 3291 type = "Exception"; 3292 else 3293 type = "Event"; 3294 3295 sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n"); 3296 3297 sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx " 3298 "Bank %d: %016Lx\n", mce->extcpu, type, 3299 mce->mcgstatus, mce->bank, mce->status); 3300 sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc); 3301 sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr); 3302 sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc); 3303 3304 sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET " 3305 "%u APIC %x\n", mce->cpuvendor, mce->cpuid, 3306 mce->time, mce->socketid, mce->apicid); 3307 3308 sbridge_mce_output_error(mci, mce); 3309 3310 /* Advice mcelog that the error were handled */ 3311 mce->kflags |= MCE_HANDLED_EDAC; 3312 return NOTIFY_OK; 3313 } 3314 3315 static struct notifier_block sbridge_mce_dec = { 3316 .notifier_call = sbridge_mce_check_error, 3317 .priority = MCE_PRIO_EDAC, 3318 }; 3319 3320 /**************************************************************************** 3321 EDAC register/unregister logic 3322 ****************************************************************************/ 3323 3324 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev) 3325 { 3326 struct mem_ctl_info *mci = sbridge_dev->mci; 3327 3328 if (unlikely(!mci || !mci->pvt_info)) { 3329 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev); 3330 3331 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n"); 3332 return; 3333 } 3334 3335 edac_dbg(0, "MC: mci = %p, dev = %p\n", 3336 mci, &sbridge_dev->pdev[0]->dev); 3337 3338 /* Remove MC sysfs nodes */ 3339 edac_mc_del_mc(mci->pdev); 3340 3341 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); 3342 kfree(mci->ctl_name); 3343 edac_mc_free(mci); 3344 sbridge_dev->mci = NULL; 3345 } 3346 3347 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type) 3348 { 3349 struct mem_ctl_info *mci; 3350 struct edac_mc_layer layers[2]; 3351 struct sbridge_pvt *pvt; 3352 struct pci_dev *pdev = sbridge_dev->pdev[0]; 3353 int rc; 3354 3355 /* allocate a new MC control structure */ 3356 layers[0].type = EDAC_MC_LAYER_CHANNEL; 3357 layers[0].size = type == KNIGHTS_LANDING ? 3358 KNL_MAX_CHANNELS : NUM_CHANNELS; 3359 layers[0].is_virt_csrow = false; 3360 layers[1].type = EDAC_MC_LAYER_SLOT; 3361 layers[1].size = type == KNIGHTS_LANDING ? 1 : MAX_DIMMS; 3362 layers[1].is_virt_csrow = true; 3363 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers, 3364 sizeof(*pvt)); 3365 3366 if (unlikely(!mci)) 3367 return -ENOMEM; 3368 3369 edac_dbg(0, "MC: mci = %p, dev = %p\n", 3370 mci, &pdev->dev); 3371 3372 pvt = mci->pvt_info; 3373 memset(pvt, 0, sizeof(*pvt)); 3374 3375 /* Associate sbridge_dev and mci for future usage */ 3376 pvt->sbridge_dev = sbridge_dev; 3377 sbridge_dev->mci = mci; 3378 3379 mci->mtype_cap = type == KNIGHTS_LANDING ? 3380 MEM_FLAG_DDR4 : MEM_FLAG_DDR3; 3381 mci->edac_ctl_cap = EDAC_FLAG_NONE; 3382 mci->edac_cap = EDAC_FLAG_NONE; 3383 mci->mod_name = EDAC_MOD_STR; 3384 mci->dev_name = pci_name(pdev); 3385 mci->ctl_page_to_phys = NULL; 3386 3387 pvt->info.type = type; 3388 switch (type) { 3389 case IVY_BRIDGE: 3390 pvt->info.rankcfgr = IB_RANK_CFG_A; 3391 pvt->info.get_tolm = ibridge_get_tolm; 3392 pvt->info.get_tohm = ibridge_get_tohm; 3393 pvt->info.dram_rule = ibridge_dram_rule; 3394 pvt->info.get_memory_type = get_memory_type; 3395 pvt->info.get_node_id = get_node_id; 3396 pvt->info.get_ha = ibridge_get_ha; 3397 pvt->info.rir_limit = rir_limit; 3398 pvt->info.sad_limit = sad_limit; 3399 pvt->info.interleave_mode = interleave_mode; 3400 pvt->info.dram_attr = dram_attr; 3401 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); 3402 pvt->info.interleave_list = ibridge_interleave_list; 3403 pvt->info.interleave_pkg = ibridge_interleave_pkg; 3404 pvt->info.get_width = ibridge_get_width; 3405 3406 /* Store pci devices at mci for faster access */ 3407 rc = ibridge_mci_bind_devs(mci, sbridge_dev); 3408 if (unlikely(rc < 0)) 3409 goto fail0; 3410 get_source_id(mci); 3411 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge SrcID#%d_Ha#%d", 3412 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); 3413 break; 3414 case SANDY_BRIDGE: 3415 pvt->info.rankcfgr = SB_RANK_CFG_A; 3416 pvt->info.get_tolm = sbridge_get_tolm; 3417 pvt->info.get_tohm = sbridge_get_tohm; 3418 pvt->info.dram_rule = sbridge_dram_rule; 3419 pvt->info.get_memory_type = get_memory_type; 3420 pvt->info.get_node_id = get_node_id; 3421 pvt->info.get_ha = sbridge_get_ha; 3422 pvt->info.rir_limit = rir_limit; 3423 pvt->info.sad_limit = sad_limit; 3424 pvt->info.interleave_mode = interleave_mode; 3425 pvt->info.dram_attr = dram_attr; 3426 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule); 3427 pvt->info.interleave_list = sbridge_interleave_list; 3428 pvt->info.interleave_pkg = sbridge_interleave_pkg; 3429 pvt->info.get_width = sbridge_get_width; 3430 3431 /* Store pci devices at mci for faster access */ 3432 rc = sbridge_mci_bind_devs(mci, sbridge_dev); 3433 if (unlikely(rc < 0)) 3434 goto fail0; 3435 get_source_id(mci); 3436 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge SrcID#%d_Ha#%d", 3437 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); 3438 break; 3439 case HASWELL: 3440 /* rankcfgr isn't used */ 3441 pvt->info.get_tolm = haswell_get_tolm; 3442 pvt->info.get_tohm = haswell_get_tohm; 3443 pvt->info.dram_rule = ibridge_dram_rule; 3444 pvt->info.get_memory_type = haswell_get_memory_type; 3445 pvt->info.get_node_id = haswell_get_node_id; 3446 pvt->info.get_ha = ibridge_get_ha; 3447 pvt->info.rir_limit = haswell_rir_limit; 3448 pvt->info.sad_limit = sad_limit; 3449 pvt->info.interleave_mode = interleave_mode; 3450 pvt->info.dram_attr = dram_attr; 3451 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); 3452 pvt->info.interleave_list = ibridge_interleave_list; 3453 pvt->info.interleave_pkg = ibridge_interleave_pkg; 3454 pvt->info.get_width = ibridge_get_width; 3455 3456 /* Store pci devices at mci for faster access */ 3457 rc = haswell_mci_bind_devs(mci, sbridge_dev); 3458 if (unlikely(rc < 0)) 3459 goto fail0; 3460 get_source_id(mci); 3461 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell SrcID#%d_Ha#%d", 3462 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); 3463 break; 3464 case BROADWELL: 3465 /* rankcfgr isn't used */ 3466 pvt->info.get_tolm = haswell_get_tolm; 3467 pvt->info.get_tohm = haswell_get_tohm; 3468 pvt->info.dram_rule = ibridge_dram_rule; 3469 pvt->info.get_memory_type = haswell_get_memory_type; 3470 pvt->info.get_node_id = haswell_get_node_id; 3471 pvt->info.get_ha = ibridge_get_ha; 3472 pvt->info.rir_limit = haswell_rir_limit; 3473 pvt->info.sad_limit = sad_limit; 3474 pvt->info.interleave_mode = interleave_mode; 3475 pvt->info.dram_attr = dram_attr; 3476 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); 3477 pvt->info.interleave_list = ibridge_interleave_list; 3478 pvt->info.interleave_pkg = ibridge_interleave_pkg; 3479 pvt->info.get_width = broadwell_get_width; 3480 3481 /* Store pci devices at mci for faster access */ 3482 rc = broadwell_mci_bind_devs(mci, sbridge_dev); 3483 if (unlikely(rc < 0)) 3484 goto fail0; 3485 get_source_id(mci); 3486 mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell SrcID#%d_Ha#%d", 3487 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); 3488 break; 3489 case KNIGHTS_LANDING: 3490 /* pvt->info.rankcfgr == ??? */ 3491 pvt->info.get_tolm = knl_get_tolm; 3492 pvt->info.get_tohm = knl_get_tohm; 3493 pvt->info.dram_rule = knl_dram_rule; 3494 pvt->info.get_memory_type = knl_get_memory_type; 3495 pvt->info.get_node_id = knl_get_node_id; 3496 pvt->info.get_ha = knl_get_ha; 3497 pvt->info.rir_limit = NULL; 3498 pvt->info.sad_limit = knl_sad_limit; 3499 pvt->info.interleave_mode = knl_interleave_mode; 3500 pvt->info.dram_attr = dram_attr_knl; 3501 pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule); 3502 pvt->info.interleave_list = knl_interleave_list; 3503 pvt->info.interleave_pkg = ibridge_interleave_pkg; 3504 pvt->info.get_width = knl_get_width; 3505 3506 rc = knl_mci_bind_devs(mci, sbridge_dev); 3507 if (unlikely(rc < 0)) 3508 goto fail0; 3509 get_source_id(mci); 3510 mci->ctl_name = kasprintf(GFP_KERNEL, "Knights Landing SrcID#%d_Ha#%d", 3511 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); 3512 break; 3513 } 3514 3515 if (!mci->ctl_name) { 3516 rc = -ENOMEM; 3517 goto fail0; 3518 } 3519 3520 /* Get dimm basic config and the memory layout */ 3521 rc = get_dimm_config(mci); 3522 if (rc < 0) { 3523 edac_dbg(0, "MC: failed to get_dimm_config()\n"); 3524 goto fail; 3525 } 3526 get_memory_layout(mci); 3527 3528 /* record ptr to the generic device */ 3529 mci->pdev = &pdev->dev; 3530 3531 /* add this new MC control structure to EDAC's list of MCs */ 3532 if (unlikely(edac_mc_add_mc(mci))) { 3533 edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); 3534 rc = -EINVAL; 3535 goto fail; 3536 } 3537 3538 return 0; 3539 3540 fail: 3541 kfree(mci->ctl_name); 3542 fail0: 3543 edac_mc_free(mci); 3544 sbridge_dev->mci = NULL; 3545 return rc; 3546 } 3547 3548 static const struct x86_cpu_id sbridge_cpuids[] = { 3549 X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &pci_dev_descr_sbridge_table), 3550 X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &pci_dev_descr_ibridge_table), 3551 X86_MATCH_VFM(INTEL_HASWELL_X, &pci_dev_descr_haswell_table), 3552 X86_MATCH_VFM(INTEL_BROADWELL_X, &pci_dev_descr_broadwell_table), 3553 X86_MATCH_VFM(INTEL_BROADWELL_D, &pci_dev_descr_broadwell_table), 3554 X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &pci_dev_descr_knl_table), 3555 X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &pci_dev_descr_knl_table), 3556 { } 3557 }; 3558 MODULE_DEVICE_TABLE(x86cpu, sbridge_cpuids); 3559 3560 /* 3561 * sbridge_probe Get all devices and register memory controllers 3562 * present. 3563 * return: 3564 * 0 for FOUND a device 3565 * < 0 for error code 3566 */ 3567 3568 static int sbridge_probe(const struct x86_cpu_id *id) 3569 { 3570 int rc; 3571 u8 mc, num_mc = 0; 3572 struct sbridge_dev *sbridge_dev; 3573 struct pci_id_table *ptable = (struct pci_id_table *)id->driver_data; 3574 3575 /* get the pci devices we want to reserve for our use */ 3576 rc = sbridge_get_all_devices(&num_mc, ptable); 3577 3578 if (unlikely(rc < 0)) { 3579 edac_dbg(0, "couldn't get all devices\n"); 3580 goto fail0; 3581 } 3582 3583 mc = 0; 3584 3585 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { 3586 edac_dbg(0, "Registering MC#%d (%d of %d)\n", 3587 mc, mc + 1, num_mc); 3588 3589 sbridge_dev->mc = mc++; 3590 rc = sbridge_register_mci(sbridge_dev, ptable->type); 3591 if (unlikely(rc < 0)) 3592 goto fail1; 3593 } 3594 3595 sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION); 3596 3597 return 0; 3598 3599 fail1: 3600 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) 3601 sbridge_unregister_mci(sbridge_dev); 3602 3603 sbridge_put_all_devices(); 3604 fail0: 3605 return rc; 3606 } 3607 3608 /* 3609 * sbridge_remove cleanup 3610 * 3611 */ 3612 static void sbridge_remove(void) 3613 { 3614 struct sbridge_dev *sbridge_dev; 3615 3616 edac_dbg(0, "\n"); 3617 3618 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) 3619 sbridge_unregister_mci(sbridge_dev); 3620 3621 /* Release PCI resources */ 3622 sbridge_put_all_devices(); 3623 } 3624 3625 /* 3626 * sbridge_init Module entry function 3627 * Try to initialize this module for its devices 3628 */ 3629 static int __init sbridge_init(void) 3630 { 3631 const struct x86_cpu_id *id; 3632 const char *owner; 3633 int rc; 3634 3635 edac_dbg(2, "\n"); 3636 3637 if (ghes_get_devices()) 3638 return -EBUSY; 3639 3640 owner = edac_get_owner(); 3641 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR))) 3642 return -EBUSY; 3643 3644 if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) 3645 return -ENODEV; 3646 3647 id = x86_match_cpu(sbridge_cpuids); 3648 if (!id) 3649 return -ENODEV; 3650 3651 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 3652 opstate_init(); 3653 3654 rc = sbridge_probe(id); 3655 3656 if (rc >= 0) { 3657 mce_register_decode_chain(&sbridge_mce_dec); 3658 return 0; 3659 } 3660 3661 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n", 3662 rc); 3663 3664 return rc; 3665 } 3666 3667 /* 3668 * sbridge_exit() Module exit function 3669 * Unregister the driver 3670 */ 3671 static void __exit sbridge_exit(void) 3672 { 3673 edac_dbg(2, "\n"); 3674 sbridge_remove(); 3675 mce_unregister_decode_chain(&sbridge_mce_dec); 3676 } 3677 3678 module_init(sbridge_init); 3679 module_exit(sbridge_exit); 3680 3681 module_param(edac_op_state, int, 0444); 3682 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 3683 3684 MODULE_LICENSE("GPL"); 3685 MODULE_AUTHOR("Mauro Carvalho Chehab"); 3686 MODULE_AUTHOR("Red Hat Inc. (https://www.redhat.com)"); 3687 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - " 3688 SBRIDGE_REVISION); 3689