1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012 Russell King
4 * Rewritten from the dovefb driver, and Armada510 manuals.
5 */
6
7 #include <linux/bitfield.h>
8
9 #include <drm/armada_drm.h>
10 #include <drm/drm_atomic.h>
11 #include <drm/drm_atomic_helper.h>
12 #include <drm/drm_atomic_uapi.h>
13 #include <drm/drm_fourcc.h>
14 #include <drm/drm_plane_helper.h>
15 #include <drm/drm_print.h>
16
17 #include "armada_crtc.h"
18 #include "armada_drm.h"
19 #include "armada_fb.h"
20 #include "armada_gem.h"
21 #include "armada_hw.h"
22 #include "armada_ioctlP.h"
23 #include "armada_plane.h"
24 #include "armada_trace.h"
25
26 #define DEFAULT_BRIGHTNESS 0
27 #define DEFAULT_CONTRAST 0x4000
28 #define DEFAULT_SATURATION 0x4000
29 #define DEFAULT_ENCODING DRM_COLOR_YCBCR_BT601
30
31 struct armada_overlay_state {
32 struct armada_plane_state base;
33 u32 colorkey_yr;
34 u32 colorkey_ug;
35 u32 colorkey_vb;
36 u32 colorkey_mode;
37 u32 colorkey_enable;
38 s16 brightness;
39 u16 contrast;
40 u16 saturation;
41 };
42 #define drm_to_overlay_state(s) \
43 container_of(s, struct armada_overlay_state, base.base)
44
armada_spu_contrast(struct drm_plane_state * state)45 static inline u32 armada_spu_contrast(struct drm_plane_state *state)
46 {
47 return drm_to_overlay_state(state)->brightness << 16 |
48 drm_to_overlay_state(state)->contrast;
49 }
50
armada_spu_saturation(struct drm_plane_state * state)51 static inline u32 armada_spu_saturation(struct drm_plane_state *state)
52 {
53 /* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */
54 return drm_to_overlay_state(state)->saturation << 16;
55 }
56
armada_csc(struct drm_plane_state * state)57 static inline u32 armada_csc(struct drm_plane_state *state)
58 {
59 /*
60 * The CFG_CSC_RGB_* settings control the output of the colour space
61 * converter, setting the range of output values it produces. Since
62 * we will be blending with the full-range graphics, we need to
63 * produce full-range RGB output from the conversion.
64 */
65 return CFG_CSC_RGB_COMPUTER |
66 (state->color_encoding == DRM_COLOR_YCBCR_BT709 ?
67 CFG_CSC_YUV_CCIR709 : CFG_CSC_YUV_CCIR601);
68 }
69
70 /* === Plane support === */
armada_drm_overlay_plane_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)71 static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane,
72 struct drm_atomic_state *state)
73 {
74 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
75 plane);
76 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
77 plane);
78 struct armada_crtc *dcrtc;
79 struct armada_regs *regs;
80 unsigned int idx;
81 u32 cfg, cfg_mask, val;
82
83 DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
84
85 if (!new_state->fb || WARN_ON(!new_state->crtc))
86 return;
87
88 DRM_DEBUG_KMS("[PLANE:%d:%s] is on [CRTC:%d:%s] with [FB:%d] visible %u->%u\n",
89 plane->base.id, plane->name,
90 new_state->crtc->base.id, new_state->crtc->name,
91 new_state->fb->base.id,
92 old_state->visible, new_state->visible);
93
94 dcrtc = drm_to_armada_crtc(new_state->crtc);
95 regs = dcrtc->regs + dcrtc->regs_idx;
96
97 idx = 0;
98 if (!old_state->visible && new_state->visible)
99 armada_reg_queue_mod(regs, idx,
100 0, CFG_PDWN16x66 | CFG_PDWN32x66,
101 LCD_SPU_SRAM_PARA1);
102 val = armada_src_hw(new_state);
103 if (armada_src_hw(old_state) != val)
104 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN);
105 val = armada_dst_yx(new_state);
106 if (armada_dst_yx(old_state) != val)
107 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN);
108 val = armada_dst_hw(new_state);
109 if (armada_dst_hw(old_state) != val)
110 armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN);
111 /* FIXME: overlay on an interlaced display */
112 if (old_state->src.x1 != new_state->src.x1 ||
113 old_state->src.y1 != new_state->src.y1 ||
114 old_state->fb != new_state->fb ||
115 new_state->crtc->state->mode_changed) {
116 const struct drm_format_info *format;
117 u16 src_x;
118
119 armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 0),
120 LCD_SPU_DMA_START_ADDR_Y0);
121 armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 1),
122 LCD_SPU_DMA_START_ADDR_U0);
123 armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 2),
124 LCD_SPU_DMA_START_ADDR_V0);
125 armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 0),
126 LCD_SPU_DMA_START_ADDR_Y1);
127 armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 1),
128 LCD_SPU_DMA_START_ADDR_U1);
129 armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 2),
130 LCD_SPU_DMA_START_ADDR_V1);
131
132 val = armada_pitch(new_state, 0) << 16 | armada_pitch(new_state,
133 0);
134 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC);
135 val = armada_pitch(new_state, 1) << 16 | armada_pitch(new_state,
136 2);
137 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV);
138
139 cfg = CFG_DMA_FMT(drm_fb_to_armada_fb(new_state->fb)->fmt) |
140 CFG_DMA_MOD(drm_fb_to_armada_fb(new_state->fb)->mod) |
141 CFG_CBSH_ENA;
142 if (new_state->visible)
143 cfg |= CFG_DMA_ENA;
144
145 /*
146 * Shifting a YUV packed format image by one pixel causes the
147 * U/V planes to swap. Compensate for it by also toggling
148 * the UV swap.
149 */
150 format = new_state->fb->format;
151 src_x = new_state->src.x1 >> 16;
152 if (format->num_planes == 1 && src_x & (format->hsub - 1))
153 cfg ^= CFG_DMA_MOD(CFG_SWAPUV);
154 if (to_armada_plane_state(new_state)->interlace)
155 cfg |= CFG_DMA_FTOGGLE;
156 cfg_mask = CFG_CBSH_ENA | CFG_DMAFORMAT |
157 CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV |
158 CFG_SWAPYU | CFG_YUV2RGB) |
159 CFG_DMA_FTOGGLE | CFG_DMA_TSTMODE |
160 CFG_DMA_ENA;
161 } else if (old_state->visible != new_state->visible) {
162 cfg = new_state->visible ? CFG_DMA_ENA : 0;
163 cfg_mask = CFG_DMA_ENA;
164 } else {
165 cfg = cfg_mask = 0;
166 }
167 if (drm_rect_width(&old_state->src) != drm_rect_width(&new_state->src) ||
168 drm_rect_width(&old_state->dst) != drm_rect_width(&new_state->dst)) {
169 cfg_mask |= CFG_DMA_HSMOOTH;
170 if (drm_rect_width(&new_state->src) >> 16 !=
171 drm_rect_width(&new_state->dst))
172 cfg |= CFG_DMA_HSMOOTH;
173 }
174
175 if (cfg_mask)
176 armada_reg_queue_mod(regs, idx, cfg, cfg_mask,
177 LCD_SPU_DMA_CTRL0);
178
179 val = armada_spu_contrast(new_state);
180 if ((!old_state->visible && new_state->visible) ||
181 armada_spu_contrast(old_state) != val)
182 armada_reg_queue_set(regs, idx, val, LCD_SPU_CONTRAST);
183 val = armada_spu_saturation(new_state);
184 if ((!old_state->visible && new_state->visible) ||
185 armada_spu_saturation(old_state) != val)
186 armada_reg_queue_set(regs, idx, val, LCD_SPU_SATURATION);
187 if (!old_state->visible && new_state->visible)
188 armada_reg_queue_set(regs, idx, 0x00002000, LCD_SPU_CBSH_HUE);
189 val = armada_csc(new_state);
190 if ((!old_state->visible && new_state->visible) ||
191 armada_csc(old_state) != val)
192 armada_reg_queue_mod(regs, idx, val, CFG_CSC_MASK,
193 LCD_SPU_IOPAD_CONTROL);
194 val = drm_to_overlay_state(new_state)->colorkey_yr;
195 if ((!old_state->visible && new_state->visible) ||
196 drm_to_overlay_state(old_state)->colorkey_yr != val)
197 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_Y);
198 val = drm_to_overlay_state(new_state)->colorkey_ug;
199 if ((!old_state->visible && new_state->visible) ||
200 drm_to_overlay_state(old_state)->colorkey_ug != val)
201 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_U);
202 val = drm_to_overlay_state(new_state)->colorkey_vb;
203 if ((!old_state->visible && new_state->visible) ||
204 drm_to_overlay_state(old_state)->colorkey_vb != val)
205 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_V);
206 val = drm_to_overlay_state(new_state)->colorkey_mode;
207 if ((!old_state->visible && new_state->visible) ||
208 drm_to_overlay_state(old_state)->colorkey_mode != val)
209 armada_reg_queue_mod(regs, idx, val, CFG_CKMODE_MASK |
210 CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
211 LCD_SPU_DMA_CTRL1);
212 val = drm_to_overlay_state(new_state)->colorkey_enable;
213 if (((!old_state->visible && new_state->visible) ||
214 drm_to_overlay_state(old_state)->colorkey_enable != val) &&
215 dcrtc->variant->has_spu_adv_reg)
216 armada_reg_queue_mod(regs, idx, val, ADV_GRACOLORKEY |
217 ADV_VIDCOLORKEY, LCD_SPU_ADV_REG);
218
219 dcrtc->regs_idx += idx;
220 }
221
armada_drm_overlay_plane_atomic_disable(struct drm_plane * plane,struct drm_atomic_state * state)222 static void armada_drm_overlay_plane_atomic_disable(struct drm_plane *plane,
223 struct drm_atomic_state *state)
224 {
225 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
226 plane);
227 struct armada_crtc *dcrtc;
228 struct armada_regs *regs;
229 unsigned int idx = 0;
230
231 DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
232
233 if (!old_state->crtc)
234 return;
235
236 DRM_DEBUG_KMS("[PLANE:%d:%s] was on [CRTC:%d:%s] with [FB:%d]\n",
237 plane->base.id, plane->name,
238 old_state->crtc->base.id, old_state->crtc->name,
239 old_state->fb->base.id);
240
241 dcrtc = drm_to_armada_crtc(old_state->crtc);
242 regs = dcrtc->regs + dcrtc->regs_idx;
243
244 /* Disable plane and power down the YUV FIFOs */
245 armada_reg_queue_mod(regs, idx, 0, CFG_DMA_ENA, LCD_SPU_DMA_CTRL0);
246 armada_reg_queue_mod(regs, idx, CFG_PDWN16x66 | CFG_PDWN32x66, 0,
247 LCD_SPU_SRAM_PARA1);
248
249 dcrtc->regs_idx += idx;
250 }
251
252 static const struct drm_plane_helper_funcs armada_overlay_plane_helper_funcs = {
253 .atomic_check = armada_drm_plane_atomic_check,
254 .atomic_update = armada_drm_overlay_plane_atomic_update,
255 .atomic_disable = armada_drm_overlay_plane_atomic_disable,
256 };
257
258 static int
armada_overlay_plane_update(struct drm_plane * plane,struct drm_crtc * crtc,struct drm_framebuffer * fb,int crtc_x,int crtc_y,unsigned crtc_w,unsigned crtc_h,uint32_t src_x,uint32_t src_y,uint32_t src_w,uint32_t src_h,struct drm_modeset_acquire_ctx * ctx)259 armada_overlay_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
260 struct drm_framebuffer *fb,
261 int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h,
262 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h,
263 struct drm_modeset_acquire_ctx *ctx)
264 {
265 struct drm_atomic_state *state;
266 struct drm_plane_state *plane_state;
267 int ret = 0;
268
269 trace_armada_ovl_plane_update(plane, crtc, fb,
270 crtc_x, crtc_y, crtc_w, crtc_h,
271 src_x, src_y, src_w, src_h);
272
273 state = drm_atomic_state_alloc(plane->dev);
274 if (!state)
275 return -ENOMEM;
276
277 state->acquire_ctx = ctx;
278 plane_state = drm_atomic_get_plane_state(state, plane);
279 if (IS_ERR(plane_state)) {
280 ret = PTR_ERR(plane_state);
281 goto fail;
282 }
283
284 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
285 if (ret != 0)
286 goto fail;
287
288 drm_atomic_set_fb_for_plane(plane_state, fb);
289 plane_state->crtc_x = crtc_x;
290 plane_state->crtc_y = crtc_y;
291 plane_state->crtc_h = crtc_h;
292 plane_state->crtc_w = crtc_w;
293 plane_state->src_x = src_x;
294 plane_state->src_y = src_y;
295 plane_state->src_h = src_h;
296 plane_state->src_w = src_w;
297
298 ret = drm_atomic_nonblocking_commit(state);
299 fail:
300 drm_atomic_state_put(state);
301 return ret;
302 }
303
armada_overlay_reset(struct drm_plane * plane)304 static void armada_overlay_reset(struct drm_plane *plane)
305 {
306 struct armada_overlay_state *state;
307
308 if (plane->state)
309 __drm_atomic_helper_plane_destroy_state(plane->state);
310 kfree(plane->state);
311 plane->state = NULL;
312
313 state = kzalloc_obj(*state);
314 if (state) {
315 state->colorkey_yr = 0xfefefe00;
316 state->colorkey_ug = 0x01010100;
317 state->colorkey_vb = 0x01010100;
318 state->colorkey_mode = CFG_CKMODE(CKMODE_RGB) |
319 CFG_ALPHAM_GRA | CFG_ALPHA(0);
320 state->colorkey_enable = ADV_GRACOLORKEY;
321 state->brightness = DEFAULT_BRIGHTNESS;
322 state->contrast = DEFAULT_CONTRAST;
323 state->saturation = DEFAULT_SATURATION;
324 __drm_atomic_helper_plane_reset(plane, &state->base.base);
325 state->base.base.color_encoding = DEFAULT_ENCODING;
326 state->base.base.color_range = DRM_COLOR_YCBCR_LIMITED_RANGE;
327 }
328 }
329
330 static struct drm_plane_state *
armada_overlay_duplicate_state(struct drm_plane * plane)331 armada_overlay_duplicate_state(struct drm_plane *plane)
332 {
333 struct armada_overlay_state *state;
334
335 if (WARN_ON(!plane->state))
336 return NULL;
337
338 state = kmemdup(plane->state, sizeof(*state), GFP_KERNEL);
339 if (state)
340 __drm_atomic_helper_plane_duplicate_state(plane,
341 &state->base.base);
342 return &state->base.base;
343 }
344
armada_overlay_set_property(struct drm_plane * plane,struct drm_plane_state * state,struct drm_property * property,uint64_t val)345 static int armada_overlay_set_property(struct drm_plane *plane,
346 struct drm_plane_state *state, struct drm_property *property,
347 uint64_t val)
348 {
349 struct armada_private *priv = drm_to_armada_dev(plane->dev);
350
351 #define K2R(val) (((val) >> 0) & 0xff)
352 #define K2G(val) (((val) >> 8) & 0xff)
353 #define K2B(val) (((val) >> 16) & 0xff)
354 if (property == priv->colorkey_prop) {
355 #define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8)
356 drm_to_overlay_state(state)->colorkey_yr = CCC(K2R(val));
357 drm_to_overlay_state(state)->colorkey_ug = CCC(K2G(val));
358 drm_to_overlay_state(state)->colorkey_vb = CCC(K2B(val));
359 #undef CCC
360 } else if (property == priv->colorkey_min_prop) {
361 drm_to_overlay_state(state)->colorkey_yr &= ~0x00ff0000;
362 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 16;
363 drm_to_overlay_state(state)->colorkey_ug &= ~0x00ff0000;
364 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 16;
365 drm_to_overlay_state(state)->colorkey_vb &= ~0x00ff0000;
366 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 16;
367 } else if (property == priv->colorkey_max_prop) {
368 drm_to_overlay_state(state)->colorkey_yr &= ~0xff000000;
369 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 24;
370 drm_to_overlay_state(state)->colorkey_ug &= ~0xff000000;
371 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 24;
372 drm_to_overlay_state(state)->colorkey_vb &= ~0xff000000;
373 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 24;
374 } else if (property == priv->colorkey_val_prop) {
375 drm_to_overlay_state(state)->colorkey_yr &= ~0x0000ff00;
376 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 8;
377 drm_to_overlay_state(state)->colorkey_ug &= ~0x0000ff00;
378 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 8;
379 drm_to_overlay_state(state)->colorkey_vb &= ~0x0000ff00;
380 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 8;
381 } else if (property == priv->colorkey_alpha_prop) {
382 drm_to_overlay_state(state)->colorkey_yr &= ~0x000000ff;
383 drm_to_overlay_state(state)->colorkey_yr |= K2R(val);
384 drm_to_overlay_state(state)->colorkey_ug &= ~0x000000ff;
385 drm_to_overlay_state(state)->colorkey_ug |= K2G(val);
386 drm_to_overlay_state(state)->colorkey_vb &= ~0x000000ff;
387 drm_to_overlay_state(state)->colorkey_vb |= K2B(val);
388 } else if (property == priv->colorkey_mode_prop) {
389 if (val == CKMODE_DISABLE) {
390 drm_to_overlay_state(state)->colorkey_mode =
391 CFG_CKMODE(CKMODE_DISABLE) |
392 CFG_ALPHAM_CFG | CFG_ALPHA(255);
393 drm_to_overlay_state(state)->colorkey_enable = 0;
394 } else {
395 drm_to_overlay_state(state)->colorkey_mode =
396 CFG_CKMODE(val) |
397 CFG_ALPHAM_GRA | CFG_ALPHA(0);
398 drm_to_overlay_state(state)->colorkey_enable =
399 ADV_GRACOLORKEY;
400 }
401 } else if (property == priv->brightness_prop) {
402 drm_to_overlay_state(state)->brightness = val - 256;
403 } else if (property == priv->contrast_prop) {
404 drm_to_overlay_state(state)->contrast = val;
405 } else if (property == priv->saturation_prop) {
406 drm_to_overlay_state(state)->saturation = val;
407 } else {
408 return -EINVAL;
409 }
410 return 0;
411 }
412
armada_overlay_get_property(struct drm_plane * plane,const struct drm_plane_state * state,struct drm_property * property,uint64_t * val)413 static int armada_overlay_get_property(struct drm_plane *plane,
414 const struct drm_plane_state *state, struct drm_property *property,
415 uint64_t *val)
416 {
417 struct armada_private *priv = drm_to_armada_dev(plane->dev);
418
419 #define C2K(c,s) (((c) >> (s)) & 0xff)
420 #define R2BGR(r,g,b,s) (C2K(r,s) << 0 | C2K(g,s) << 8 | C2K(b,s) << 16)
421 if (property == priv->colorkey_prop) {
422 /* Do best-efforts here for this property */
423 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
424 drm_to_overlay_state(state)->colorkey_ug,
425 drm_to_overlay_state(state)->colorkey_vb, 16);
426 /* If min != max, or min != val, error out */
427 if (*val != R2BGR(drm_to_overlay_state(state)->colorkey_yr,
428 drm_to_overlay_state(state)->colorkey_ug,
429 drm_to_overlay_state(state)->colorkey_vb, 24) ||
430 *val != R2BGR(drm_to_overlay_state(state)->colorkey_yr,
431 drm_to_overlay_state(state)->colorkey_ug,
432 drm_to_overlay_state(state)->colorkey_vb, 8))
433 return -EINVAL;
434 } else if (property == priv->colorkey_min_prop) {
435 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
436 drm_to_overlay_state(state)->colorkey_ug,
437 drm_to_overlay_state(state)->colorkey_vb, 16);
438 } else if (property == priv->colorkey_max_prop) {
439 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
440 drm_to_overlay_state(state)->colorkey_ug,
441 drm_to_overlay_state(state)->colorkey_vb, 24);
442 } else if (property == priv->colorkey_val_prop) {
443 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
444 drm_to_overlay_state(state)->colorkey_ug,
445 drm_to_overlay_state(state)->colorkey_vb, 8);
446 } else if (property == priv->colorkey_alpha_prop) {
447 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
448 drm_to_overlay_state(state)->colorkey_ug,
449 drm_to_overlay_state(state)->colorkey_vb, 0);
450 } else if (property == priv->colorkey_mode_prop) {
451 *val = FIELD_GET(CFG_CKMODE_MASK,
452 drm_to_overlay_state(state)->colorkey_mode);
453 } else if (property == priv->brightness_prop) {
454 *val = drm_to_overlay_state(state)->brightness + 256;
455 } else if (property == priv->contrast_prop) {
456 *val = drm_to_overlay_state(state)->contrast;
457 } else if (property == priv->saturation_prop) {
458 *val = drm_to_overlay_state(state)->saturation;
459 } else {
460 return -EINVAL;
461 }
462 return 0;
463 }
464
465 static const struct drm_plane_funcs armada_ovl_plane_funcs = {
466 .update_plane = armada_overlay_plane_update,
467 .disable_plane = drm_atomic_helper_disable_plane,
468 .destroy = drm_plane_helper_destroy,
469 .reset = armada_overlay_reset,
470 .atomic_duplicate_state = armada_overlay_duplicate_state,
471 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
472 .atomic_set_property = armada_overlay_set_property,
473 .atomic_get_property = armada_overlay_get_property,
474 };
475
476 static const uint32_t armada_ovl_formats[] = {
477 DRM_FORMAT_UYVY,
478 DRM_FORMAT_YUYV,
479 DRM_FORMAT_YUV420,
480 DRM_FORMAT_YVU420,
481 DRM_FORMAT_YUV422,
482 DRM_FORMAT_YVU422,
483 DRM_FORMAT_VYUY,
484 DRM_FORMAT_YVYU,
485 DRM_FORMAT_ARGB8888,
486 DRM_FORMAT_ABGR8888,
487 DRM_FORMAT_XRGB8888,
488 DRM_FORMAT_XBGR8888,
489 DRM_FORMAT_RGB888,
490 DRM_FORMAT_BGR888,
491 DRM_FORMAT_ARGB1555,
492 DRM_FORMAT_ABGR1555,
493 DRM_FORMAT_RGB565,
494 DRM_FORMAT_BGR565,
495 };
496
497 static const struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = {
498 { CKMODE_DISABLE, "disabled" },
499 { CKMODE_Y, "Y component" },
500 { CKMODE_U, "U component" },
501 { CKMODE_V, "V component" },
502 { CKMODE_RGB, "RGB" },
503 { CKMODE_R, "R component" },
504 { CKMODE_G, "G component" },
505 { CKMODE_B, "B component" },
506 };
507
armada_overlay_create_properties(struct drm_device * dev)508 static int armada_overlay_create_properties(struct drm_device *dev)
509 {
510 struct armada_private *priv = drm_to_armada_dev(dev);
511
512 if (priv->colorkey_prop)
513 return 0;
514
515 priv->colorkey_prop = drm_property_create_range(dev, 0,
516 "colorkey", 0, 0xffffff);
517 priv->colorkey_min_prop = drm_property_create_range(dev, 0,
518 "colorkey_min", 0, 0xffffff);
519 priv->colorkey_max_prop = drm_property_create_range(dev, 0,
520 "colorkey_max", 0, 0xffffff);
521 priv->colorkey_val_prop = drm_property_create_range(dev, 0,
522 "colorkey_val", 0, 0xffffff);
523 priv->colorkey_alpha_prop = drm_property_create_range(dev, 0,
524 "colorkey_alpha", 0, 0xffffff);
525 priv->colorkey_mode_prop = drm_property_create_enum(dev, 0,
526 "colorkey_mode",
527 armada_drm_colorkey_enum_list,
528 ARRAY_SIZE(armada_drm_colorkey_enum_list));
529 priv->brightness_prop = drm_property_create_range(dev, 0,
530 "brightness", 0, 256 + 255);
531 priv->contrast_prop = drm_property_create_range(dev, 0,
532 "contrast", 0, 0x7fff);
533 priv->saturation_prop = drm_property_create_range(dev, 0,
534 "saturation", 0, 0x7fff);
535
536 if (!priv->colorkey_prop)
537 return -ENOMEM;
538
539 return 0;
540 }
541
armada_overlay_plane_create(struct drm_device * dev,unsigned long crtcs)542 int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs)
543 {
544 struct armada_private *priv = drm_to_armada_dev(dev);
545 struct drm_mode_object *mobj;
546 struct drm_plane *overlay;
547 int ret;
548
549 ret = armada_overlay_create_properties(dev);
550 if (ret)
551 return ret;
552
553 overlay = kzalloc_obj(*overlay);
554 if (!overlay)
555 return -ENOMEM;
556
557 drm_plane_helper_add(overlay, &armada_overlay_plane_helper_funcs);
558
559 ret = drm_universal_plane_init(dev, overlay, crtcs,
560 &armada_ovl_plane_funcs,
561 armada_ovl_formats,
562 ARRAY_SIZE(armada_ovl_formats),
563 NULL,
564 DRM_PLANE_TYPE_OVERLAY, NULL);
565 if (ret) {
566 kfree(overlay);
567 return ret;
568 }
569
570 mobj = &overlay->base;
571 drm_object_attach_property(mobj, priv->colorkey_prop,
572 0x0101fe);
573 drm_object_attach_property(mobj, priv->colorkey_min_prop,
574 0x0101fe);
575 drm_object_attach_property(mobj, priv->colorkey_max_prop,
576 0x0101fe);
577 drm_object_attach_property(mobj, priv->colorkey_val_prop,
578 0x0101fe);
579 drm_object_attach_property(mobj, priv->colorkey_alpha_prop,
580 0x000000);
581 drm_object_attach_property(mobj, priv->colorkey_mode_prop,
582 CKMODE_RGB);
583 drm_object_attach_property(mobj, priv->brightness_prop,
584 256 + DEFAULT_BRIGHTNESS);
585 drm_object_attach_property(mobj, priv->contrast_prop,
586 DEFAULT_CONTRAST);
587 drm_object_attach_property(mobj, priv->saturation_prop,
588 DEFAULT_SATURATION);
589
590 ret = drm_plane_create_color_properties(overlay,
591 BIT(DRM_COLOR_YCBCR_BT601) |
592 BIT(DRM_COLOR_YCBCR_BT709),
593 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE),
594 DEFAULT_ENCODING,
595 DRM_COLOR_YCBCR_LIMITED_RANGE);
596
597 return ret;
598 }
599