1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 29 #include "oss/osssys_7_0_0_offset.h" 30 #include "oss/osssys_7_0_0_sh_mask.h" 31 32 #include "soc15_common.h" 33 #include "ih_v7_0.h" 34 35 #define MAX_REARM_RETRY 10 36 37 static void ih_v7_0_set_interrupt_funcs(struct amdgpu_device *adev); 38 39 /** 40 * ih_v7_0_init_register_offset - Initialize register offset for ih rings 41 * 42 * @adev: amdgpu_device pointer 43 * 44 * Initialize register offset ih rings (IH_V7_0). 45 */ 46 static void ih_v7_0_init_register_offset(struct amdgpu_device *adev) 47 { 48 struct amdgpu_ih_regs *ih_regs; 49 50 /* ih ring 2 is removed 51 * ih ring and ih ring 1 are available */ 52 if (adev->irq.ih.ring_size) { 53 ih_regs = &adev->irq.ih.ih_regs; 54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE); 55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI); 56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL); 57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR); 58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR); 59 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR); 60 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_LO); 61 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_HI); 62 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 63 } 64 65 if (adev->irq.ih1.ring_size) { 66 ih_regs = &adev->irq.ih1.ih_regs; 67 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_RING1); 68 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI_RING1); 69 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL_RING1); 70 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_RING1); 71 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR_RING1); 72 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR_RING1); 73 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 74 } 75 } 76 77 /** 78 * force_update_wptr_for_self_int - Force update the wptr for self interrupt 79 * 80 * @adev: amdgpu_device pointer 81 * @threshold: threshold to trigger the wptr reporting 82 * @timeout: timeout to trigger the wptr reporting 83 * @enabled: Enable/disable timeout flush mechanism 84 * 85 * threshold input range: 0 ~ 15, default 0, 86 * real_threshold = 2^threshold 87 * timeout input range: 0 ~ 20, default 8, 88 * real_timeout = (2^timeout) * 1024 / (socclk_freq) 89 * 90 * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 91 */ 92 static void 93 force_update_wptr_for_self_int(struct amdgpu_device *adev, 94 u32 threshold, u32 timeout, bool enabled) 95 { 96 u32 ih_cntl, ih_rb_cntl; 97 98 ih_cntl = RREG32_SOC15(OSSSYS, 0, regIH_CNTL2); 99 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1); 100 101 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 102 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 103 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 104 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 105 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 106 RB_USED_INT_THRESHOLD, threshold); 107 108 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { 109 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl)) 110 return; 111 } else { 112 WREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1, ih_rb_cntl); 113 } 114 115 WREG32_SOC15(OSSSYS, 0, regIH_CNTL2, ih_cntl); 116 } 117 118 /** 119 * ih_v7_0_toggle_ring_interrupts - toggle the interrupt ring buffer 120 * 121 * @adev: amdgpu_device pointer 122 * @ih: amdgpu_ih_ring pointet 123 * @enable: true - enable the interrupts, false - disable the interrupts 124 * 125 * Toggle the interrupt ring buffer (IH_V7_0) 126 */ 127 static int ih_v7_0_toggle_ring_interrupts(struct amdgpu_device *adev, 128 struct amdgpu_ih_ring *ih, 129 bool enable) 130 { 131 struct amdgpu_ih_regs *ih_regs; 132 uint32_t tmp; 133 134 ih_regs = &ih->ih_regs; 135 136 tmp = RREG32(ih_regs->ih_rb_cntl); 137 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 138 /* enable_intr field is only valid in ring0 */ 139 if (ih == &adev->irq.ih) 140 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 141 142 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { 143 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) 144 return -ETIMEDOUT; 145 } else { 146 WREG32(ih_regs->ih_rb_cntl, tmp); 147 } 148 149 if (enable) { 150 ih->enabled = true; 151 } else { 152 /* set rptr, wptr to 0 */ 153 WREG32(ih_regs->ih_rb_rptr, 0); 154 WREG32(ih_regs->ih_rb_wptr, 0); 155 ih->enabled = false; 156 ih->rptr = 0; 157 } 158 159 return 0; 160 } 161 162 /** 163 * ih_v7_0_toggle_interrupts - Toggle all the available interrupt ring buffers 164 * 165 * @adev: amdgpu_device pointer 166 * @enable: enable or disable interrupt ring buffers 167 * 168 * Toggle all the available interrupt ring buffers (IH_V7_0). 169 */ 170 static int ih_v7_0_toggle_interrupts(struct amdgpu_device *adev, bool enable) 171 { 172 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; 173 int i; 174 int r; 175 176 for (i = 0; i < ARRAY_SIZE(ih); i++) { 177 if (ih[i]->ring_size) { 178 r = ih_v7_0_toggle_ring_interrupts(adev, ih[i], enable); 179 if (r) 180 return r; 181 } 182 } 183 184 return 0; 185 } 186 187 static uint32_t ih_v7_0_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 188 { 189 int rb_bufsz = order_base_2(ih->ring_size / 4); 190 191 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 192 MC_SPACE, ih->use_bus_addr ? 2 : 4); 193 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 194 WPTR_OVERFLOW_CLEAR, 1); 195 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 196 WPTR_OVERFLOW_ENABLE, 1); 197 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 198 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 199 * value is written to memory 200 */ 201 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 202 WPTR_WRITEBACK_ENABLE, 1); 203 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 204 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 205 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 206 207 return ih_rb_cntl; 208 } 209 210 static uint32_t ih_v7_0_doorbell_rptr(struct amdgpu_ih_ring *ih) 211 { 212 u32 ih_doorbell_rtpr = 0; 213 214 if (ih->use_doorbell) { 215 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 216 IH_DOORBELL_RPTR, OFFSET, 217 ih->doorbell_index); 218 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 219 IH_DOORBELL_RPTR, 220 ENABLE, 1); 221 } else { 222 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 223 IH_DOORBELL_RPTR, 224 ENABLE, 0); 225 } 226 return ih_doorbell_rtpr; 227 } 228 229 /** 230 * ih_v7_0_enable_ring - enable an ih ring buffer 231 * 232 * @adev: amdgpu_device pointer 233 * @ih: amdgpu_ih_ring pointer 234 * 235 * Enable an ih ring buffer (IH_V7_0) 236 */ 237 static int ih_v7_0_enable_ring(struct amdgpu_device *adev, 238 struct amdgpu_ih_ring *ih) 239 { 240 struct amdgpu_ih_regs *ih_regs; 241 uint32_t tmp; 242 243 ih_regs = &ih->ih_regs; 244 245 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 246 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 247 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 248 249 tmp = RREG32(ih_regs->ih_rb_cntl); 250 tmp = ih_v7_0_rb_cntl(ih, tmp); 251 if (ih == &adev->irq.ih) 252 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 253 if (ih == &adev->irq.ih1) { 254 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 255 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 256 } 257 258 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { 259 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 260 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 261 return -ETIMEDOUT; 262 } 263 } else { 264 WREG32(ih_regs->ih_rb_cntl, tmp); 265 } 266 267 if (ih == &adev->irq.ih) { 268 /* set the ih ring 0 writeback address whether it's enabled or not */ 269 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 270 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 271 } 272 273 /* set rptr, wptr to 0 */ 274 WREG32(ih_regs->ih_rb_wptr, 0); 275 WREG32(ih_regs->ih_rb_rptr, 0); 276 277 WREG32(ih_regs->ih_doorbell_rptr, ih_v7_0_doorbell_rptr(ih)); 278 279 return 0; 280 } 281 282 static uint32_t ih_v7_0_setup_retry_doorbell(u32 doorbell_index) 283 { 284 u32 val = 0; 285 286 val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, OFFSET, doorbell_index); 287 val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1); 288 289 return val; 290 } 291 292 /** 293 * ih_v7_0_irq_init - init and enable the interrupt ring 294 * 295 * @adev: amdgpu_device pointer 296 * 297 * Allocate a ring buffer for the interrupt controller, 298 * enable the RLC, disable interrupts, enable the IH 299 * ring buffer and enable it. 300 * Called at device load and reume. 301 * Returns 0 for success, errors for failure. 302 */ 303 static int ih_v7_0_irq_init(struct amdgpu_device *adev) 304 { 305 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; 306 u32 ih_chicken; 307 u32 tmp; 308 int ret; 309 int i; 310 311 /* disable irqs */ 312 ret = ih_v7_0_toggle_interrupts(adev, false); 313 if (ret) 314 return ret; 315 316 adev->nbio.funcs->ih_control(adev); 317 318 if (unlikely((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 319 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO))) { 320 if (ih[0]->use_bus_addr) { 321 ih_chicken = RREG32_SOC15(OSSSYS, 0, regIH_CHICKEN); 322 ih_chicken = REG_SET_FIELD(ih_chicken, 323 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 324 WREG32_SOC15(OSSSYS, 0, regIH_CHICKEN, ih_chicken); 325 } 326 } 327 328 for (i = 0; i < ARRAY_SIZE(ih); i++) { 329 if (ih[i]->ring_size) { 330 ret = ih_v7_0_enable_ring(adev, ih[i]); 331 if (ret) 332 return ret; 333 } 334 } 335 336 /* update doorbell range for ih ring 0 */ 337 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, 338 ih[0]->doorbell_index); 339 340 tmp = RREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL); 341 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 342 CLIENT18_IS_STORM_CLIENT, 1); 343 WREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL, tmp); 344 345 tmp = RREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL); 346 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 347 WREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL, tmp); 348 349 /* GC/MMHUB UTCL2 page fault interrupts are configured as 350 * MSI storm capable interrupts by deafult. The delay is 351 * used to avoid ISR being called too frequently 352 * when page fault happens on several continuous page 353 * and thus avoid MSI storm */ 354 tmp = RREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL); 355 tmp = REG_SET_FIELD(tmp, IH_MSI_STORM_CTRL, 356 DELAY, 3); 357 WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp); 358 359 /* Redirect the interrupts to IH RB1 for dGPU */ 360 if (adev->irq.ih1.ring_size) { 361 tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX); 362 tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0); 363 WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp); 364 365 tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA); 366 tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa); 367 tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0); 368 tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, 369 SOURCE_ID_MATCH_ENABLE, 0x1); 370 371 WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp); 372 } 373 374 pci_set_master(adev->pdev); 375 376 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(7, 1, 0)) { 377 /* Allocate the doorbell for IH Retry CAM */ 378 adev->irq.retry_cam_doorbell_index = (adev->doorbell_index.ih + 2) << 1; 379 WREG32_SOC15(OSSSYS, 0, regIH_DOORBELL_RETRY_CAM, 380 ih_v7_0_setup_retry_doorbell(adev->irq.retry_cam_doorbell_index)); 381 382 /* Enable IH Retry CAM */ 383 tmp = RREG32_SOC15(OSSSYS, 0, regIH_RETRY_INT_CAM_CNTL); 384 tmp = REG_SET_FIELD(tmp, IH_RETRY_INT_CAM_CNTL, ENABLE, 1); 385 tmp = REG_SET_FIELD(tmp, IH_RETRY_INT_CAM_CNTL, CAM_SIZE, 0xF); 386 WREG32_SOC15(OSSSYS, 0, regIH_RETRY_INT_CAM_CNTL, tmp); 387 388 adev->irq.retry_cam_enabled = true; 389 } 390 391 /* enable interrupts */ 392 ret = ih_v7_0_toggle_interrupts(adev, true); 393 if (ret) 394 return ret; 395 /* enable wptr force update for self int */ 396 force_update_wptr_for_self_int(adev, 0, 8, true); 397 398 if (adev->irq.ih_soft.ring_size) 399 adev->irq.ih_soft.enabled = true; 400 401 return 0; 402 } 403 404 /** 405 * ih_v7_0_irq_disable - disable interrupts 406 * 407 * @adev: amdgpu_device pointer 408 * 409 * Disable interrupts on the hw. 410 */ 411 static void ih_v7_0_irq_disable(struct amdgpu_device *adev) 412 { 413 force_update_wptr_for_self_int(adev, 0, 8, false); 414 ih_v7_0_toggle_interrupts(adev, false); 415 416 /* Wait and acknowledge irq */ 417 mdelay(1); 418 } 419 420 /** 421 * ih_v7_0_get_wptr() - get the IH ring buffer wptr 422 * 423 * @adev: amdgpu_device pointer 424 * @ih: IH ring buffer to fetch wptr 425 * 426 * Get the IH ring buffer wptr from either the register 427 * or the writeback memory buffer. Also check for 428 * ring buffer overflow and deal with it. 429 * Returns the value of the wptr. 430 */ 431 static u32 ih_v7_0_get_wptr(struct amdgpu_device *adev, 432 struct amdgpu_ih_ring *ih) 433 { 434 u32 wptr, tmp; 435 struct amdgpu_ih_regs *ih_regs; 436 437 wptr = le32_to_cpu(*ih->wptr_cpu); 438 ih_regs = &ih->ih_regs; 439 440 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 441 goto out; 442 443 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 444 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 445 goto out; 446 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 447 448 /* When a ring buffer overflow happen start parsing interrupt 449 * from the last not overwritten vector (wptr + 32). Hopefully 450 * this should allow us to catch up. 451 */ 452 tmp = (wptr + 32) & ih->ptr_mask; 453 dev_warn(adev->dev, "IH ring buffer overflow " 454 "(0x%08X, 0x%08X, 0x%08X)\n", 455 wptr, ih->rptr, tmp); 456 ih->rptr = tmp; 457 458 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 459 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 460 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 461 462 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows 463 * can be detected. 464 */ 465 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); 466 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 467 out: 468 return (wptr & ih->ptr_mask); 469 } 470 471 /** 472 * ih_v7_0_irq_rearm - rearm IRQ if lost 473 * 474 * @adev: amdgpu_device pointer 475 * @ih: IH ring to match 476 * 477 */ 478 static void ih_v7_0_irq_rearm(struct amdgpu_device *adev, 479 struct amdgpu_ih_ring *ih) 480 { 481 uint32_t v = 0; 482 uint32_t i = 0; 483 struct amdgpu_ih_regs *ih_regs; 484 485 ih_regs = &ih->ih_regs; 486 487 /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 488 for (i = 0; i < MAX_REARM_RETRY; i++) { 489 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 490 if ((v < ih->ring_size) && (v != ih->rptr)) 491 WDOORBELL32(ih->doorbell_index, ih->rptr); 492 else 493 break; 494 } 495 } 496 497 /** 498 * ih_v7_0_set_rptr - set the IH ring buffer rptr 499 * 500 * @adev: amdgpu_device pointer 501 * @ih: IH ring buffer to set rptr 502 */ 503 static void ih_v7_0_set_rptr(struct amdgpu_device *adev, 504 struct amdgpu_ih_ring *ih) 505 { 506 struct amdgpu_ih_regs *ih_regs; 507 508 if (ih->use_doorbell) { 509 /* XXX check if swapping is necessary on BE */ 510 *ih->rptr_cpu = ih->rptr; 511 WDOORBELL32(ih->doorbell_index, ih->rptr); 512 513 if (amdgpu_sriov_vf(adev)) 514 ih_v7_0_irq_rearm(adev, ih); 515 } else { 516 ih_regs = &ih->ih_regs; 517 WREG32(ih_regs->ih_rb_rptr, ih->rptr); 518 } 519 } 520 521 /** 522 * ih_v7_0_self_irq - dispatch work for ring 1 523 * 524 * @adev: amdgpu_device pointer 525 * @source: irq source 526 * @entry: IV with WPTR update 527 * 528 * Update the WPTR from the IV and schedule work to handle the entries. 529 */ 530 static int ih_v7_0_self_irq(struct amdgpu_device *adev, 531 struct amdgpu_irq_src *source, 532 struct amdgpu_iv_entry *entry) 533 { 534 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 535 536 switch (entry->ring_id) { 537 case 1: 538 *adev->irq.ih1.wptr_cpu = wptr; 539 schedule_work(&adev->irq.ih1_work); 540 break; 541 default: break; 542 } 543 return 0; 544 } 545 546 static const struct amdgpu_irq_src_funcs ih_v7_0_self_irq_funcs = { 547 .process = ih_v7_0_self_irq, 548 }; 549 550 static void ih_v7_0_set_self_irq_funcs(struct amdgpu_device *adev) 551 { 552 adev->irq.self_irq.num_types = 0; 553 adev->irq.self_irq.funcs = &ih_v7_0_self_irq_funcs; 554 } 555 556 static int ih_v7_0_early_init(struct amdgpu_ip_block *ip_block) 557 { 558 struct amdgpu_device *adev = ip_block->adev; 559 560 ih_v7_0_set_interrupt_funcs(adev); 561 ih_v7_0_set_self_irq_funcs(adev); 562 return 0; 563 } 564 565 static int ih_v7_0_sw_init(struct amdgpu_ip_block *ip_block) 566 { 567 int r; 568 struct amdgpu_device *adev = ip_block->adev; 569 bool use_bus_addr; 570 unsigned int sw_ring_size; 571 572 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_IH, 0, 573 &adev->irq.self_irq); 574 575 if (r) 576 return r; 577 578 /* use gpu virtual address for ih ring 579 * until ih_checken is programmed to allow 580 * use bus address for ih ring by psp bl */ 581 use_bus_addr = adev->firmware.load_type != AMDGPU_FW_LOAD_PSP; 582 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 583 if (r) 584 return r; 585 586 adev->irq.ih.use_doorbell = true; 587 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 588 589 if (!(adev->flags & AMD_IS_APU)) { 590 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE, 591 use_bus_addr); 592 if (r) 593 return r; 594 595 adev->irq.ih1.use_doorbell = true; 596 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 597 } 598 599 /* initialize ih control register offset */ 600 ih_v7_0_init_register_offset(adev); 601 602 sw_ring_size = (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(7, 1, 0)) ? 603 IH_SW_RING_SIZE : PAGE_SIZE; 604 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, sw_ring_size, true); 605 if (r) 606 return r; 607 608 r = amdgpu_irq_init(adev); 609 610 return r; 611 } 612 613 static int ih_v7_0_sw_fini(struct amdgpu_ip_block *ip_block) 614 { 615 struct amdgpu_device *adev = ip_block->adev; 616 617 amdgpu_irq_fini_sw(adev); 618 619 return 0; 620 } 621 622 static int ih_v7_0_hw_init(struct amdgpu_ip_block *ip_block) 623 { 624 int r; 625 struct amdgpu_device *adev = ip_block->adev; 626 627 r = ih_v7_0_irq_init(adev); 628 if (r) 629 return r; 630 631 return 0; 632 } 633 634 static int ih_v7_0_hw_fini(struct amdgpu_ip_block *ip_block) 635 { 636 ih_v7_0_irq_disable(ip_block->adev); 637 638 return 0; 639 } 640 641 static int ih_v7_0_suspend(struct amdgpu_ip_block *ip_block) 642 { 643 return ih_v7_0_hw_fini(ip_block); 644 } 645 646 static int ih_v7_0_resume(struct amdgpu_ip_block *ip_block) 647 { 648 return ih_v7_0_hw_init(ip_block); 649 } 650 651 static bool ih_v7_0_is_idle(struct amdgpu_ip_block *ip_block) 652 { 653 /* todo */ 654 return true; 655 } 656 657 static int ih_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 658 { 659 /* todo */ 660 return -ETIMEDOUT; 661 } 662 663 static int ih_v7_0_soft_reset(struct amdgpu_ip_block *ip_block) 664 { 665 /* todo */ 666 return 0; 667 } 668 669 static void ih_v7_0_update_clockgating_state(struct amdgpu_device *adev, 670 bool enable) 671 { 672 uint32_t data, def, field_val; 673 674 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 675 def = data = RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL); 676 field_val = enable ? 0 : 1; 677 data = REG_SET_FIELD(data, IH_CLK_CTRL, 678 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 679 data = REG_SET_FIELD(data, IH_CLK_CTRL, 680 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 681 data = REG_SET_FIELD(data, IH_CLK_CTRL, 682 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 683 data = REG_SET_FIELD(data, IH_CLK_CTRL, 684 DYN_CLK_SOFT_OVERRIDE, field_val); 685 data = REG_SET_FIELD(data, IH_CLK_CTRL, 686 REG_CLK_SOFT_OVERRIDE, field_val); 687 if (def != data) 688 WREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL, data); 689 } 690 691 return; 692 } 693 694 static int ih_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 695 enum amd_clockgating_state state) 696 { 697 struct amdgpu_device *adev = ip_block->adev; 698 699 ih_v7_0_update_clockgating_state(adev, 700 state == AMD_CG_STATE_GATE); 701 return 0; 702 } 703 704 static void ih_v7_0_update_ih_mem_power_gating(struct amdgpu_device *adev, 705 bool enable) 706 { 707 uint32_t ih_mem_pwr_cntl; 708 709 /* Disable ih sram power cntl before switch powergating mode */ 710 ih_mem_pwr_cntl = RREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL); 711 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 712 IH_BUFFER_MEM_POWER_CTRL_EN, 0); 713 WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl); 714 715 /* It is recommended to set mem powergating mode to DS mode */ 716 if (enable) { 717 /* mem power mode */ 718 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 719 IH_BUFFER_MEM_POWER_LS_EN, 0); 720 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 721 IH_BUFFER_MEM_POWER_DS_EN, 1); 722 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 723 IH_BUFFER_MEM_POWER_SD_EN, 0); 724 /* cam mem power mode */ 725 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 726 IH_RETRY_INT_CAM_MEM_POWER_LS_EN, 0); 727 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 728 IH_RETRY_INT_CAM_MEM_POWER_DS_EN, 1); 729 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 730 IH_RETRY_INT_CAM_MEM_POWER_SD_EN, 0); 731 /* re-enable power cntl */ 732 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 733 IH_BUFFER_MEM_POWER_CTRL_EN, 1); 734 } else { 735 /* mem power mode */ 736 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 737 IH_BUFFER_MEM_POWER_LS_EN, 0); 738 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 739 IH_BUFFER_MEM_POWER_DS_EN, 0); 740 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 741 IH_BUFFER_MEM_POWER_SD_EN, 0); 742 /* cam mem power mode */ 743 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 744 IH_RETRY_INT_CAM_MEM_POWER_LS_EN, 0); 745 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 746 IH_RETRY_INT_CAM_MEM_POWER_DS_EN, 0); 747 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 748 IH_RETRY_INT_CAM_MEM_POWER_SD_EN, 0); 749 /* re-enable power cntl*/ 750 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 751 IH_BUFFER_MEM_POWER_CTRL_EN, 1); 752 } 753 754 WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl); 755 } 756 757 static int ih_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 758 enum amd_powergating_state state) 759 { 760 struct amdgpu_device *adev = ip_block->adev; 761 bool enable = (state == AMD_PG_STATE_GATE); 762 763 if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG) 764 ih_v7_0_update_ih_mem_power_gating(adev, enable); 765 766 return 0; 767 } 768 769 static void ih_v7_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 770 { 771 struct amdgpu_device *adev = ip_block->adev; 772 773 if (!RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL)) 774 *flags |= AMD_CG_SUPPORT_IH_CG; 775 776 return; 777 } 778 779 static const struct amd_ip_funcs ih_v7_0_ip_funcs = { 780 .name = "ih_v7_0", 781 .early_init = ih_v7_0_early_init, 782 .sw_init = ih_v7_0_sw_init, 783 .sw_fini = ih_v7_0_sw_fini, 784 .hw_init = ih_v7_0_hw_init, 785 .hw_fini = ih_v7_0_hw_fini, 786 .suspend = ih_v7_0_suspend, 787 .resume = ih_v7_0_resume, 788 .is_idle = ih_v7_0_is_idle, 789 .wait_for_idle = ih_v7_0_wait_for_idle, 790 .soft_reset = ih_v7_0_soft_reset, 791 .set_clockgating_state = ih_v7_0_set_clockgating_state, 792 .set_powergating_state = ih_v7_0_set_powergating_state, 793 .get_clockgating_state = ih_v7_0_get_clockgating_state, 794 }; 795 796 static const struct amdgpu_ih_funcs ih_v7_0_funcs = { 797 .get_wptr = ih_v7_0_get_wptr, 798 .decode_iv = amdgpu_ih_decode_iv_helper, 799 .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper, 800 .set_rptr = ih_v7_0_set_rptr 801 }; 802 803 static void ih_v7_0_set_interrupt_funcs(struct amdgpu_device *adev) 804 { 805 adev->irq.ih_funcs = &ih_v7_0_funcs; 806 } 807 808 const struct amdgpu_ip_block_version ih_v7_0_ip_block = 809 { 810 .type = AMD_IP_BLOCK_TYPE_IH, 811 .major = 7, 812 .minor = 0, 813 .rev = 0, 814 .funcs = &ih_v7_0_ip_funcs, 815 }; 816