1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: monk liu <monk.liu@amd.com> 23 */ 24 25 #include <drm/drm_auth.h> 26 #include <drm/drm_drv.h> 27 #include "amdgpu.h" 28 #include "amdgpu_sched.h" 29 #include "amdgpu_ras.h" 30 #include <linux/nospec.h> 31 32 #define to_amdgpu_ctx_entity(e) \ 33 container_of((e), struct amdgpu_ctx_entity, entity) 34 35 const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM] = { 36 [AMDGPU_HW_IP_GFX] = 1, 37 [AMDGPU_HW_IP_COMPUTE] = 4, 38 [AMDGPU_HW_IP_DMA] = 2, 39 [AMDGPU_HW_IP_UVD] = 1, 40 [AMDGPU_HW_IP_VCE] = 1, 41 [AMDGPU_HW_IP_UVD_ENC] = 1, 42 [AMDGPU_HW_IP_VCN_DEC] = 1, 43 [AMDGPU_HW_IP_VCN_ENC] = 1, 44 [AMDGPU_HW_IP_VCN_JPEG] = 1, 45 [AMDGPU_HW_IP_VPE] = 1, 46 }; 47 48 bool amdgpu_ctx_priority_is_valid(int32_t ctx_prio) 49 { 50 switch (ctx_prio) { 51 case AMDGPU_CTX_PRIORITY_VERY_LOW: 52 case AMDGPU_CTX_PRIORITY_LOW: 53 case AMDGPU_CTX_PRIORITY_NORMAL: 54 case AMDGPU_CTX_PRIORITY_HIGH: 55 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 56 return true; 57 default: 58 case AMDGPU_CTX_PRIORITY_UNSET: 59 /* UNSET priority is not valid and we don't carry that 60 * around, but set it to NORMAL in the only place this 61 * function is called, amdgpu_ctx_ioctl(). 62 */ 63 return false; 64 } 65 } 66 67 static enum drm_sched_priority 68 amdgpu_ctx_to_drm_sched_prio(int32_t ctx_prio) 69 { 70 switch (ctx_prio) { 71 case AMDGPU_CTX_PRIORITY_UNSET: 72 pr_warn_once("AMD-->DRM context priority value UNSET-->NORMAL"); 73 return DRM_SCHED_PRIORITY_NORMAL; 74 75 case AMDGPU_CTX_PRIORITY_VERY_LOW: 76 return DRM_SCHED_PRIORITY_LOW; 77 78 case AMDGPU_CTX_PRIORITY_LOW: 79 return DRM_SCHED_PRIORITY_LOW; 80 81 case AMDGPU_CTX_PRIORITY_NORMAL: 82 return DRM_SCHED_PRIORITY_NORMAL; 83 84 case AMDGPU_CTX_PRIORITY_HIGH: 85 return DRM_SCHED_PRIORITY_HIGH; 86 87 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 88 return DRM_SCHED_PRIORITY_HIGH; 89 90 /* This should not happen as we sanitized userspace provided priority 91 * already, WARN if this happens. 92 */ 93 default: 94 WARN(1, "Invalid context priority %d\n", ctx_prio); 95 return DRM_SCHED_PRIORITY_NORMAL; 96 } 97 98 } 99 100 static int amdgpu_ctx_priority_permit(struct drm_file *filp, 101 int32_t priority) 102 { 103 /* NORMAL and below are accessible by everyone */ 104 if (priority <= AMDGPU_CTX_PRIORITY_NORMAL) 105 return 0; 106 107 if (capable(CAP_SYS_NICE)) 108 return 0; 109 110 if (drm_is_current_master(filp)) 111 return 0; 112 113 return -EACCES; 114 } 115 116 static enum amdgpu_gfx_pipe_priority amdgpu_ctx_prio_to_gfx_pipe_prio(int32_t prio) 117 { 118 switch (prio) { 119 case AMDGPU_CTX_PRIORITY_HIGH: 120 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 121 return AMDGPU_GFX_PIPE_PRIO_HIGH; 122 default: 123 return AMDGPU_GFX_PIPE_PRIO_NORMAL; 124 } 125 } 126 127 static enum amdgpu_ring_priority_level amdgpu_ctx_sched_prio_to_ring_prio(int32_t prio) 128 { 129 switch (prio) { 130 case AMDGPU_CTX_PRIORITY_HIGH: 131 return AMDGPU_RING_PRIO_1; 132 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 133 return AMDGPU_RING_PRIO_2; 134 default: 135 return AMDGPU_RING_PRIO_0; 136 } 137 } 138 139 static unsigned int amdgpu_ctx_get_hw_prio(struct amdgpu_ctx *ctx, u32 hw_ip) 140 { 141 struct amdgpu_device *adev = ctx->mgr->adev; 142 unsigned int hw_prio; 143 int32_t ctx_prio; 144 145 ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? 146 ctx->init_priority : ctx->override_priority; 147 148 switch (hw_ip) { 149 case AMDGPU_HW_IP_GFX: 150 case AMDGPU_HW_IP_COMPUTE: 151 hw_prio = amdgpu_ctx_prio_to_gfx_pipe_prio(ctx_prio); 152 break; 153 case AMDGPU_HW_IP_VCE: 154 case AMDGPU_HW_IP_VCN_ENC: 155 hw_prio = amdgpu_ctx_sched_prio_to_ring_prio(ctx_prio); 156 break; 157 default: 158 hw_prio = AMDGPU_RING_PRIO_DEFAULT; 159 break; 160 } 161 162 hw_ip = array_index_nospec(hw_ip, AMDGPU_HW_IP_NUM); 163 if (adev->gpu_sched[hw_ip][hw_prio].num_scheds == 0) 164 hw_prio = AMDGPU_RING_PRIO_DEFAULT; 165 166 return hw_prio; 167 } 168 169 /* Calculate the time spend on the hw */ 170 static ktime_t amdgpu_ctx_fence_time(struct dma_fence *fence) 171 { 172 struct drm_sched_fence *s_fence; 173 174 if (!fence) 175 return ns_to_ktime(0); 176 177 /* When the fence is not even scheduled it can't have spend time */ 178 s_fence = to_drm_sched_fence(fence); 179 if (!test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &s_fence->scheduled.flags)) 180 return ns_to_ktime(0); 181 182 /* When it is still running account how much already spend */ 183 if (!test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &s_fence->finished.flags)) 184 return ktime_sub(ktime_get(), s_fence->scheduled.timestamp); 185 186 return ktime_sub(s_fence->finished.timestamp, 187 s_fence->scheduled.timestamp); 188 } 189 190 static ktime_t amdgpu_ctx_entity_time(struct amdgpu_ctx *ctx, 191 struct amdgpu_ctx_entity *centity) 192 { 193 ktime_t res = ns_to_ktime(0); 194 uint32_t i; 195 196 spin_lock(&ctx->ring_lock); 197 for (i = 0; i < amdgpu_sched_jobs; i++) { 198 res = ktime_add(res, amdgpu_ctx_fence_time(centity->fences[i])); 199 } 200 spin_unlock(&ctx->ring_lock); 201 return res; 202 } 203 204 static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, 205 const u32 ring) 206 { 207 struct drm_gpu_scheduler **scheds = NULL, *sched = NULL; 208 struct amdgpu_device *adev = ctx->mgr->adev; 209 struct amdgpu_ctx_entity *entity; 210 enum drm_sched_priority drm_prio; 211 unsigned int hw_prio, num_scheds; 212 int32_t ctx_prio; 213 int r; 214 215 entity = kzalloc_flex(*entity, fences, amdgpu_sched_jobs, GFP_KERNEL); 216 if (!entity) 217 return -ENOMEM; 218 219 ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? 220 ctx->init_priority : ctx->override_priority; 221 entity->hw_ip = hw_ip; 222 entity->sequence = 1; 223 hw_prio = amdgpu_ctx_get_hw_prio(ctx, hw_ip); 224 drm_prio = amdgpu_ctx_to_drm_sched_prio(ctx_prio); 225 226 hw_ip = array_index_nospec(hw_ip, AMDGPU_HW_IP_NUM); 227 228 if (!(adev)->xcp_mgr) { 229 scheds = adev->gpu_sched[hw_ip][hw_prio].sched; 230 num_scheds = adev->gpu_sched[hw_ip][hw_prio].num_scheds; 231 } else { 232 struct amdgpu_fpriv *fpriv; 233 234 fpriv = container_of(ctx->ctx_mgr, struct amdgpu_fpriv, ctx_mgr); 235 r = amdgpu_xcp_select_scheds(adev, hw_ip, hw_prio, fpriv, 236 &num_scheds, &scheds); 237 if (r) 238 goto error_free_entity; 239 } 240 241 /* disable load balance if the hw engine retains context among dependent jobs */ 242 if (hw_ip == AMDGPU_HW_IP_VCN_ENC || 243 hw_ip == AMDGPU_HW_IP_VCN_DEC || 244 hw_ip == AMDGPU_HW_IP_UVD_ENC || 245 hw_ip == AMDGPU_HW_IP_UVD) { 246 sched = drm_sched_pick_best(scheds, num_scheds); 247 scheds = &sched; 248 num_scheds = 1; 249 } 250 251 r = drm_sched_entity_init(&entity->entity, drm_prio, scheds, num_scheds, 252 &ctx->guilty); 253 if (r) 254 goto error_free_entity; 255 256 /* It's not an error if we fail to install the new entity */ 257 if (cmpxchg(&ctx->entities[hw_ip][ring], NULL, entity)) 258 goto cleanup_entity; 259 260 return 0; 261 262 cleanup_entity: 263 drm_sched_entity_fini(&entity->entity); 264 265 error_free_entity: 266 kfree(entity); 267 268 return r; 269 } 270 271 static ktime_t amdgpu_ctx_fini_entity(struct amdgpu_device *adev, 272 struct amdgpu_ctx_entity *entity) 273 { 274 ktime_t res = ns_to_ktime(0); 275 int i; 276 277 if (!entity) 278 return res; 279 280 for (i = 0; i < amdgpu_sched_jobs; ++i) { 281 res = ktime_add(res, amdgpu_ctx_fence_time(entity->fences[i])); 282 dma_fence_put(entity->fences[i]); 283 } 284 285 amdgpu_xcp_release_sched(adev, entity); 286 287 kfree(entity); 288 return res; 289 } 290 291 static int amdgpu_ctx_get_stable_pstate(struct amdgpu_ctx *ctx, 292 u32 *stable_pstate) 293 { 294 struct amdgpu_device *adev = ctx->mgr->adev; 295 enum amd_dpm_forced_level current_level; 296 297 current_level = amdgpu_dpm_get_performance_level(adev); 298 299 switch (current_level) { 300 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 301 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_STANDARD; 302 break; 303 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 304 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK; 305 break; 306 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 307 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK; 308 break; 309 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 310 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_PEAK; 311 break; 312 default: 313 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_NONE; 314 break; 315 } 316 return 0; 317 } 318 319 static int amdgpu_ctx_init(struct amdgpu_ctx_mgr *mgr, int32_t priority, 320 struct drm_file *filp, struct amdgpu_ctx *ctx) 321 { 322 struct amdgpu_fpriv *fpriv = filp->driver_priv; 323 u32 current_stable_pstate; 324 int r; 325 326 r = amdgpu_ctx_priority_permit(filp, priority); 327 if (r) 328 return r; 329 330 memset(ctx, 0, sizeof(*ctx)); 331 332 kref_init(&ctx->refcount); 333 ctx->mgr = mgr; 334 spin_lock_init(&ctx->ring_lock); 335 336 ctx->reset_counter = atomic_read(&mgr->adev->gpu_reset_counter); 337 ctx->reset_counter_query = ctx->reset_counter; 338 ctx->generation = amdgpu_vm_generation(mgr->adev, &fpriv->vm); 339 ctx->init_priority = priority; 340 ctx->override_priority = AMDGPU_CTX_PRIORITY_UNSET; 341 342 r = amdgpu_ctx_get_stable_pstate(ctx, ¤t_stable_pstate); 343 if (r) 344 return r; 345 346 if (mgr->adev->pm.stable_pstate_ctx) 347 ctx->stable_pstate = mgr->adev->pm.stable_pstate_ctx->stable_pstate; 348 else 349 ctx->stable_pstate = current_stable_pstate; 350 351 ctx->ctx_mgr = &(fpriv->ctx_mgr); 352 return 0; 353 } 354 355 static int amdgpu_ctx_set_stable_pstate(struct amdgpu_ctx *ctx, 356 u32 stable_pstate) 357 { 358 struct amdgpu_device *adev = ctx->mgr->adev; 359 enum amd_dpm_forced_level level; 360 u32 current_stable_pstate; 361 int r; 362 363 mutex_lock(&adev->pm.stable_pstate_ctx_lock); 364 if (adev->pm.stable_pstate_ctx && adev->pm.stable_pstate_ctx != ctx) { 365 r = -EBUSY; 366 goto done; 367 } 368 369 r = amdgpu_ctx_get_stable_pstate(ctx, ¤t_stable_pstate); 370 if (r || (stable_pstate == current_stable_pstate)) 371 goto done; 372 373 switch (stable_pstate) { 374 case AMDGPU_CTX_STABLE_PSTATE_NONE: 375 level = AMD_DPM_FORCED_LEVEL_AUTO; 376 break; 377 case AMDGPU_CTX_STABLE_PSTATE_STANDARD: 378 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; 379 break; 380 case AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK: 381 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; 382 break; 383 case AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK: 384 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; 385 break; 386 case AMDGPU_CTX_STABLE_PSTATE_PEAK: 387 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 388 break; 389 default: 390 r = -EINVAL; 391 goto done; 392 } 393 394 r = amdgpu_dpm_force_performance_level(adev, level); 395 396 if (level == AMD_DPM_FORCED_LEVEL_AUTO) 397 adev->pm.stable_pstate_ctx = NULL; 398 else 399 adev->pm.stable_pstate_ctx = ctx; 400 done: 401 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 402 403 return r; 404 } 405 406 static void amdgpu_ctx_fini(struct kref *ref) 407 { 408 struct amdgpu_ctx *ctx = container_of(ref, struct amdgpu_ctx, refcount); 409 struct amdgpu_ctx_mgr *mgr = ctx->mgr; 410 struct amdgpu_device *adev = mgr->adev; 411 unsigned i, j, idx; 412 413 if (!adev) 414 return; 415 416 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 417 for (j = 0; j < AMDGPU_MAX_ENTITY_NUM; ++j) { 418 ktime_t spend; 419 420 spend = amdgpu_ctx_fini_entity(adev, ctx->entities[i][j]); 421 atomic64_add(ktime_to_ns(spend), &mgr->time_spend[i]); 422 } 423 } 424 425 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 426 amdgpu_ctx_set_stable_pstate(ctx, ctx->stable_pstate); 427 drm_dev_exit(idx); 428 } 429 430 kfree(ctx); 431 } 432 433 int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance, 434 u32 ring, struct drm_sched_entity **entity) 435 { 436 int r; 437 struct drm_sched_entity *ctx_entity; 438 439 if (hw_ip >= AMDGPU_HW_IP_NUM) { 440 drm_err(adev_to_drm(ctx->mgr->adev), 441 "unknown HW IP type: %d\n", hw_ip); 442 return -EINVAL; 443 } 444 445 /* Right now all IPs have only one instance - multiple rings. */ 446 if (instance != 0) { 447 drm_dbg(adev_to_drm(ctx->mgr->adev), 448 "invalid ip instance: %d\n", instance); 449 return -EINVAL; 450 } 451 452 if (ring >= amdgpu_ctx_num_entities[hw_ip]) { 453 drm_dbg(adev_to_drm(ctx->mgr->adev), 454 "invalid ring: %d %d\n", hw_ip, ring); 455 return -EINVAL; 456 } 457 458 if (ctx->entities[hw_ip][ring] == NULL) { 459 r = amdgpu_ctx_init_entity(ctx, hw_ip, ring); 460 if (r) 461 return r; 462 } 463 464 ctx_entity = &ctx->entities[hw_ip][ring]->entity; 465 r = drm_sched_entity_error(ctx_entity); 466 if (r) { 467 DRM_DEBUG("error entity %p\n", ctx_entity); 468 return r; 469 } 470 471 *entity = ctx_entity; 472 return 0; 473 } 474 475 static int amdgpu_ctx_alloc(struct amdgpu_device *adev, 476 struct amdgpu_fpriv *fpriv, 477 struct drm_file *filp, 478 int32_t priority, 479 uint32_t *id) 480 { 481 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 482 struct amdgpu_ctx *ctx; 483 int r; 484 485 ctx = kmalloc_obj(*ctx, GFP_KERNEL); 486 if (!ctx) 487 return -ENOMEM; 488 489 mutex_lock(&mgr->lock); 490 r = idr_alloc(&mgr->ctx_handles, ctx, 1, AMDGPU_VM_MAX_NUM_CTX, GFP_KERNEL); 491 if (r < 0) { 492 mutex_unlock(&mgr->lock); 493 kfree(ctx); 494 return r; 495 } 496 497 *id = (uint32_t)r; 498 r = amdgpu_ctx_init(mgr, priority, filp, ctx); 499 if (r) { 500 idr_remove(&mgr->ctx_handles, *id); 501 *id = 0; 502 kfree(ctx); 503 } 504 mutex_unlock(&mgr->lock); 505 return r; 506 } 507 508 static void amdgpu_ctx_do_release(struct kref *ref) 509 { 510 struct amdgpu_ctx *ctx; 511 u32 i, j; 512 513 ctx = container_of(ref, struct amdgpu_ctx, refcount); 514 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 515 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 516 if (!ctx->entities[i][j]) 517 continue; 518 519 drm_sched_entity_destroy(&ctx->entities[i][j]->entity); 520 } 521 } 522 523 amdgpu_ctx_fini(ref); 524 } 525 526 static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id) 527 { 528 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 529 struct amdgpu_ctx *ctx; 530 531 mutex_lock(&mgr->lock); 532 ctx = idr_remove(&mgr->ctx_handles, id); 533 if (ctx) 534 kref_put(&ctx->refcount, amdgpu_ctx_do_release); 535 mutex_unlock(&mgr->lock); 536 return ctx ? 0 : -EINVAL; 537 } 538 539 static int amdgpu_ctx_query(struct amdgpu_device *adev, 540 struct amdgpu_fpriv *fpriv, uint32_t id, 541 union drm_amdgpu_ctx_out *out) 542 { 543 struct amdgpu_ctx *ctx; 544 struct amdgpu_ctx_mgr *mgr; 545 unsigned reset_counter; 546 547 if (!fpriv) 548 return -EINVAL; 549 550 mgr = &fpriv->ctx_mgr; 551 mutex_lock(&mgr->lock); 552 ctx = idr_find(&mgr->ctx_handles, id); 553 if (!ctx) { 554 mutex_unlock(&mgr->lock); 555 return -EINVAL; 556 } 557 558 /* TODO: these two are always zero */ 559 out->state.flags = 0x0; 560 out->state.hangs = 0x0; 561 562 /* determine if a GPU reset has occured since the last call */ 563 reset_counter = atomic_read(&adev->gpu_reset_counter); 564 /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */ 565 if (ctx->reset_counter_query == reset_counter) 566 out->state.reset_status = AMDGPU_CTX_NO_RESET; 567 else 568 out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET; 569 ctx->reset_counter_query = reset_counter; 570 571 mutex_unlock(&mgr->lock); 572 return 0; 573 } 574 575 #define AMDGPU_RAS_COUNTE_DELAY_MS 3000 576 577 static int amdgpu_ctx_query2(struct amdgpu_device *adev, 578 struct amdgpu_fpriv *fpriv, uint32_t id, 579 union drm_amdgpu_ctx_out *out) 580 { 581 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 582 struct amdgpu_ctx *ctx; 583 struct amdgpu_ctx_mgr *mgr; 584 585 if (!fpriv) 586 return -EINVAL; 587 588 mgr = &fpriv->ctx_mgr; 589 mutex_lock(&mgr->lock); 590 ctx = idr_find(&mgr->ctx_handles, id); 591 if (!ctx) { 592 mutex_unlock(&mgr->lock); 593 return -EINVAL; 594 } 595 596 out->state.flags = 0x0; 597 out->state.hangs = 0x0; 598 599 if (ctx->reset_counter != atomic_read(&adev->gpu_reset_counter)) 600 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RESET; 601 602 if (ctx->generation != amdgpu_vm_generation(adev, &fpriv->vm)) 603 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST; 604 605 if (atomic_read(&ctx->guilty)) 606 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY; 607 608 if (amdgpu_in_reset(adev)) 609 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS; 610 611 if (adev->ras_enabled && con) { 612 /* Return the cached values in O(1), 613 * and schedule delayed work to cache 614 * new vaues. 615 */ 616 int ce_count, ue_count; 617 618 ce_count = atomic_read(&con->ras_ce_count); 619 ue_count = atomic_read(&con->ras_ue_count); 620 621 if (ce_count != ctx->ras_counter_ce) { 622 ctx->ras_counter_ce = ce_count; 623 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE; 624 } 625 626 if (ue_count != ctx->ras_counter_ue) { 627 ctx->ras_counter_ue = ue_count; 628 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE; 629 } 630 631 schedule_delayed_work(&con->ras_counte_delay_work, 632 msecs_to_jiffies(AMDGPU_RAS_COUNTE_DELAY_MS)); 633 } 634 635 mutex_unlock(&mgr->lock); 636 return 0; 637 } 638 639 static int amdgpu_ctx_stable_pstate(struct amdgpu_device *adev, 640 struct amdgpu_fpriv *fpriv, uint32_t id, 641 bool set, u32 *stable_pstate) 642 { 643 struct amdgpu_ctx *ctx; 644 struct amdgpu_ctx_mgr *mgr; 645 int r; 646 647 if (!fpriv) 648 return -EINVAL; 649 650 mgr = &fpriv->ctx_mgr; 651 mutex_lock(&mgr->lock); 652 ctx = idr_find(&mgr->ctx_handles, id); 653 if (!ctx) { 654 mutex_unlock(&mgr->lock); 655 return -EINVAL; 656 } 657 658 if (set) 659 r = amdgpu_ctx_set_stable_pstate(ctx, *stable_pstate); 660 else 661 r = amdgpu_ctx_get_stable_pstate(ctx, stable_pstate); 662 663 mutex_unlock(&mgr->lock); 664 return r; 665 } 666 667 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 668 struct drm_file *filp) 669 { 670 int r; 671 uint32_t id, stable_pstate; 672 int32_t priority; 673 674 union drm_amdgpu_ctx *args = data; 675 struct amdgpu_device *adev = drm_to_adev(dev); 676 struct amdgpu_fpriv *fpriv = filp->driver_priv; 677 678 id = args->in.ctx_id; 679 priority = args->in.priority; 680 681 /* For backwards compatibility, we need to accept ioctls with garbage 682 * in the priority field. Garbage values in the priority field, result 683 * in the priority being set to NORMAL. 684 */ 685 if (!amdgpu_ctx_priority_is_valid(priority)) 686 priority = AMDGPU_CTX_PRIORITY_NORMAL; 687 688 switch (args->in.op) { 689 case AMDGPU_CTX_OP_ALLOC_CTX: 690 if (args->in.flags) 691 return -EINVAL; 692 r = amdgpu_ctx_alloc(adev, fpriv, filp, priority, &id); 693 args->out.alloc.ctx_id = id; 694 break; 695 case AMDGPU_CTX_OP_FREE_CTX: 696 if (args->in.flags) 697 return -EINVAL; 698 r = amdgpu_ctx_free(fpriv, id); 699 break; 700 case AMDGPU_CTX_OP_QUERY_STATE: 701 if (args->in.flags) 702 return -EINVAL; 703 r = amdgpu_ctx_query(adev, fpriv, id, &args->out); 704 break; 705 case AMDGPU_CTX_OP_QUERY_STATE2: 706 if (args->in.flags) 707 return -EINVAL; 708 r = amdgpu_ctx_query2(adev, fpriv, id, &args->out); 709 break; 710 case AMDGPU_CTX_OP_GET_STABLE_PSTATE: 711 if (args->in.flags) 712 return -EINVAL; 713 r = amdgpu_ctx_stable_pstate(adev, fpriv, id, false, &stable_pstate); 714 if (!r) 715 args->out.pstate.flags = stable_pstate; 716 break; 717 case AMDGPU_CTX_OP_SET_STABLE_PSTATE: 718 if (args->in.flags & ~AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK) 719 return -EINVAL; 720 stable_pstate = args->in.flags & AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK; 721 if (stable_pstate > AMDGPU_CTX_STABLE_PSTATE_PEAK) 722 return -EINVAL; 723 r = amdgpu_ctx_stable_pstate(adev, fpriv, id, true, &stable_pstate); 724 break; 725 default: 726 return -EINVAL; 727 } 728 729 return r; 730 } 731 732 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id) 733 { 734 struct amdgpu_ctx *ctx; 735 struct amdgpu_ctx_mgr *mgr; 736 737 if (!fpriv) 738 return NULL; 739 740 mgr = &fpriv->ctx_mgr; 741 742 mutex_lock(&mgr->lock); 743 ctx = idr_find(&mgr->ctx_handles, id); 744 if (ctx) 745 kref_get(&ctx->refcount); 746 mutex_unlock(&mgr->lock); 747 return ctx; 748 } 749 750 int amdgpu_ctx_put(struct amdgpu_ctx *ctx) 751 { 752 if (ctx == NULL) 753 return -EINVAL; 754 755 kref_put(&ctx->refcount, amdgpu_ctx_do_release); 756 return 0; 757 } 758 759 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, 760 struct drm_sched_entity *entity, 761 struct dma_fence *fence) 762 { 763 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 764 uint64_t seq = centity->sequence; 765 struct dma_fence *other = NULL; 766 unsigned idx = 0; 767 768 idx = seq & (amdgpu_sched_jobs - 1); 769 other = centity->fences[idx]; 770 WARN_ON(other && !dma_fence_is_signaled(other)); 771 772 dma_fence_get(fence); 773 774 spin_lock(&ctx->ring_lock); 775 centity->fences[idx] = fence; 776 centity->sequence++; 777 spin_unlock(&ctx->ring_lock); 778 779 atomic64_add(ktime_to_ns(amdgpu_ctx_fence_time(other)), 780 &ctx->mgr->time_spend[centity->hw_ip]); 781 782 dma_fence_put(other); 783 return seq; 784 } 785 786 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 787 struct drm_sched_entity *entity, 788 uint64_t seq) 789 { 790 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 791 struct dma_fence *fence; 792 793 spin_lock(&ctx->ring_lock); 794 795 if (seq == ~0ull) 796 seq = centity->sequence - 1; 797 798 if (seq >= centity->sequence) { 799 spin_unlock(&ctx->ring_lock); 800 return ERR_PTR(-EINVAL); 801 } 802 803 804 if (seq + amdgpu_sched_jobs < centity->sequence) { 805 spin_unlock(&ctx->ring_lock); 806 return NULL; 807 } 808 809 fence = dma_fence_get(centity->fences[seq & (amdgpu_sched_jobs - 1)]); 810 spin_unlock(&ctx->ring_lock); 811 812 return fence; 813 } 814 815 static void amdgpu_ctx_set_entity_priority(struct amdgpu_ctx *ctx, 816 struct amdgpu_ctx_entity *aentity, 817 int hw_ip, 818 int32_t priority) 819 { 820 struct amdgpu_device *adev = ctx->mgr->adev; 821 unsigned int hw_prio; 822 struct drm_gpu_scheduler **scheds = NULL; 823 unsigned num_scheds; 824 825 /* set sw priority */ 826 drm_sched_entity_set_priority(&aentity->entity, 827 amdgpu_ctx_to_drm_sched_prio(priority)); 828 829 /* set hw priority */ 830 if (hw_ip == AMDGPU_HW_IP_COMPUTE || hw_ip == AMDGPU_HW_IP_GFX) { 831 hw_prio = amdgpu_ctx_get_hw_prio(ctx, hw_ip); 832 hw_prio = array_index_nospec(hw_prio, AMDGPU_RING_PRIO_MAX); 833 scheds = adev->gpu_sched[hw_ip][hw_prio].sched; 834 num_scheds = adev->gpu_sched[hw_ip][hw_prio].num_scheds; 835 drm_sched_entity_modify_sched(&aentity->entity, scheds, 836 num_scheds); 837 } 838 } 839 840 void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, 841 int32_t priority) 842 { 843 int32_t ctx_prio; 844 unsigned i, j; 845 846 ctx->override_priority = priority; 847 848 ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? 849 ctx->init_priority : ctx->override_priority; 850 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 851 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 852 if (!ctx->entities[i][j]) 853 continue; 854 855 amdgpu_ctx_set_entity_priority(ctx, ctx->entities[i][j], 856 i, ctx_prio); 857 } 858 } 859 } 860 861 int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, 862 struct drm_sched_entity *entity) 863 { 864 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 865 struct dma_fence *other; 866 unsigned idx; 867 long r; 868 869 spin_lock(&ctx->ring_lock); 870 idx = centity->sequence & (amdgpu_sched_jobs - 1); 871 other = dma_fence_get(centity->fences[idx]); 872 spin_unlock(&ctx->ring_lock); 873 874 if (!other) 875 return 0; 876 877 r = dma_fence_wait(other, true); 878 if (r < 0 && r != -ERESTARTSYS) 879 drm_err(adev_to_drm(ctx->mgr->adev), 880 "AMDGPU: Error waiting for fence in ctx %p\n", ctx); 881 882 dma_fence_put(other); 883 return r; 884 } 885 886 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr, 887 struct amdgpu_device *adev) 888 { 889 unsigned int i; 890 891 mgr->adev = adev; 892 mutex_init(&mgr->lock); 893 idr_init_base(&mgr->ctx_handles, 1); 894 895 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) 896 atomic64_set(&mgr->time_spend[i], 0); 897 } 898 899 long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout) 900 { 901 struct amdgpu_ctx *ctx; 902 struct idr *idp; 903 uint32_t id, i, j; 904 905 idp = &mgr->ctx_handles; 906 907 mutex_lock(&mgr->lock); 908 idr_for_each_entry(idp, ctx, id) { 909 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 910 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 911 struct drm_sched_entity *entity; 912 913 if (!ctx->entities[i][j]) 914 continue; 915 916 entity = &ctx->entities[i][j]->entity; 917 timeout = drm_sched_entity_flush(entity, timeout); 918 } 919 } 920 } 921 mutex_unlock(&mgr->lock); 922 return timeout; 923 } 924 925 static void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr) 926 { 927 struct amdgpu_ctx *ctx; 928 struct idr *idp; 929 uint32_t id, i, j; 930 931 idp = &mgr->ctx_handles; 932 933 idr_for_each_entry(idp, ctx, id) { 934 if (kref_read(&ctx->refcount) != 1) { 935 drm_err(adev_to_drm(mgr->adev), "ctx %p is still alive\n", ctx); 936 continue; 937 } 938 939 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 940 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 941 struct drm_sched_entity *entity; 942 943 if (!ctx->entities[i][j]) 944 continue; 945 946 entity = &ctx->entities[i][j]->entity; 947 drm_sched_entity_fini(entity); 948 } 949 } 950 kref_put(&ctx->refcount, amdgpu_ctx_fini); 951 } 952 } 953 954 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr) 955 { 956 amdgpu_ctx_mgr_entity_fini(mgr); 957 idr_destroy(&mgr->ctx_handles); 958 mutex_destroy(&mgr->lock); 959 } 960 961 void amdgpu_ctx_mgr_usage(struct amdgpu_ctx_mgr *mgr, 962 ktime_t usage[AMDGPU_HW_IP_NUM]) 963 { 964 struct amdgpu_ctx *ctx; 965 unsigned int hw_ip, i; 966 uint32_t id; 967 968 /* 969 * This is a little bit racy because it can be that a ctx or a fence are 970 * destroyed just in the moment we try to account them. But that is ok 971 * since exactly that case is explicitely allowed by the interface. 972 */ 973 mutex_lock(&mgr->lock); 974 for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) { 975 uint64_t ns = atomic64_read(&mgr->time_spend[hw_ip]); 976 977 usage[hw_ip] = ns_to_ktime(ns); 978 } 979 980 idr_for_each_entry(&mgr->ctx_handles, ctx, id) { 981 for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) { 982 for (i = 0; i < amdgpu_ctx_num_entities[hw_ip]; ++i) { 983 struct amdgpu_ctx_entity *centity; 984 ktime_t spend; 985 986 centity = ctx->entities[hw_ip][i]; 987 if (!centity) 988 continue; 989 spend = amdgpu_ctx_entity_time(ctx, centity); 990 usage[hw_ip] = ktime_add(usage[hw_ip], spend); 991 } 992 } 993 } 994 mutex_unlock(&mgr->lock); 995 } 996