1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/dma-mapping.h>
8 #include <linux/mailbox_controller.h>
9 #include <linux/of.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/soc/mediatek/mtk-cmdq.h>
12 #include <linux/soc/mediatek/mtk-mmsys.h>
13 #include <linux/soc/mediatek/mtk-mutex.h>
14
15 #include <asm/barrier.h>
16
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_print.h>
20 #include <drm/drm_probe_helper.h>
21 #include <drm/drm_vblank.h>
22
23 #include "mtk_crtc.h"
24 #include "mtk_ddp_comp.h"
25 #include "mtk_drm_drv.h"
26 #include "mtk_gem.h"
27 #include "mtk_plane.h"
28
29 /*
30 * struct mtk_crtc - MediaTek specific crtc structure.
31 * @base: crtc object.
32 * @enabled: records whether crtc_enable succeeded
33 * @planes: array of 4 drm_plane structures, one for each overlay plane
34 * @pending_planes: whether any plane has pending changes to be applied
35 * @mmsys_dev: pointer to the mmsys device for configuration registers
36 * @mutex: handle to one of the ten disp_mutex streams
37 * @ddp_comp_nr: number of components in ddp_comp
38 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
39 *
40 * TODO: Needs update: this header is missing a bunch of member descriptions.
41 */
42 struct mtk_crtc {
43 struct drm_crtc base;
44 bool enabled;
45
46 bool pending_needs_vblank;
47 struct drm_pending_vblank_event *event;
48
49 struct drm_plane *planes;
50 unsigned int layer_nr;
51 bool pending_planes;
52 bool pending_async_planes;
53
54 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
55 struct cmdq_client cmdq_client;
56 struct cmdq_pkt cmdq_handle;
57 u32 cmdq_event;
58 u32 cmdq_vblank_cnt;
59 wait_queue_head_t cb_blocking_queue;
60 #endif
61
62 struct device *mmsys_dev;
63 struct device *dma_dev;
64 struct mtk_mutex *mutex;
65 unsigned int ddp_comp_nr;
66 struct mtk_ddp_comp **ddp_comp;
67 unsigned int num_conn_routes;
68 const struct mtk_drm_route *conn_routes;
69
70 /* lock for display hardware access */
71 struct mutex hw_lock;
72 bool config_updating;
73 /* lock for config_updating to cmd buffer */
74 spinlock_t config_lock;
75 };
76
77 struct mtk_crtc_state {
78 struct drm_crtc_state base;
79
80 bool pending_config;
81 unsigned int pending_width;
82 unsigned int pending_height;
83 unsigned int pending_vrefresh;
84 };
85
to_mtk_crtc(struct drm_crtc * c)86 static inline struct mtk_crtc *to_mtk_crtc(struct drm_crtc *c)
87 {
88 return container_of(c, struct mtk_crtc, base);
89 }
90
to_mtk_crtc_state(struct drm_crtc_state * s)91 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s)
92 {
93 return container_of(s, struct mtk_crtc_state, base);
94 }
95
mtk_crtc_finish_page_flip(struct mtk_crtc * mtk_crtc)96 static void mtk_crtc_finish_page_flip(struct mtk_crtc *mtk_crtc)
97 {
98 struct drm_crtc *crtc = &mtk_crtc->base;
99 unsigned long flags;
100
101 if (mtk_crtc->event) {
102 spin_lock_irqsave(&crtc->dev->event_lock, flags);
103 drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
104 drm_crtc_vblank_put(crtc);
105 mtk_crtc->event = NULL;
106 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
107 }
108 }
109
mtk_drm_finish_page_flip(struct mtk_crtc * mtk_crtc)110 static void mtk_drm_finish_page_flip(struct mtk_crtc *mtk_crtc)
111 {
112 unsigned long flags;
113
114 drm_crtc_handle_vblank(&mtk_crtc->base);
115
116 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
117 if (mtk_crtc->cmdq_client.chan)
118 return;
119 #endif
120
121 spin_lock_irqsave(&mtk_crtc->config_lock, flags);
122 if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) {
123 mtk_crtc_finish_page_flip(mtk_crtc);
124 mtk_crtc->pending_needs_vblank = false;
125 }
126 spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
127 }
128
mtk_crtc_destroy(struct drm_crtc * crtc)129 static void mtk_crtc_destroy(struct drm_crtc *crtc)
130 {
131 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
132 int i;
133
134 mtk_mutex_put(mtk_crtc->mutex);
135 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
136 if (mtk_crtc->cmdq_client.chan) {
137 cmdq_pkt_destroy(&mtk_crtc->cmdq_client, &mtk_crtc->cmdq_handle);
138 mbox_free_channel(mtk_crtc->cmdq_client.chan);
139 mtk_crtc->cmdq_client.chan = NULL;
140 }
141 #endif
142
143 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
144 struct mtk_ddp_comp *comp;
145
146 comp = mtk_crtc->ddp_comp[i];
147 mtk_ddp_comp_unregister_vblank_cb(comp);
148 }
149
150 drm_crtc_cleanup(crtc);
151 }
152
mtk_crtc_reset(struct drm_crtc * crtc)153 static void mtk_crtc_reset(struct drm_crtc *crtc)
154 {
155 struct mtk_crtc_state *state;
156
157 if (crtc->state)
158 __drm_atomic_helper_crtc_destroy_state(crtc->state);
159
160 kfree(to_mtk_crtc_state(crtc->state));
161 crtc->state = NULL;
162
163 state = kzalloc_obj(*state);
164 if (state)
165 __drm_atomic_helper_crtc_reset(crtc, &state->base);
166 }
167
mtk_crtc_duplicate_state(struct drm_crtc * crtc)168 static struct drm_crtc_state *mtk_crtc_duplicate_state(struct drm_crtc *crtc)
169 {
170 struct mtk_crtc_state *state;
171
172 state = kmalloc_obj(*state);
173 if (!state)
174 return NULL;
175
176 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
177
178 WARN_ON(state->base.crtc != crtc);
179 state->base.crtc = crtc;
180 state->pending_config = false;
181
182 return &state->base;
183 }
184
mtk_crtc_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)185 static void mtk_crtc_destroy_state(struct drm_crtc *crtc,
186 struct drm_crtc_state *state)
187 {
188 __drm_atomic_helper_crtc_destroy_state(state);
189 kfree(to_mtk_crtc_state(state));
190 }
191
192 static enum drm_mode_status
mtk_crtc_mode_valid(struct drm_crtc * crtc,const struct drm_display_mode * mode)193 mtk_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
194 {
195 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
196 enum drm_mode_status status = MODE_OK;
197 int i;
198
199 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
200 status = mtk_ddp_comp_mode_valid(mtk_crtc->ddp_comp[i], mode);
201 if (status != MODE_OK)
202 break;
203 }
204 return status;
205 }
206
mtk_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)207 static bool mtk_crtc_mode_fixup(struct drm_crtc *crtc,
208 const struct drm_display_mode *mode,
209 struct drm_display_mode *adjusted_mode)
210 {
211 /* Nothing to do here, but this callback is mandatory. */
212 return true;
213 }
214
mtk_crtc_mode_set_nofb(struct drm_crtc * crtc)215 static void mtk_crtc_mode_set_nofb(struct drm_crtc *crtc)
216 {
217 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
218
219 state->pending_width = crtc->mode.hdisplay;
220 state->pending_height = crtc->mode.vdisplay;
221 state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode);
222 wmb(); /* Make sure the above parameters are set before update */
223 state->pending_config = true;
224 }
225
mtk_crtc_ddp_clk_enable(struct mtk_crtc * mtk_crtc)226 static int mtk_crtc_ddp_clk_enable(struct mtk_crtc *mtk_crtc)
227 {
228 struct drm_device *dev = mtk_crtc->base.dev;
229 int ret;
230 int i;
231
232 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
233 ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]);
234 if (ret) {
235 drm_err(dev, "Failed to enable clock %d: %d\n", i, ret);
236 goto err;
237 }
238 }
239
240 return 0;
241 err:
242 while (--i >= 0)
243 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
244 return ret;
245 }
246
mtk_crtc_ddp_clk_disable(struct mtk_crtc * mtk_crtc)247 static void mtk_crtc_ddp_clk_disable(struct mtk_crtc *mtk_crtc)
248 {
249 int i;
250
251 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
252 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
253 }
254
255 static
mtk_ddp_comp_for_plane(struct drm_crtc * crtc,struct drm_plane * plane,unsigned int * local_layer)256 struct mtk_ddp_comp *mtk_ddp_comp_for_plane(struct drm_crtc *crtc,
257 struct drm_plane *plane,
258 unsigned int *local_layer)
259 {
260 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
261 struct mtk_ddp_comp *comp;
262 int i, count = 0;
263 unsigned int local_index = plane - mtk_crtc->planes;
264
265 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
266 comp = mtk_crtc->ddp_comp[i];
267 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) {
268 *local_layer = local_index - count;
269 return comp;
270 }
271 count += mtk_ddp_comp_layer_nr(comp);
272 }
273
274 WARN(1, "Failed to find component for plane %d\n", plane->index);
275 return NULL;
276 }
277
278 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
ddp_cmdq_cb(struct mbox_client * cl,void * mssg)279 static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg)
280 {
281 struct cmdq_cb_data *data = mssg;
282 struct cmdq_client *cmdq_cl = container_of(cl, struct cmdq_client, client);
283 struct mtk_crtc *mtk_crtc = container_of(cmdq_cl, struct mtk_crtc, cmdq_client);
284 struct mtk_crtc_state *state;
285 unsigned int i;
286 unsigned long flags;
287
288 /* release GCE HW usage and start autosuspend */
289 pm_runtime_mark_last_busy(cmdq_cl->chan->mbox->dev);
290 pm_runtime_put_autosuspend(cmdq_cl->chan->mbox->dev);
291
292 if (data->sta < 0)
293 return;
294
295 state = to_mtk_crtc_state(mtk_crtc->base.state);
296
297 spin_lock_irqsave(&mtk_crtc->config_lock, flags);
298 if (mtk_crtc->config_updating)
299 goto ddp_cmdq_cb_out;
300
301 state->pending_config = false;
302
303 if (mtk_crtc->pending_planes) {
304 for (i = 0; i < mtk_crtc->layer_nr; i++) {
305 struct drm_plane *plane = &mtk_crtc->planes[i];
306 struct mtk_plane_state *plane_state;
307
308 plane_state = to_mtk_plane_state(plane->state);
309
310 plane_state->pending.config = false;
311 }
312 mtk_crtc->pending_planes = false;
313 }
314
315 if (mtk_crtc->pending_async_planes) {
316 for (i = 0; i < mtk_crtc->layer_nr; i++) {
317 struct drm_plane *plane = &mtk_crtc->planes[i];
318 struct mtk_plane_state *plane_state;
319
320 plane_state = to_mtk_plane_state(plane->state);
321
322 plane_state->pending.async_config = false;
323 }
324 mtk_crtc->pending_async_planes = false;
325 }
326
327 ddp_cmdq_cb_out:
328
329 if (mtk_crtc->pending_needs_vblank) {
330 mtk_crtc_finish_page_flip(mtk_crtc);
331 mtk_crtc->pending_needs_vblank = false;
332 }
333
334 spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
335
336 mtk_crtc->cmdq_vblank_cnt = 0;
337 wake_up(&mtk_crtc->cb_blocking_queue);
338 }
339 #endif
340
mtk_crtc_ddp_hw_init(struct mtk_crtc * mtk_crtc)341 static int mtk_crtc_ddp_hw_init(struct mtk_crtc *mtk_crtc)
342 {
343 struct drm_crtc *crtc = &mtk_crtc->base;
344 struct drm_connector *connector;
345 struct drm_encoder *encoder;
346 struct drm_connector_list_iter conn_iter;
347 struct drm_device *dev = mtk_crtc->base.dev;
348 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
349 int ret;
350 int i;
351
352 if (WARN_ON(!crtc->state))
353 return -EINVAL;
354
355 width = crtc->state->adjusted_mode.hdisplay;
356 height = crtc->state->adjusted_mode.vdisplay;
357 vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode);
358
359 drm_for_each_encoder(encoder, crtc->dev) {
360 if (encoder->crtc != crtc)
361 continue;
362
363 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
364 drm_for_each_connector_iter(connector, &conn_iter) {
365 if (connector->encoder != encoder)
366 continue;
367 if (connector->display_info.bpc != 0 &&
368 bpc > connector->display_info.bpc)
369 bpc = connector->display_info.bpc;
370 }
371 drm_connector_list_iter_end(&conn_iter);
372 }
373
374 ret = pm_runtime_resume_and_get(crtc->dev->dev);
375 if (ret < 0) {
376 drm_err(dev, "Failed to enable power domain: %d\n", ret);
377 return ret;
378 }
379
380 ret = mtk_mutex_prepare(mtk_crtc->mutex);
381 if (ret < 0) {
382 drm_err(dev, "Failed to enable mutex clock: %d\n", ret);
383 goto err_pm_runtime_put;
384 }
385
386 ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
387 if (ret < 0) {
388 drm_err(dev, "Failed to enable component clocks: %d\n", ret);
389 goto err_mutex_unprepare;
390 }
391
392 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
393 if (!mtk_ddp_comp_connect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev,
394 mtk_crtc->ddp_comp[i + 1]->id))
395 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
396 mtk_crtc->ddp_comp[i]->id,
397 mtk_crtc->ddp_comp[i + 1]->id);
398 if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
399 mtk_mutex_add_comp(mtk_crtc->mutex,
400 mtk_crtc->ddp_comp[i]->id);
401 }
402 if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
403 mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
404 mtk_mutex_enable(mtk_crtc->mutex);
405
406 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
407 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
408
409 if (i == 1)
410 mtk_ddp_comp_bgclr_in_on(comp);
411
412 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL);
413 mtk_ddp_comp_start(comp);
414 }
415
416 /* Initially configure all planes */
417 for (i = 0; i < mtk_crtc->layer_nr; i++) {
418 struct drm_plane *plane = &mtk_crtc->planes[i];
419 struct mtk_plane_state *plane_state;
420 struct mtk_ddp_comp *comp;
421 unsigned int local_layer;
422
423 plane_state = to_mtk_plane_state(plane->state);
424
425 /* should not enable layer before crtc enabled */
426 plane_state->pending.enable = false;
427 comp = mtk_ddp_comp_for_plane(crtc, plane, &local_layer);
428 if (comp)
429 mtk_ddp_comp_layer_config(comp, local_layer,
430 plane_state, NULL);
431 }
432
433 return 0;
434
435 err_mutex_unprepare:
436 mtk_mutex_unprepare(mtk_crtc->mutex);
437 err_pm_runtime_put:
438 pm_runtime_put(crtc->dev->dev);
439 return ret;
440 }
441
mtk_crtc_ddp_hw_fini(struct mtk_crtc * mtk_crtc)442 static void mtk_crtc_ddp_hw_fini(struct mtk_crtc *mtk_crtc)
443 {
444 struct drm_device *drm = mtk_crtc->base.dev;
445 struct drm_crtc *crtc = &mtk_crtc->base;
446 unsigned long flags;
447 int i;
448
449 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
450 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
451 if (i == 1)
452 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]);
453 }
454
455 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
456 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
457 mtk_mutex_remove_comp(mtk_crtc->mutex,
458 mtk_crtc->ddp_comp[i]->id);
459 mtk_mutex_disable(mtk_crtc->mutex);
460 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
461 if (!mtk_ddp_comp_disconnect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev,
462 mtk_crtc->ddp_comp[i + 1]->id))
463 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
464 mtk_crtc->ddp_comp[i]->id,
465 mtk_crtc->ddp_comp[i + 1]->id);
466 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
467 mtk_mutex_remove_comp(mtk_crtc->mutex,
468 mtk_crtc->ddp_comp[i]->id);
469 }
470 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
471 mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
472 mtk_crtc_ddp_clk_disable(mtk_crtc);
473 mtk_mutex_unprepare(mtk_crtc->mutex);
474
475 pm_runtime_put(drm->dev);
476
477 if (crtc->state->event && !crtc->state->active) {
478 spin_lock_irqsave(&crtc->dev->event_lock, flags);
479 drm_crtc_send_vblank_event(crtc, crtc->state->event);
480 crtc->state->event = NULL;
481 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
482 }
483 }
484
mtk_crtc_ddp_config(struct drm_crtc * crtc,struct cmdq_pkt * cmdq_handle)485 static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
486 struct cmdq_pkt *cmdq_handle)
487 {
488 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
489 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
490 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
491 unsigned int i;
492 unsigned int local_layer;
493
494 /*
495 * TODO: instead of updating the registers here, we should prepare
496 * working registers in atomic_commit and let the hardware command
497 * queue update module registers on vblank.
498 */
499 if (state->pending_config) {
500 mtk_ddp_comp_config(comp, state->pending_width,
501 state->pending_height,
502 state->pending_vrefresh, 0,
503 cmdq_handle);
504
505 if (!cmdq_handle)
506 state->pending_config = false;
507 }
508
509 if (mtk_crtc->pending_planes) {
510 for (i = 0; i < mtk_crtc->layer_nr; i++) {
511 struct drm_plane *plane = &mtk_crtc->planes[i];
512 struct mtk_plane_state *plane_state;
513
514 plane_state = to_mtk_plane_state(plane->state);
515
516 if (!plane_state->pending.config)
517 continue;
518
519 comp = mtk_ddp_comp_for_plane(crtc, plane, &local_layer);
520
521 if (comp)
522 mtk_ddp_comp_layer_config(comp, local_layer,
523 plane_state,
524 cmdq_handle);
525 if (!cmdq_handle)
526 plane_state->pending.config = false;
527 }
528
529 if (!cmdq_handle)
530 mtk_crtc->pending_planes = false;
531 }
532
533 if (mtk_crtc->pending_async_planes) {
534 for (i = 0; i < mtk_crtc->layer_nr; i++) {
535 struct drm_plane *plane = &mtk_crtc->planes[i];
536 struct mtk_plane_state *plane_state;
537
538 plane_state = to_mtk_plane_state(plane->state);
539
540 if (!plane_state->pending.async_config)
541 continue;
542
543 comp = mtk_ddp_comp_for_plane(crtc, plane, &local_layer);
544
545 if (comp)
546 mtk_ddp_comp_layer_config(comp, local_layer,
547 plane_state,
548 cmdq_handle);
549 if (!cmdq_handle)
550 plane_state->pending.async_config = false;
551 }
552
553 if (!cmdq_handle)
554 mtk_crtc->pending_async_planes = false;
555 }
556 }
557
mtk_crtc_update_config(struct mtk_crtc * mtk_crtc,bool needs_vblank)558 static void mtk_crtc_update_config(struct mtk_crtc *mtk_crtc, bool needs_vblank)
559 {
560 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
561 struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle;
562 #endif
563 struct drm_crtc *crtc = &mtk_crtc->base;
564 struct mtk_drm_private *priv = crtc->dev->dev_private;
565 unsigned int pending_planes = 0, pending_async_planes = 0;
566 int i;
567 unsigned long flags;
568
569 mutex_lock(&mtk_crtc->hw_lock);
570
571 spin_lock_irqsave(&mtk_crtc->config_lock, flags);
572 mtk_crtc->config_updating = true;
573 spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
574
575 if (needs_vblank)
576 mtk_crtc->pending_needs_vblank = true;
577
578 for (i = 0; i < mtk_crtc->layer_nr; i++) {
579 struct drm_plane *plane = &mtk_crtc->planes[i];
580 struct mtk_plane_state *plane_state;
581
582 plane_state = to_mtk_plane_state(plane->state);
583 if (plane_state->pending.dirty) {
584 plane_state->pending.config = true;
585 plane_state->pending.dirty = false;
586 pending_planes |= BIT(i);
587 } else if (plane_state->pending.async_dirty) {
588 plane_state->pending.async_config = true;
589 plane_state->pending.async_dirty = false;
590 pending_async_planes |= BIT(i);
591 }
592 }
593 if (pending_planes)
594 mtk_crtc->pending_planes = true;
595 if (pending_async_planes)
596 mtk_crtc->pending_async_planes = true;
597
598 if (priv->data->shadow_register) {
599 mtk_mutex_acquire(mtk_crtc->mutex);
600 mtk_crtc_ddp_config(crtc, NULL);
601 mtk_mutex_release(mtk_crtc->mutex);
602 }
603 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
604 if (mtk_crtc->cmdq_client.chan) {
605 mbox_flush(mtk_crtc->cmdq_client.chan, 2000);
606 cmdq_handle->cmd_buf_size = 0;
607 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
608 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
609 mtk_crtc_ddp_config(crtc, cmdq_handle);
610 cmdq_pkt_eoc(cmdq_handle);
611 dma_sync_single_for_device(mtk_crtc->cmdq_client.chan->mbox->dev,
612 cmdq_handle->pa_base,
613 cmdq_handle->cmd_buf_size,
614 DMA_TO_DEVICE);
615 /*
616 * CMDQ command should execute in next 3 vblank.
617 * One vblank interrupt before send message (occasionally)
618 * and one vblank interrupt after cmdq done,
619 * so it's timeout after 3 vblank interrupt.
620 * If it fail to execute in next 3 vblank, timeout happen.
621 */
622 mtk_crtc->cmdq_vblank_cnt = 3;
623
624 spin_lock_irqsave(&mtk_crtc->config_lock, flags);
625 mtk_crtc->config_updating = false;
626 spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
627
628 if (pm_runtime_resume_and_get(mtk_crtc->cmdq_client.chan->mbox->dev) < 0)
629 goto update_config_out;
630
631 mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle);
632 mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0);
633 goto update_config_out;
634 }
635 #endif
636 spin_lock_irqsave(&mtk_crtc->config_lock, flags);
637 mtk_crtc->config_updating = false;
638 spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
639
640 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
641 update_config_out:
642 #endif
643 mutex_unlock(&mtk_crtc->hw_lock);
644 }
645
mtk_crtc_ddp_irq(void * data)646 static void mtk_crtc_ddp_irq(void *data)
647 {
648 struct drm_crtc *crtc = data;
649 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
650 struct mtk_drm_private *priv = crtc->dev->dev_private;
651
652 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
653 struct drm_device *dev = mtk_crtc->base.dev;
654 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client.chan)
655 mtk_crtc_ddp_config(crtc, NULL);
656 else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0)
657 drm_err(dev, "mtk_crtc %d CMDQ execute command timeout!\n",
658 drm_crtc_index(&mtk_crtc->base));
659 #else
660 if (!priv->data->shadow_register)
661 mtk_crtc_ddp_config(crtc, NULL);
662 #endif
663 mtk_drm_finish_page_flip(mtk_crtc);
664 }
665
mtk_crtc_enable_vblank(struct drm_crtc * crtc)666 static int mtk_crtc_enable_vblank(struct drm_crtc *crtc)
667 {
668 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
669 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
670
671 mtk_ddp_comp_enable_vblank(comp);
672
673 return 0;
674 }
675
mtk_crtc_disable_vblank(struct drm_crtc * crtc)676 static void mtk_crtc_disable_vblank(struct drm_crtc *crtc)
677 {
678 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
679 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
680
681 mtk_ddp_comp_disable_vblank(comp);
682 }
683
mtk_crtc_update_output(struct drm_crtc * crtc,struct drm_atomic_state * state)684 static void mtk_crtc_update_output(struct drm_crtc *crtc,
685 struct drm_atomic_state *state)
686 {
687 int crtc_index = drm_crtc_index(crtc);
688 int i;
689 struct device *dev;
690 struct drm_crtc_state *crtc_state = state->crtcs[crtc_index].new_state;
691 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
692 struct mtk_drm_private *priv;
693 unsigned int encoder_mask = crtc_state->encoder_mask;
694
695 if (!crtc_state->connectors_changed)
696 return;
697
698 if (!mtk_crtc->num_conn_routes)
699 return;
700
701 priv = ((struct mtk_drm_private *)crtc->dev->dev_private)->all_drm_private[crtc_index];
702 dev = priv->dev;
703
704 dev_dbg(dev, "connector change:%d, encoder mask:0x%x for crtc:%d\n",
705 crtc_state->connectors_changed, encoder_mask, crtc_index);
706
707 for (i = 0; i < mtk_crtc->num_conn_routes; i++) {
708 unsigned int comp_id = mtk_crtc->conn_routes[i].route_ddp;
709 struct mtk_ddp_comp *comp = &priv->ddp_comp[comp_id];
710
711 if (comp->encoder_index >= 0 &&
712 (encoder_mask & BIT(comp->encoder_index))) {
713 mtk_crtc->ddp_comp[mtk_crtc->ddp_comp_nr - 1] = comp;
714 dev_dbg(dev, "Add comp_id: %d at path index %d\n",
715 comp->id, mtk_crtc->ddp_comp_nr - 1);
716 break;
717 }
718 }
719 }
720
mtk_crtc_plane_check(struct drm_crtc * crtc,struct drm_plane * plane,struct mtk_plane_state * state)721 int mtk_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
722 struct mtk_plane_state *state)
723 {
724 unsigned int local_layer;
725 struct mtk_ddp_comp *comp;
726
727 comp = mtk_ddp_comp_for_plane(crtc, plane, &local_layer);
728 if (comp)
729 return mtk_ddp_comp_layer_check(comp, local_layer, state);
730 return 0;
731 }
732
mtk_crtc_plane_disable(struct drm_crtc * crtc,struct drm_plane * plane)733 void mtk_crtc_plane_disable(struct drm_crtc *crtc, struct drm_plane *plane)
734 {
735 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
736 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
737 struct mtk_plane_state *plane_state = to_mtk_plane_state(plane->state);
738 int i;
739
740 /* no need to wait for disabling the plane by CPU */
741 if (!mtk_crtc->cmdq_client.chan)
742 return;
743
744 if (!mtk_crtc->enabled)
745 return;
746
747 /* set pending plane state to disabled */
748 for (i = 0; i < mtk_crtc->layer_nr; i++) {
749 struct drm_plane *mtk_plane = &mtk_crtc->planes[i];
750 struct mtk_plane_state *mtk_plane_state = to_mtk_plane_state(mtk_plane->state);
751
752 if (mtk_plane->index == plane->index) {
753 memcpy(mtk_plane_state, plane_state, sizeof(*plane_state));
754 break;
755 }
756 }
757 mtk_crtc_update_config(mtk_crtc, false);
758
759 /* wait for planes to be disabled by CMDQ */
760 wait_event_timeout(mtk_crtc->cb_blocking_queue,
761 mtk_crtc->cmdq_vblank_cnt == 0,
762 msecs_to_jiffies(500));
763 #endif
764 }
765
mtk_crtc_async_update(struct drm_crtc * crtc,struct drm_plane * plane,struct drm_atomic_state * state)766 void mtk_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
767 struct drm_atomic_state *state)
768 {
769 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
770
771 if (!mtk_crtc->enabled)
772 return;
773
774 mtk_crtc_update_config(mtk_crtc, false);
775 }
776
mtk_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)777 static void mtk_crtc_atomic_enable(struct drm_crtc *crtc,
778 struct drm_atomic_state *state)
779 {
780 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
781 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
782 struct drm_device *dev = mtk_crtc->base.dev;
783 int ret;
784
785 drm_dbg_driver(dev, "%s %d\n", __func__, crtc->base.id);
786
787 ret = mtk_ddp_comp_power_on(comp);
788 if (ret < 0) {
789 DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n", ret);
790 return;
791 }
792
793 mtk_crtc_update_output(crtc, state);
794
795 ret = mtk_crtc_ddp_hw_init(mtk_crtc);
796 if (ret) {
797 mtk_ddp_comp_power_off(comp);
798 return;
799 }
800
801 drm_crtc_vblank_on(crtc);
802 mtk_crtc->enabled = true;
803 }
804
mtk_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_atomic_state * state)805 static void mtk_crtc_atomic_disable(struct drm_crtc *crtc,
806 struct drm_atomic_state *state)
807 {
808 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
809 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
810 struct drm_device *dev = mtk_crtc->base.dev;
811 int i;
812
813 drm_dbg_driver(dev, "%s %d\n", __func__, crtc->base.id);
814 if (!mtk_crtc->enabled)
815 return;
816
817 /* Set all pending plane state to disabled */
818 for (i = 0; i < mtk_crtc->layer_nr; i++) {
819 struct drm_plane *plane = &mtk_crtc->planes[i];
820 struct mtk_plane_state *plane_state;
821
822 plane_state = to_mtk_plane_state(plane->state);
823 plane_state->pending.enable = false;
824 plane_state->pending.config = true;
825 }
826 mtk_crtc->pending_planes = true;
827
828 mtk_crtc_update_config(mtk_crtc, false);
829 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
830 /* Wait for planes to be disabled by cmdq */
831 if (mtk_crtc->cmdq_client.chan)
832 wait_event_timeout(mtk_crtc->cb_blocking_queue,
833 mtk_crtc->cmdq_vblank_cnt == 0,
834 msecs_to_jiffies(500));
835 #endif
836 /* Wait for planes to be disabled */
837 drm_crtc_wait_one_vblank(crtc);
838
839 drm_crtc_vblank_off(crtc);
840 mtk_crtc_ddp_hw_fini(mtk_crtc);
841 mtk_ddp_comp_power_off(comp);
842
843 mtk_crtc->enabled = false;
844 }
845
mtk_crtc_atomic_begin(struct drm_crtc * crtc,struct drm_atomic_state * state)846 static void mtk_crtc_atomic_begin(struct drm_crtc *crtc,
847 struct drm_atomic_state *state)
848 {
849 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
850 crtc);
851 struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state);
852 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
853 struct drm_device *dev = mtk_crtc->base.dev;
854 unsigned long flags;
855
856 if (mtk_crtc->event && mtk_crtc_state->base.event)
857 drm_err(dev, "new event while there is still a pending event\n");
858
859 if (mtk_crtc_state->base.event) {
860 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc);
861 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
862
863 spin_lock_irqsave(&crtc->dev->event_lock, flags);
864 mtk_crtc->event = mtk_crtc_state->base.event;
865 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
866
867 mtk_crtc_state->base.event = NULL;
868 }
869 }
870
mtk_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_atomic_state * state)871 static void mtk_crtc_atomic_flush(struct drm_crtc *crtc,
872 struct drm_atomic_state *state)
873 {
874 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
875 int i;
876
877 if (crtc->state->color_mgmt_changed)
878 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
879 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
880 mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
881 }
882 mtk_crtc_update_config(mtk_crtc, !!mtk_crtc->event);
883 }
884
885 static const struct drm_crtc_funcs mtk_crtc_funcs = {
886 .set_config = drm_atomic_helper_set_config,
887 .page_flip = drm_atomic_helper_page_flip,
888 .destroy = mtk_crtc_destroy,
889 .reset = mtk_crtc_reset,
890 .atomic_duplicate_state = mtk_crtc_duplicate_state,
891 .atomic_destroy_state = mtk_crtc_destroy_state,
892 .enable_vblank = mtk_crtc_enable_vblank,
893 .disable_vblank = mtk_crtc_disable_vblank,
894 };
895
896 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
897 .mode_fixup = mtk_crtc_mode_fixup,
898 .mode_set_nofb = mtk_crtc_mode_set_nofb,
899 .mode_valid = mtk_crtc_mode_valid,
900 .atomic_begin = mtk_crtc_atomic_begin,
901 .atomic_flush = mtk_crtc_atomic_flush,
902 .atomic_enable = mtk_crtc_atomic_enable,
903 .atomic_disable = mtk_crtc_atomic_disable,
904 };
905
mtk_crtc_init(struct drm_device * drm,struct mtk_crtc * mtk_crtc,unsigned int pipe)906 static int mtk_crtc_init(struct drm_device *drm, struct mtk_crtc *mtk_crtc,
907 unsigned int pipe)
908 {
909 struct drm_plane *primary = NULL;
910 struct drm_plane *cursor = NULL;
911 int i, ret;
912
913 for (i = 0; i < mtk_crtc->layer_nr; i++) {
914 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY)
915 primary = &mtk_crtc->planes[i];
916 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR)
917 cursor = &mtk_crtc->planes[i];
918 }
919
920 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
921 &mtk_crtc_funcs, NULL);
922 if (ret)
923 goto err_cleanup_crtc;
924
925 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs);
926
927 return 0;
928
929 err_cleanup_crtc:
930 drm_crtc_cleanup(&mtk_crtc->base);
931 return ret;
932 }
933
mtk_crtc_num_comp_planes(struct mtk_crtc * mtk_crtc,int comp_idx)934 static int mtk_crtc_num_comp_planes(struct mtk_crtc *mtk_crtc, int comp_idx)
935 {
936 struct mtk_ddp_comp *comp;
937
938 if (comp_idx > 1)
939 return 0;
940
941 comp = mtk_crtc->ddp_comp[comp_idx];
942 if (!comp->funcs)
943 return 0;
944
945 if (comp_idx == 1 && !comp->funcs->bgclr_in_on)
946 return 0;
947
948 return mtk_ddp_comp_layer_nr(comp);
949 }
950
951 static inline
mtk_crtc_plane_type(unsigned int plane_idx,unsigned int num_planes)952 enum drm_plane_type mtk_crtc_plane_type(unsigned int plane_idx,
953 unsigned int num_planes)
954 {
955 if (plane_idx == 0)
956 return DRM_PLANE_TYPE_PRIMARY;
957 else if (plane_idx == (num_planes - 1))
958 return DRM_PLANE_TYPE_CURSOR;
959 else
960 return DRM_PLANE_TYPE_OVERLAY;
961
962 }
963
mtk_crtc_init_comp_planes(struct drm_device * drm_dev,struct mtk_crtc * mtk_crtc,int comp_idx,int pipe)964 static int mtk_crtc_init_comp_planes(struct drm_device *drm_dev,
965 struct mtk_crtc *mtk_crtc,
966 int comp_idx, int pipe)
967 {
968 int num_planes = mtk_crtc_num_comp_planes(mtk_crtc, comp_idx);
969 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx];
970 int i, ret;
971
972 for (i = 0; i < num_planes; i++) {
973 ret = mtk_plane_init(drm_dev,
974 &mtk_crtc->planes[mtk_crtc->layer_nr],
975 BIT(pipe),
976 mtk_crtc_plane_type(mtk_crtc->layer_nr, num_planes),
977 mtk_ddp_comp_supported_rotations(comp),
978 mtk_ddp_comp_get_blend_modes(comp),
979 mtk_ddp_comp_get_formats(comp),
980 mtk_ddp_comp_get_num_formats(comp),
981 mtk_ddp_comp_is_afbc_supported(comp), i);
982 if (ret)
983 return ret;
984
985 mtk_crtc->layer_nr++;
986 }
987 return 0;
988 }
989
mtk_crtc_dma_dev_get(struct drm_crtc * crtc)990 struct device *mtk_crtc_dma_dev_get(struct drm_crtc *crtc)
991 {
992 struct mtk_crtc *mtk_crtc = NULL;
993
994 if (!crtc)
995 return NULL;
996
997 mtk_crtc = to_mtk_crtc(crtc);
998 if (!mtk_crtc)
999 return NULL;
1000
1001 return mtk_crtc->dma_dev;
1002 }
1003
mtk_crtc_create(struct drm_device * drm_dev,const unsigned int * path,unsigned int path_len,int priv_data_index,const struct mtk_drm_route * conn_routes,unsigned int num_conn_routes)1004 int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
1005 unsigned int path_len, int priv_data_index,
1006 const struct mtk_drm_route *conn_routes,
1007 unsigned int num_conn_routes)
1008 {
1009 struct mtk_drm_private *priv = drm_dev->dev_private;
1010 struct device *dev = drm_dev->dev;
1011 struct mtk_crtc *mtk_crtc;
1012 unsigned int num_comp_planes = 0;
1013 int ret;
1014 int i;
1015 bool has_ctm = false;
1016 uint gamma_lut_size = 0;
1017 struct drm_crtc *tmp;
1018 int crtc_i = 0;
1019
1020 if (!path)
1021 return 0;
1022
1023 priv = priv->all_drm_private[priv_data_index];
1024
1025 drm_for_each_crtc(tmp, drm_dev)
1026 crtc_i++;
1027
1028 for (i = 0; i < path_len; i++) {
1029 enum mtk_ddp_comp_id comp_id = path[i];
1030 struct device_node *node;
1031 struct mtk_ddp_comp *comp;
1032
1033 node = priv->comp_node[comp_id];
1034 comp = &priv->ddp_comp[comp_id];
1035
1036 /* Not all drm components have a DTS device node, such as ovl_adaptor,
1037 * which is the drm bring up sub driver
1038 */
1039 if (!node && comp_id != DDP_COMPONENT_DRM_OVL_ADAPTOR) {
1040 dev_info(dev,
1041 "Not creating crtc %d because component %d is disabled or missing\n",
1042 crtc_i, comp_id);
1043 return 0;
1044 }
1045
1046 if (!comp->dev) {
1047 dev_err(dev, "Component %pOF not initialized\n", node);
1048 return -ENODEV;
1049 }
1050 }
1051
1052 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL);
1053 if (!mtk_crtc)
1054 return -ENOMEM;
1055
1056 mtk_crtc->mmsys_dev = priv->mmsys_dev;
1057 mtk_crtc->ddp_comp_nr = path_len;
1058 mtk_crtc->ddp_comp = devm_kcalloc(dev,
1059 mtk_crtc->ddp_comp_nr + (conn_routes ? 1 : 0),
1060 sizeof(*mtk_crtc->ddp_comp),
1061 GFP_KERNEL);
1062 if (!mtk_crtc->ddp_comp)
1063 return -ENOMEM;
1064
1065 mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev);
1066 if (IS_ERR(mtk_crtc->mutex)) {
1067 ret = PTR_ERR(mtk_crtc->mutex);
1068 dev_err(dev, "Failed to get mutex: %d\n", ret);
1069 return ret;
1070 }
1071
1072 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
1073 unsigned int comp_id = path[i];
1074 struct mtk_ddp_comp *comp;
1075
1076 comp = &priv->ddp_comp[comp_id];
1077 mtk_crtc->ddp_comp[i] = comp;
1078
1079 if (comp->funcs) {
1080 if (comp->funcs->gamma_set && comp->funcs->gamma_get_lut_size) {
1081 unsigned int lut_sz = mtk_ddp_gamma_get_lut_size(comp);
1082
1083 if (lut_sz)
1084 gamma_lut_size = lut_sz;
1085 }
1086
1087 if (comp->funcs->ctm_set)
1088 has_ctm = true;
1089 }
1090
1091 mtk_ddp_comp_register_vblank_cb(comp, mtk_crtc_ddp_irq,
1092 &mtk_crtc->base);
1093 }
1094
1095 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
1096 num_comp_planes += mtk_crtc_num_comp_planes(mtk_crtc, i);
1097
1098 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes,
1099 sizeof(struct drm_plane), GFP_KERNEL);
1100 if (!mtk_crtc->planes)
1101 return -ENOMEM;
1102
1103 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
1104 ret = mtk_crtc_init_comp_planes(drm_dev, mtk_crtc, i, crtc_i);
1105 if (ret)
1106 return ret;
1107 }
1108
1109 /*
1110 * Default to use the first component as the dma dev.
1111 * In the case of ovl_adaptor sub driver, it needs to use the
1112 * dma_dev_get function to get representative dma dev.
1113 */
1114 mtk_crtc->dma_dev = mtk_ddp_comp_dma_dev_get(&priv->ddp_comp[path[0]]);
1115
1116 ret = mtk_crtc_init(drm_dev, mtk_crtc, crtc_i);
1117 if (ret < 0)
1118 return ret;
1119
1120 if (gamma_lut_size)
1121 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
1122 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
1123 mutex_init(&mtk_crtc->hw_lock);
1124 spin_lock_init(&mtk_crtc->config_lock);
1125
1126 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
1127 i = priv->mbox_index++;
1128 mtk_crtc->cmdq_client.client.dev = mtk_crtc->mmsys_dev;
1129 mtk_crtc->cmdq_client.client.tx_block = false;
1130 mtk_crtc->cmdq_client.client.knows_txdone = true;
1131 mtk_crtc->cmdq_client.client.rx_callback = ddp_cmdq_cb;
1132 mtk_crtc->cmdq_client.chan =
1133 mbox_request_channel(&mtk_crtc->cmdq_client.client, i);
1134 if (IS_ERR(mtk_crtc->cmdq_client.chan)) {
1135 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
1136 drm_crtc_index(&mtk_crtc->base));
1137 mtk_crtc->cmdq_client.chan = NULL;
1138 }
1139
1140 if (mtk_crtc->cmdq_client.chan) {
1141 ret = of_property_read_u32_index(priv->mutex_node,
1142 "mediatek,gce-events",
1143 i,
1144 &mtk_crtc->cmdq_event);
1145 if (ret) {
1146 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
1147 drm_crtc_index(&mtk_crtc->base));
1148 mbox_free_channel(mtk_crtc->cmdq_client.chan);
1149 mtk_crtc->cmdq_client.chan = NULL;
1150 } else {
1151 ret = cmdq_pkt_create(&mtk_crtc->cmdq_client,
1152 &mtk_crtc->cmdq_handle,
1153 PAGE_SIZE);
1154 if (ret) {
1155 dev_dbg(dev, "mtk_crtc %d failed to create cmdq packet\n",
1156 drm_crtc_index(&mtk_crtc->base));
1157 mbox_free_channel(mtk_crtc->cmdq_client.chan);
1158 mtk_crtc->cmdq_client.chan = NULL;
1159 }
1160 }
1161
1162 /* for sending blocking cmd in crtc disable */
1163 init_waitqueue_head(&mtk_crtc->cb_blocking_queue);
1164 }
1165 #endif
1166
1167 if (conn_routes) {
1168 for (i = 0; i < num_conn_routes; i++) {
1169 unsigned int comp_id = conn_routes[i].route_ddp;
1170 struct device_node *node = priv->comp_node[comp_id];
1171 struct mtk_ddp_comp *comp = &priv->ddp_comp[comp_id];
1172
1173 if (!comp->dev) {
1174 dev_dbg(dev, "comp_id:%d, Component %pOF not initialized\n",
1175 comp_id, node);
1176 /* mark encoder_index to -1, if route comp device is not enabled */
1177 comp->encoder_index = -1;
1178 continue;
1179 }
1180
1181 mtk_ddp_comp_encoder_index_set(&priv->ddp_comp[comp_id]);
1182 }
1183
1184 mtk_crtc->num_conn_routes = num_conn_routes;
1185 mtk_crtc->conn_routes = conn_routes;
1186
1187 /* increase ddp_comp_nr at the end of mtk_crtc_create */
1188 mtk_crtc->ddp_comp_nr++;
1189 }
1190
1191 return 0;
1192 }
1193