1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/dma-mapping.h>
8 #include <linux/mailbox_controller.h>
9 #include <linux/of.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/soc/mediatek/mtk-cmdq.h>
12 #include <linux/soc/mediatek/mtk-mmsys.h>
13 #include <linux/soc/mediatek/mtk-mutex.h>
14
15 #include <asm/barrier.h>
16
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_probe_helper.h>
20 #include <drm/drm_vblank.h>
21
22 #include "mtk_crtc.h"
23 #include "mtk_ddp_comp.h"
24 #include "mtk_drm_drv.h"
25 #include "mtk_gem.h"
26 #include "mtk_plane.h"
27
28 /*
29 * struct mtk_crtc - MediaTek specific crtc structure.
30 * @base: crtc object.
31 * @enabled: records whether crtc_enable succeeded
32 * @planes: array of 4 drm_plane structures, one for each overlay plane
33 * @pending_planes: whether any plane has pending changes to be applied
34 * @mmsys_dev: pointer to the mmsys device for configuration registers
35 * @mutex: handle to one of the ten disp_mutex streams
36 * @ddp_comp_nr: number of components in ddp_comp
37 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
38 *
39 * TODO: Needs update: this header is missing a bunch of member descriptions.
40 */
41 struct mtk_crtc {
42 struct drm_crtc base;
43 bool enabled;
44
45 bool pending_needs_vblank;
46 struct drm_pending_vblank_event *event;
47
48 struct drm_plane *planes;
49 unsigned int layer_nr;
50 bool pending_planes;
51 bool pending_async_planes;
52
53 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
54 struct cmdq_client cmdq_client;
55 struct cmdq_pkt cmdq_handle;
56 u32 cmdq_event;
57 u32 cmdq_vblank_cnt;
58 wait_queue_head_t cb_blocking_queue;
59 #endif
60
61 struct device *mmsys_dev;
62 struct device *dma_dev;
63 struct mtk_mutex *mutex;
64 unsigned int ddp_comp_nr;
65 struct mtk_ddp_comp **ddp_comp;
66 unsigned int num_conn_routes;
67 const struct mtk_drm_route *conn_routes;
68
69 /* lock for display hardware access */
70 struct mutex hw_lock;
71 bool config_updating;
72 /* lock for config_updating to cmd buffer */
73 spinlock_t config_lock;
74 };
75
76 struct mtk_crtc_state {
77 struct drm_crtc_state base;
78
79 bool pending_config;
80 unsigned int pending_width;
81 unsigned int pending_height;
82 unsigned int pending_vrefresh;
83 };
84
to_mtk_crtc(struct drm_crtc * c)85 static inline struct mtk_crtc *to_mtk_crtc(struct drm_crtc *c)
86 {
87 return container_of(c, struct mtk_crtc, base);
88 }
89
to_mtk_crtc_state(struct drm_crtc_state * s)90 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s)
91 {
92 return container_of(s, struct mtk_crtc_state, base);
93 }
94
mtk_crtc_finish_page_flip(struct mtk_crtc * mtk_crtc)95 static void mtk_crtc_finish_page_flip(struct mtk_crtc *mtk_crtc)
96 {
97 struct drm_crtc *crtc = &mtk_crtc->base;
98 unsigned long flags;
99
100 if (mtk_crtc->event) {
101 spin_lock_irqsave(&crtc->dev->event_lock, flags);
102 drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
103 drm_crtc_vblank_put(crtc);
104 mtk_crtc->event = NULL;
105 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
106 }
107 }
108
mtk_drm_finish_page_flip(struct mtk_crtc * mtk_crtc)109 static void mtk_drm_finish_page_flip(struct mtk_crtc *mtk_crtc)
110 {
111 unsigned long flags;
112
113 drm_crtc_handle_vblank(&mtk_crtc->base);
114
115 spin_lock_irqsave(&mtk_crtc->config_lock, flags);
116 if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) {
117 mtk_crtc_finish_page_flip(mtk_crtc);
118 mtk_crtc->pending_needs_vblank = false;
119 }
120 spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
121 }
122
mtk_crtc_destroy(struct drm_crtc * crtc)123 static void mtk_crtc_destroy(struct drm_crtc *crtc)
124 {
125 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
126 int i;
127
128 mtk_mutex_put(mtk_crtc->mutex);
129 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
130 if (mtk_crtc->cmdq_client.chan) {
131 cmdq_pkt_destroy(&mtk_crtc->cmdq_client, &mtk_crtc->cmdq_handle);
132 mbox_free_channel(mtk_crtc->cmdq_client.chan);
133 mtk_crtc->cmdq_client.chan = NULL;
134 }
135 #endif
136
137 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
138 struct mtk_ddp_comp *comp;
139
140 comp = mtk_crtc->ddp_comp[i];
141 mtk_ddp_comp_unregister_vblank_cb(comp);
142 }
143
144 drm_crtc_cleanup(crtc);
145 }
146
mtk_crtc_reset(struct drm_crtc * crtc)147 static void mtk_crtc_reset(struct drm_crtc *crtc)
148 {
149 struct mtk_crtc_state *state;
150
151 if (crtc->state)
152 __drm_atomic_helper_crtc_destroy_state(crtc->state);
153
154 kfree(to_mtk_crtc_state(crtc->state));
155 crtc->state = NULL;
156
157 state = kzalloc(sizeof(*state), GFP_KERNEL);
158 if (state)
159 __drm_atomic_helper_crtc_reset(crtc, &state->base);
160 }
161
mtk_crtc_duplicate_state(struct drm_crtc * crtc)162 static struct drm_crtc_state *mtk_crtc_duplicate_state(struct drm_crtc *crtc)
163 {
164 struct mtk_crtc_state *state;
165
166 state = kmalloc(sizeof(*state), GFP_KERNEL);
167 if (!state)
168 return NULL;
169
170 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
171
172 WARN_ON(state->base.crtc != crtc);
173 state->base.crtc = crtc;
174 state->pending_config = false;
175
176 return &state->base;
177 }
178
mtk_crtc_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)179 static void mtk_crtc_destroy_state(struct drm_crtc *crtc,
180 struct drm_crtc_state *state)
181 {
182 __drm_atomic_helper_crtc_destroy_state(state);
183 kfree(to_mtk_crtc_state(state));
184 }
185
186 static enum drm_mode_status
mtk_crtc_mode_valid(struct drm_crtc * crtc,const struct drm_display_mode * mode)187 mtk_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
188 {
189 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
190 enum drm_mode_status status = MODE_OK;
191 int i;
192
193 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
194 status = mtk_ddp_comp_mode_valid(mtk_crtc->ddp_comp[i], mode);
195 if (status != MODE_OK)
196 break;
197 }
198 return status;
199 }
200
mtk_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)201 static bool mtk_crtc_mode_fixup(struct drm_crtc *crtc,
202 const struct drm_display_mode *mode,
203 struct drm_display_mode *adjusted_mode)
204 {
205 /* Nothing to do here, but this callback is mandatory. */
206 return true;
207 }
208
mtk_crtc_mode_set_nofb(struct drm_crtc * crtc)209 static void mtk_crtc_mode_set_nofb(struct drm_crtc *crtc)
210 {
211 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
212
213 state->pending_width = crtc->mode.hdisplay;
214 state->pending_height = crtc->mode.vdisplay;
215 state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode);
216 wmb(); /* Make sure the above parameters are set before update */
217 state->pending_config = true;
218 }
219
mtk_crtc_ddp_clk_enable(struct mtk_crtc * mtk_crtc)220 static int mtk_crtc_ddp_clk_enable(struct mtk_crtc *mtk_crtc)
221 {
222 int ret;
223 int i;
224
225 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
226 ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]);
227 if (ret) {
228 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
229 goto err;
230 }
231 }
232
233 return 0;
234 err:
235 while (--i >= 0)
236 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
237 return ret;
238 }
239
mtk_crtc_ddp_clk_disable(struct mtk_crtc * mtk_crtc)240 static void mtk_crtc_ddp_clk_disable(struct mtk_crtc *mtk_crtc)
241 {
242 int i;
243
244 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
245 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
246 }
247
248 static
mtk_ddp_comp_for_plane(struct drm_crtc * crtc,struct drm_plane * plane,unsigned int * local_layer)249 struct mtk_ddp_comp *mtk_ddp_comp_for_plane(struct drm_crtc *crtc,
250 struct drm_plane *plane,
251 unsigned int *local_layer)
252 {
253 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
254 struct mtk_ddp_comp *comp;
255 int i, count = 0;
256 unsigned int local_index = plane - mtk_crtc->planes;
257
258 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
259 comp = mtk_crtc->ddp_comp[i];
260 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) {
261 *local_layer = local_index - count;
262 return comp;
263 }
264 count += mtk_ddp_comp_layer_nr(comp);
265 }
266
267 WARN(1, "Failed to find component for plane %d\n", plane->index);
268 return NULL;
269 }
270
271 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
ddp_cmdq_cb(struct mbox_client * cl,void * mssg)272 static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg)
273 {
274 struct cmdq_cb_data *data = mssg;
275 struct cmdq_client *cmdq_cl = container_of(cl, struct cmdq_client, client);
276 struct mtk_crtc *mtk_crtc = container_of(cmdq_cl, struct mtk_crtc, cmdq_client);
277 struct mtk_crtc_state *state;
278 unsigned int i;
279 unsigned long flags;
280
281 if (data->sta < 0)
282 return;
283
284 state = to_mtk_crtc_state(mtk_crtc->base.state);
285
286 spin_lock_irqsave(&mtk_crtc->config_lock, flags);
287 if (mtk_crtc->config_updating) {
288 spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
289 goto ddp_cmdq_cb_out;
290 }
291
292 state->pending_config = false;
293
294 if (mtk_crtc->pending_planes) {
295 for (i = 0; i < mtk_crtc->layer_nr; i++) {
296 struct drm_plane *plane = &mtk_crtc->planes[i];
297 struct mtk_plane_state *plane_state;
298
299 plane_state = to_mtk_plane_state(plane->state);
300
301 plane_state->pending.config = false;
302 }
303 mtk_crtc->pending_planes = false;
304 }
305
306 if (mtk_crtc->pending_async_planes) {
307 for (i = 0; i < mtk_crtc->layer_nr; i++) {
308 struct drm_plane *plane = &mtk_crtc->planes[i];
309 struct mtk_plane_state *plane_state;
310
311 plane_state = to_mtk_plane_state(plane->state);
312
313 plane_state->pending.async_config = false;
314 }
315 mtk_crtc->pending_async_planes = false;
316 }
317
318 spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
319
320 ddp_cmdq_cb_out:
321
322 mtk_crtc->cmdq_vblank_cnt = 0;
323 wake_up(&mtk_crtc->cb_blocking_queue);
324 }
325 #endif
326
mtk_crtc_ddp_hw_init(struct mtk_crtc * mtk_crtc)327 static int mtk_crtc_ddp_hw_init(struct mtk_crtc *mtk_crtc)
328 {
329 struct drm_crtc *crtc = &mtk_crtc->base;
330 struct drm_connector *connector;
331 struct drm_encoder *encoder;
332 struct drm_connector_list_iter conn_iter;
333 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
334 int ret;
335 int i;
336
337 if (WARN_ON(!crtc->state))
338 return -EINVAL;
339
340 width = crtc->state->adjusted_mode.hdisplay;
341 height = crtc->state->adjusted_mode.vdisplay;
342 vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode);
343
344 drm_for_each_encoder(encoder, crtc->dev) {
345 if (encoder->crtc != crtc)
346 continue;
347
348 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
349 drm_for_each_connector_iter(connector, &conn_iter) {
350 if (connector->encoder != encoder)
351 continue;
352 if (connector->display_info.bpc != 0 &&
353 bpc > connector->display_info.bpc)
354 bpc = connector->display_info.bpc;
355 }
356 drm_connector_list_iter_end(&conn_iter);
357 }
358
359 ret = pm_runtime_resume_and_get(crtc->dev->dev);
360 if (ret < 0) {
361 DRM_ERROR("Failed to enable power domain: %d\n", ret);
362 return ret;
363 }
364
365 ret = mtk_mutex_prepare(mtk_crtc->mutex);
366 if (ret < 0) {
367 DRM_ERROR("Failed to enable mutex clock: %d\n", ret);
368 goto err_pm_runtime_put;
369 }
370
371 ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
372 if (ret < 0) {
373 DRM_ERROR("Failed to enable component clocks: %d\n", ret);
374 goto err_mutex_unprepare;
375 }
376
377 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
378 if (!mtk_ddp_comp_connect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev,
379 mtk_crtc->ddp_comp[i + 1]->id))
380 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
381 mtk_crtc->ddp_comp[i]->id,
382 mtk_crtc->ddp_comp[i + 1]->id);
383 if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
384 mtk_mutex_add_comp(mtk_crtc->mutex,
385 mtk_crtc->ddp_comp[i]->id);
386 }
387 if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
388 mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
389 mtk_mutex_enable(mtk_crtc->mutex);
390
391 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
392 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
393
394 if (i == 1)
395 mtk_ddp_comp_bgclr_in_on(comp);
396
397 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL);
398 mtk_ddp_comp_start(comp);
399 }
400
401 /* Initially configure all planes */
402 for (i = 0; i < mtk_crtc->layer_nr; i++) {
403 struct drm_plane *plane = &mtk_crtc->planes[i];
404 struct mtk_plane_state *plane_state;
405 struct mtk_ddp_comp *comp;
406 unsigned int local_layer;
407
408 plane_state = to_mtk_plane_state(plane->state);
409
410 /* should not enable layer before crtc enabled */
411 plane_state->pending.enable = false;
412 comp = mtk_ddp_comp_for_plane(crtc, plane, &local_layer);
413 if (comp)
414 mtk_ddp_comp_layer_config(comp, local_layer,
415 plane_state, NULL);
416 }
417
418 return 0;
419
420 err_mutex_unprepare:
421 mtk_mutex_unprepare(mtk_crtc->mutex);
422 err_pm_runtime_put:
423 pm_runtime_put(crtc->dev->dev);
424 return ret;
425 }
426
mtk_crtc_ddp_hw_fini(struct mtk_crtc * mtk_crtc)427 static void mtk_crtc_ddp_hw_fini(struct mtk_crtc *mtk_crtc)
428 {
429 struct drm_device *drm = mtk_crtc->base.dev;
430 struct drm_crtc *crtc = &mtk_crtc->base;
431 unsigned long flags;
432 int i;
433
434 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
435 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
436 if (i == 1)
437 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]);
438 }
439
440 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
441 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
442 mtk_mutex_remove_comp(mtk_crtc->mutex,
443 mtk_crtc->ddp_comp[i]->id);
444 mtk_mutex_disable(mtk_crtc->mutex);
445 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
446 if (!mtk_ddp_comp_disconnect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev,
447 mtk_crtc->ddp_comp[i + 1]->id))
448 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
449 mtk_crtc->ddp_comp[i]->id,
450 mtk_crtc->ddp_comp[i + 1]->id);
451 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
452 mtk_mutex_remove_comp(mtk_crtc->mutex,
453 mtk_crtc->ddp_comp[i]->id);
454 }
455 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
456 mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
457 mtk_crtc_ddp_clk_disable(mtk_crtc);
458 mtk_mutex_unprepare(mtk_crtc->mutex);
459
460 pm_runtime_put(drm->dev);
461
462 if (crtc->state->event && !crtc->state->active) {
463 spin_lock_irqsave(&crtc->dev->event_lock, flags);
464 drm_crtc_send_vblank_event(crtc, crtc->state->event);
465 crtc->state->event = NULL;
466 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
467 }
468 }
469
mtk_crtc_ddp_config(struct drm_crtc * crtc,struct cmdq_pkt * cmdq_handle)470 static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
471 struct cmdq_pkt *cmdq_handle)
472 {
473 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
474 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
475 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
476 unsigned int i;
477 unsigned int local_layer;
478
479 /*
480 * TODO: instead of updating the registers here, we should prepare
481 * working registers in atomic_commit and let the hardware command
482 * queue update module registers on vblank.
483 */
484 if (state->pending_config) {
485 mtk_ddp_comp_config(comp, state->pending_width,
486 state->pending_height,
487 state->pending_vrefresh, 0,
488 cmdq_handle);
489
490 if (!cmdq_handle)
491 state->pending_config = false;
492 }
493
494 if (mtk_crtc->pending_planes) {
495 for (i = 0; i < mtk_crtc->layer_nr; i++) {
496 struct drm_plane *plane = &mtk_crtc->planes[i];
497 struct mtk_plane_state *plane_state;
498
499 plane_state = to_mtk_plane_state(plane->state);
500
501 if (!plane_state->pending.config)
502 continue;
503
504 comp = mtk_ddp_comp_for_plane(crtc, plane, &local_layer);
505
506 if (comp)
507 mtk_ddp_comp_layer_config(comp, local_layer,
508 plane_state,
509 cmdq_handle);
510 if (!cmdq_handle)
511 plane_state->pending.config = false;
512 }
513
514 if (!cmdq_handle)
515 mtk_crtc->pending_planes = false;
516 }
517
518 if (mtk_crtc->pending_async_planes) {
519 for (i = 0; i < mtk_crtc->layer_nr; i++) {
520 struct drm_plane *plane = &mtk_crtc->planes[i];
521 struct mtk_plane_state *plane_state;
522
523 plane_state = to_mtk_plane_state(plane->state);
524
525 if (!plane_state->pending.async_config)
526 continue;
527
528 comp = mtk_ddp_comp_for_plane(crtc, plane, &local_layer);
529
530 if (comp)
531 mtk_ddp_comp_layer_config(comp, local_layer,
532 plane_state,
533 cmdq_handle);
534 if (!cmdq_handle)
535 plane_state->pending.async_config = false;
536 }
537
538 if (!cmdq_handle)
539 mtk_crtc->pending_async_planes = false;
540 }
541 }
542
mtk_crtc_update_config(struct mtk_crtc * mtk_crtc,bool needs_vblank)543 static void mtk_crtc_update_config(struct mtk_crtc *mtk_crtc, bool needs_vblank)
544 {
545 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
546 struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle;
547 #endif
548 struct drm_crtc *crtc = &mtk_crtc->base;
549 struct mtk_drm_private *priv = crtc->dev->dev_private;
550 unsigned int pending_planes = 0, pending_async_planes = 0;
551 int i;
552 unsigned long flags;
553
554 mutex_lock(&mtk_crtc->hw_lock);
555
556 spin_lock_irqsave(&mtk_crtc->config_lock, flags);
557 mtk_crtc->config_updating = true;
558 spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
559
560 if (needs_vblank)
561 mtk_crtc->pending_needs_vblank = true;
562
563 for (i = 0; i < mtk_crtc->layer_nr; i++) {
564 struct drm_plane *plane = &mtk_crtc->planes[i];
565 struct mtk_plane_state *plane_state;
566
567 plane_state = to_mtk_plane_state(plane->state);
568 if (plane_state->pending.dirty) {
569 plane_state->pending.config = true;
570 plane_state->pending.dirty = false;
571 pending_planes |= BIT(i);
572 } else if (plane_state->pending.async_dirty) {
573 plane_state->pending.async_config = true;
574 plane_state->pending.async_dirty = false;
575 pending_async_planes |= BIT(i);
576 }
577 }
578 if (pending_planes)
579 mtk_crtc->pending_planes = true;
580 if (pending_async_planes)
581 mtk_crtc->pending_async_planes = true;
582
583 if (priv->data->shadow_register) {
584 mtk_mutex_acquire(mtk_crtc->mutex);
585 mtk_crtc_ddp_config(crtc, NULL);
586 mtk_mutex_release(mtk_crtc->mutex);
587 }
588 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
589 if (mtk_crtc->cmdq_client.chan) {
590 mbox_flush(mtk_crtc->cmdq_client.chan, 2000);
591 cmdq_handle->cmd_buf_size = 0;
592 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
593 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
594 mtk_crtc_ddp_config(crtc, cmdq_handle);
595 cmdq_pkt_eoc(cmdq_handle);
596 dma_sync_single_for_device(mtk_crtc->cmdq_client.chan->mbox->dev,
597 cmdq_handle->pa_base,
598 cmdq_handle->cmd_buf_size,
599 DMA_TO_DEVICE);
600 /*
601 * CMDQ command should execute in next 3 vblank.
602 * One vblank interrupt before send message (occasionally)
603 * and one vblank interrupt after cmdq done,
604 * so it's timeout after 3 vblank interrupt.
605 * If it fail to execute in next 3 vblank, timeout happen.
606 */
607 mtk_crtc->cmdq_vblank_cnt = 3;
608
609 mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle);
610 mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0);
611 }
612 #endif
613 spin_lock_irqsave(&mtk_crtc->config_lock, flags);
614 mtk_crtc->config_updating = false;
615 spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
616
617 mutex_unlock(&mtk_crtc->hw_lock);
618 }
619
mtk_crtc_ddp_irq(void * data)620 static void mtk_crtc_ddp_irq(void *data)
621 {
622 struct drm_crtc *crtc = data;
623 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
624 struct mtk_drm_private *priv = crtc->dev->dev_private;
625
626 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
627 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client.chan)
628 mtk_crtc_ddp_config(crtc, NULL);
629 else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0)
630 DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n",
631 drm_crtc_index(&mtk_crtc->base));
632 #else
633 if (!priv->data->shadow_register)
634 mtk_crtc_ddp_config(crtc, NULL);
635 #endif
636 mtk_drm_finish_page_flip(mtk_crtc);
637 }
638
mtk_crtc_enable_vblank(struct drm_crtc * crtc)639 static int mtk_crtc_enable_vblank(struct drm_crtc *crtc)
640 {
641 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
642 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
643
644 mtk_ddp_comp_enable_vblank(comp);
645
646 return 0;
647 }
648
mtk_crtc_disable_vblank(struct drm_crtc * crtc)649 static void mtk_crtc_disable_vblank(struct drm_crtc *crtc)
650 {
651 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
652 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
653
654 mtk_ddp_comp_disable_vblank(comp);
655 }
656
mtk_crtc_update_output(struct drm_crtc * crtc,struct drm_atomic_state * state)657 static void mtk_crtc_update_output(struct drm_crtc *crtc,
658 struct drm_atomic_state *state)
659 {
660 int crtc_index = drm_crtc_index(crtc);
661 int i;
662 struct device *dev;
663 struct drm_crtc_state *crtc_state = state->crtcs[crtc_index].new_state;
664 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
665 struct mtk_drm_private *priv;
666 unsigned int encoder_mask = crtc_state->encoder_mask;
667
668 if (!crtc_state->connectors_changed)
669 return;
670
671 if (!mtk_crtc->num_conn_routes)
672 return;
673
674 priv = ((struct mtk_drm_private *)crtc->dev->dev_private)->all_drm_private[crtc_index];
675 dev = priv->dev;
676
677 dev_dbg(dev, "connector change:%d, encoder mask:0x%x for crtc:%d\n",
678 crtc_state->connectors_changed, encoder_mask, crtc_index);
679
680 for (i = 0; i < mtk_crtc->num_conn_routes; i++) {
681 unsigned int comp_id = mtk_crtc->conn_routes[i].route_ddp;
682 struct mtk_ddp_comp *comp = &priv->ddp_comp[comp_id];
683
684 if (comp->encoder_index >= 0 &&
685 (encoder_mask & BIT(comp->encoder_index))) {
686 mtk_crtc->ddp_comp[mtk_crtc->ddp_comp_nr - 1] = comp;
687 dev_dbg(dev, "Add comp_id: %d at path index %d\n",
688 comp->id, mtk_crtc->ddp_comp_nr - 1);
689 break;
690 }
691 }
692 }
693
mtk_crtc_plane_check(struct drm_crtc * crtc,struct drm_plane * plane,struct mtk_plane_state * state)694 int mtk_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
695 struct mtk_plane_state *state)
696 {
697 unsigned int local_layer;
698 struct mtk_ddp_comp *comp;
699
700 comp = mtk_ddp_comp_for_plane(crtc, plane, &local_layer);
701 if (comp)
702 return mtk_ddp_comp_layer_check(comp, local_layer, state);
703 return 0;
704 }
705
mtk_crtc_async_update(struct drm_crtc * crtc,struct drm_plane * plane,struct drm_atomic_state * state)706 void mtk_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
707 struct drm_atomic_state *state)
708 {
709 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
710
711 if (!mtk_crtc->enabled)
712 return;
713
714 mtk_crtc_update_config(mtk_crtc, false);
715 }
716
mtk_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)717 static void mtk_crtc_atomic_enable(struct drm_crtc *crtc,
718 struct drm_atomic_state *state)
719 {
720 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
721 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
722 int ret;
723
724 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
725
726 ret = mtk_ddp_comp_power_on(comp);
727 if (ret < 0) {
728 DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n", ret);
729 return;
730 }
731
732 mtk_crtc_update_output(crtc, state);
733
734 ret = mtk_crtc_ddp_hw_init(mtk_crtc);
735 if (ret) {
736 mtk_ddp_comp_power_off(comp);
737 return;
738 }
739
740 drm_crtc_vblank_on(crtc);
741 mtk_crtc->enabled = true;
742 }
743
mtk_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_atomic_state * state)744 static void mtk_crtc_atomic_disable(struct drm_crtc *crtc,
745 struct drm_atomic_state *state)
746 {
747 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
748 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
749 int i;
750
751 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
752 if (!mtk_crtc->enabled)
753 return;
754
755 /* Set all pending plane state to disabled */
756 for (i = 0; i < mtk_crtc->layer_nr; i++) {
757 struct drm_plane *plane = &mtk_crtc->planes[i];
758 struct mtk_plane_state *plane_state;
759
760 plane_state = to_mtk_plane_state(plane->state);
761 plane_state->pending.enable = false;
762 plane_state->pending.config = true;
763 }
764 mtk_crtc->pending_planes = true;
765
766 mtk_crtc_update_config(mtk_crtc, false);
767 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
768 /* Wait for planes to be disabled by cmdq */
769 if (mtk_crtc->cmdq_client.chan)
770 wait_event_timeout(mtk_crtc->cb_blocking_queue,
771 mtk_crtc->cmdq_vblank_cnt == 0,
772 msecs_to_jiffies(500));
773 #endif
774 /* Wait for planes to be disabled */
775 drm_crtc_wait_one_vblank(crtc);
776
777 drm_crtc_vblank_off(crtc);
778 mtk_crtc_ddp_hw_fini(mtk_crtc);
779 mtk_ddp_comp_power_off(comp);
780
781 mtk_crtc->enabled = false;
782 }
783
mtk_crtc_atomic_begin(struct drm_crtc * crtc,struct drm_atomic_state * state)784 static void mtk_crtc_atomic_begin(struct drm_crtc *crtc,
785 struct drm_atomic_state *state)
786 {
787 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
788 crtc);
789 struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state);
790 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
791 unsigned long flags;
792
793 if (mtk_crtc->event && mtk_crtc_state->base.event)
794 DRM_ERROR("new event while there is still a pending event\n");
795
796 if (mtk_crtc_state->base.event) {
797 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc);
798 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
799
800 spin_lock_irqsave(&crtc->dev->event_lock, flags);
801 mtk_crtc->event = mtk_crtc_state->base.event;
802 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
803
804 mtk_crtc_state->base.event = NULL;
805 }
806 }
807
mtk_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_atomic_state * state)808 static void mtk_crtc_atomic_flush(struct drm_crtc *crtc,
809 struct drm_atomic_state *state)
810 {
811 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
812 int i;
813
814 if (crtc->state->color_mgmt_changed)
815 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
816 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
817 mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
818 }
819 mtk_crtc_update_config(mtk_crtc, !!mtk_crtc->event);
820 }
821
822 static const struct drm_crtc_funcs mtk_crtc_funcs = {
823 .set_config = drm_atomic_helper_set_config,
824 .page_flip = drm_atomic_helper_page_flip,
825 .destroy = mtk_crtc_destroy,
826 .reset = mtk_crtc_reset,
827 .atomic_duplicate_state = mtk_crtc_duplicate_state,
828 .atomic_destroy_state = mtk_crtc_destroy_state,
829 .enable_vblank = mtk_crtc_enable_vblank,
830 .disable_vblank = mtk_crtc_disable_vblank,
831 };
832
833 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
834 .mode_fixup = mtk_crtc_mode_fixup,
835 .mode_set_nofb = mtk_crtc_mode_set_nofb,
836 .mode_valid = mtk_crtc_mode_valid,
837 .atomic_begin = mtk_crtc_atomic_begin,
838 .atomic_flush = mtk_crtc_atomic_flush,
839 .atomic_enable = mtk_crtc_atomic_enable,
840 .atomic_disable = mtk_crtc_atomic_disable,
841 };
842
mtk_crtc_init(struct drm_device * drm,struct mtk_crtc * mtk_crtc,unsigned int pipe)843 static int mtk_crtc_init(struct drm_device *drm, struct mtk_crtc *mtk_crtc,
844 unsigned int pipe)
845 {
846 struct drm_plane *primary = NULL;
847 struct drm_plane *cursor = NULL;
848 int i, ret;
849
850 for (i = 0; i < mtk_crtc->layer_nr; i++) {
851 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY)
852 primary = &mtk_crtc->planes[i];
853 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR)
854 cursor = &mtk_crtc->planes[i];
855 }
856
857 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
858 &mtk_crtc_funcs, NULL);
859 if (ret)
860 goto err_cleanup_crtc;
861
862 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs);
863
864 return 0;
865
866 err_cleanup_crtc:
867 drm_crtc_cleanup(&mtk_crtc->base);
868 return ret;
869 }
870
mtk_crtc_num_comp_planes(struct mtk_crtc * mtk_crtc,int comp_idx)871 static int mtk_crtc_num_comp_planes(struct mtk_crtc *mtk_crtc, int comp_idx)
872 {
873 struct mtk_ddp_comp *comp;
874
875 if (comp_idx > 1)
876 return 0;
877
878 comp = mtk_crtc->ddp_comp[comp_idx];
879 if (!comp->funcs)
880 return 0;
881
882 if (comp_idx == 1 && !comp->funcs->bgclr_in_on)
883 return 0;
884
885 return mtk_ddp_comp_layer_nr(comp);
886 }
887
888 static inline
mtk_crtc_plane_type(unsigned int plane_idx,unsigned int num_planes)889 enum drm_plane_type mtk_crtc_plane_type(unsigned int plane_idx,
890 unsigned int num_planes)
891 {
892 if (plane_idx == 0)
893 return DRM_PLANE_TYPE_PRIMARY;
894 else if (plane_idx == (num_planes - 1))
895 return DRM_PLANE_TYPE_CURSOR;
896 else
897 return DRM_PLANE_TYPE_OVERLAY;
898
899 }
900
mtk_crtc_init_comp_planes(struct drm_device * drm_dev,struct mtk_crtc * mtk_crtc,int comp_idx,int pipe)901 static int mtk_crtc_init_comp_planes(struct drm_device *drm_dev,
902 struct mtk_crtc *mtk_crtc,
903 int comp_idx, int pipe)
904 {
905 int num_planes = mtk_crtc_num_comp_planes(mtk_crtc, comp_idx);
906 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx];
907 int i, ret;
908
909 for (i = 0; i < num_planes; i++) {
910 ret = mtk_plane_init(drm_dev,
911 &mtk_crtc->planes[mtk_crtc->layer_nr],
912 BIT(pipe),
913 mtk_crtc_plane_type(mtk_crtc->layer_nr, num_planes),
914 mtk_ddp_comp_supported_rotations(comp),
915 mtk_ddp_comp_get_blend_modes(comp),
916 mtk_ddp_comp_get_formats(comp),
917 mtk_ddp_comp_get_num_formats(comp), i);
918 if (ret)
919 return ret;
920
921 mtk_crtc->layer_nr++;
922 }
923 return 0;
924 }
925
mtk_crtc_dma_dev_get(struct drm_crtc * crtc)926 struct device *mtk_crtc_dma_dev_get(struct drm_crtc *crtc)
927 {
928 struct mtk_crtc *mtk_crtc = NULL;
929
930 if (!crtc)
931 return NULL;
932
933 mtk_crtc = to_mtk_crtc(crtc);
934 if (!mtk_crtc)
935 return NULL;
936
937 return mtk_crtc->dma_dev;
938 }
939
mtk_crtc_create(struct drm_device * drm_dev,const unsigned int * path,unsigned int path_len,int priv_data_index,const struct mtk_drm_route * conn_routes,unsigned int num_conn_routes)940 int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
941 unsigned int path_len, int priv_data_index,
942 const struct mtk_drm_route *conn_routes,
943 unsigned int num_conn_routes)
944 {
945 struct mtk_drm_private *priv = drm_dev->dev_private;
946 struct device *dev = drm_dev->dev;
947 struct mtk_crtc *mtk_crtc;
948 unsigned int num_comp_planes = 0;
949 int ret;
950 int i;
951 bool has_ctm = false;
952 uint gamma_lut_size = 0;
953 struct drm_crtc *tmp;
954 int crtc_i = 0;
955
956 if (!path)
957 return 0;
958
959 priv = priv->all_drm_private[priv_data_index];
960
961 drm_for_each_crtc(tmp, drm_dev)
962 crtc_i++;
963
964 for (i = 0; i < path_len; i++) {
965 enum mtk_ddp_comp_id comp_id = path[i];
966 struct device_node *node;
967 struct mtk_ddp_comp *comp;
968
969 node = priv->comp_node[comp_id];
970 comp = &priv->ddp_comp[comp_id];
971
972 /* Not all drm components have a DTS device node, such as ovl_adaptor,
973 * which is the drm bring up sub driver
974 */
975 if (!node && comp_id != DDP_COMPONENT_DRM_OVL_ADAPTOR) {
976 dev_info(dev,
977 "Not creating crtc %d because component %d is disabled or missing\n",
978 crtc_i, comp_id);
979 return 0;
980 }
981
982 if (!comp->dev) {
983 dev_err(dev, "Component %pOF not initialized\n", node);
984 return -ENODEV;
985 }
986 }
987
988 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL);
989 if (!mtk_crtc)
990 return -ENOMEM;
991
992 mtk_crtc->mmsys_dev = priv->mmsys_dev;
993 mtk_crtc->ddp_comp_nr = path_len;
994 mtk_crtc->ddp_comp = devm_kcalloc(dev,
995 mtk_crtc->ddp_comp_nr + (conn_routes ? 1 : 0),
996 sizeof(*mtk_crtc->ddp_comp),
997 GFP_KERNEL);
998 if (!mtk_crtc->ddp_comp)
999 return -ENOMEM;
1000
1001 mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev);
1002 if (IS_ERR(mtk_crtc->mutex)) {
1003 ret = PTR_ERR(mtk_crtc->mutex);
1004 dev_err(dev, "Failed to get mutex: %d\n", ret);
1005 return ret;
1006 }
1007
1008 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
1009 unsigned int comp_id = path[i];
1010 struct mtk_ddp_comp *comp;
1011
1012 comp = &priv->ddp_comp[comp_id];
1013 mtk_crtc->ddp_comp[i] = comp;
1014
1015 if (comp->funcs) {
1016 if (comp->funcs->gamma_set && comp->funcs->gamma_get_lut_size) {
1017 unsigned int lut_sz = mtk_ddp_gamma_get_lut_size(comp);
1018
1019 if (lut_sz)
1020 gamma_lut_size = lut_sz;
1021 }
1022
1023 if (comp->funcs->ctm_set)
1024 has_ctm = true;
1025 }
1026
1027 mtk_ddp_comp_register_vblank_cb(comp, mtk_crtc_ddp_irq,
1028 &mtk_crtc->base);
1029 }
1030
1031 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
1032 num_comp_planes += mtk_crtc_num_comp_planes(mtk_crtc, i);
1033
1034 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes,
1035 sizeof(struct drm_plane), GFP_KERNEL);
1036 if (!mtk_crtc->planes)
1037 return -ENOMEM;
1038
1039 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
1040 ret = mtk_crtc_init_comp_planes(drm_dev, mtk_crtc, i, crtc_i);
1041 if (ret)
1042 return ret;
1043 }
1044
1045 /*
1046 * Default to use the first component as the dma dev.
1047 * In the case of ovl_adaptor sub driver, it needs to use the
1048 * dma_dev_get function to get representative dma dev.
1049 */
1050 mtk_crtc->dma_dev = mtk_ddp_comp_dma_dev_get(&priv->ddp_comp[path[0]]);
1051
1052 ret = mtk_crtc_init(drm_dev, mtk_crtc, crtc_i);
1053 if (ret < 0)
1054 return ret;
1055
1056 if (gamma_lut_size)
1057 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
1058 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
1059 mutex_init(&mtk_crtc->hw_lock);
1060 spin_lock_init(&mtk_crtc->config_lock);
1061
1062 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
1063 i = priv->mbox_index++;
1064 mtk_crtc->cmdq_client.client.dev = mtk_crtc->mmsys_dev;
1065 mtk_crtc->cmdq_client.client.tx_block = false;
1066 mtk_crtc->cmdq_client.client.knows_txdone = true;
1067 mtk_crtc->cmdq_client.client.rx_callback = ddp_cmdq_cb;
1068 mtk_crtc->cmdq_client.chan =
1069 mbox_request_channel(&mtk_crtc->cmdq_client.client, i);
1070 if (IS_ERR(mtk_crtc->cmdq_client.chan)) {
1071 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
1072 drm_crtc_index(&mtk_crtc->base));
1073 mtk_crtc->cmdq_client.chan = NULL;
1074 }
1075
1076 if (mtk_crtc->cmdq_client.chan) {
1077 ret = of_property_read_u32_index(priv->mutex_node,
1078 "mediatek,gce-events",
1079 i,
1080 &mtk_crtc->cmdq_event);
1081 if (ret) {
1082 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
1083 drm_crtc_index(&mtk_crtc->base));
1084 mbox_free_channel(mtk_crtc->cmdq_client.chan);
1085 mtk_crtc->cmdq_client.chan = NULL;
1086 } else {
1087 ret = cmdq_pkt_create(&mtk_crtc->cmdq_client,
1088 &mtk_crtc->cmdq_handle,
1089 PAGE_SIZE);
1090 if (ret) {
1091 dev_dbg(dev, "mtk_crtc %d failed to create cmdq packet\n",
1092 drm_crtc_index(&mtk_crtc->base));
1093 mbox_free_channel(mtk_crtc->cmdq_client.chan);
1094 mtk_crtc->cmdq_client.chan = NULL;
1095 }
1096 }
1097
1098 /* for sending blocking cmd in crtc disable */
1099 init_waitqueue_head(&mtk_crtc->cb_blocking_queue);
1100 }
1101 #endif
1102
1103 if (conn_routes) {
1104 for (i = 0; i < num_conn_routes; i++) {
1105 unsigned int comp_id = conn_routes[i].route_ddp;
1106 struct device_node *node = priv->comp_node[comp_id];
1107 struct mtk_ddp_comp *comp = &priv->ddp_comp[comp_id];
1108
1109 if (!comp->dev) {
1110 dev_dbg(dev, "comp_id:%d, Component %pOF not initialized\n",
1111 comp_id, node);
1112 /* mark encoder_index to -1, if route comp device is not enabled */
1113 comp->encoder_index = -1;
1114 continue;
1115 }
1116
1117 mtk_ddp_comp_encoder_index_set(&priv->ddp_comp[comp_id]);
1118 }
1119
1120 mtk_crtc->num_conn_routes = num_conn_routes;
1121 mtk_crtc->conn_routes = conn_routes;
1122
1123 /* increase ddp_comp_nr at the end of mtk_crtc_create */
1124 mtk_crtc->ddp_comp_nr++;
1125 }
1126
1127 return 0;
1128 }
1129