1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PIC32 Integrated Serial Driver. 4 * 5 * Copyright (C) 2015 Microchip Technology, Inc. 6 * 7 * Authors: 8 * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com> 9 */ 10 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/platform_device.h> 14 #include <linux/of.h> 15 #include <linux/of_irq.h> 16 #include <linux/init.h> 17 #include <linux/module.h> 18 #include <linux/slab.h> 19 #include <linux/console.h> 20 #include <linux/clk.h> 21 #include <linux/tty.h> 22 #include <linux/tty_flip.h> 23 #include <linux/serial_core.h> 24 #include <linux/delay.h> 25 #include <linux/platform_data/pic32.h> 26 27 /* UART name and device definitions */ 28 #define PIC32_DEV_NAME "pic32-uart" 29 #define PIC32_MAX_UARTS 6 30 #define PIC32_SDEV_NAME "ttyPIC" 31 32 #define PIC32_UART_DFLT_BRATE 9600 33 #define PIC32_UART_TX_FIFO_DEPTH 8 34 #define PIC32_UART_RX_FIFO_DEPTH 8 35 36 #define PIC32_UART_MODE 0x00 37 #define PIC32_UART_STA 0x10 38 #define PIC32_UART_TX 0x20 39 #define PIC32_UART_RX 0x30 40 #define PIC32_UART_BRG 0x40 41 42 /* struct pic32_sport - pic32 serial port descriptor 43 * @port: uart port descriptor 44 * @idx: port index 45 * @irq_fault: virtual fault interrupt number 46 * @irq_fault_name: irq fault name 47 * @irq_rx: virtual rx interrupt number 48 * @irq_rx_name: irq rx name 49 * @irq_tx: virtual tx interrupt number 50 * @irq_tx_name: irq tx name 51 * @cts_gpiod: clear to send GPIO 52 * @dev: device descriptor 53 **/ 54 struct pic32_sport { 55 struct uart_port port; 56 int idx; 57 58 int irq_fault; 59 const char *irq_fault_name; 60 int irq_rx; 61 const char *irq_rx_name; 62 int irq_tx; 63 const char *irq_tx_name; 64 bool enable_tx_irq; 65 66 struct gpio_desc *cts_gpiod; 67 68 struct clk *clk; 69 70 struct device *dev; 71 }; 72 73 static inline struct pic32_sport *to_pic32_sport(struct uart_port *port) 74 { 75 return container_of(port, struct pic32_sport, port); 76 } 77 78 static inline void pic32_uart_writel(struct pic32_sport *sport, 79 u32 reg, u32 val) 80 { 81 __raw_writel(val, sport->port.membase + reg); 82 } 83 84 static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg) 85 { 86 return __raw_readl(sport->port.membase + reg); 87 } 88 89 /* pic32 uart mode register bits */ 90 #define PIC32_UART_MODE_ON BIT(15) 91 #define PIC32_UART_MODE_FRZ BIT(14) 92 #define PIC32_UART_MODE_SIDL BIT(13) 93 #define PIC32_UART_MODE_IREN BIT(12) 94 #define PIC32_UART_MODE_RTSMD BIT(11) 95 #define PIC32_UART_MODE_RESV1 BIT(10) 96 #define PIC32_UART_MODE_UEN1 BIT(9) 97 #define PIC32_UART_MODE_UEN0 BIT(8) 98 #define PIC32_UART_MODE_WAKE BIT(7) 99 #define PIC32_UART_MODE_LPBK BIT(6) 100 #define PIC32_UART_MODE_ABAUD BIT(5) 101 #define PIC32_UART_MODE_RXINV BIT(4) 102 #define PIC32_UART_MODE_BRGH BIT(3) 103 #define PIC32_UART_MODE_PDSEL1 BIT(2) 104 #define PIC32_UART_MODE_PDSEL0 BIT(1) 105 #define PIC32_UART_MODE_STSEL BIT(0) 106 107 /* pic32 uart status register bits */ 108 #define PIC32_UART_STA_UTXISEL1 BIT(15) 109 #define PIC32_UART_STA_UTXISEL0 BIT(14) 110 #define PIC32_UART_STA_UTXINV BIT(13) 111 #define PIC32_UART_STA_URXEN BIT(12) 112 #define PIC32_UART_STA_UTXBRK BIT(11) 113 #define PIC32_UART_STA_UTXEN BIT(10) 114 #define PIC32_UART_STA_UTXBF BIT(9) 115 #define PIC32_UART_STA_TRMT BIT(8) 116 #define PIC32_UART_STA_URXISEL1 BIT(7) 117 #define PIC32_UART_STA_URXISEL0 BIT(6) 118 #define PIC32_UART_STA_ADDEN BIT(5) 119 #define PIC32_UART_STA_RIDLE BIT(4) 120 #define PIC32_UART_STA_PERR BIT(3) 121 #define PIC32_UART_STA_FERR BIT(2) 122 #define PIC32_UART_STA_OERR BIT(1) 123 #define PIC32_UART_STA_URXDA BIT(0) 124 125 /* pic32_sport pointer for console use */ 126 static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS]; 127 128 static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport) 129 { 130 /* wait for tx empty, otherwise chars will be lost or corrupted */ 131 while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT)) 132 udelay(1); 133 } 134 135 /* serial core request to check if uart tx buffer is empty */ 136 static unsigned int pic32_uart_tx_empty(struct uart_port *port) 137 { 138 struct pic32_sport *sport = to_pic32_sport(port); 139 u32 val = pic32_uart_readl(sport, PIC32_UART_STA); 140 141 return (val & PIC32_UART_STA_TRMT) ? 1 : 0; 142 } 143 144 /* serial core request to set UART outputs */ 145 static void pic32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 146 { 147 struct pic32_sport *sport = to_pic32_sport(port); 148 149 /* set loopback mode */ 150 if (mctrl & TIOCM_LOOP) 151 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 152 PIC32_UART_MODE_LPBK); 153 else 154 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 155 PIC32_UART_MODE_LPBK); 156 } 157 158 /* serial core request to return the state of misc UART input pins */ 159 static unsigned int pic32_uart_get_mctrl(struct uart_port *port) 160 { 161 struct pic32_sport *sport = to_pic32_sport(port); 162 unsigned int mctrl = 0; 163 164 /* get the state of CTS input pin for this port */ 165 if (!sport->cts_gpiod) 166 mctrl |= TIOCM_CTS; 167 else if (gpiod_get_value(sport->cts_gpiod)) 168 mctrl |= TIOCM_CTS; 169 170 /* DSR and CD are not supported in PIC32, so return 1 171 * RI is not supported in PIC32, so return 0 172 */ 173 mctrl |= TIOCM_CD; 174 mctrl |= TIOCM_DSR; 175 176 return mctrl; 177 } 178 179 /* stop tx and start tx are not called in pairs, therefore a flag indicates 180 * the status of irq to control the irq-depth. 181 */ 182 static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en) 183 { 184 if (en && !sport->enable_tx_irq) { 185 enable_irq(sport->irq_tx); 186 sport->enable_tx_irq = true; 187 } else if (!en && sport->enable_tx_irq) { 188 /* use disable_irq_nosync() and not disable_irq() to avoid self 189 * imposed deadlock by not waiting for irq handler to end, 190 * since this callback is called from interrupt context. 191 */ 192 disable_irq_nosync(sport->irq_tx); 193 sport->enable_tx_irq = false; 194 } 195 } 196 197 /* serial core request to disable tx ASAP (used for flow control) */ 198 static void pic32_uart_stop_tx(struct uart_port *port) 199 { 200 struct pic32_sport *sport = to_pic32_sport(port); 201 202 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON)) 203 return; 204 205 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN)) 206 return; 207 208 /* wait for tx empty */ 209 pic32_wait_deplete_txbuf(sport); 210 211 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 212 PIC32_UART_STA_UTXEN); 213 pic32_uart_irqtxen(sport, 0); 214 } 215 216 /* serial core request to (re)enable tx */ 217 static void pic32_uart_start_tx(struct uart_port *port) 218 { 219 struct pic32_sport *sport = to_pic32_sport(port); 220 221 pic32_uart_irqtxen(sport, 1); 222 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA), 223 PIC32_UART_STA_UTXEN); 224 } 225 226 /* serial core request to stop rx, called before port shutdown */ 227 static void pic32_uart_stop_rx(struct uart_port *port) 228 { 229 struct pic32_sport *sport = to_pic32_sport(port); 230 231 /* disable rx interrupts */ 232 disable_irq(sport->irq_rx); 233 234 /* receiver Enable bit OFF */ 235 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 236 PIC32_UART_STA_URXEN); 237 } 238 239 /* serial core request to start/stop emitting break char */ 240 static void pic32_uart_break_ctl(struct uart_port *port, int ctl) 241 { 242 struct pic32_sport *sport = to_pic32_sport(port); 243 unsigned long flags; 244 245 uart_port_lock_irqsave(port, &flags); 246 247 if (ctl) 248 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA), 249 PIC32_UART_STA_UTXBRK); 250 else 251 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 252 PIC32_UART_STA_UTXBRK); 253 254 uart_port_unlock_irqrestore(port, flags); 255 } 256 257 /* get port type in string format */ 258 static const char *pic32_uart_type(struct uart_port *port) 259 { 260 return (port->type == PORT_PIC32) ? PIC32_DEV_NAME : NULL; 261 } 262 263 /* read all chars in rx fifo and send them to core */ 264 static void pic32_uart_do_rx(struct uart_port *port) 265 { 266 struct pic32_sport *sport = to_pic32_sport(port); 267 struct tty_port *tty; 268 unsigned int max_count; 269 270 /* limit number of char read in interrupt, should not be 271 * higher than fifo size anyway since we're much faster than 272 * serial port 273 */ 274 max_count = PIC32_UART_RX_FIFO_DEPTH; 275 276 uart_port_lock(port); 277 278 tty = &port->state->port; 279 280 do { 281 u32 sta_reg, c; 282 char flag; 283 284 /* get overrun/fifo empty information from status register */ 285 sta_reg = pic32_uart_readl(sport, PIC32_UART_STA); 286 if (unlikely(sta_reg & PIC32_UART_STA_OERR)) { 287 288 /* fifo reset is required to clear interrupt */ 289 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 290 PIC32_UART_STA_OERR); 291 292 port->icount.overrun++; 293 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 294 } 295 296 /* Can at least one more character can be read? */ 297 if (!(sta_reg & PIC32_UART_STA_URXDA)) 298 break; 299 300 /* read the character and increment the rx counter */ 301 c = pic32_uart_readl(sport, PIC32_UART_RX); 302 303 port->icount.rx++; 304 flag = TTY_NORMAL; 305 c &= 0xff; 306 307 if (unlikely((sta_reg & PIC32_UART_STA_PERR) || 308 (sta_reg & PIC32_UART_STA_FERR))) { 309 310 /* do stats first */ 311 if (sta_reg & PIC32_UART_STA_PERR) 312 port->icount.parity++; 313 if (sta_reg & PIC32_UART_STA_FERR) 314 port->icount.frame++; 315 316 /* update flag wrt read_status_mask */ 317 sta_reg &= port->read_status_mask; 318 319 if (sta_reg & PIC32_UART_STA_FERR) 320 flag = TTY_FRAME; 321 if (sta_reg & PIC32_UART_STA_PERR) 322 flag = TTY_PARITY; 323 } 324 325 if (uart_handle_sysrq_char(port, c)) 326 continue; 327 328 if ((sta_reg & port->ignore_status_mask) == 0) 329 tty_insert_flip_char(tty, c, flag); 330 331 } while (--max_count); 332 333 uart_port_unlock(port); 334 335 tty_flip_buffer_push(tty); 336 } 337 338 /* fill tx fifo with chars to send, stop when fifo is about to be full 339 * or when all chars have been sent. 340 */ 341 static void pic32_uart_do_tx(struct uart_port *port) 342 { 343 struct pic32_sport *sport = to_pic32_sport(port); 344 struct tty_port *tport = &port->state->port; 345 unsigned int max_count = PIC32_UART_TX_FIFO_DEPTH; 346 347 if (port->x_char) { 348 pic32_uart_writel(sport, PIC32_UART_TX, port->x_char); 349 port->icount.tx++; 350 port->x_char = 0; 351 return; 352 } 353 354 if (uart_tx_stopped(port)) { 355 pic32_uart_stop_tx(port); 356 return; 357 } 358 359 if (kfifo_is_empty(&tport->xmit_fifo)) 360 goto txq_empty; 361 362 /* keep stuffing chars into uart tx buffer 363 * 1) until uart fifo is full 364 * or 365 * 2) until the circ buffer is empty 366 * (all chars have been sent) 367 * or 368 * 3) until the max count is reached 369 * (prevents lingering here for too long in certain cases) 370 */ 371 while (!(PIC32_UART_STA_UTXBF & 372 pic32_uart_readl(sport, PIC32_UART_STA))) { 373 unsigned char c; 374 375 if (!uart_fifo_get(port, &c)) 376 break; 377 pic32_uart_writel(sport, PIC32_UART_TX, c); 378 379 if (--max_count == 0) 380 break; 381 } 382 383 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 384 uart_write_wakeup(port); 385 386 if (kfifo_is_empty(&tport->xmit_fifo)) 387 goto txq_empty; 388 389 return; 390 391 txq_empty: 392 pic32_uart_irqtxen(sport, 0); 393 } 394 395 /* RX interrupt handler */ 396 static irqreturn_t pic32_uart_rx_interrupt(int irq, void *dev_id) 397 { 398 struct uart_port *port = dev_id; 399 400 pic32_uart_do_rx(port); 401 402 return IRQ_HANDLED; 403 } 404 405 /* TX interrupt handler */ 406 static irqreturn_t pic32_uart_tx_interrupt(int irq, void *dev_id) 407 { 408 struct uart_port *port = dev_id; 409 unsigned long flags; 410 411 uart_port_lock_irqsave(port, &flags); 412 pic32_uart_do_tx(port); 413 uart_port_unlock_irqrestore(port, flags); 414 415 return IRQ_HANDLED; 416 } 417 418 /* FAULT interrupt handler */ 419 static irqreturn_t pic32_uart_fault_interrupt(int irq, void *dev_id) 420 { 421 /* do nothing: pic32_uart_do_rx() handles faults. */ 422 return IRQ_HANDLED; 423 } 424 425 /* enable rx & tx operation on uart */ 426 static void pic32_uart_en_and_unmask(struct uart_port *port) 427 { 428 struct pic32_sport *sport = to_pic32_sport(port); 429 430 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA), 431 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN); 432 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 433 PIC32_UART_MODE_ON); 434 } 435 436 /* disable rx & tx operation on uart */ 437 static void pic32_uart_dsbl_and_mask(struct uart_port *port) 438 { 439 struct pic32_sport *sport = to_pic32_sport(port); 440 441 /* wait for tx empty, otherwise chars will be lost or corrupted */ 442 pic32_wait_deplete_txbuf(sport); 443 444 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 445 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN); 446 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 447 PIC32_UART_MODE_ON); 448 } 449 450 /* serial core request to initialize uart and start rx operation */ 451 static int pic32_uart_startup(struct uart_port *port) 452 { 453 struct pic32_sport *sport = to_pic32_sport(port); 454 u32 dflt_baud = (port->uartclk / PIC32_UART_DFLT_BRATE / 16) - 1; 455 unsigned long flags; 456 int ret; 457 458 local_irq_save(flags); 459 460 ret = clk_prepare_enable(sport->clk); 461 if (ret) { 462 local_irq_restore(flags); 463 goto out_done; 464 } 465 466 /* clear status and mode registers */ 467 pic32_uart_writel(sport, PIC32_UART_MODE, 0); 468 pic32_uart_writel(sport, PIC32_UART_STA, 0); 469 470 /* disable uart and mask all interrupts */ 471 pic32_uart_dsbl_and_mask(port); 472 473 /* set default baud */ 474 pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud); 475 476 local_irq_restore(flags); 477 478 /* Each UART of a PIC32 has three interrupts therefore, 479 * we setup driver to register the 3 irqs for the device. 480 * 481 * For each irq request_irq() is called with interrupt disabled. 482 * And the irq is enabled as soon as we are ready to handle them. 483 */ 484 sport->enable_tx_irq = false; 485 486 sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault", 487 pic32_uart_type(port), 488 sport->idx); 489 if (!sport->irq_fault_name) { 490 dev_err(port->dev, "%s: kasprintf err!", __func__); 491 ret = -ENOMEM; 492 goto out_disable_clk; 493 } 494 irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN); 495 ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt, 496 IRQF_NO_THREAD, sport->irq_fault_name, port); 497 if (ret) { 498 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n", 499 __func__, sport->irq_fault, ret, 500 pic32_uart_type(port)); 501 goto out_f; 502 } 503 504 sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx", 505 pic32_uart_type(port), 506 sport->idx); 507 if (!sport->irq_rx_name) { 508 dev_err(port->dev, "%s: kasprintf err!", __func__); 509 ret = -ENOMEM; 510 goto out_f; 511 } 512 irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN); 513 ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt, 514 IRQF_NO_THREAD, sport->irq_rx_name, port); 515 if (ret) { 516 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n", 517 __func__, sport->irq_rx, ret, 518 pic32_uart_type(port)); 519 goto out_r; 520 } 521 522 sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx", 523 pic32_uart_type(port), 524 sport->idx); 525 if (!sport->irq_tx_name) { 526 dev_err(port->dev, "%s: kasprintf err!", __func__); 527 ret = -ENOMEM; 528 goto out_r; 529 } 530 irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN); 531 ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt, 532 IRQF_NO_THREAD, sport->irq_tx_name, port); 533 if (ret) { 534 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n", 535 __func__, sport->irq_tx, ret, 536 pic32_uart_type(port)); 537 goto out_t; 538 } 539 540 local_irq_save(flags); 541 542 /* set rx interrupt on first receive */ 543 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 544 PIC32_UART_STA_URXISEL1 | PIC32_UART_STA_URXISEL0); 545 546 /* set interrupt on empty */ 547 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 548 PIC32_UART_STA_UTXISEL1); 549 550 /* enable all interrupts and eanable uart */ 551 pic32_uart_en_and_unmask(port); 552 553 local_irq_restore(flags); 554 555 enable_irq(sport->irq_rx); 556 557 return 0; 558 559 out_t: 560 free_irq(sport->irq_tx, port); 561 kfree(sport->irq_tx_name); 562 out_r: 563 free_irq(sport->irq_rx, port); 564 kfree(sport->irq_rx_name); 565 out_f: 566 free_irq(sport->irq_fault, port); 567 kfree(sport->irq_fault_name); 568 out_disable_clk: 569 clk_disable_unprepare(sport->clk); 570 out_done: 571 return ret; 572 } 573 574 /* serial core request to flush & disable uart */ 575 static void pic32_uart_shutdown(struct uart_port *port) 576 { 577 struct pic32_sport *sport = to_pic32_sport(port); 578 unsigned long flags; 579 580 /* disable uart */ 581 uart_port_lock_irqsave(port, &flags); 582 pic32_uart_dsbl_and_mask(port); 583 uart_port_unlock_irqrestore(port, flags); 584 clk_disable_unprepare(sport->clk); 585 586 /* free all 3 interrupts for this UART */ 587 free_irq(sport->irq_fault, port); 588 kfree(sport->irq_fault_name); 589 free_irq(sport->irq_tx, port); 590 kfree(sport->irq_tx_name); 591 free_irq(sport->irq_rx, port); 592 kfree(sport->irq_rx_name); 593 } 594 595 /* serial core request to change current uart setting */ 596 static void pic32_uart_set_termios(struct uart_port *port, 597 struct ktermios *new, 598 const struct ktermios *old) 599 { 600 struct pic32_sport *sport = to_pic32_sport(port); 601 unsigned int baud; 602 unsigned int quot; 603 unsigned long flags; 604 605 uart_port_lock_irqsave(port, &flags); 606 607 /* disable uart and mask all interrupts while changing speed */ 608 pic32_uart_dsbl_and_mask(port); 609 610 /* stop bit options */ 611 if (new->c_cflag & CSTOPB) 612 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 613 PIC32_UART_MODE_STSEL); 614 else 615 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 616 PIC32_UART_MODE_STSEL); 617 618 /* parity options */ 619 if (new->c_cflag & PARENB) { 620 if (new->c_cflag & PARODD) { 621 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 622 PIC32_UART_MODE_PDSEL1); 623 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 624 PIC32_UART_MODE_PDSEL0); 625 } else { 626 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 627 PIC32_UART_MODE_PDSEL0); 628 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 629 PIC32_UART_MODE_PDSEL1); 630 } 631 } else { 632 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 633 PIC32_UART_MODE_PDSEL1 | 634 PIC32_UART_MODE_PDSEL0); 635 } 636 /* if hw flow ctrl, then the pins must be specified in device tree */ 637 if ((new->c_cflag & CRTSCTS) && sport->cts_gpiod) { 638 /* enable hardware flow control */ 639 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 640 PIC32_UART_MODE_UEN1); 641 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 642 PIC32_UART_MODE_UEN0); 643 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 644 PIC32_UART_MODE_RTSMD); 645 } else { 646 /* disable hardware flow control */ 647 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 648 PIC32_UART_MODE_UEN1); 649 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 650 PIC32_UART_MODE_UEN0); 651 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 652 PIC32_UART_MODE_RTSMD); 653 } 654 655 /* Always 8-bit */ 656 new->c_cflag |= CS8; 657 658 /* Mark/Space parity is not supported */ 659 new->c_cflag &= ~CMSPAR; 660 661 /* update baud */ 662 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); 663 quot = uart_get_divisor(port, baud) - 1; 664 pic32_uart_writel(sport, PIC32_UART_BRG, quot); 665 uart_update_timeout(port, new->c_cflag, baud); 666 667 if (tty_termios_baud_rate(new)) 668 tty_termios_encode_baud_rate(new, baud, baud); 669 670 /* enable uart */ 671 pic32_uart_en_and_unmask(port); 672 673 uart_port_unlock_irqrestore(port, flags); 674 } 675 676 /* serial core request to claim uart iomem */ 677 static int pic32_uart_request_port(struct uart_port *port) 678 { 679 struct platform_device *pdev = to_platform_device(port->dev); 680 struct resource *res_mem; 681 682 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 683 if (unlikely(!res_mem)) 684 return -EINVAL; 685 686 if (!request_mem_region(port->mapbase, resource_size(res_mem), 687 "pic32_uart_mem")) 688 return -EBUSY; 689 690 port->membase = devm_ioremap(port->dev, port->mapbase, 691 resource_size(res_mem)); 692 if (!port->membase) { 693 dev_err(port->dev, "Unable to map registers\n"); 694 release_mem_region(port->mapbase, resource_size(res_mem)); 695 return -ENOMEM; 696 } 697 698 return 0; 699 } 700 701 /* serial core request to release uart iomem */ 702 static void pic32_uart_release_port(struct uart_port *port) 703 { 704 struct platform_device *pdev = to_platform_device(port->dev); 705 struct resource *res_mem; 706 unsigned int res_size; 707 708 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 709 if (unlikely(!res_mem)) 710 return; 711 res_size = resource_size(res_mem); 712 713 release_mem_region(port->mapbase, res_size); 714 } 715 716 /* serial core request to do any port required auto-configuration */ 717 static void pic32_uart_config_port(struct uart_port *port, int flags) 718 { 719 if (flags & UART_CONFIG_TYPE) { 720 if (pic32_uart_request_port(port)) 721 return; 722 port->type = PORT_PIC32; 723 } 724 } 725 726 /* serial core request to check that port information in serinfo are suitable */ 727 static int pic32_uart_verify_port(struct uart_port *port, 728 struct serial_struct *serinfo) 729 { 730 if (port->type != PORT_PIC32) 731 return -EINVAL; 732 if (port->irq != serinfo->irq) 733 return -EINVAL; 734 if (port->iotype != serinfo->io_type) 735 return -EINVAL; 736 if (port->mapbase != (unsigned long)serinfo->iomem_base) 737 return -EINVAL; 738 739 return 0; 740 } 741 742 /* serial core callbacks */ 743 static const struct uart_ops pic32_uart_ops = { 744 .tx_empty = pic32_uart_tx_empty, 745 .get_mctrl = pic32_uart_get_mctrl, 746 .set_mctrl = pic32_uart_set_mctrl, 747 .start_tx = pic32_uart_start_tx, 748 .stop_tx = pic32_uart_stop_tx, 749 .stop_rx = pic32_uart_stop_rx, 750 .break_ctl = pic32_uart_break_ctl, 751 .startup = pic32_uart_startup, 752 .shutdown = pic32_uart_shutdown, 753 .set_termios = pic32_uart_set_termios, 754 .type = pic32_uart_type, 755 .release_port = pic32_uart_release_port, 756 .request_port = pic32_uart_request_port, 757 .config_port = pic32_uart_config_port, 758 .verify_port = pic32_uart_verify_port, 759 }; 760 761 #ifdef CONFIG_SERIAL_PIC32_CONSOLE 762 /* output given char */ 763 static void pic32_console_putchar(struct uart_port *port, unsigned char ch) 764 { 765 struct pic32_sport *sport = to_pic32_sport(port); 766 767 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON)) 768 return; 769 770 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN)) 771 return; 772 773 /* wait for tx empty */ 774 pic32_wait_deplete_txbuf(sport); 775 776 pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff); 777 } 778 779 /* console core request to output given string */ 780 static void pic32_console_write(struct console *co, const char *s, 781 unsigned int count) 782 { 783 struct pic32_sport *sport = pic32_sports[co->index]; 784 785 /* call uart helper to deal with \r\n */ 786 uart_console_write(&sport->port, s, count, pic32_console_putchar); 787 } 788 789 /* console core request to setup given console, find matching uart 790 * port and setup it. 791 */ 792 static int pic32_console_setup(struct console *co, char *options) 793 { 794 struct pic32_sport *sport; 795 int baud = 115200; 796 int bits = 8; 797 int parity = 'n'; 798 int flow = 'n'; 799 int ret = 0; 800 801 if (unlikely(co->index < 0 || co->index >= PIC32_MAX_UARTS)) 802 return -ENODEV; 803 804 sport = pic32_sports[co->index]; 805 if (!sport) 806 return -ENODEV; 807 808 ret = clk_prepare_enable(sport->clk); 809 if (ret) 810 return ret; 811 812 if (options) 813 uart_parse_options(options, &baud, &parity, &bits, &flow); 814 815 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 816 } 817 818 static struct uart_driver pic32_uart_driver; 819 static struct console pic32_console = { 820 .name = PIC32_SDEV_NAME, 821 .write = pic32_console_write, 822 .device = uart_console_device, 823 .setup = pic32_console_setup, 824 .flags = CON_PRINTBUFFER, 825 .index = -1, 826 .data = &pic32_uart_driver, 827 }; 828 #define PIC32_SCONSOLE (&pic32_console) 829 830 static int __init pic32_console_init(void) 831 { 832 register_console(&pic32_console); 833 return 0; 834 } 835 console_initcall(pic32_console_init); 836 837 /* 838 * Late console initialization. 839 */ 840 static int __init pic32_late_console_init(void) 841 { 842 if (!console_is_registered(&pic32_console)) 843 register_console(&pic32_console); 844 845 return 0; 846 } 847 848 core_initcall(pic32_late_console_init); 849 850 #else 851 #define PIC32_SCONSOLE NULL 852 #endif 853 854 static struct uart_driver pic32_uart_driver = { 855 .owner = THIS_MODULE, 856 .driver_name = PIC32_DEV_NAME, 857 .dev_name = PIC32_SDEV_NAME, 858 .nr = PIC32_MAX_UARTS, 859 .cons = PIC32_SCONSOLE, 860 }; 861 862 static int pic32_uart_probe(struct platform_device *pdev) 863 { 864 struct device *dev = &pdev->dev; 865 struct device_node *np = dev->of_node; 866 struct pic32_sport *sport; 867 int uart_idx = 0; 868 struct resource *res_mem; 869 struct uart_port *port; 870 int ret; 871 872 uart_idx = of_alias_get_id(np, "serial"); 873 if (uart_idx < 0 || uart_idx >= PIC32_MAX_UARTS) 874 return -EINVAL; 875 876 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 877 if (!res_mem) 878 return -EINVAL; 879 880 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 881 if (!sport) 882 return -ENOMEM; 883 884 sport->idx = uart_idx; 885 sport->irq_fault = irq_of_parse_and_map(np, 0); 886 sport->irq_rx = irq_of_parse_and_map(np, 1); 887 sport->irq_tx = irq_of_parse_and_map(np, 2); 888 sport->clk = devm_clk_get(&pdev->dev, NULL); 889 if (IS_ERR(sport->clk)) 890 return PTR_ERR(sport->clk); 891 sport->dev = &pdev->dev; 892 893 /* Hardware flow control: gpios 894 * !Note: Basically, CTS is needed for reading the status. 895 */ 896 sport->cts_gpiod = devm_gpiod_get_optional(dev, "cts", GPIOD_IN); 897 if (IS_ERR(sport->cts_gpiod)) 898 return dev_err_probe(dev, PTR_ERR(sport->cts_gpiod), "error requesting CTS GPIO\n"); 899 gpiod_set_consumer_name(sport->cts_gpiod, "CTS"); 900 901 pic32_sports[uart_idx] = sport; 902 port = &sport->port; 903 port->iotype = UPIO_MEM; 904 port->mapbase = res_mem->start; 905 port->ops = &pic32_uart_ops; 906 port->flags = UPF_BOOT_AUTOCONF; 907 port->dev = &pdev->dev; 908 port->fifosize = PIC32_UART_TX_FIFO_DEPTH; 909 port->uartclk = clk_get_rate(sport->clk); 910 port->line = uart_idx; 911 912 ret = uart_add_one_port(&pic32_uart_driver, port); 913 if (ret) { 914 port->membase = NULL; 915 dev_err(port->dev, "%s: uart add port error!\n", __func__); 916 goto err; 917 } 918 919 #ifdef CONFIG_SERIAL_PIC32_CONSOLE 920 if (uart_console_registered(port)) { 921 /* The peripheral clock has been enabled by console_setup, 922 * so disable it till the port is used. 923 */ 924 clk_disable_unprepare(sport->clk); 925 } 926 #endif 927 928 platform_set_drvdata(pdev, port); 929 930 dev_info(&pdev->dev, "%s: uart(%d) driver initialized.\n", 931 __func__, uart_idx); 932 933 return 0; 934 err: 935 /* automatic unroll of sport and gpios */ 936 return ret; 937 } 938 939 static void pic32_uart_remove(struct platform_device *pdev) 940 { 941 struct uart_port *port = platform_get_drvdata(pdev); 942 struct pic32_sport *sport = to_pic32_sport(port); 943 944 uart_remove_one_port(&pic32_uart_driver, port); 945 clk_disable_unprepare(sport->clk); 946 platform_set_drvdata(pdev, NULL); 947 pic32_sports[sport->idx] = NULL; 948 } 949 950 static const struct of_device_id pic32_serial_dt_ids[] = { 951 { .compatible = "microchip,pic32mzda-uart" }, 952 { /* sentinel */ } 953 }; 954 MODULE_DEVICE_TABLE(of, pic32_serial_dt_ids); 955 956 static struct platform_driver pic32_uart_platform_driver = { 957 .probe = pic32_uart_probe, 958 .remove = pic32_uart_remove, 959 .driver = { 960 .name = PIC32_DEV_NAME, 961 .of_match_table = of_match_ptr(pic32_serial_dt_ids), 962 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_PIC32), 963 }, 964 }; 965 966 static int __init pic32_uart_init(void) 967 { 968 int ret; 969 970 ret = uart_register_driver(&pic32_uart_driver); 971 if (ret) { 972 pr_err("failed to register %s:%d\n", 973 pic32_uart_driver.driver_name, ret); 974 return ret; 975 } 976 977 ret = platform_driver_register(&pic32_uart_platform_driver); 978 if (ret) { 979 pr_err("fail to register pic32 uart\n"); 980 uart_unregister_driver(&pic32_uart_driver); 981 } 982 983 return ret; 984 } 985 arch_initcall(pic32_uart_init); 986 987 static void __exit pic32_uart_exit(void) 988 { 989 #ifdef CONFIG_SERIAL_PIC32_CONSOLE 990 unregister_console(&pic32_console); 991 #endif 992 platform_driver_unregister(&pic32_uart_platform_driver); 993 uart_unregister_driver(&pic32_uart_driver); 994 } 995 module_exit(pic32_uart_exit); 996 997 MODULE_AUTHOR("Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>"); 998 MODULE_DESCRIPTION("Microchip PIC32 integrated serial port driver"); 999 MODULE_LICENSE("GPL v2"); 1000