1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2014 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "amdgpu_amdkfd.h" 25 #include "amd_pcie.h" 26 #include "amd_shared.h" 27 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_dma_buf.h" 31 #include <drm/ttm/ttm_tt.h> 32 #include <linux/module.h> 33 #include <linux/dma-buf.h> 34 #include "amdgpu_xgmi.h" 35 #include <uapi/linux/kfd_ioctl.h> 36 #include "amdgpu_ras.h" 37 #include "amdgpu_umc.h" 38 #include "amdgpu_reset.h" 39 40 /* Total memory size in system memory and all GPU VRAM. Used to 41 * estimate worst case amount of memory to reserve for page tables 42 */ 43 uint64_t amdgpu_amdkfd_total_mem_size; 44 45 static bool kfd_initialized; 46 47 int amdgpu_amdkfd_init(void) 48 { 49 struct sysinfo si; 50 int ret; 51 52 si_meminfo(&si); 53 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh; 54 amdgpu_amdkfd_total_mem_size *= si.mem_unit; 55 56 ret = kgd2kfd_init(); 57 kfd_initialized = !ret; 58 59 return ret; 60 } 61 62 void amdgpu_amdkfd_fini(void) 63 { 64 if (kfd_initialized) { 65 kgd2kfd_exit(); 66 kfd_initialized = false; 67 } 68 } 69 70 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) 71 { 72 bool vf = amdgpu_sriov_vf(adev); 73 74 if (!kfd_initialized) 75 return; 76 77 adev->kfd.dev = kgd2kfd_probe(adev, vf); 78 } 79 80 /** 81 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to 82 * setup amdkfd 83 * 84 * @adev: amdgpu_device pointer 85 * @aperture_base: output returning doorbell aperture base physical address 86 * @aperture_size: output returning doorbell aperture size in bytes 87 * @start_offset: output returning # of doorbell bytes reserved for amdgpu. 88 * 89 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, 90 * takes doorbells required for its own rings and reports the setup to amdkfd. 91 * amdgpu reserved doorbells are at the start of the doorbell aperture. 92 */ 93 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 94 phys_addr_t *aperture_base, 95 size_t *aperture_size, 96 size_t *start_offset) 97 { 98 /* 99 * The first num_kernel_doorbells are used by amdgpu. 100 * amdkfd takes whatever's left in the aperture. 101 */ 102 if (adev->enable_mes) { 103 /* 104 * With MES enabled, we only need to initialize 105 * the base address. The size and offset are 106 * not initialized as AMDGPU manages the whole 107 * doorbell space. 108 */ 109 *aperture_base = adev->doorbell.base; 110 *aperture_size = 0; 111 *start_offset = 0; 112 } else if (adev->doorbell.size > adev->doorbell.num_kernel_doorbells * 113 sizeof(u32)) { 114 *aperture_base = adev->doorbell.base; 115 *aperture_size = adev->doorbell.size; 116 *start_offset = adev->doorbell.num_kernel_doorbells * sizeof(u32); 117 } else { 118 *aperture_base = 0; 119 *aperture_size = 0; 120 *start_offset = 0; 121 } 122 } 123 124 125 static void amdgpu_amdkfd_reset_work(struct work_struct *work) 126 { 127 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 128 kfd.reset_work); 129 130 struct amdgpu_reset_context reset_context; 131 132 memset(&reset_context, 0, sizeof(reset_context)); 133 134 reset_context.method = AMD_RESET_METHOD_NONE; 135 reset_context.reset_req_dev = adev; 136 reset_context.src = adev->enable_mes ? 137 AMDGPU_RESET_SRC_MES : 138 AMDGPU_RESET_SRC_HWS; 139 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 140 141 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 142 } 143 144 static const struct drm_client_funcs kfd_client_funcs = { 145 .unregister = drm_client_release, 146 }; 147 148 int amdgpu_amdkfd_drm_client_create(struct amdgpu_device *adev) 149 { 150 int ret; 151 152 if (!adev->kfd.init_complete || adev->kfd.client.dev) 153 return 0; 154 155 ret = drm_client_init(&adev->ddev, &adev->kfd.client, "kfd", 156 &kfd_client_funcs); 157 if (ret) { 158 dev_err(adev->dev, "Failed to init DRM client: %d\n", 159 ret); 160 return ret; 161 } 162 163 drm_client_register(&adev->kfd.client); 164 165 return 0; 166 } 167 168 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 169 { 170 int i; 171 int last_valid_bit; 172 173 amdgpu_amdkfd_gpuvm_init_mem_limits(); 174 175 if (adev->kfd.dev) { 176 struct kgd2kfd_shared_resources gpu_resources = { 177 .compute_vmid_bitmap = 178 ((1 << AMDGPU_NUM_VMID) - 1) - 179 ((1 << adev->vm_manager.first_kfd_vmid) - 1), 180 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, 181 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, 182 .gpuvm_size = min(adev->vm_manager.max_pfn 183 << AMDGPU_GPU_PAGE_SHIFT, 184 AMDGPU_GMC_HOLE_START), 185 .drm_render_minor = adev_to_drm(adev)->render->index, 186 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine, 187 .enable_mes = adev->enable_mes, 188 }; 189 190 /* this is going to have a few of the MSBs set that we need to 191 * clear 192 */ 193 bitmap_complement(gpu_resources.cp_queue_bitmap, 194 adev->gfx.mec_bitmap[0].queue_bitmap, 195 AMDGPU_MAX_QUEUES); 196 197 /* According to linux/bitmap.h we shouldn't use bitmap_clear if 198 * nbits is not compile time constant 199 */ 200 last_valid_bit = 1 /* only first MEC can have compute queues */ 201 * adev->gfx.mec.num_pipe_per_mec 202 * adev->gfx.mec.num_queue_per_pipe; 203 for (i = last_valid_bit; i < AMDGPU_MAX_QUEUES; ++i) 204 clear_bit(i, gpu_resources.cp_queue_bitmap); 205 206 amdgpu_doorbell_get_kfd_info(adev, 207 &gpu_resources.doorbell_physical_address, 208 &gpu_resources.doorbell_aperture_size, 209 &gpu_resources.doorbell_start_offset); 210 211 /* Since SOC15, BIF starts to statically use the 212 * lower 12 bits of doorbell addresses for routing 213 * based on settings in registers like 214 * SDMA0_DOORBELL_RANGE etc.. 215 * In order to route a doorbell to CP engine, the lower 216 * 12 bits of its address has to be outside the range 217 * set for SDMA, VCN, and IH blocks. 218 */ 219 if (adev->asic_type >= CHIP_VEGA10) { 220 gpu_resources.non_cp_doorbells_start = 221 adev->doorbell_index.first_non_cp; 222 gpu_resources.non_cp_doorbells_end = 223 adev->doorbell_index.last_non_cp; 224 } 225 226 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev, 227 &gpu_resources); 228 229 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; 230 231 INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work); 232 } 233 } 234 235 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev) 236 { 237 if (adev->kfd.dev) { 238 kgd2kfd_device_exit(adev->kfd.dev); 239 adev->kfd.dev = NULL; 240 amdgpu_amdkfd_total_mem_size -= adev->gmc.real_vram_size; 241 } 242 } 243 244 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 245 const void *ih_ring_entry) 246 { 247 if (adev->kfd.dev) 248 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); 249 } 250 251 void amdgpu_amdkfd_teardown_processes(struct amdgpu_device *adev) 252 { 253 kgd2kfd_teardown_processes(adev); 254 } 255 256 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc) 257 { 258 if (adev->kfd.dev) { 259 if (adev->in_s0ix) 260 kgd2kfd_stop_sched_all_nodes(adev->kfd.dev); 261 else 262 kgd2kfd_suspend(adev->kfd.dev, suspend_proc); 263 } 264 } 265 266 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc) 267 { 268 int r = 0; 269 270 if (adev->kfd.dev) { 271 if (adev->in_s0ix) 272 r = kgd2kfd_start_sched_all_nodes(adev->kfd.dev); 273 else 274 r = kgd2kfd_resume(adev->kfd.dev, resume_proc); 275 } 276 277 return r; 278 } 279 280 void amdgpu_amdkfd_suspend_process(struct amdgpu_device *adev) 281 { 282 if (adev->kfd.dev) 283 kgd2kfd_suspend_process(adev->kfd.dev); 284 } 285 286 int amdgpu_amdkfd_resume_process(struct amdgpu_device *adev) 287 { 288 int r = 0; 289 290 if (adev->kfd.dev) 291 r = kgd2kfd_resume_process(adev->kfd.dev); 292 293 return r; 294 } 295 296 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev, 297 struct amdgpu_reset_context *reset_context) 298 { 299 int r = 0; 300 301 if (adev->kfd.dev) 302 r = kgd2kfd_pre_reset(adev->kfd.dev, reset_context); 303 304 return r; 305 } 306 307 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) 308 { 309 int r = 0; 310 311 if (adev->kfd.dev) 312 r = kgd2kfd_post_reset(adev->kfd.dev); 313 314 return r; 315 } 316 317 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) 318 { 319 if (amdgpu_device_should_recover_gpu(adev)) 320 (void)amdgpu_reset_domain_schedule(adev->reset_domain, &adev->kfd.reset_work); 321 } 322 323 int amdgpu_amdkfd_alloc_kernel_mem(struct amdgpu_device *adev, size_t size, 324 u32 domain, void **mem_obj, uint64_t *gpu_addr, 325 void **cpu_ptr, bool cp_mqd_gfx9) 326 { 327 struct amdgpu_bo *bo = NULL; 328 struct amdgpu_bo_param bp; 329 int r; 330 void *cpu_ptr_tmp = NULL; 331 332 memset(&bp, 0, sizeof(bp)); 333 bp.size = size; 334 bp.byte_align = PAGE_SIZE; 335 bp.domain = domain; 336 bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | 337 AMDGPU_GEM_CREATE_CPU_GTT_USWC; 338 bp.type = ttm_bo_type_kernel; 339 bp.resv = NULL; 340 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 341 342 if (cp_mqd_gfx9) 343 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9; 344 345 r = amdgpu_bo_create(adev, &bp, &bo); 346 if (r) { 347 dev_err(adev->dev, 348 "failed to allocate BO for amdkfd (%d)\n", r); 349 return r; 350 } 351 352 /* map the buffer */ 353 r = amdgpu_bo_reserve(bo, true); 354 if (r) { 355 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r); 356 goto allocate_mem_reserve_bo_failed; 357 } 358 359 r = amdgpu_bo_pin(bo, domain); 360 if (r) { 361 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); 362 goto allocate_mem_pin_bo_failed; 363 } 364 365 r = amdgpu_ttm_alloc_gart(&bo->tbo); 366 if (r) { 367 dev_err(adev->dev, "%p bind failed\n", bo); 368 goto allocate_mem_kmap_bo_failed; 369 } 370 371 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp); 372 if (r) { 373 dev_err(adev->dev, 374 "(%d) failed to map bo to kernel for amdkfd\n", r); 375 goto allocate_mem_kmap_bo_failed; 376 } 377 378 *mem_obj = bo; 379 *gpu_addr = amdgpu_bo_gpu_offset(bo); 380 *cpu_ptr = cpu_ptr_tmp; 381 382 amdgpu_bo_unreserve(bo); 383 384 return 0; 385 386 allocate_mem_kmap_bo_failed: 387 amdgpu_bo_unpin(bo); 388 allocate_mem_pin_bo_failed: 389 amdgpu_bo_unreserve(bo); 390 allocate_mem_reserve_bo_failed: 391 amdgpu_bo_unref(&bo); 392 393 return r; 394 } 395 396 void amdgpu_amdkfd_free_kernel_mem(struct amdgpu_device *adev, void **mem_obj) 397 { 398 struct amdgpu_bo **bo = (struct amdgpu_bo **) mem_obj; 399 400 if (!bo || !*bo) 401 return; 402 403 (void)amdgpu_bo_reserve(*bo, true); 404 amdgpu_bo_kunmap(*bo); 405 amdgpu_bo_unpin(*bo); 406 amdgpu_bo_unreserve(*bo); 407 amdgpu_bo_unref(bo); 408 } 409 410 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, 411 void **mem_obj) 412 { 413 struct amdgpu_bo *bo = NULL; 414 struct amdgpu_bo_user *ubo; 415 struct amdgpu_bo_param bp; 416 int r; 417 418 memset(&bp, 0, sizeof(bp)); 419 bp.size = size; 420 bp.byte_align = 1; 421 bp.domain = AMDGPU_GEM_DOMAIN_GWS; 422 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 423 bp.type = ttm_bo_type_device; 424 bp.resv = NULL; 425 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 426 427 r = amdgpu_bo_create_user(adev, &bp, &ubo); 428 if (r) { 429 dev_err(adev->dev, 430 "failed to allocate gws BO for amdkfd (%d)\n", r); 431 return r; 432 } 433 434 bo = &ubo->bo; 435 *mem_obj = bo; 436 return 0; 437 } 438 439 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj) 440 { 441 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj; 442 443 amdgpu_bo_unref(&bo); 444 } 445 446 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev, 447 enum kgd_engine_type type) 448 { 449 switch (type) { 450 case KGD_ENGINE_PFP: 451 return adev->gfx.pfp_fw_version; 452 453 case KGD_ENGINE_ME: 454 return adev->gfx.me_fw_version; 455 456 case KGD_ENGINE_CE: 457 return adev->gfx.ce_fw_version; 458 459 case KGD_ENGINE_MEC1: 460 return adev->gfx.mec_fw_version; 461 462 case KGD_ENGINE_MEC2: 463 return adev->gfx.mec2_fw_version; 464 465 case KGD_ENGINE_RLC: 466 return adev->gfx.rlc_fw_version; 467 468 case KGD_ENGINE_SDMA1: 469 return adev->sdma.instance[0].fw_version; 470 471 case KGD_ENGINE_SDMA2: 472 return adev->sdma.instance[1].fw_version; 473 474 default: 475 return 0; 476 } 477 478 return 0; 479 } 480 481 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, 482 struct kfd_local_mem_info *mem_info, 483 struct amdgpu_xcp *xcp) 484 { 485 memset(mem_info, 0, sizeof(*mem_info)); 486 487 if (xcp) { 488 if (adev->gmc.real_vram_size == adev->gmc.visible_vram_size) 489 mem_info->local_mem_size_public = 490 KFD_XCP_MEMORY_SIZE(adev, xcp->id); 491 else 492 mem_info->local_mem_size_private = 493 KFD_XCP_MEMORY_SIZE(adev, xcp->id); 494 } else if (adev->apu_prefer_gtt) { 495 mem_info->local_mem_size_public = (ttm_tt_pages_limit() << PAGE_SHIFT); 496 mem_info->local_mem_size_private = 0; 497 } else { 498 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; 499 mem_info->local_mem_size_private = adev->gmc.real_vram_size - 500 adev->gmc.visible_vram_size; 501 } 502 mem_info->vram_width = adev->gmc.vram_width; 503 504 pr_debug("Address base: %pap public 0x%llx private 0x%llx\n", 505 &adev->gmc.aper_base, 506 mem_info->local_mem_size_public, 507 mem_info->local_mem_size_private); 508 509 if (adev->pm.dpm_enabled) { 510 if (amdgpu_emu_mode == 1) 511 mem_info->mem_clk_max = 0; 512 else 513 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100; 514 } else 515 mem_info->mem_clk_max = 100; 516 } 517 518 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev) 519 { 520 if (adev->gfx.funcs->get_gpu_clock_counter) 521 return adev->gfx.funcs->get_gpu_clock_counter(adev); 522 return 0; 523 } 524 525 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev) 526 { 527 /* the sclk is in quantas of 10kHz */ 528 if (adev->pm.dpm_enabled) 529 return amdgpu_dpm_get_sclk(adev, false) / 100; 530 else 531 return 100; 532 } 533 534 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, 535 struct amdgpu_device **dmabuf_adev, 536 uint64_t *bo_size, void *metadata_buffer, 537 size_t buffer_size, uint32_t *metadata_size, 538 uint32_t *flags, int8_t *xcp_id) 539 { 540 struct dma_buf *dma_buf; 541 struct drm_gem_object *obj; 542 struct amdgpu_bo *bo; 543 uint64_t metadata_flags; 544 int r = -EINVAL; 545 546 dma_buf = dma_buf_get(dma_buf_fd); 547 if (IS_ERR(dma_buf)) 548 return PTR_ERR(dma_buf); 549 550 if (dma_buf->ops != &amdgpu_dmabuf_ops) 551 /* Can't handle non-graphics buffers */ 552 goto out_put; 553 554 obj = dma_buf->priv; 555 if (obj->dev->driver != adev_to_drm(adev)->driver) 556 /* Can't handle buffers from different drivers */ 557 goto out_put; 558 559 adev = drm_to_adev(obj->dev); 560 bo = gem_to_amdgpu_bo(obj); 561 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | 562 AMDGPU_GEM_DOMAIN_GTT))) 563 /* Only VRAM and GTT BOs are supported */ 564 goto out_put; 565 566 r = 0; 567 if (dmabuf_adev) 568 *dmabuf_adev = adev; 569 if (bo_size) 570 *bo_size = amdgpu_bo_size(bo); 571 if (metadata_buffer) 572 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size, 573 metadata_size, &metadata_flags); 574 if (flags) { 575 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 576 KFD_IOC_ALLOC_MEM_FLAGS_VRAM 577 : KFD_IOC_ALLOC_MEM_FLAGS_GTT; 578 579 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 580 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC; 581 } 582 if (xcp_id) 583 *xcp_id = bo->xcp_id; 584 585 out_put: 586 dma_buf_put(dma_buf); 587 return r; 588 } 589 590 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min) 591 { 592 int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) : 593 fls(adev->pm.pcie_mlw_mask)) - 1; 594 int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask & 595 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) : 596 fls(adev->pm.pcie_gen_mask & 597 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1; 598 uint32_t num_lanes_mask = 1 << num_lanes_shift; 599 uint32_t gen_speed_mask = 1 << gen_speed_shift; 600 int num_lanes_factor = 0, gen_speed_mbits_factor = 0; 601 602 switch (num_lanes_mask) { 603 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1: 604 num_lanes_factor = 1; 605 break; 606 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2: 607 num_lanes_factor = 2; 608 break; 609 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4: 610 num_lanes_factor = 4; 611 break; 612 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8: 613 num_lanes_factor = 8; 614 break; 615 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12: 616 num_lanes_factor = 12; 617 break; 618 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16: 619 num_lanes_factor = 16; 620 break; 621 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32: 622 num_lanes_factor = 32; 623 break; 624 } 625 626 switch (gen_speed_mask) { 627 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1: 628 gen_speed_mbits_factor = 2500; 629 break; 630 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2: 631 gen_speed_mbits_factor = 5000; 632 break; 633 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3: 634 gen_speed_mbits_factor = 8000; 635 break; 636 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4: 637 gen_speed_mbits_factor = 16000; 638 break; 639 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5: 640 gen_speed_mbits_factor = 32000; 641 break; 642 } 643 644 return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE; 645 } 646 647 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, 648 enum kgd_engine_type engine, 649 uint32_t vmid, uint64_t gpu_addr, 650 uint32_t *ib_cmd, uint32_t ib_len) 651 { 652 struct amdgpu_job *job; 653 struct amdgpu_ib *ib; 654 struct amdgpu_ring *ring; 655 struct dma_fence *f = NULL; 656 int ret; 657 658 switch (engine) { 659 case KGD_ENGINE_MEC1: 660 ring = &adev->gfx.compute_ring[0]; 661 break; 662 case KGD_ENGINE_SDMA1: 663 ring = &adev->sdma.instance[0].ring; 664 break; 665 case KGD_ENGINE_SDMA2: 666 ring = &adev->sdma.instance[1].ring; 667 break; 668 default: 669 pr_err("Invalid engine in IB submission: %d\n", engine); 670 ret = -EINVAL; 671 goto err; 672 } 673 674 ret = amdgpu_job_alloc(adev, NULL, NULL, NULL, 1, &job, 0); 675 if (ret) 676 goto err; 677 678 ib = &job->ibs[0]; 679 memset(ib, 0, sizeof(struct amdgpu_ib)); 680 681 ib->gpu_addr = gpu_addr; 682 ib->ptr = ib_cmd; 683 ib->length_dw = ib_len; 684 /* This works for NO_HWS. TODO: need to handle without knowing VMID */ 685 job->vmid = vmid; 686 job->num_ibs = 1; 687 688 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); 689 690 if (ret) { 691 drm_err(adev_to_drm(adev), "failed to schedule IB.\n"); 692 goto err_ib_sched; 693 } 694 695 /* Drop the initial kref_init count (see drm_sched_main as example) */ 696 dma_fence_put(f); 697 ret = dma_fence_wait(f, false); 698 699 err_ib_sched: 700 amdgpu_job_free(job); 701 err: 702 return ret; 703 } 704 705 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle) 706 { 707 enum amd_powergating_state state = idle ? AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE; 708 if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 11 && 709 ((adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK) <= 64)) || 710 (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 12)) { 711 pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled"); 712 amdgpu_gfx_off_ctrl(adev, idle); 713 } else if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 9) && 714 (adev->flags & AMD_IS_APU)) { 715 /* Disable GFXOFF and PG. Temporary workaround 716 * to fix some compute applications issue on GFX9. 717 */ 718 struct amdgpu_ip_block *gfx_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); 719 if (gfx_block != NULL) 720 gfx_block->version->funcs->set_powergating_state((void *)gfx_block, state); 721 } 722 (void)amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_COMPUTE, !idle); 723 724 } 725 726 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) 727 { 728 if (adev->kfd.dev) 729 return vmid >= adev->vm_manager.first_kfd_vmid; 730 731 return false; 732 } 733 734 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev) 735 { 736 return adev->have_atomics_support; 737 } 738 739 void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev) 740 { 741 amdgpu_device_flush_hdp(adev, NULL); 742 } 743 744 bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev) 745 { 746 return amdgpu_ras_get_fed_status(adev); 747 } 748 749 void amdgpu_amdkfd_ras_pasid_poison_consumption_handler(struct amdgpu_device *adev, 750 enum amdgpu_ras_block block, uint16_t pasid, 751 pasid_notify pasid_fn, void *data, uint32_t reset) 752 { 753 amdgpu_umc_pasid_poison_handler(adev, block, pasid, pasid_fn, data, reset); 754 } 755 756 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, 757 enum amdgpu_ras_block block, uint32_t reset) 758 { 759 amdgpu_umc_pasid_poison_handler(adev, block, 0, NULL, NULL, reset); 760 } 761 762 int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, 763 uint32_t *payload) 764 { 765 int ret; 766 767 /* Device or IH ring is not ready so bail. */ 768 ret = amdgpu_ih_wait_on_checkpoint_process_ts(adev, &adev->irq.ih); 769 if (ret) 770 return ret; 771 772 /* Send payload to fence KFD interrupts */ 773 amdgpu_amdkfd_interrupt(adev, payload); 774 775 return 0; 776 } 777 778 int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev) 779 { 780 return kgd2kfd_check_and_lock_kfd(adev->kfd.dev); 781 } 782 783 void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev) 784 { 785 kgd2kfd_unlock_kfd(adev->kfd.dev); 786 } 787 788 789 u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id) 790 { 791 s8 mem_id = KFD_XCP_MEM_ID(adev, xcp_id); 792 u64 tmp; 793 794 if (adev->gmc.num_mem_partitions && xcp_id >= 0 && mem_id >= 0) { 795 if (adev->gmc.is_app_apu && adev->gmc.num_mem_partitions == 1) { 796 /* In NPS1 mode, we should restrict the vram reporting 797 * tied to the ttm_pages_limit which is 1/2 of the system 798 * memory. For other partition modes, the HBM is uniformly 799 * divided already per numa node reported. If user wants to 800 * go beyond the default ttm limit and maximize the ROCm 801 * allocations, they can go up to max ttm and sysmem limits. 802 */ 803 804 tmp = (ttm_tt_pages_limit() << PAGE_SHIFT) / num_online_nodes(); 805 } else { 806 tmp = adev->gmc.mem_partitions[mem_id].size; 807 } 808 do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition); 809 return ALIGN_DOWN(tmp, PAGE_SIZE); 810 } else if (adev->apu_prefer_gtt) { 811 return (ttm_tt_pages_limit() << PAGE_SHIFT); 812 } else { 813 return adev->gmc.real_vram_size; 814 } 815 } 816 817 int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off, 818 u32 inst) 819 { 820 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; 821 struct amdgpu_ring *kiq_ring = &kiq->ring; 822 struct amdgpu_ring_funcs *ring_funcs; 823 struct amdgpu_ring *ring; 824 int r = 0; 825 826 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 827 return -EINVAL; 828 829 if (!kiq_ring->sched.ready || amdgpu_in_reset(adev)) 830 return 0; 831 832 ring_funcs = kzalloc_obj(*ring_funcs, GFP_KERNEL); 833 if (!ring_funcs) 834 return -ENOMEM; 835 836 ring = kzalloc_obj(*ring, GFP_KERNEL); 837 if (!ring) { 838 r = -ENOMEM; 839 goto free_ring_funcs; 840 } 841 842 ring_funcs->type = AMDGPU_RING_TYPE_COMPUTE; 843 ring->doorbell_index = doorbell_off; 844 ring->funcs = ring_funcs; 845 846 spin_lock(&kiq->ring_lock); 847 848 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 849 spin_unlock(&kiq->ring_lock); 850 r = -ENOMEM; 851 goto free_ring; 852 } 853 854 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 0, 0); 855 856 /* Submit unmap queue packet */ 857 amdgpu_ring_commit(kiq_ring); 858 /* 859 * Ring test will do a basic scratch register change check. Just run 860 * this to ensure that unmap queues that is submitted before got 861 * processed successfully before returning. 862 */ 863 r = amdgpu_ring_test_helper(kiq_ring); 864 865 spin_unlock(&kiq->ring_lock); 866 867 free_ring: 868 kfree(ring); 869 870 free_ring_funcs: 871 kfree(ring_funcs); 872 873 return r; 874 } 875 876 /* Stop scheduling on KFD */ 877 int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id) 878 { 879 if (!adev->kfd.init_complete) 880 return 0; 881 882 return kgd2kfd_stop_sched(adev->kfd.dev, node_id); 883 } 884 885 /* Start scheduling on KFD */ 886 int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id) 887 { 888 if (!adev->kfd.init_complete) 889 return 0; 890 891 return kgd2kfd_start_sched(adev->kfd.dev, node_id); 892 } 893 894 /* check if there are KFD queues active */ 895 bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id) 896 { 897 if (!adev->kfd.init_complete) 898 return false; 899 900 return kgd2kfd_compute_active(adev->kfd.dev, node_id); 901 } 902 903 /* Config CGTT_SQ_CLK_CTRL */ 904 int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, 905 bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable) 906 { 907 int r; 908 909 if (!adev->kfd.init_complete) 910 return 0; 911 912 r = psp_config_sq_perfmon(&adev->psp, xcp_id, core_override_enable, 913 reg_override_enable, perfmon_override_enable); 914 915 return r; 916 } 917