1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2020 Google Inc 4 * Copyright 2025 Linaro Ltd. 5 * 6 * Samsung S2MPG1x ACPM driver 7 */ 8 9 #include <linux/array_size.h> 10 #include <linux/bitops.h> 11 #include <linux/device.h> 12 #include <linux/firmware/samsung/exynos-acpm-protocol.h> 13 #include <linux/mfd/samsung/core.h> 14 #include <linux/mfd/samsung/rtc.h> 15 #include <linux/mfd/samsung/s2mpg10.h> 16 #include <linux/mfd/samsung/s2mpg11.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm.h> 22 #include <linux/property.h> 23 #include <linux/regmap.h> 24 #include "sec-core.h" 25 26 #define ACPM_ADDR_BITS 8 27 #define ACPM_MAX_BULK_DATA 8 28 29 struct sec_pmic_acpm_platform_data { 30 int device_type; 31 32 unsigned int acpm_chan_id; 33 u8 speedy_channel; 34 35 const struct regmap_config *regmap_cfg_common; 36 const struct regmap_config *regmap_cfg_pmic; 37 const struct regmap_config *regmap_cfg_rtc; 38 const struct regmap_config *regmap_cfg_meter; 39 }; 40 41 static const struct regmap_range s2mpg10_common_registers[] = { 42 regmap_reg_range(0x00, 0x02), /* CHIP_ID_M, INT, INT_MASK */ 43 regmap_reg_range(0x0a, 0x0c), /* Speedy control */ 44 regmap_reg_range(0x1a, 0x2a), /* Debug */ 45 }; 46 47 static const struct regmap_range s2mpg10_common_ro_registers[] = { 48 regmap_reg_range(0x00, 0x01), /* CHIP_ID_M, INT */ 49 regmap_reg_range(0x28, 0x2a), /* Debug */ 50 }; 51 52 static const struct regmap_range s2mpg10_common_nonvolatile_registers[] = { 53 regmap_reg_range(0x00, 0x00), /* CHIP_ID_M */ 54 regmap_reg_range(0x02, 0x02), /* INT_MASK */ 55 regmap_reg_range(0x0a, 0x0c), /* Speedy control */ 56 }; 57 58 static const struct regmap_range s2mpg10_common_precious_registers[] = { 59 regmap_reg_range(0x01, 0x01), /* INT */ 60 }; 61 62 static const struct regmap_access_table s2mpg10_common_wr_table = { 63 .yes_ranges = s2mpg10_common_registers, 64 .n_yes_ranges = ARRAY_SIZE(s2mpg10_common_registers), 65 .no_ranges = s2mpg10_common_ro_registers, 66 .n_no_ranges = ARRAY_SIZE(s2mpg10_common_ro_registers), 67 }; 68 69 static const struct regmap_access_table s2mpg10_common_rd_table = { 70 .yes_ranges = s2mpg10_common_registers, 71 .n_yes_ranges = ARRAY_SIZE(s2mpg10_common_registers), 72 }; 73 74 static const struct regmap_access_table s2mpg10_common_volatile_table = { 75 .no_ranges = s2mpg10_common_nonvolatile_registers, 76 .n_no_ranges = ARRAY_SIZE(s2mpg10_common_nonvolatile_registers), 77 }; 78 79 static const struct regmap_access_table s2mpg10_common_precious_table = { 80 .yes_ranges = s2mpg10_common_precious_registers, 81 .n_yes_ranges = ARRAY_SIZE(s2mpg10_common_precious_registers), 82 }; 83 84 static const struct regmap_config s2mpg10_regmap_config_common = { 85 .name = "common", 86 .reg_bits = ACPM_ADDR_BITS, 87 .val_bits = 8, 88 .max_register = S2MPG10_COMMON_SPD_DEBUG4, 89 .wr_table = &s2mpg10_common_wr_table, 90 .rd_table = &s2mpg10_common_rd_table, 91 .volatile_table = &s2mpg10_common_volatile_table, 92 .precious_table = &s2mpg10_common_precious_table, 93 .num_reg_defaults_raw = S2MPG10_COMMON_SPD_DEBUG4 + 1, 94 .cache_type = REGCACHE_FLAT, 95 }; 96 97 static const struct regmap_range s2mpg10_pmic_registers[] = { 98 regmap_reg_range(0x00, 0xf6), /* All PMIC registers */ 99 }; 100 101 static const struct regmap_range s2mpg10_pmic_ro_registers[] = { 102 regmap_reg_range(0x00, 0x05), /* INTx */ 103 regmap_reg_range(0x0c, 0x0f), /* STATUSx PWRONSRC OFFSRC */ 104 regmap_reg_range(0xc7, 0xc7), /* GPIO input */ 105 }; 106 107 static const struct regmap_range s2mpg10_pmic_nonvolatile_registers[] = { 108 regmap_reg_range(0x06, 0x0b), /* INTxM */ 109 }; 110 111 static const struct regmap_range s2mpg10_pmic_precious_registers[] = { 112 regmap_reg_range(0x00, 0x05), /* INTx */ 113 }; 114 115 static const struct regmap_access_table s2mpg10_pmic_wr_table = { 116 .yes_ranges = s2mpg10_pmic_registers, 117 .n_yes_ranges = ARRAY_SIZE(s2mpg10_pmic_registers), 118 .no_ranges = s2mpg10_pmic_ro_registers, 119 .n_no_ranges = ARRAY_SIZE(s2mpg10_pmic_ro_registers), 120 }; 121 122 static const struct regmap_access_table s2mpg10_pmic_rd_table = { 123 .yes_ranges = s2mpg10_pmic_registers, 124 .n_yes_ranges = ARRAY_SIZE(s2mpg10_pmic_registers), 125 }; 126 127 static const struct regmap_access_table s2mpg10_pmic_volatile_table = { 128 .no_ranges = s2mpg10_pmic_nonvolatile_registers, 129 .n_no_ranges = ARRAY_SIZE(s2mpg10_pmic_nonvolatile_registers), 130 }; 131 132 static const struct regmap_access_table s2mpg10_pmic_precious_table = { 133 .yes_ranges = s2mpg10_pmic_precious_registers, 134 .n_yes_ranges = ARRAY_SIZE(s2mpg10_pmic_precious_registers), 135 }; 136 137 static const struct regmap_config s2mpg10_regmap_config_pmic = { 138 .name = "pmic", 139 .reg_bits = ACPM_ADDR_BITS, 140 .val_bits = 8, 141 .max_register = S2MPG10_PMIC_LDO_SENSE4, 142 .wr_table = &s2mpg10_pmic_wr_table, 143 .rd_table = &s2mpg10_pmic_rd_table, 144 .volatile_table = &s2mpg10_pmic_volatile_table, 145 .precious_table = &s2mpg10_pmic_precious_table, 146 .num_reg_defaults_raw = S2MPG10_PMIC_LDO_SENSE4 + 1, 147 .cache_type = REGCACHE_FLAT, 148 }; 149 150 static const struct regmap_range s2mpg10_rtc_registers[] = { 151 regmap_reg_range(0x00, 0x2b), /* All RTC registers */ 152 }; 153 154 static const struct regmap_range s2mpg10_rtc_volatile_registers[] = { 155 regmap_reg_range(0x01, 0x01), /* RTC_UPDATE */ 156 regmap_reg_range(0x05, 0x0c), /* Time / date */ 157 }; 158 159 static const struct regmap_access_table s2mpg10_rtc_rd_table = { 160 .yes_ranges = s2mpg10_rtc_registers, 161 .n_yes_ranges = ARRAY_SIZE(s2mpg10_rtc_registers), 162 }; 163 164 static const struct regmap_access_table s2mpg10_rtc_volatile_table = { 165 .yes_ranges = s2mpg10_rtc_volatile_registers, 166 .n_yes_ranges = ARRAY_SIZE(s2mpg10_rtc_volatile_registers), 167 }; 168 169 static const struct regmap_config s2mpg10_regmap_config_rtc = { 170 .name = "rtc", 171 .reg_bits = ACPM_ADDR_BITS, 172 .val_bits = 8, 173 .max_register = S2MPG10_RTC_OSC_CTRL, 174 .rd_table = &s2mpg10_rtc_rd_table, 175 .volatile_table = &s2mpg10_rtc_volatile_table, 176 .num_reg_defaults_raw = S2MPG10_RTC_OSC_CTRL + 1, 177 .cache_type = REGCACHE_FLAT, 178 }; 179 180 static const struct regmap_range s2mpg10_meter_registers[] = { 181 regmap_reg_range(0x00, 0x21), /* Meter config */ 182 regmap_reg_range(0x40, 0x8a), /* Meter data */ 183 regmap_reg_range(0xee, 0xee), /* Offset */ 184 regmap_reg_range(0xf1, 0xf1), /* Trim */ 185 }; 186 187 static const struct regmap_range s2mpg10_meter_ro_registers[] = { 188 regmap_reg_range(0x40, 0x8a), /* Meter data */ 189 }; 190 191 static const struct regmap_access_table s2mpg10_meter_wr_table = { 192 .yes_ranges = s2mpg10_meter_registers, 193 .n_yes_ranges = ARRAY_SIZE(s2mpg10_meter_registers), 194 .no_ranges = s2mpg10_meter_ro_registers, 195 .n_no_ranges = ARRAY_SIZE(s2mpg10_meter_ro_registers), 196 }; 197 198 static const struct regmap_access_table s2mpg10_meter_rd_table = { 199 .yes_ranges = s2mpg10_meter_registers, 200 .n_yes_ranges = ARRAY_SIZE(s2mpg10_meter_registers), 201 }; 202 203 static const struct regmap_access_table s2mpg10_meter_volatile_table = { 204 .yes_ranges = s2mpg10_meter_ro_registers, 205 .n_yes_ranges = ARRAY_SIZE(s2mpg10_meter_ro_registers), 206 }; 207 208 static const struct regmap_config s2mpg10_regmap_config_meter = { 209 .name = "meter", 210 .reg_bits = ACPM_ADDR_BITS, 211 .val_bits = 8, 212 .max_register = S2MPG10_METER_BUCK_METER_TRIM3, 213 .wr_table = &s2mpg10_meter_wr_table, 214 .rd_table = &s2mpg10_meter_rd_table, 215 .volatile_table = &s2mpg10_meter_volatile_table, 216 .num_reg_defaults_raw = S2MPG10_METER_BUCK_METER_TRIM3 + 1, 217 .cache_type = REGCACHE_FLAT, 218 }; 219 220 static const struct regmap_range s2mpg11_common_registers[] = { 221 regmap_reg_range(0x00, 0x02), /* CHIP_ID_S, INT, INT_MASK */ 222 regmap_reg_range(0x0a, 0x0c), /* Speedy control */ 223 regmap_reg_range(0x1a, 0x27), /* Debug */ 224 }; 225 226 static const struct regmap_range s2mpg11_common_ro_registers[] = { 227 regmap_reg_range(0x00, 0x01), /* CHIP_ID_S, INT */ 228 regmap_reg_range(0x25, 0x27), /* Debug */ 229 }; 230 231 static const struct regmap_range s2mpg11_common_nonvolatile_registers[] = { 232 regmap_reg_range(0x00, 0x00), /* CHIP_ID_S */ 233 regmap_reg_range(0x02, 0x02), /* INT_MASK */ 234 regmap_reg_range(0x0a, 0x0c), /* Speedy control */ 235 }; 236 237 static const struct regmap_range s2mpg11_common_precious_registers[] = { 238 regmap_reg_range(0x01, 0x01), /* INT */ 239 }; 240 241 static const struct regmap_access_table s2mpg11_common_wr_table = { 242 .yes_ranges = s2mpg11_common_registers, 243 .n_yes_ranges = ARRAY_SIZE(s2mpg11_common_registers), 244 .no_ranges = s2mpg11_common_ro_registers, 245 .n_no_ranges = ARRAY_SIZE(s2mpg11_common_ro_registers), 246 }; 247 248 static const struct regmap_access_table s2mpg11_common_rd_table = { 249 .yes_ranges = s2mpg11_common_registers, 250 .n_yes_ranges = ARRAY_SIZE(s2mpg11_common_registers), 251 }; 252 253 static const struct regmap_access_table s2mpg11_common_volatile_table = { 254 .no_ranges = s2mpg11_common_nonvolatile_registers, 255 .n_no_ranges = ARRAY_SIZE(s2mpg11_common_nonvolatile_registers), 256 }; 257 258 static const struct regmap_access_table s2mpg11_common_precious_table = { 259 .yes_ranges = s2mpg11_common_precious_registers, 260 .n_yes_ranges = ARRAY_SIZE(s2mpg11_common_precious_registers), 261 }; 262 263 static const struct regmap_config s2mpg11_regmap_config_common = { 264 .name = "common", 265 .reg_bits = ACPM_ADDR_BITS, 266 .val_bits = 8, 267 .max_register = S2MPG11_COMMON_SPD_DEBUG4, 268 .wr_table = &s2mpg11_common_wr_table, 269 .rd_table = &s2mpg11_common_rd_table, 270 .volatile_table = &s2mpg11_common_volatile_table, 271 .precious_table = &s2mpg11_common_precious_table, 272 .num_reg_defaults_raw = S2MPG11_COMMON_SPD_DEBUG4 + 1, 273 .cache_type = REGCACHE_FLAT, 274 }; 275 276 static const struct regmap_range s2mpg11_pmic_registers[] = { 277 regmap_reg_range(0x00, 0x5a), /* All PMIC registers */ 278 regmap_reg_range(0x5c, 0xb7), /* All PMIC registers */ 279 }; 280 281 static const struct regmap_range s2mpg11_pmic_ro_registers[] = { 282 regmap_reg_range(0x00, 0x05), /* INTx */ 283 regmap_reg_range(0x0c, 0x0d), /* STATUS OFFSRC */ 284 regmap_reg_range(0x98, 0x98), /* GPIO input */ 285 }; 286 287 static const struct regmap_range s2mpg11_pmic_nonvolatile_registers[] = { 288 regmap_reg_range(0x06, 0x0b), /* INTxM */ 289 }; 290 291 static const struct regmap_range s2mpg11_pmic_precious_registers[] = { 292 regmap_reg_range(0x00, 0x05), /* INTx */ 293 }; 294 295 static const struct regmap_access_table s2mpg11_pmic_wr_table = { 296 .yes_ranges = s2mpg11_pmic_registers, 297 .n_yes_ranges = ARRAY_SIZE(s2mpg11_pmic_registers), 298 .no_ranges = s2mpg11_pmic_ro_registers, 299 .n_no_ranges = ARRAY_SIZE(s2mpg11_pmic_ro_registers), 300 }; 301 302 static const struct regmap_access_table s2mpg11_pmic_rd_table = { 303 .yes_ranges = s2mpg11_pmic_registers, 304 .n_yes_ranges = ARRAY_SIZE(s2mpg11_pmic_registers), 305 }; 306 307 static const struct regmap_access_table s2mpg11_pmic_volatile_table = { 308 .no_ranges = s2mpg11_pmic_nonvolatile_registers, 309 .n_no_ranges = ARRAY_SIZE(s2mpg11_pmic_nonvolatile_registers), 310 }; 311 312 static const struct regmap_access_table s2mpg11_pmic_precious_table = { 313 .yes_ranges = s2mpg11_pmic_precious_registers, 314 .n_yes_ranges = ARRAY_SIZE(s2mpg11_pmic_precious_registers), 315 }; 316 317 static const struct regmap_config s2mpg11_regmap_config_pmic = { 318 .name = "pmic", 319 .reg_bits = ACPM_ADDR_BITS, 320 .val_bits = 8, 321 .max_register = S2MPG11_PMIC_LDO_SENSE2, 322 .wr_table = &s2mpg11_pmic_wr_table, 323 .rd_table = &s2mpg11_pmic_rd_table, 324 .volatile_table = &s2mpg11_pmic_volatile_table, 325 .precious_table = &s2mpg11_pmic_precious_table, 326 .num_reg_defaults_raw = S2MPG11_PMIC_LDO_SENSE2 + 1, 327 .cache_type = REGCACHE_FLAT, 328 }; 329 330 static const struct regmap_range s2mpg11_meter_registers[] = { 331 regmap_reg_range(0x00, 0x3e), /* Meter config */ 332 regmap_reg_range(0x40, 0x8a), /* Meter data */ 333 regmap_reg_range(0x8d, 0x9c), /* Meter data */ 334 }; 335 336 static const struct regmap_range s2mpg11_meter_ro_registers[] = { 337 regmap_reg_range(0x40, 0x9c), /* Meter data */ 338 }; 339 340 static const struct regmap_access_table s2mpg11_meter_wr_table = { 341 .yes_ranges = s2mpg11_meter_registers, 342 .n_yes_ranges = ARRAY_SIZE(s2mpg11_meter_registers), 343 .no_ranges = s2mpg11_meter_ro_registers, 344 .n_no_ranges = ARRAY_SIZE(s2mpg11_meter_ro_registers), 345 }; 346 347 static const struct regmap_access_table s2mpg11_meter_rd_table = { 348 .yes_ranges = s2mpg11_meter_registers, 349 .n_yes_ranges = ARRAY_SIZE(s2mpg11_meter_registers), 350 }; 351 352 static const struct regmap_access_table s2mpg11_meter_volatile_table = { 353 .yes_ranges = s2mpg11_meter_ro_registers, 354 .n_yes_ranges = ARRAY_SIZE(s2mpg11_meter_ro_registers), 355 }; 356 357 static const struct regmap_config s2mpg11_regmap_config_meter = { 358 .name = "meter", 359 .reg_bits = ACPM_ADDR_BITS, 360 .val_bits = 8, 361 .max_register = S2MPG11_METER_LPF_DATA_NTC7_2, 362 .wr_table = &s2mpg11_meter_wr_table, 363 .rd_table = &s2mpg11_meter_rd_table, 364 .volatile_table = &s2mpg11_meter_volatile_table, 365 .num_reg_defaults_raw = S2MPG11_METER_LPF_DATA_NTC7_2 + 1, 366 .cache_type = REGCACHE_FLAT, 367 }; 368 369 struct sec_pmic_acpm_shared_bus_context { 370 const struct acpm_handle *acpm; 371 unsigned int acpm_chan_id; 372 u8 speedy_channel; 373 }; 374 375 enum sec_pmic_acpm_accesstype { 376 SEC_PMIC_ACPM_ACCESSTYPE_COMMON = 0x00, 377 SEC_PMIC_ACPM_ACCESSTYPE_PMIC = 0x01, 378 SEC_PMIC_ACPM_ACCESSTYPE_RTC = 0x02, 379 SEC_PMIC_ACPM_ACCESSTYPE_METER = 0x0a, 380 SEC_PMIC_ACPM_ACCESSTYPE_WLWP = 0x0b, 381 SEC_PMIC_ACPM_ACCESSTYPE_TRIM = 0x0f, 382 }; 383 384 struct sec_pmic_acpm_bus_context { 385 struct sec_pmic_acpm_shared_bus_context *shared; 386 enum sec_pmic_acpm_accesstype type; 387 }; 388 389 static int sec_pmic_acpm_bus_write(void *context, const void *data, 390 size_t count) 391 { 392 struct sec_pmic_acpm_bus_context *ctx = context; 393 const struct acpm_handle *acpm = ctx->shared->acpm; 394 const struct acpm_pmic_ops *pmic_ops = &acpm->ops.pmic_ops; 395 size_t val_count = count - BITS_TO_BYTES(ACPM_ADDR_BITS); 396 const u8 *d = data; 397 const u8 *vals = &d[BITS_TO_BYTES(ACPM_ADDR_BITS)]; 398 u8 reg; 399 400 if (val_count < 1 || val_count > ACPM_MAX_BULK_DATA) 401 return -EINVAL; 402 403 reg = d[0]; 404 405 return pmic_ops->bulk_write(acpm, ctx->shared->acpm_chan_id, ctx->type, reg, 406 ctx->shared->speedy_channel, val_count, vals); 407 } 408 409 static int sec_pmic_acpm_bus_read(void *context, const void *reg_buf, size_t reg_size, 410 void *val_buf, size_t val_size) 411 { 412 struct sec_pmic_acpm_bus_context *ctx = context; 413 const struct acpm_handle *acpm = ctx->shared->acpm; 414 const struct acpm_pmic_ops *pmic_ops = &acpm->ops.pmic_ops; 415 const u8 *r = reg_buf; 416 u8 reg; 417 418 if (reg_size != BITS_TO_BYTES(ACPM_ADDR_BITS) || !val_size || 419 val_size > ACPM_MAX_BULK_DATA) 420 return -EINVAL; 421 422 reg = r[0]; 423 424 return pmic_ops->bulk_read(acpm, ctx->shared->acpm_chan_id, ctx->type, reg, 425 ctx->shared->speedy_channel, val_size, val_buf); 426 } 427 428 static int sec_pmic_acpm_bus_reg_update_bits(void *context, unsigned int reg, unsigned int mask, 429 unsigned int val) 430 { 431 struct sec_pmic_acpm_bus_context *ctx = context; 432 const struct acpm_handle *acpm = ctx->shared->acpm; 433 const struct acpm_pmic_ops *pmic_ops = &acpm->ops.pmic_ops; 434 435 return pmic_ops->update_reg(acpm, ctx->shared->acpm_chan_id, ctx->type, reg & 0xff, 436 ctx->shared->speedy_channel, val, mask); 437 } 438 439 static const struct regmap_bus sec_pmic_acpm_regmap_bus = { 440 .write = sec_pmic_acpm_bus_write, 441 .read = sec_pmic_acpm_bus_read, 442 .reg_update_bits = sec_pmic_acpm_bus_reg_update_bits, 443 .max_raw_read = ACPM_MAX_BULK_DATA, 444 .max_raw_write = ACPM_MAX_BULK_DATA, 445 }; 446 447 static struct regmap *sec_pmic_acpm_regmap_init(struct device *dev, 448 struct sec_pmic_acpm_shared_bus_context *shared_ctx, 449 enum sec_pmic_acpm_accesstype type, 450 const struct regmap_config *cfg, bool do_attach) 451 { 452 struct sec_pmic_acpm_bus_context *ctx; 453 struct regmap *regmap; 454 455 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 456 if (!ctx) 457 return ERR_PTR(-ENOMEM); 458 459 ctx->shared = shared_ctx; 460 ctx->type = type; 461 462 regmap = devm_regmap_init(dev, &sec_pmic_acpm_regmap_bus, ctx, cfg); 463 if (IS_ERR(regmap)) 464 return dev_err_cast_probe(dev, regmap, "regmap init (%s) failed\n", cfg->name); 465 466 if (do_attach) { 467 int ret; 468 469 ret = regmap_attach_dev(dev, regmap, cfg); 470 if (ret) 471 return dev_err_ptr_probe(dev, ret, "regmap attach (%s) failed\n", 472 cfg->name); 473 } 474 475 return regmap; 476 } 477 478 static int sec_pmic_acpm_probe(struct platform_device *pdev) 479 { 480 struct regmap *regmap_common, *regmap_pmic, *regmap; 481 const struct sec_pmic_acpm_platform_data *pdata; 482 struct sec_pmic_acpm_shared_bus_context *shared_ctx; 483 const struct acpm_handle *acpm; 484 struct device *dev = &pdev->dev; 485 int ret, irq; 486 487 pdata = device_get_match_data(dev); 488 if (!pdata) 489 return dev_err_probe(dev, -ENODEV, "unsupported device type\n"); 490 491 acpm = devm_acpm_get_by_node(dev, dev->parent->of_node); 492 if (IS_ERR(acpm)) 493 return dev_err_probe(dev, PTR_ERR(acpm), "failed to get acpm\n"); 494 495 irq = platform_get_irq(pdev, 0); 496 if (irq < 0) 497 return irq; 498 499 shared_ctx = devm_kzalloc(dev, sizeof(*shared_ctx), GFP_KERNEL); 500 if (!shared_ctx) 501 return -ENOMEM; 502 503 shared_ctx->acpm = acpm; 504 shared_ctx->acpm_chan_id = pdata->acpm_chan_id; 505 shared_ctx->speedy_channel = pdata->speedy_channel; 506 507 regmap_common = sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCESSTYPE_COMMON, 508 pdata->regmap_cfg_common, true); 509 if (IS_ERR(regmap_common)) 510 return PTR_ERR(regmap_common); 511 512 regmap_pmic = sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCESSTYPE_PMIC, 513 pdata->regmap_cfg_pmic, false); 514 if (IS_ERR(regmap_pmic)) 515 return PTR_ERR(regmap_pmic); 516 517 if (pdata->regmap_cfg_rtc) { 518 regmap = sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCESSTYPE_RTC, 519 pdata->regmap_cfg_rtc, true); 520 if (IS_ERR(regmap)) 521 return PTR_ERR(regmap); 522 } 523 524 regmap = sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCESSTYPE_METER, 525 pdata->regmap_cfg_meter, true); 526 if (IS_ERR(regmap)) 527 return PTR_ERR(regmap); 528 529 ret = sec_pmic_probe(dev, pdata->device_type, irq, regmap_pmic, NULL); 530 if (ret) 531 return ret; 532 533 if (device_property_read_bool(dev, "wakeup-source")) 534 devm_device_init_wakeup(dev); 535 536 return 0; 537 } 538 539 static void sec_pmic_acpm_shutdown(struct platform_device *pdev) 540 { 541 sec_pmic_shutdown(&pdev->dev); 542 } 543 544 static const struct sec_pmic_acpm_platform_data s2mpg10_data = { 545 .device_type = S2MPG10, 546 .acpm_chan_id = 2, 547 .speedy_channel = 0, 548 .regmap_cfg_common = &s2mpg10_regmap_config_common, 549 .regmap_cfg_pmic = &s2mpg10_regmap_config_pmic, 550 .regmap_cfg_rtc = &s2mpg10_regmap_config_rtc, 551 .regmap_cfg_meter = &s2mpg10_regmap_config_meter, 552 }; 553 554 static const struct sec_pmic_acpm_platform_data s2mpg11_data = { 555 .device_type = S2MPG11, 556 .acpm_chan_id = 2, 557 .speedy_channel = 1, 558 .regmap_cfg_common = &s2mpg11_regmap_config_common, 559 .regmap_cfg_pmic = &s2mpg11_regmap_config_pmic, 560 .regmap_cfg_meter = &s2mpg11_regmap_config_meter, 561 }; 562 563 static const struct of_device_id sec_pmic_acpm_of_match[] = { 564 { .compatible = "samsung,s2mpg10-pmic", .data = &s2mpg10_data, }, 565 { .compatible = "samsung,s2mpg11-pmic", .data = &s2mpg11_data, }, 566 { }, 567 }; 568 MODULE_DEVICE_TABLE(of, sec_pmic_acpm_of_match); 569 570 static struct platform_driver sec_pmic_acpm_driver = { 571 .driver = { 572 .name = "sec-pmic-acpm", 573 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 574 .pm = pm_sleep_ptr(&sec_pmic_pm_ops), 575 .of_match_table = sec_pmic_acpm_of_match, 576 }, 577 .probe = sec_pmic_acpm_probe, 578 .shutdown = sec_pmic_acpm_shutdown, 579 }; 580 module_platform_driver(sec_pmic_acpm_driver); 581 582 MODULE_AUTHOR("André Draszik <andre.draszik@linaro.org>"); 583 MODULE_DESCRIPTION("ACPM driver for the Samsung S2MPG1x"); 584 MODULE_LICENSE("GPL"); 585