1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2014-2018 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #include <linux/dma-buf.h> 24 #include <linux/list.h> 25 #include <linux/pagemap.h> 26 #include <linux/sched/mm.h> 27 #include <linux/sched/task.h> 28 #include <drm/ttm/ttm_tt.h> 29 30 #include <drm/drm_exec.h> 31 32 #include "amdgpu_object.h" 33 #include "amdgpu_gem.h" 34 #include "amdgpu_vm.h" 35 #include "amdgpu_hmm.h" 36 #include "amdgpu_amdkfd.h" 37 #include "amdgpu_dma_buf.h" 38 #include <uapi/linux/kfd_ioctl.h> 39 #include "amdgpu_xgmi.h" 40 #include "kfd_priv.h" 41 #include "kfd_smi_events.h" 42 43 /* Userptr restore delay, just long enough to allow consecutive VM 44 * changes to accumulate 45 */ 46 #define AMDGPU_USERPTR_RESTORE_DELAY_MS 1 47 #define AMDGPU_RESERVE_MEM_LIMIT (3UL << 29) 48 49 /* 50 * Align VRAM availability to 2MB to avoid fragmentation caused by 4K allocations in the tail 2MB 51 * BO chunk 52 */ 53 #define VRAM_AVAILABLITY_ALIGN (1 << 21) 54 55 /* Impose limit on how much memory KFD can use */ 56 static struct { 57 uint64_t max_system_mem_limit; 58 uint64_t max_ttm_mem_limit; 59 int64_t system_mem_used; 60 int64_t ttm_mem_used; 61 spinlock_t mem_limit_lock; 62 } kfd_mem_limit; 63 64 static const char * const domain_bit_to_string[] = { 65 "CPU", 66 "GTT", 67 "VRAM", 68 "GDS", 69 "GWS", 70 "OA" 71 }; 72 73 #define domain_string(domain) domain_bit_to_string[ffs(domain)-1] 74 75 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work); 76 77 static bool kfd_mem_is_attached(struct amdgpu_vm *avm, 78 struct kgd_mem *mem) 79 { 80 struct kfd_mem_attachment *entry; 81 82 list_for_each_entry(entry, &mem->attachments, list) 83 if (entry->bo_va->base.vm == avm) 84 return true; 85 86 return false; 87 } 88 89 /** 90 * reuse_dmamap() - Check whether adev can share the original 91 * userptr BO 92 * 93 * If both adev and bo_adev are in direct mapping or 94 * in the same iommu group, they can share the original BO. 95 * 96 * @adev: Device to which can or cannot share the original BO 97 * @bo_adev: Device to which allocated BO belongs to 98 * 99 * Return: returns true if adev can share original userptr BO, 100 * false otherwise. 101 */ 102 static bool reuse_dmamap(struct amdgpu_device *adev, struct amdgpu_device *bo_adev) 103 { 104 return (adev->ram_is_direct_mapped && bo_adev->ram_is_direct_mapped) || 105 (adev->dev->iommu_group == bo_adev->dev->iommu_group); 106 } 107 108 /* Set memory usage limits. Current, limits are 109 * System (TTM + userptr) memory - 15/16th System RAM 110 * TTM memory - 3/8th System RAM 111 */ 112 void amdgpu_amdkfd_gpuvm_init_mem_limits(void) 113 { 114 struct sysinfo si; 115 uint64_t mem; 116 117 if (kfd_mem_limit.max_system_mem_limit) 118 return; 119 120 si_meminfo(&si); 121 mem = si.totalram - si.totalhigh; 122 mem *= si.mem_unit; 123 124 spin_lock_init(&kfd_mem_limit.mem_limit_lock); 125 kfd_mem_limit.max_system_mem_limit = mem - (mem >> 6); 126 if (kfd_mem_limit.max_system_mem_limit < 2 * AMDGPU_RESERVE_MEM_LIMIT) 127 kfd_mem_limit.max_system_mem_limit >>= 1; 128 else 129 kfd_mem_limit.max_system_mem_limit -= AMDGPU_RESERVE_MEM_LIMIT; 130 131 kfd_mem_limit.max_ttm_mem_limit = ttm_tt_pages_limit() << PAGE_SHIFT; 132 pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n", 133 (kfd_mem_limit.max_system_mem_limit >> 20), 134 (kfd_mem_limit.max_ttm_mem_limit >> 20)); 135 } 136 137 void amdgpu_amdkfd_reserve_system_mem(uint64_t size) 138 { 139 kfd_mem_limit.system_mem_used += size; 140 } 141 142 /* Estimate page table size needed to represent a given memory size 143 * 144 * With 4KB pages, we need one 8 byte PTE for each 4KB of memory 145 * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB 146 * of memory (factor 256K, >> 18). ROCm user mode tries to optimize 147 * for 2MB pages for TLB efficiency. However, small allocations and 148 * fragmented system memory still need some 4KB pages. We choose a 149 * compromise that should work in most cases without reserving too 150 * much memory for page tables unnecessarily (factor 16K, >> 14). 151 */ 152 153 #define ESTIMATE_PT_SIZE(mem_size) max(((mem_size) >> 14), AMDGPU_VM_RESERVED_VRAM) 154 155 /** 156 * amdgpu_amdkfd_reserve_mem_limit() - Decrease available memory by size 157 * of buffer. 158 * 159 * @adev: Device to which allocated BO belongs to 160 * @size: Size of buffer, in bytes, encapsulated by B0. This should be 161 * equivalent to amdgpu_bo_size(BO) 162 * @alloc_flag: Flag used in allocating a BO as noted above 163 * @xcp_id: xcp_id is used to get xcp from xcp manager, one xcp is 164 * managed as one compute node in driver for app 165 * 166 * Return: 167 * returns -ENOMEM in case of error, ZERO otherwise 168 */ 169 int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev, 170 uint64_t size, u32 alloc_flag, int8_t xcp_id) 171 { 172 uint64_t reserved_for_pt = 173 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size); 174 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 175 uint64_t reserved_for_ras = (con ? con->reserved_pages_in_bytes : 0); 176 size_t system_mem_needed, ttm_mem_needed, vram_needed; 177 int ret = 0; 178 uint64_t vram_size = 0; 179 180 system_mem_needed = 0; 181 ttm_mem_needed = 0; 182 vram_needed = 0; 183 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) { 184 system_mem_needed = size; 185 ttm_mem_needed = size; 186 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 187 /* 188 * Conservatively round up the allocation requirement to 2 MB 189 * to avoid fragmentation caused by 4K allocations in the tail 190 * 2M BO chunk. 191 */ 192 vram_needed = size; 193 /* 194 * For GFX 9.4.3, get the VRAM size from XCP structs 195 */ 196 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id)) 197 return -EINVAL; 198 199 vram_size = KFD_XCP_MEMORY_SIZE(adev, xcp_id); 200 if (adev->apu_prefer_gtt) { 201 system_mem_needed = size; 202 ttm_mem_needed = size; 203 } 204 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 205 system_mem_needed = size; 206 } else if (!(alloc_flag & 207 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | 208 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { 209 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag); 210 return -ENOMEM; 211 } 212 213 spin_lock(&kfd_mem_limit.mem_limit_lock); 214 215 if (kfd_mem_limit.system_mem_used + system_mem_needed > 216 kfd_mem_limit.max_system_mem_limit) { 217 pr_debug("Set no_system_mem_limit=1 if using shared memory\n"); 218 if (!no_system_mem_limit) { 219 ret = -ENOMEM; 220 goto release; 221 } 222 } 223 224 if (kfd_mem_limit.ttm_mem_used + ttm_mem_needed > 225 kfd_mem_limit.max_ttm_mem_limit) { 226 ret = -ENOMEM; 227 goto release; 228 } 229 230 /*if is_app_apu is false and apu_prefer_gtt is true, it is an APU with 231 * carve out < gtt. In that case, VRAM allocation will go to gtt domain, skip 232 * VRAM check since ttm_mem_limit check already cover this allocation 233 */ 234 235 if (adev && xcp_id >= 0 && (!adev->apu_prefer_gtt || adev->gmc.is_app_apu)) { 236 uint64_t vram_available = 237 vram_size - reserved_for_pt - reserved_for_ras - 238 atomic64_read(&adev->vram_pin_size); 239 if (adev->kfd.vram_used[xcp_id] + vram_needed > vram_available) { 240 ret = -ENOMEM; 241 goto release; 242 } 243 } 244 245 /* Update memory accounting by decreasing available system 246 * memory, TTM memory and GPU memory as computed above 247 */ 248 WARN_ONCE(vram_needed && !adev, 249 "adev reference can't be null when vram is used"); 250 if (adev && xcp_id >= 0) { 251 adev->kfd.vram_used[xcp_id] += vram_needed; 252 adev->kfd.vram_used_aligned[xcp_id] += 253 adev->apu_prefer_gtt ? 254 vram_needed : 255 ALIGN(vram_needed, VRAM_AVAILABLITY_ALIGN); 256 } 257 kfd_mem_limit.system_mem_used += system_mem_needed; 258 kfd_mem_limit.ttm_mem_used += ttm_mem_needed; 259 260 release: 261 spin_unlock(&kfd_mem_limit.mem_limit_lock); 262 return ret; 263 } 264 265 void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev, 266 uint64_t size, u32 alloc_flag, int8_t xcp_id) 267 { 268 spin_lock(&kfd_mem_limit.mem_limit_lock); 269 270 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) { 271 kfd_mem_limit.system_mem_used -= size; 272 kfd_mem_limit.ttm_mem_used -= size; 273 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 274 WARN_ONCE(!adev, 275 "adev reference can't be null when alloc mem flags vram is set"); 276 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id)) 277 goto release; 278 279 if (adev) { 280 adev->kfd.vram_used[xcp_id] -= size; 281 if (adev->apu_prefer_gtt) { 282 adev->kfd.vram_used_aligned[xcp_id] -= size; 283 kfd_mem_limit.system_mem_used -= size; 284 kfd_mem_limit.ttm_mem_used -= size; 285 } else { 286 adev->kfd.vram_used_aligned[xcp_id] -= 287 ALIGN(size, VRAM_AVAILABLITY_ALIGN); 288 } 289 } 290 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 291 kfd_mem_limit.system_mem_used -= size; 292 } else if (!(alloc_flag & 293 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | 294 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { 295 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag); 296 goto release; 297 } 298 WARN_ONCE(adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] < 0, 299 "KFD VRAM memory accounting unbalanced for xcp: %d", xcp_id); 300 WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0, 301 "KFD TTM memory accounting unbalanced"); 302 WARN_ONCE(kfd_mem_limit.system_mem_used < 0, 303 "KFD system memory accounting unbalanced"); 304 305 release: 306 spin_unlock(&kfd_mem_limit.mem_limit_lock); 307 } 308 309 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) 310 { 311 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 312 u32 alloc_flags = bo->kfd_bo->alloc_flags; 313 u64 size = amdgpu_bo_size(bo); 314 315 amdgpu_amdkfd_unreserve_mem_limit(adev, size, alloc_flags, 316 bo->xcp_id); 317 318 kfree(bo->kfd_bo); 319 } 320 321 /** 322 * create_dmamap_sg_bo() - Creates a amdgpu_bo object to reflect information 323 * about USERPTR or DOOREBELL or MMIO BO. 324 * 325 * @adev: Device for which dmamap BO is being created 326 * @mem: BO of peer device that is being DMA mapped. Provides parameters 327 * in building the dmamap BO 328 * @bo_out: Output parameter updated with handle of dmamap BO 329 */ 330 static int 331 create_dmamap_sg_bo(struct amdgpu_device *adev, 332 struct kgd_mem *mem, struct amdgpu_bo **bo_out) 333 { 334 struct drm_gem_object *gem_obj; 335 int ret; 336 uint64_t flags = 0; 337 338 ret = amdgpu_bo_reserve(mem->bo, false); 339 if (ret) 340 return ret; 341 342 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) 343 flags |= mem->bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 344 AMDGPU_GEM_CREATE_UNCACHED); 345 346 ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, 1, 347 AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE | flags, 348 ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj, 0); 349 350 amdgpu_bo_unreserve(mem->bo); 351 352 if (ret) { 353 pr_err("Error in creating DMA mappable SG BO on domain: %d\n", ret); 354 return -EINVAL; 355 } 356 357 *bo_out = gem_to_amdgpu_bo(gem_obj); 358 (*bo_out)->parent = amdgpu_bo_ref(mem->bo); 359 return ret; 360 } 361 362 /* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's 363 * reservation object. 364 * 365 * @bo: [IN] Remove eviction fence(s) from this BO 366 * @ef: [IN] This eviction fence is removed if it 367 * is present in the shared list. 368 * 369 * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held. 370 */ 371 static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo, 372 struct amdgpu_amdkfd_fence *ef) 373 { 374 struct dma_fence *replacement; 375 376 if (!ef) 377 return -EINVAL; 378 379 /* TODO: Instead of block before we should use the fence of the page 380 * table update and TLB flush here directly. 381 */ 382 replacement = dma_fence_get_stub(); 383 dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context, 384 replacement, DMA_RESV_USAGE_BOOKKEEP); 385 dma_fence_put(replacement); 386 return 0; 387 } 388 389 /** 390 * amdgpu_amdkfd_remove_all_eviction_fences - Remove all eviction fences 391 * @bo: the BO where to remove the evictions fences from. 392 * 393 * This functions should only be used on release when all references to the BO 394 * are already dropped. We remove the eviction fence from the private copy of 395 * the dma_resv object here since that is what is used during release to 396 * determine of the BO is idle or not. 397 */ 398 void amdgpu_amdkfd_remove_all_eviction_fences(struct amdgpu_bo *bo) 399 { 400 struct dma_resv *resv = &bo->tbo.base._resv; 401 struct dma_fence *fence, *stub; 402 struct dma_resv_iter cursor; 403 404 dma_resv_assert_held(resv); 405 406 stub = dma_fence_get_stub(); 407 dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP, fence) { 408 if (!to_amdgpu_amdkfd_fence(fence)) 409 continue; 410 411 dma_resv_replace_fences(resv, fence->context, stub, 412 DMA_RESV_USAGE_BOOKKEEP); 413 } 414 dma_fence_put(stub); 415 } 416 417 static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain, 418 bool wait) 419 { 420 struct ttm_operation_ctx ctx = { false, false }; 421 int ret; 422 423 if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm), 424 "Called with userptr BO")) 425 return -EINVAL; 426 427 /* bo has been pinned, not need validate it */ 428 if (bo->tbo.pin_count) 429 return 0; 430 431 amdgpu_bo_placement_from_domain(bo, domain); 432 433 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 434 if (ret) 435 goto validate_fail; 436 if (wait) 437 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false); 438 439 validate_fail: 440 return ret; 441 } 442 443 int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, 444 uint32_t domain, 445 struct dma_fence *fence) 446 { 447 int ret = amdgpu_bo_reserve(bo, false); 448 449 if (ret) 450 return ret; 451 452 ret = amdgpu_amdkfd_bo_validate(bo, domain, true); 453 if (ret) 454 goto unreserve_out; 455 456 ret = dma_resv_reserve_fences(bo->tbo.base.resv, 1); 457 if (ret) 458 goto unreserve_out; 459 460 dma_resv_add_fence(bo->tbo.base.resv, fence, 461 DMA_RESV_USAGE_BOOKKEEP); 462 463 unreserve_out: 464 amdgpu_bo_unreserve(bo); 465 466 return ret; 467 } 468 469 static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo) 470 { 471 return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false); 472 } 473 474 /* vm_validate_pt_pd_bos - Validate page table and directory BOs 475 * 476 * Page directories are not updated here because huge page handling 477 * during page table updates can invalidate page directory entries 478 * again. Page directories are only updated after updating page 479 * tables. 480 */ 481 static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm, 482 struct ww_acquire_ctx *ticket) 483 { 484 struct amdgpu_bo *pd = vm->root.bo; 485 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev); 486 int ret; 487 488 ret = amdgpu_vm_validate(adev, vm, ticket, 489 amdgpu_amdkfd_validate_vm_bo, NULL); 490 if (ret) { 491 pr_err("failed to validate PT BOs\n"); 492 return ret; 493 } 494 495 vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo); 496 497 return 0; 498 } 499 500 static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync) 501 { 502 struct amdgpu_bo *pd = vm->root.bo; 503 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev); 504 int ret; 505 506 ret = amdgpu_vm_update_pdes(adev, vm, false); 507 if (ret) 508 return ret; 509 510 return amdgpu_sync_fence(sync, vm->last_update, GFP_KERNEL); 511 } 512 513 static uint64_t get_pte_flags(struct amdgpu_device *adev, struct amdgpu_vm *vm, 514 struct kgd_mem *mem) 515 { 516 uint32_t mapping_flags = AMDGPU_VM_PAGE_READABLE | 517 AMDGPU_VM_MTYPE_DEFAULT; 518 519 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE) 520 mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE; 521 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE) 522 mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE; 523 524 return mapping_flags; 525 } 526 527 /** 528 * create_sg_table() - Create an sg_table for a contiguous DMA addr range 529 * @addr: The starting address to point to 530 * @size: Size of memory area in bytes being pointed to 531 * 532 * Allocates an instance of sg_table and initializes it to point to memory 533 * area specified by input parameters. The address used to build is assumed 534 * to be DMA mapped, if needed. 535 * 536 * DOORBELL or MMIO BOs use only one scatterlist node in their sg_table 537 * because they are physically contiguous. 538 * 539 * Return: Initialized instance of SG Table or NULL 540 */ 541 static struct sg_table *create_sg_table(uint64_t addr, uint32_t size) 542 { 543 struct sg_table *sg = kmalloc_obj(*sg, GFP_KERNEL); 544 545 if (!sg) 546 return NULL; 547 if (sg_alloc_table(sg, 1, GFP_KERNEL)) { 548 kfree(sg); 549 return NULL; 550 } 551 sg_dma_address(sg->sgl) = addr; 552 sg->sgl->length = size; 553 #ifdef CONFIG_NEED_SG_DMA_LENGTH 554 sg->sgl->dma_length = size; 555 #endif 556 return sg; 557 } 558 559 static int 560 kfd_mem_dmamap_userptr(struct kgd_mem *mem, 561 struct kfd_mem_attachment *attachment) 562 { 563 enum dma_data_direction direction = 564 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? 565 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 566 struct ttm_operation_ctx ctx = {.interruptible = true}; 567 struct amdgpu_bo *bo = attachment->bo_va->base.bo; 568 struct amdgpu_device *adev = attachment->adev; 569 struct ttm_tt *src_ttm = mem->bo->tbo.ttm; 570 struct ttm_tt *ttm = bo->tbo.ttm; 571 int ret; 572 573 if (WARN_ON(ttm->num_pages != src_ttm->num_pages)) 574 return -EINVAL; 575 576 ttm->sg = kmalloc_obj(*ttm->sg, GFP_KERNEL); 577 if (unlikely(!ttm->sg)) 578 return -ENOMEM; 579 580 /* Same sequence as in amdgpu_ttm_tt_pin_userptr */ 581 ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages, 582 ttm->num_pages, 0, 583 (u64)ttm->num_pages << PAGE_SHIFT, 584 GFP_KERNEL); 585 if (unlikely(ret)) 586 goto free_sg; 587 588 ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 589 if (unlikely(ret)) 590 goto release_sg; 591 592 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 593 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 594 if (ret) 595 goto unmap_sg; 596 597 return 0; 598 599 unmap_sg: 600 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 601 release_sg: 602 pr_err("DMA map userptr failed: %d\n", ret); 603 sg_free_table(ttm->sg); 604 free_sg: 605 kfree(ttm->sg); 606 ttm->sg = NULL; 607 return ret; 608 } 609 610 static int 611 kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment) 612 { 613 struct ttm_operation_ctx ctx = {.interruptible = true}; 614 struct amdgpu_bo *bo = attachment->bo_va->base.bo; 615 616 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 617 return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 618 } 619 620 /** 621 * kfd_mem_dmamap_sg_bo() - Create DMA mapped sg_table to access DOORBELL or MMIO BO 622 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device 623 * @attachment: Virtual address attachment of the BO on accessing device 624 * 625 * An access request from the device that owns DOORBELL does not require DMA mapping. 626 * This is because the request doesn't go through PCIe root complex i.e. it instead 627 * loops back. The need to DMA map arises only when accessing peer device's DOORBELL 628 * 629 * In contrast, all access requests for MMIO need to be DMA mapped without regard to 630 * device ownership. This is because access requests for MMIO go through PCIe root 631 * complex. 632 * 633 * This is accomplished in two steps: 634 * - Obtain DMA mapped address of DOORBELL or MMIO memory that could be used 635 * in updating requesting device's page table 636 * - Signal TTM to mark memory pointed to by requesting device's BO as GPU 637 * accessible. This allows an update of requesting device's page table 638 * with entries associated with DOOREBELL or MMIO memory 639 * 640 * This method is invoked in the following contexts: 641 * - Mapping of DOORBELL or MMIO BO of same or peer device 642 * - Validating an evicted DOOREBELL or MMIO BO on device seeking access 643 * 644 * Return: ZERO if successful, NON-ZERO otherwise 645 */ 646 static int 647 kfd_mem_dmamap_sg_bo(struct kgd_mem *mem, 648 struct kfd_mem_attachment *attachment) 649 { 650 struct ttm_operation_ctx ctx = {.interruptible = true}; 651 struct amdgpu_bo *bo = attachment->bo_va->base.bo; 652 struct amdgpu_device *adev = attachment->adev; 653 struct ttm_tt *ttm = bo->tbo.ttm; 654 enum dma_data_direction dir; 655 dma_addr_t dma_addr; 656 bool mmio; 657 int ret; 658 659 /* Expect SG Table of dmapmap BO to be NULL */ 660 mmio = (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); 661 if (unlikely(ttm->sg)) { 662 pr_err("SG Table of %d BO for peer device is UNEXPECTEDLY NON-NULL", mmio); 663 return -EINVAL; 664 } 665 666 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? 667 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 668 dma_addr = mem->bo->tbo.sg->sgl->dma_address; 669 pr_debug("%d BO size: %d\n", mmio, mem->bo->tbo.sg->sgl->length); 670 pr_debug("%d BO address before DMA mapping: %llx\n", mmio, dma_addr); 671 dma_addr = dma_map_resource(adev->dev, dma_addr, 672 mem->bo->tbo.sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC); 673 ret = dma_mapping_error(adev->dev, dma_addr); 674 if (unlikely(ret)) 675 return ret; 676 pr_debug("%d BO address after DMA mapping: %llx\n", mmio, dma_addr); 677 678 ttm->sg = create_sg_table(dma_addr, mem->bo->tbo.sg->sgl->length); 679 if (unlikely(!ttm->sg)) { 680 ret = -ENOMEM; 681 goto unmap_sg; 682 } 683 684 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 685 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 686 if (unlikely(ret)) 687 goto free_sg; 688 689 return ret; 690 691 free_sg: 692 sg_free_table(ttm->sg); 693 kfree(ttm->sg); 694 ttm->sg = NULL; 695 unmap_sg: 696 dma_unmap_resource(adev->dev, dma_addr, mem->bo->tbo.sg->sgl->length, 697 dir, DMA_ATTR_SKIP_CPU_SYNC); 698 return ret; 699 } 700 701 static int 702 kfd_mem_dmamap_attachment(struct kgd_mem *mem, 703 struct kfd_mem_attachment *attachment) 704 { 705 switch (attachment->type) { 706 case KFD_MEM_ATT_SHARED: 707 return 0; 708 case KFD_MEM_ATT_USERPTR: 709 return kfd_mem_dmamap_userptr(mem, attachment); 710 case KFD_MEM_ATT_DMABUF: 711 return kfd_mem_dmamap_dmabuf(attachment); 712 case KFD_MEM_ATT_SG: 713 return kfd_mem_dmamap_sg_bo(mem, attachment); 714 default: 715 WARN_ON_ONCE(1); 716 } 717 return -EINVAL; 718 } 719 720 static void 721 kfd_mem_dmaunmap_userptr(struct kgd_mem *mem, 722 struct kfd_mem_attachment *attachment) 723 { 724 enum dma_data_direction direction = 725 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? 726 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 727 struct ttm_operation_ctx ctx = {.interruptible = false}; 728 struct amdgpu_bo *bo = attachment->bo_va->base.bo; 729 struct amdgpu_device *adev = attachment->adev; 730 struct ttm_tt *ttm = bo->tbo.ttm; 731 732 if (unlikely(!ttm->sg)) 733 return; 734 735 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 736 (void)ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 737 738 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 739 sg_free_table(ttm->sg); 740 kfree(ttm->sg); 741 ttm->sg = NULL; 742 } 743 744 static void 745 kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment) 746 { 747 /* This is a no-op. We don't want to trigger eviction fences when 748 * unmapping DMABufs. Therefore the invalidation (moving to system 749 * domain) is done in kfd_mem_dmamap_dmabuf. 750 */ 751 } 752 753 /** 754 * kfd_mem_dmaunmap_sg_bo() - Free DMA mapped sg_table of DOORBELL or MMIO BO 755 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device 756 * @attachment: Virtual address attachment of the BO on accessing device 757 * 758 * The method performs following steps: 759 * - Signal TTM to mark memory pointed to by BO as GPU inaccessible 760 * - Free SG Table that is used to encapsulate DMA mapped memory of 761 * peer device's DOORBELL or MMIO memory 762 * 763 * This method is invoked in the following contexts: 764 * UNMapping of DOORBELL or MMIO BO on a device having access to its memory 765 * Eviction of DOOREBELL or MMIO BO on device having access to its memory 766 * 767 * Return: void 768 */ 769 static void 770 kfd_mem_dmaunmap_sg_bo(struct kgd_mem *mem, 771 struct kfd_mem_attachment *attachment) 772 { 773 struct ttm_operation_ctx ctx = {.interruptible = true}; 774 struct amdgpu_bo *bo = attachment->bo_va->base.bo; 775 struct amdgpu_device *adev = attachment->adev; 776 struct ttm_tt *ttm = bo->tbo.ttm; 777 enum dma_data_direction dir; 778 779 if (unlikely(!ttm->sg)) { 780 pr_debug("SG Table of BO is NULL"); 781 return; 782 } 783 784 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 785 (void)ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 786 787 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? 788 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 789 dma_unmap_resource(adev->dev, ttm->sg->sgl->dma_address, 790 ttm->sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC); 791 sg_free_table(ttm->sg); 792 kfree(ttm->sg); 793 ttm->sg = NULL; 794 bo->tbo.sg = NULL; 795 } 796 797 static void 798 kfd_mem_dmaunmap_attachment(struct kgd_mem *mem, 799 struct kfd_mem_attachment *attachment) 800 { 801 switch (attachment->type) { 802 case KFD_MEM_ATT_SHARED: 803 break; 804 case KFD_MEM_ATT_USERPTR: 805 kfd_mem_dmaunmap_userptr(mem, attachment); 806 break; 807 case KFD_MEM_ATT_DMABUF: 808 kfd_mem_dmaunmap_dmabuf(attachment); 809 break; 810 case KFD_MEM_ATT_SG: 811 kfd_mem_dmaunmap_sg_bo(mem, attachment); 812 break; 813 default: 814 WARN_ON_ONCE(1); 815 } 816 } 817 818 static int kfd_mem_export_dmabuf(struct kgd_mem *mem) 819 { 820 if (!mem->dmabuf) { 821 struct amdgpu_device *bo_adev; 822 struct dma_buf *dmabuf; 823 824 bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev); 825 dmabuf = drm_gem_prime_handle_to_dmabuf(&bo_adev->ddev, bo_adev->kfd.client.file, 826 mem->gem_handle, 827 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? 828 DRM_RDWR : 0); 829 if (IS_ERR(dmabuf)) 830 return PTR_ERR(dmabuf); 831 mem->dmabuf = dmabuf; 832 } 833 834 return 0; 835 } 836 837 static int 838 kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, 839 struct amdgpu_bo **bo) 840 { 841 struct drm_gem_object *gobj; 842 int ret; 843 844 ret = kfd_mem_export_dmabuf(mem); 845 if (ret) 846 return ret; 847 848 gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf); 849 if (IS_ERR(gobj)) 850 return PTR_ERR(gobj); 851 852 *bo = gem_to_amdgpu_bo(gobj); 853 (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE; 854 855 return 0; 856 } 857 858 /* kfd_mem_attach - Add a BO to a VM 859 * 860 * Everything that needs to bo done only once when a BO is first added 861 * to a VM. It can later be mapped and unmapped many times without 862 * repeating these steps. 863 * 864 * 0. Create BO for DMA mapping, if needed 865 * 1. Allocate and initialize BO VA entry data structure 866 * 2. Add BO to the VM 867 * 3. Determine ASIC-specific PTE flags 868 * 4. Alloc page tables and directories if needed 869 * 4a. Validate new page tables and directories 870 */ 871 static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, 872 struct amdgpu_vm *vm, bool is_aql) 873 { 874 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev); 875 unsigned long bo_size = mem->bo->tbo.base.size; 876 uint64_t va = mem->va; 877 struct kfd_mem_attachment *attachment[2] = {NULL, NULL}; 878 struct amdgpu_bo *bo[2] = {NULL, NULL}; 879 struct amdgpu_bo_va *bo_va; 880 bool same_hive = false; 881 struct drm_exec exec; 882 int i, ret; 883 884 if (!va) { 885 pr_err("Invalid VA when adding BO to VM\n"); 886 return -EINVAL; 887 } 888 889 /* Determine access to VRAM, MMIO and DOORBELL BOs of peer devices 890 * 891 * The access path of MMIO and DOORBELL BOs of is always over PCIe. 892 * In contrast the access path of VRAM BOs depens upon the type of 893 * link that connects the peer device. Access over PCIe is allowed 894 * if peer device has large BAR. In contrast, access over xGMI is 895 * allowed for both small and large BAR configurations of peer device 896 */ 897 if ((adev != bo_adev && !adev->apu_prefer_gtt) && 898 ((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) || 899 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) || 900 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { 901 if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM) 902 same_hive = amdgpu_xgmi_same_hive(adev, bo_adev); 903 if (!same_hive && !amdgpu_device_is_peer_accessible(bo_adev, adev)) 904 return -EINVAL; 905 } 906 907 for (i = 0; i <= is_aql; i++) { 908 attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL); 909 if (unlikely(!attachment[i])) { 910 ret = -ENOMEM; 911 goto unwind; 912 } 913 914 pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va, 915 va + bo_size, vm); 916 917 if ((adev == bo_adev && !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) || 918 (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && reuse_dmamap(adev, bo_adev)) || 919 (mem->domain == AMDGPU_GEM_DOMAIN_GTT && reuse_dmamap(adev, bo_adev)) || 920 same_hive) { 921 /* Mappings on the local GPU, or VRAM mappings in the 922 * local hive, or userptr, or GTT mapping can reuse dma map 923 * address space share the original BO 924 */ 925 attachment[i]->type = KFD_MEM_ATT_SHARED; 926 bo[i] = mem->bo; 927 drm_gem_object_get(&bo[i]->tbo.base); 928 } else if (i > 0) { 929 /* Multiple mappings on the same GPU share the BO */ 930 attachment[i]->type = KFD_MEM_ATT_SHARED; 931 bo[i] = bo[0]; 932 drm_gem_object_get(&bo[i]->tbo.base); 933 } else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) { 934 /* Create an SG BO to DMA-map userptrs on other GPUs */ 935 attachment[i]->type = KFD_MEM_ATT_USERPTR; 936 ret = create_dmamap_sg_bo(adev, mem, &bo[i]); 937 if (ret) 938 goto unwind; 939 /* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */ 940 } else if (mem->bo->tbo.type == ttm_bo_type_sg) { 941 WARN_ONCE(!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL || 942 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP), 943 "Handing invalid SG BO in ATTACH request"); 944 attachment[i]->type = KFD_MEM_ATT_SG; 945 ret = create_dmamap_sg_bo(adev, mem, &bo[i]); 946 if (ret) 947 goto unwind; 948 /* Enable acces to GTT and VRAM BOs of peer devices */ 949 } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT || 950 mem->domain == AMDGPU_GEM_DOMAIN_VRAM) { 951 attachment[i]->type = KFD_MEM_ATT_DMABUF; 952 ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]); 953 if (ret) 954 goto unwind; 955 pr_debug("Employ DMABUF mechanism to enable peer GPU access\n"); 956 } else { 957 WARN_ONCE(true, "Handling invalid ATTACH request"); 958 ret = -EINVAL; 959 goto unwind; 960 } 961 962 drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0); 963 drm_exec_until_all_locked(&exec) { 964 ret = amdgpu_vm_lock_pd(vm, &exec, 0); 965 drm_exec_retry_on_contention(&exec); 966 if (unlikely(ret)) 967 goto unwind; 968 ret = drm_exec_lock_obj(&exec, &bo[i]->tbo.base); 969 drm_exec_retry_on_contention(&exec); 970 if (unlikely(ret)) 971 goto unwind; 972 } 973 974 bo_va = amdgpu_vm_bo_find(vm, bo[i]); 975 if (!bo_va) 976 bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]); 977 else 978 ++bo_va->ref_count; 979 attachment[i]->bo_va = bo_va; 980 drm_exec_fini(&exec); 981 if (unlikely(!attachment[i]->bo_va)) { 982 ret = -ENOMEM; 983 pr_err("Failed to add BO object to VM. ret == %d\n", 984 ret); 985 goto unwind; 986 } 987 attachment[i]->va = va; 988 attachment[i]->pte_flags = get_pte_flags(adev, vm, mem); 989 attachment[i]->adev = adev; 990 list_add(&attachment[i]->list, &mem->attachments); 991 992 va += bo_size; 993 } 994 995 return 0; 996 997 unwind: 998 for (; i >= 0; i--) { 999 if (!attachment[i]) 1000 continue; 1001 if (attachment[i]->bo_va) { 1002 (void)amdgpu_bo_reserve(bo[i], true); 1003 if (--attachment[i]->bo_va->ref_count == 0) 1004 amdgpu_vm_bo_del(adev, attachment[i]->bo_va); 1005 amdgpu_bo_unreserve(bo[i]); 1006 list_del(&attachment[i]->list); 1007 } 1008 if (bo[i]) 1009 drm_gem_object_put(&bo[i]->tbo.base); 1010 kfree(attachment[i]); 1011 } 1012 return ret; 1013 } 1014 1015 static void kfd_mem_detach(struct kfd_mem_attachment *attachment) 1016 { 1017 struct amdgpu_bo *bo = attachment->bo_va->base.bo; 1018 1019 pr_debug("\t remove VA 0x%llx in entry %p\n", 1020 attachment->va, attachment); 1021 if (--attachment->bo_va->ref_count == 0) 1022 amdgpu_vm_bo_del(attachment->adev, attachment->bo_va); 1023 drm_gem_object_put(&bo->tbo.base); 1024 list_del(&attachment->list); 1025 kfree(attachment); 1026 } 1027 1028 static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem, 1029 struct amdkfd_process_info *process_info, 1030 bool userptr) 1031 { 1032 mutex_lock(&process_info->lock); 1033 if (userptr) 1034 list_add_tail(&mem->validate_list, 1035 &process_info->userptr_valid_list); 1036 else 1037 list_add_tail(&mem->validate_list, &process_info->kfd_bo_list); 1038 mutex_unlock(&process_info->lock); 1039 } 1040 1041 static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem, 1042 struct amdkfd_process_info *process_info) 1043 { 1044 mutex_lock(&process_info->lock); 1045 list_del(&mem->validate_list); 1046 mutex_unlock(&process_info->lock); 1047 } 1048 1049 /* Initializes user pages. It registers the MMU notifier and validates 1050 * the userptr BO in the GTT domain. 1051 * 1052 * The BO must already be on the userptr_valid_list. Otherwise an 1053 * eviction and restore may happen that leaves the new BO unmapped 1054 * with the user mode queues running. 1055 * 1056 * Takes the process_info->lock to protect against concurrent restore 1057 * workers. 1058 * 1059 * Returns 0 for success, negative errno for errors. 1060 */ 1061 static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, 1062 bool criu_resume) 1063 { 1064 struct amdkfd_process_info *process_info = mem->process_info; 1065 struct amdgpu_bo *bo = mem->bo; 1066 struct ttm_operation_ctx ctx = { true, false }; 1067 struct amdgpu_hmm_range *range; 1068 int ret = 0; 1069 1070 mutex_lock(&process_info->lock); 1071 1072 ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0); 1073 if (ret) { 1074 pr_err("%s: Failed to set userptr: %d\n", __func__, ret); 1075 goto out; 1076 } 1077 1078 ret = amdgpu_hmm_register(bo, user_addr); 1079 if (ret) { 1080 pr_err("%s: Failed to register MMU notifier: %d\n", 1081 __func__, ret); 1082 goto out; 1083 } 1084 1085 if (criu_resume) { 1086 /* 1087 * During a CRIU restore operation, the userptr buffer objects 1088 * will be validated in the restore_userptr_work worker at a 1089 * later stage when it is scheduled by another ioctl called by 1090 * CRIU master process for the target pid for restore. 1091 */ 1092 mutex_lock(&process_info->notifier_lock); 1093 mem->invalid++; 1094 mutex_unlock(&process_info->notifier_lock); 1095 mutex_unlock(&process_info->lock); 1096 return 0; 1097 } 1098 1099 range = amdgpu_hmm_range_alloc(NULL); 1100 if (unlikely(!range)) { 1101 ret = -ENOMEM; 1102 goto unregister_out; 1103 } 1104 1105 ret = amdgpu_ttm_tt_get_user_pages(bo, range); 1106 if (ret) { 1107 amdgpu_hmm_range_free(range); 1108 if (ret == -EAGAIN) 1109 pr_debug("Failed to get user pages, try again\n"); 1110 else 1111 pr_err("%s: Failed to get user pages: %d\n", __func__, ret); 1112 goto unregister_out; 1113 } 1114 1115 ret = amdgpu_bo_reserve(bo, true); 1116 if (ret) { 1117 pr_err("%s: Failed to reserve BO\n", __func__); 1118 goto release_out; 1119 } 1120 1121 amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, range); 1122 1123 amdgpu_bo_placement_from_domain(bo, mem->domain); 1124 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1125 if (ret) 1126 pr_err("%s: failed to validate BO\n", __func__); 1127 amdgpu_bo_unreserve(bo); 1128 1129 release_out: 1130 amdgpu_hmm_range_free(range); 1131 unregister_out: 1132 if (ret) 1133 amdgpu_hmm_unregister(bo); 1134 out: 1135 mutex_unlock(&process_info->lock); 1136 return ret; 1137 } 1138 1139 /* Reserving a BO and its page table BOs must happen atomically to 1140 * avoid deadlocks. Some operations update multiple VMs at once. Track 1141 * all the reservation info in a context structure. Optionally a sync 1142 * object can track VM updates. 1143 */ 1144 struct bo_vm_reservation_context { 1145 /* DRM execution context for the reservation */ 1146 struct drm_exec exec; 1147 /* Number of VMs reserved */ 1148 unsigned int n_vms; 1149 /* Pointer to sync object */ 1150 struct amdgpu_sync *sync; 1151 }; 1152 1153 enum bo_vm_match { 1154 BO_VM_NOT_MAPPED = 0, /* Match VMs where a BO is not mapped */ 1155 BO_VM_MAPPED, /* Match VMs where a BO is mapped */ 1156 BO_VM_ALL, /* Match all VMs a BO was added to */ 1157 }; 1158 1159 /** 1160 * reserve_bo_and_vm - reserve a BO and a VM unconditionally. 1161 * @mem: KFD BO structure. 1162 * @vm: the VM to reserve. 1163 * @ctx: the struct that will be used in unreserve_bo_and_vms(). 1164 */ 1165 static int reserve_bo_and_vm(struct kgd_mem *mem, 1166 struct amdgpu_vm *vm, 1167 struct bo_vm_reservation_context *ctx) 1168 { 1169 struct amdgpu_bo *bo = mem->bo; 1170 int ret; 1171 1172 WARN_ON(!vm); 1173 1174 ctx->n_vms = 1; 1175 ctx->sync = &mem->sync; 1176 drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0); 1177 drm_exec_until_all_locked(&ctx->exec) { 1178 ret = amdgpu_vm_lock_pd(vm, &ctx->exec, 2); 1179 drm_exec_retry_on_contention(&ctx->exec); 1180 if (unlikely(ret)) 1181 goto error; 1182 1183 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1); 1184 drm_exec_retry_on_contention(&ctx->exec); 1185 if (unlikely(ret)) 1186 goto error; 1187 } 1188 return 0; 1189 1190 error: 1191 pr_err("Failed to reserve buffers in ttm.\n"); 1192 drm_exec_fini(&ctx->exec); 1193 return ret; 1194 } 1195 1196 /** 1197 * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally 1198 * @mem: KFD BO structure. 1199 * @vm: the VM to reserve. If NULL, then all VMs associated with the BO 1200 * is used. Otherwise, a single VM associated with the BO. 1201 * @map_type: the mapping status that will be used to filter the VMs. 1202 * @ctx: the struct that will be used in unreserve_bo_and_vms(). 1203 * 1204 * Returns 0 for success, negative for failure. 1205 */ 1206 static int reserve_bo_and_cond_vms(struct kgd_mem *mem, 1207 struct amdgpu_vm *vm, enum bo_vm_match map_type, 1208 struct bo_vm_reservation_context *ctx) 1209 { 1210 struct kfd_mem_attachment *entry; 1211 struct amdgpu_bo *bo = mem->bo; 1212 int ret; 1213 1214 ctx->sync = &mem->sync; 1215 drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT | 1216 DRM_EXEC_IGNORE_DUPLICATES, 0); 1217 drm_exec_until_all_locked(&ctx->exec) { 1218 ctx->n_vms = 0; 1219 list_for_each_entry(entry, &mem->attachments, list) { 1220 if ((vm && vm != entry->bo_va->base.vm) || 1221 (entry->is_mapped != map_type 1222 && map_type != BO_VM_ALL)) 1223 continue; 1224 1225 ret = amdgpu_vm_lock_pd(entry->bo_va->base.vm, 1226 &ctx->exec, 2); 1227 drm_exec_retry_on_contention(&ctx->exec); 1228 if (unlikely(ret)) 1229 goto error; 1230 ++ctx->n_vms; 1231 } 1232 1233 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1); 1234 drm_exec_retry_on_contention(&ctx->exec); 1235 if (unlikely(ret)) 1236 goto error; 1237 } 1238 return 0; 1239 1240 error: 1241 pr_err("Failed to reserve buffers in ttm.\n"); 1242 drm_exec_fini(&ctx->exec); 1243 return ret; 1244 } 1245 1246 /** 1247 * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context 1248 * @ctx: Reservation context to unreserve 1249 * @wait: Optionally wait for a sync object representing pending VM updates 1250 * @intr: Whether the wait is interruptible 1251 * 1252 * Also frees any resources allocated in 1253 * reserve_bo_and_(cond_)vm(s). Returns the status from 1254 * amdgpu_sync_wait. 1255 */ 1256 static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx, 1257 bool wait, bool intr) 1258 { 1259 int ret = 0; 1260 1261 if (wait) 1262 ret = amdgpu_sync_wait(ctx->sync, intr); 1263 1264 drm_exec_fini(&ctx->exec); 1265 ctx->sync = NULL; 1266 return ret; 1267 } 1268 1269 static int unmap_bo_from_gpuvm(struct kgd_mem *mem, 1270 struct kfd_mem_attachment *entry, 1271 struct amdgpu_sync *sync) 1272 { 1273 struct amdgpu_bo_va *bo_va = entry->bo_va; 1274 struct amdgpu_device *adev = entry->adev; 1275 struct amdgpu_vm *vm = bo_va->base.vm; 1276 1277 if (bo_va->queue_refcount) { 1278 pr_debug("bo_va->queue_refcount %d\n", bo_va->queue_refcount); 1279 return -EBUSY; 1280 } 1281 1282 (void)amdgpu_vm_bo_unmap(adev, bo_va, entry->va); 1283 1284 /* VM entity stopped if process killed, don't clear freed pt bo */ 1285 if (!amdgpu_vm_ready(vm)) 1286 return 0; 1287 1288 (void)amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update); 1289 1290 (void)amdgpu_sync_fence(sync, bo_va->last_pt_update, GFP_KERNEL); 1291 1292 return 0; 1293 } 1294 1295 static int update_gpuvm_pte(struct kgd_mem *mem, 1296 struct kfd_mem_attachment *entry, 1297 struct amdgpu_sync *sync) 1298 { 1299 struct amdgpu_bo_va *bo_va = entry->bo_va; 1300 struct amdgpu_device *adev = entry->adev; 1301 int ret; 1302 1303 ret = kfd_mem_dmamap_attachment(mem, entry); 1304 if (ret) 1305 return ret; 1306 1307 /* Update the page tables */ 1308 ret = amdgpu_vm_bo_update(adev, bo_va, false); 1309 if (ret) { 1310 pr_err("amdgpu_vm_bo_update failed\n"); 1311 return ret; 1312 } 1313 1314 return amdgpu_sync_fence(sync, bo_va->last_pt_update, GFP_KERNEL); 1315 } 1316 1317 static int map_bo_to_gpuvm(struct kgd_mem *mem, 1318 struct kfd_mem_attachment *entry, 1319 struct amdgpu_sync *sync, 1320 bool no_update_pte) 1321 { 1322 int ret; 1323 1324 /* Set virtual address for the allocation */ 1325 ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0, 1326 amdgpu_bo_size(entry->bo_va->base.bo), 1327 entry->pte_flags); 1328 if (ret) { 1329 pr_err("Failed to map VA 0x%llx in vm. ret %d\n", 1330 entry->va, ret); 1331 return ret; 1332 } 1333 1334 if (no_update_pte) 1335 return 0; 1336 1337 ret = update_gpuvm_pte(mem, entry, sync); 1338 if (ret) { 1339 pr_err("update_gpuvm_pte() failed\n"); 1340 goto update_gpuvm_pte_failed; 1341 } 1342 1343 return 0; 1344 1345 update_gpuvm_pte_failed: 1346 unmap_bo_from_gpuvm(mem, entry, sync); 1347 kfd_mem_dmaunmap_attachment(mem, entry); 1348 return ret; 1349 } 1350 1351 static int process_validate_vms(struct amdkfd_process_info *process_info, 1352 struct ww_acquire_ctx *ticket) 1353 { 1354 struct amdgpu_vm *peer_vm; 1355 int ret; 1356 1357 list_for_each_entry(peer_vm, &process_info->vm_list_head, 1358 vm_list_node) { 1359 ret = vm_validate_pt_pd_bos(peer_vm, ticket); 1360 if (ret) 1361 return ret; 1362 } 1363 1364 return 0; 1365 } 1366 1367 static int process_sync_pds_resv(struct amdkfd_process_info *process_info, 1368 struct amdgpu_sync *sync) 1369 { 1370 struct amdgpu_vm *peer_vm; 1371 int ret; 1372 1373 list_for_each_entry(peer_vm, &process_info->vm_list_head, 1374 vm_list_node) { 1375 struct amdgpu_bo *pd = peer_vm->root.bo; 1376 1377 ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv, 1378 AMDGPU_SYNC_NE_OWNER, 1379 AMDGPU_FENCE_OWNER_KFD); 1380 if (ret) 1381 return ret; 1382 } 1383 1384 return 0; 1385 } 1386 1387 static int process_update_pds(struct amdkfd_process_info *process_info, 1388 struct amdgpu_sync *sync) 1389 { 1390 struct amdgpu_vm *peer_vm; 1391 int ret; 1392 1393 list_for_each_entry(peer_vm, &process_info->vm_list_head, 1394 vm_list_node) { 1395 ret = vm_update_pds(peer_vm, sync); 1396 if (ret) 1397 return ret; 1398 } 1399 1400 return 0; 1401 } 1402 1403 static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, 1404 struct dma_fence **ef) 1405 { 1406 struct amdkfd_process_info *info = NULL; 1407 struct kfd_process *process = NULL; 1408 int ret; 1409 1410 process = container_of(process_info, struct kfd_process, kgd_process_info); 1411 if (!*process_info) { 1412 info = kzalloc_obj(*info, GFP_KERNEL); 1413 if (!info) 1414 return -ENOMEM; 1415 1416 mutex_init(&info->lock); 1417 mutex_init(&info->notifier_lock); 1418 INIT_LIST_HEAD(&info->vm_list_head); 1419 INIT_LIST_HEAD(&info->kfd_bo_list); 1420 INIT_LIST_HEAD(&info->userptr_valid_list); 1421 INIT_LIST_HEAD(&info->userptr_inval_list); 1422 1423 info->eviction_fence = 1424 amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1), 1425 current->mm, 1426 NULL, process->context_id); 1427 if (!info->eviction_fence) { 1428 pr_err("Failed to create eviction fence\n"); 1429 ret = -ENOMEM; 1430 goto create_evict_fence_fail; 1431 } 1432 1433 info->pid = get_task_pid(current, PIDTYPE_TGID); 1434 INIT_DELAYED_WORK(&info->restore_userptr_work, 1435 amdgpu_amdkfd_restore_userptr_worker); 1436 1437 info->context_id = process->context_id; 1438 1439 *process_info = info; 1440 } 1441 1442 vm->process_info = *process_info; 1443 1444 /* Validate page directory and attach eviction fence */ 1445 ret = amdgpu_bo_reserve(vm->root.bo, true); 1446 if (ret) 1447 goto reserve_pd_fail; 1448 ret = vm_validate_pt_pd_bos(vm, NULL); 1449 if (ret) { 1450 pr_err("validate_pt_pd_bos() failed\n"); 1451 goto validate_pd_fail; 1452 } 1453 ret = amdgpu_bo_sync_wait(vm->root.bo, 1454 AMDGPU_FENCE_OWNER_KFD, false); 1455 if (ret) 1456 goto wait_pd_fail; 1457 ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1); 1458 if (ret) 1459 goto reserve_shared_fail; 1460 dma_resv_add_fence(vm->root.bo->tbo.base.resv, 1461 &vm->process_info->eviction_fence->base, 1462 DMA_RESV_USAGE_BOOKKEEP); 1463 amdgpu_bo_unreserve(vm->root.bo); 1464 1465 /* Update process info */ 1466 mutex_lock(&vm->process_info->lock); 1467 list_add_tail(&vm->vm_list_node, 1468 &(vm->process_info->vm_list_head)); 1469 vm->process_info->n_vms++; 1470 if (ef) 1471 *ef = dma_fence_get(&vm->process_info->eviction_fence->base); 1472 mutex_unlock(&vm->process_info->lock); 1473 1474 return 0; 1475 1476 reserve_shared_fail: 1477 wait_pd_fail: 1478 validate_pd_fail: 1479 amdgpu_bo_unreserve(vm->root.bo); 1480 reserve_pd_fail: 1481 vm->process_info = NULL; 1482 if (info) { 1483 dma_fence_put(&info->eviction_fence->base); 1484 *process_info = NULL; 1485 put_pid(info->pid); 1486 create_evict_fence_fail: 1487 mutex_destroy(&info->lock); 1488 mutex_destroy(&info->notifier_lock); 1489 kfree(info); 1490 } 1491 return ret; 1492 } 1493 1494 /** 1495 * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria 1496 * @bo: Handle of buffer object being pinned 1497 * @domain: Domain into which BO should be pinned 1498 * 1499 * - USERPTR BOs are UNPINNABLE and will return error 1500 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their 1501 * PIN count incremented. It is valid to PIN a BO multiple times 1502 * 1503 * Return: ZERO if successful in pinning, Non-Zero in case of error. 1504 */ 1505 static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain) 1506 { 1507 int ret = 0; 1508 1509 ret = amdgpu_bo_reserve(bo, false); 1510 if (unlikely(ret)) 1511 return ret; 1512 1513 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) { 1514 /* 1515 * If bo is not contiguous on VRAM, move to system memory first to ensure 1516 * we can get contiguous VRAM space after evicting other BOs. 1517 */ 1518 if (!(bo->tbo.resource->placement & TTM_PL_FLAG_CONTIGUOUS)) { 1519 struct ttm_operation_ctx ctx = { true, false }; 1520 1521 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 1522 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1523 if (unlikely(ret)) { 1524 pr_debug("validate bo 0x%p to GTT failed %d\n", &bo->tbo, ret); 1525 goto out; 1526 } 1527 } 1528 } 1529 1530 ret = amdgpu_bo_pin(bo, domain); 1531 if (ret) 1532 pr_err("Error in Pinning BO to domain: %d\n", domain); 1533 1534 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false); 1535 out: 1536 amdgpu_bo_unreserve(bo); 1537 return ret; 1538 } 1539 1540 /** 1541 * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria 1542 * @bo: Handle of buffer object being unpinned 1543 * 1544 * - Is a illegal request for USERPTR BOs and is ignored 1545 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their 1546 * PIN count decremented. Calls to UNPIN must balance calls to PIN 1547 */ 1548 static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo) 1549 { 1550 int ret = 0; 1551 1552 ret = amdgpu_bo_reserve(bo, false); 1553 if (unlikely(ret)) 1554 return; 1555 1556 amdgpu_bo_unpin(bo); 1557 amdgpu_bo_unreserve(bo); 1558 } 1559 1560 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev, 1561 struct amdgpu_vm *avm, 1562 void **process_info, 1563 struct dma_fence **ef) 1564 { 1565 int ret; 1566 1567 /* Already a compute VM? */ 1568 if (avm->process_info) 1569 return -EINVAL; 1570 1571 /* Convert VM into a compute VM */ 1572 ret = amdgpu_vm_make_compute(adev, avm); 1573 if (ret) 1574 return ret; 1575 1576 /* Initialize KFD part of the VM and process info */ 1577 ret = init_kfd_vm(avm, process_info, ef); 1578 if (ret) 1579 return ret; 1580 1581 amdgpu_vm_set_task_info(avm); 1582 1583 return 0; 1584 } 1585 1586 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 1587 struct amdgpu_vm *vm) 1588 { 1589 struct amdkfd_process_info *process_info = vm->process_info; 1590 1591 if (!process_info) 1592 return; 1593 1594 /* Update process info */ 1595 mutex_lock(&process_info->lock); 1596 process_info->n_vms--; 1597 list_del(&vm->vm_list_node); 1598 mutex_unlock(&process_info->lock); 1599 1600 vm->process_info = NULL; 1601 1602 /* Release per-process resources when last compute VM is destroyed */ 1603 if (!process_info->n_vms) { 1604 WARN_ON(!list_empty(&process_info->kfd_bo_list)); 1605 WARN_ON(!list_empty(&process_info->userptr_valid_list)); 1606 WARN_ON(!list_empty(&process_info->userptr_inval_list)); 1607 1608 dma_fence_put(&process_info->eviction_fence->base); 1609 cancel_delayed_work_sync(&process_info->restore_userptr_work); 1610 put_pid(process_info->pid); 1611 mutex_destroy(&process_info->lock); 1612 mutex_destroy(&process_info->notifier_lock); 1613 kfree(process_info); 1614 } 1615 } 1616 1617 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv) 1618 { 1619 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); 1620 struct amdgpu_bo *pd = avm->root.bo; 1621 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev); 1622 1623 if (adev->asic_type < CHIP_VEGA10) 1624 return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT; 1625 return avm->pd_phys_addr; 1626 } 1627 1628 void amdgpu_amdkfd_block_mmu_notifications(void *p) 1629 { 1630 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p; 1631 1632 mutex_lock(&pinfo->lock); 1633 WRITE_ONCE(pinfo->block_mmu_notifications, true); 1634 mutex_unlock(&pinfo->lock); 1635 } 1636 1637 int amdgpu_amdkfd_criu_resume(void *p) 1638 { 1639 int ret = 0; 1640 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p; 1641 1642 mutex_lock(&pinfo->lock); 1643 pr_debug("scheduling work\n"); 1644 mutex_lock(&pinfo->notifier_lock); 1645 pinfo->evicted_bos++; 1646 mutex_unlock(&pinfo->notifier_lock); 1647 if (!READ_ONCE(pinfo->block_mmu_notifications)) { 1648 ret = -EINVAL; 1649 goto out_unlock; 1650 } 1651 WRITE_ONCE(pinfo->block_mmu_notifications, false); 1652 queue_delayed_work(system_freezable_wq, 1653 &pinfo->restore_userptr_work, 0); 1654 1655 out_unlock: 1656 mutex_unlock(&pinfo->lock); 1657 return ret; 1658 } 1659 1660 size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, 1661 uint8_t xcp_id) 1662 { 1663 uint64_t reserved_for_pt = 1664 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size); 1665 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1666 uint64_t reserved_for_ras = (con ? con->reserved_pages_in_bytes : 0); 1667 ssize_t available; 1668 uint64_t vram_available, system_mem_available, ttm_mem_available; 1669 1670 spin_lock(&kfd_mem_limit.mem_limit_lock); 1671 if (adev->apu_prefer_gtt && !adev->gmc.is_app_apu) 1672 vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id) 1673 - adev->kfd.vram_used_aligned[xcp_id]; 1674 else 1675 vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id) 1676 - adev->kfd.vram_used_aligned[xcp_id] 1677 - atomic64_read(&adev->vram_pin_size) 1678 - reserved_for_pt 1679 - reserved_for_ras; 1680 1681 if (adev->apu_prefer_gtt) { 1682 system_mem_available = no_system_mem_limit ? 1683 kfd_mem_limit.max_system_mem_limit : 1684 kfd_mem_limit.max_system_mem_limit - 1685 kfd_mem_limit.system_mem_used; 1686 1687 ttm_mem_available = kfd_mem_limit.max_ttm_mem_limit - 1688 kfd_mem_limit.ttm_mem_used; 1689 1690 available = min3(system_mem_available, ttm_mem_available, 1691 vram_available); 1692 available = ALIGN_DOWN(available, PAGE_SIZE); 1693 } else { 1694 available = ALIGN_DOWN(vram_available, VRAM_AVAILABLITY_ALIGN); 1695 } 1696 1697 spin_unlock(&kfd_mem_limit.mem_limit_lock); 1698 1699 if (available < 0) 1700 available = 0; 1701 1702 return available; 1703 } 1704 1705 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 1706 struct amdgpu_device *adev, uint64_t va, uint64_t size, 1707 void *drm_priv, struct kgd_mem **mem, 1708 uint64_t *offset, uint32_t flags, bool criu_resume) 1709 { 1710 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); 1711 struct amdgpu_fpriv *fpriv = container_of(avm, struct amdgpu_fpriv, vm); 1712 enum ttm_bo_type bo_type = ttm_bo_type_device; 1713 struct sg_table *sg = NULL; 1714 uint64_t user_addr = 0; 1715 struct amdgpu_bo *bo; 1716 struct drm_gem_object *gobj = NULL; 1717 u32 domain, alloc_domain; 1718 uint64_t aligned_size; 1719 int8_t xcp_id = -1; 1720 u64 alloc_flags; 1721 int ret; 1722 1723 /* 1724 * Check on which domain to allocate BO 1725 */ 1726 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 1727 domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM; 1728 1729 if (adev->apu_prefer_gtt) { 1730 domain = AMDGPU_GEM_DOMAIN_GTT; 1731 alloc_domain = AMDGPU_GEM_DOMAIN_GTT; 1732 alloc_flags = 0; 1733 } else { 1734 alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; 1735 alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ? 1736 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0; 1737 1738 /* For contiguous VRAM allocation */ 1739 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_CONTIGUOUS) 1740 alloc_flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 1741 } 1742 xcp_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ? 1743 0 : fpriv->xcp_id; 1744 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) { 1745 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT; 1746 alloc_flags = 0; 1747 } else { 1748 domain = AMDGPU_GEM_DOMAIN_GTT; 1749 alloc_domain = AMDGPU_GEM_DOMAIN_CPU; 1750 alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE; 1751 1752 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 1753 if (!offset || !*offset) 1754 return -EINVAL; 1755 user_addr = untagged_addr(*offset); 1756 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | 1757 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) { 1758 bo_type = ttm_bo_type_sg; 1759 if (size > UINT_MAX) 1760 return -EINVAL; 1761 sg = create_sg_table(*offset, size); 1762 if (!sg) 1763 return -ENOMEM; 1764 } else { 1765 return -EINVAL; 1766 } 1767 } 1768 1769 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT) 1770 alloc_flags |= AMDGPU_GEM_CREATE_COHERENT; 1771 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_EXT_COHERENT) 1772 alloc_flags |= AMDGPU_GEM_CREATE_EXT_COHERENT; 1773 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED) 1774 alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED; 1775 1776 *mem = kzalloc_obj(struct kgd_mem, GFP_KERNEL); 1777 if (!*mem) { 1778 ret = -ENOMEM; 1779 goto err; 1780 } 1781 INIT_LIST_HEAD(&(*mem)->attachments); 1782 mutex_init(&(*mem)->lock); 1783 (*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM); 1784 1785 /* Workaround for AQL queue wraparound bug. Map the same 1786 * memory twice. That means we only actually allocate half 1787 * the memory. 1788 */ 1789 if ((*mem)->aql_queue) 1790 size >>= 1; 1791 aligned_size = PAGE_ALIGN(size); 1792 1793 (*mem)->alloc_flags = flags; 1794 1795 amdgpu_sync_create(&(*mem)->sync); 1796 1797 ret = amdgpu_amdkfd_reserve_mem_limit(adev, aligned_size, flags, 1798 xcp_id); 1799 if (ret) { 1800 pr_debug("Insufficient memory\n"); 1801 goto err_reserve_limit; 1802 } 1803 1804 pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s xcp_id %d\n", 1805 va, (*mem)->aql_queue ? size << 1 : size, 1806 domain_string(alloc_domain), xcp_id); 1807 1808 ret = amdgpu_gem_object_create(adev, aligned_size, 1, alloc_domain, alloc_flags, 1809 bo_type, NULL, &gobj, xcp_id + 1); 1810 if (ret) { 1811 pr_debug("Failed to create BO on domain %s. ret %d\n", 1812 domain_string(alloc_domain), ret); 1813 goto err_bo_create; 1814 } 1815 ret = drm_vma_node_allow(&gobj->vma_node, drm_priv); 1816 if (ret) { 1817 pr_debug("Failed to allow vma node access. ret %d\n", ret); 1818 goto err_node_allow; 1819 } 1820 ret = drm_gem_handle_create(adev->kfd.client.file, gobj, &(*mem)->gem_handle); 1821 if (ret) 1822 goto err_gem_handle_create; 1823 bo = gem_to_amdgpu_bo(gobj); 1824 if (bo_type == ttm_bo_type_sg) { 1825 bo->tbo.sg = sg; 1826 bo->tbo.ttm->sg = sg; 1827 } 1828 bo->kfd_bo = *mem; 1829 (*mem)->bo = bo; 1830 if (user_addr) 1831 bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO; 1832 1833 (*mem)->va = va; 1834 (*mem)->domain = domain; 1835 (*mem)->mapped_to_gpu_memory = 0; 1836 (*mem)->process_info = avm->process_info; 1837 1838 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr); 1839 1840 if (user_addr) { 1841 pr_debug("creating userptr BO for user_addr = %llx\n", user_addr); 1842 ret = init_user_pages(*mem, user_addr, criu_resume); 1843 if (ret) 1844 goto allocate_init_user_pages_failed; 1845 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | 1846 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) { 1847 ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT); 1848 if (ret) { 1849 pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n"); 1850 goto err_pin_bo; 1851 } 1852 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 1853 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 1854 } else { 1855 mutex_lock(&avm->process_info->lock); 1856 if (avm->process_info->eviction_fence && 1857 !dma_fence_is_signaled(&avm->process_info->eviction_fence->base)) 1858 ret = amdgpu_amdkfd_bo_validate_and_fence(bo, domain, 1859 &avm->process_info->eviction_fence->base); 1860 mutex_unlock(&avm->process_info->lock); 1861 if (ret) 1862 goto err_validate_bo; 1863 } 1864 1865 if (offset) 1866 *offset = amdgpu_bo_mmap_offset(bo); 1867 1868 return 0; 1869 1870 allocate_init_user_pages_failed: 1871 err_pin_bo: 1872 err_validate_bo: 1873 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info); 1874 drm_gem_handle_delete(adev->kfd.client.file, (*mem)->gem_handle); 1875 err_gem_handle_create: 1876 drm_vma_node_revoke(&gobj->vma_node, drm_priv); 1877 err_node_allow: 1878 /* Don't unreserve system mem limit twice */ 1879 goto err_reserve_limit; 1880 err_bo_create: 1881 amdgpu_amdkfd_unreserve_mem_limit(adev, aligned_size, flags, xcp_id); 1882 err_reserve_limit: 1883 amdgpu_sync_free(&(*mem)->sync); 1884 mutex_destroy(&(*mem)->lock); 1885 if (gobj) 1886 drm_gem_object_put(gobj); 1887 else 1888 kfree(*mem); 1889 err: 1890 if (sg) { 1891 sg_free_table(sg); 1892 kfree(sg); 1893 } 1894 return ret; 1895 } 1896 1897 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( 1898 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv, 1899 uint64_t *size) 1900 { 1901 struct amdkfd_process_info *process_info = mem->process_info; 1902 unsigned long bo_size = mem->bo->tbo.base.size; 1903 bool use_release_notifier = (mem->bo->kfd_bo == mem); 1904 struct kfd_mem_attachment *entry, *tmp; 1905 struct bo_vm_reservation_context ctx; 1906 unsigned int mapped_to_gpu_memory; 1907 int ret; 1908 bool is_imported = false; 1909 1910 mutex_lock(&mem->lock); 1911 1912 /* Unpin MMIO/DOORBELL BO's that were pinned during allocation */ 1913 if (mem->alloc_flags & 1914 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | 1915 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) { 1916 amdgpu_amdkfd_gpuvm_unpin_bo(mem->bo); 1917 } 1918 1919 mapped_to_gpu_memory = mem->mapped_to_gpu_memory; 1920 is_imported = mem->is_imported; 1921 mutex_unlock(&mem->lock); 1922 /* lock is not needed after this, since mem is unused and will 1923 * be freed anyway 1924 */ 1925 1926 if (mapped_to_gpu_memory > 0) { 1927 pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n", 1928 mem->va, bo_size); 1929 return -EBUSY; 1930 } 1931 1932 /* Make sure restore workers don't access the BO any more */ 1933 mutex_lock(&process_info->lock); 1934 if (!list_empty(&mem->validate_list)) 1935 list_del_init(&mem->validate_list); 1936 mutex_unlock(&process_info->lock); 1937 1938 ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx); 1939 if (unlikely(ret)) 1940 return ret; 1941 1942 /* Cleanup user pages and MMU notifiers */ 1943 if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) { 1944 amdgpu_hmm_unregister(mem->bo); 1945 amdgpu_hmm_range_free(mem->range); 1946 mem->range = NULL; 1947 } 1948 1949 amdgpu_amdkfd_remove_eviction_fence(mem->bo, 1950 process_info->eviction_fence); 1951 pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va, 1952 mem->va + bo_size * (1 + mem->aql_queue)); 1953 1954 /* Remove from VM internal data structures */ 1955 list_for_each_entry_safe(entry, tmp, &mem->attachments, list) { 1956 kfd_mem_dmaunmap_attachment(mem, entry); 1957 kfd_mem_detach(entry); 1958 } 1959 1960 ret = unreserve_bo_and_vms(&ctx, false, false); 1961 1962 /* Free the sync object */ 1963 amdgpu_sync_free(&mem->sync); 1964 1965 /* If the SG is not NULL, it's one we created for a doorbell or mmio 1966 * remap BO. We need to free it. 1967 */ 1968 if (mem->bo->tbo.sg) { 1969 sg_free_table(mem->bo->tbo.sg); 1970 kfree(mem->bo->tbo.sg); 1971 } 1972 1973 /* Update the size of the BO being freed if it was allocated from 1974 * VRAM and is not imported. For APP APU VRAM allocations are done 1975 * in GTT domain 1976 */ 1977 if (size) { 1978 if (!is_imported && 1979 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) 1980 *size = bo_size; 1981 else 1982 *size = 0; 1983 } 1984 1985 /* Free the BO*/ 1986 drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv); 1987 drm_gem_handle_delete(adev->kfd.client.file, mem->gem_handle); 1988 if (mem->dmabuf) { 1989 dma_buf_put(mem->dmabuf); 1990 mem->dmabuf = NULL; 1991 } 1992 mutex_destroy(&mem->lock); 1993 1994 /* If this releases the last reference, it will end up calling 1995 * amdgpu_amdkfd_release_notify and kfree the mem struct. That's why 1996 * this needs to be the last call here. 1997 */ 1998 drm_gem_object_put(&mem->bo->tbo.base); 1999 2000 /* 2001 * For kgd_mem allocated in import_obj_create() via 2002 * amdgpu_amdkfd_gpuvm_import_dmabuf_fd(), 2003 * explicitly free it here. 2004 */ 2005 if (!use_release_notifier) 2006 kfree(mem); 2007 2008 return ret; 2009 } 2010 2011 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu( 2012 struct amdgpu_device *adev, struct kgd_mem *mem, 2013 void *drm_priv) 2014 { 2015 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); 2016 int ret; 2017 struct amdgpu_bo *bo; 2018 uint32_t domain; 2019 struct kfd_mem_attachment *entry; 2020 struct bo_vm_reservation_context ctx; 2021 unsigned long bo_size; 2022 bool is_invalid_userptr = false; 2023 2024 bo = mem->bo; 2025 if (!bo) { 2026 pr_err("Invalid BO when mapping memory to GPU\n"); 2027 return -EINVAL; 2028 } 2029 2030 /* Make sure restore is not running concurrently. Since we 2031 * don't map invalid userptr BOs, we rely on the next restore 2032 * worker to do the mapping 2033 */ 2034 mutex_lock(&mem->process_info->lock); 2035 2036 /* Lock notifier lock. If we find an invalid userptr BO, we can be 2037 * sure that the MMU notifier is no longer running 2038 * concurrently and the queues are actually stopped 2039 */ 2040 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) { 2041 mutex_lock(&mem->process_info->notifier_lock); 2042 is_invalid_userptr = !!mem->invalid; 2043 mutex_unlock(&mem->process_info->notifier_lock); 2044 } 2045 2046 mutex_lock(&mem->lock); 2047 2048 domain = mem->domain; 2049 bo_size = bo->tbo.base.size; 2050 2051 pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n", 2052 mem->va, 2053 mem->va + bo_size * (1 + mem->aql_queue), 2054 avm, domain_string(domain)); 2055 2056 if (!kfd_mem_is_attached(avm, mem)) { 2057 ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue); 2058 if (ret) 2059 goto out; 2060 } 2061 2062 ret = reserve_bo_and_vm(mem, avm, &ctx); 2063 if (unlikely(ret)) 2064 goto out; 2065 2066 /* Userptr can be marked as "not invalid", but not actually be 2067 * validated yet (still in the system domain). In that case 2068 * the queues are still stopped and we can leave mapping for 2069 * the next restore worker 2070 */ 2071 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && 2072 bo->tbo.resource->mem_type == TTM_PL_SYSTEM) 2073 is_invalid_userptr = true; 2074 2075 ret = vm_validate_pt_pd_bos(avm, NULL); 2076 if (unlikely(ret)) 2077 goto out_unreserve; 2078 2079 list_for_each_entry(entry, &mem->attachments, list) { 2080 if (entry->bo_va->base.vm != avm || entry->is_mapped) 2081 continue; 2082 2083 pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n", 2084 entry->va, entry->va + bo_size, entry); 2085 2086 ret = map_bo_to_gpuvm(mem, entry, ctx.sync, 2087 is_invalid_userptr); 2088 if (ret) { 2089 pr_err("Failed to map bo to gpuvm\n"); 2090 goto out_unreserve; 2091 } 2092 2093 ret = vm_update_pds(avm, ctx.sync); 2094 if (ret) { 2095 pr_err("Failed to update page directories\n"); 2096 goto out_unreserve; 2097 } 2098 2099 entry->is_mapped = true; 2100 mem->mapped_to_gpu_memory++; 2101 pr_debug("\t INC mapping count %d\n", 2102 mem->mapped_to_gpu_memory); 2103 } 2104 2105 ret = unreserve_bo_and_vms(&ctx, false, false); 2106 2107 goto out; 2108 2109 out_unreserve: 2110 unreserve_bo_and_vms(&ctx, false, false); 2111 out: 2112 mutex_unlock(&mem->process_info->lock); 2113 mutex_unlock(&mem->lock); 2114 return ret; 2115 } 2116 2117 int amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv) 2118 { 2119 struct kfd_mem_attachment *entry; 2120 struct amdgpu_vm *vm; 2121 int ret; 2122 2123 vm = drm_priv_to_vm(drm_priv); 2124 2125 mutex_lock(&mem->lock); 2126 2127 ret = amdgpu_bo_reserve(mem->bo, true); 2128 if (ret) 2129 goto out; 2130 2131 list_for_each_entry(entry, &mem->attachments, list) { 2132 if (entry->bo_va->base.vm != vm) 2133 continue; 2134 if (entry->bo_va->base.bo->tbo.ttm && 2135 !entry->bo_va->base.bo->tbo.ttm->sg) 2136 continue; 2137 2138 kfd_mem_dmaunmap_attachment(mem, entry); 2139 } 2140 2141 amdgpu_bo_unreserve(mem->bo); 2142 out: 2143 mutex_unlock(&mem->lock); 2144 2145 return ret; 2146 } 2147 2148 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 2149 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv) 2150 { 2151 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); 2152 unsigned long bo_size = mem->bo->tbo.base.size; 2153 struct kfd_mem_attachment *entry; 2154 struct bo_vm_reservation_context ctx; 2155 int ret; 2156 2157 mutex_lock(&mem->lock); 2158 2159 ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx); 2160 if (unlikely(ret)) 2161 goto out; 2162 /* If no VMs were reserved, it means the BO wasn't actually mapped */ 2163 if (ctx.n_vms == 0) { 2164 ret = -EINVAL; 2165 goto unreserve_out; 2166 } 2167 2168 ret = vm_validate_pt_pd_bos(avm, NULL); 2169 if (unlikely(ret)) 2170 goto unreserve_out; 2171 2172 pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n", 2173 mem->va, 2174 mem->va + bo_size * (1 + mem->aql_queue), 2175 avm); 2176 2177 list_for_each_entry(entry, &mem->attachments, list) { 2178 if (entry->bo_va->base.vm != avm || !entry->is_mapped) 2179 continue; 2180 2181 pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n", 2182 entry->va, entry->va + bo_size, entry); 2183 2184 ret = unmap_bo_from_gpuvm(mem, entry, ctx.sync); 2185 if (ret) 2186 goto unreserve_out; 2187 2188 entry->is_mapped = false; 2189 2190 mem->mapped_to_gpu_memory--; 2191 pr_debug("\t DEC mapping count %d\n", 2192 mem->mapped_to_gpu_memory); 2193 } 2194 2195 unreserve_out: 2196 unreserve_bo_and_vms(&ctx, false, false); 2197 out: 2198 mutex_unlock(&mem->lock); 2199 return ret; 2200 } 2201 2202 int amdgpu_amdkfd_gpuvm_sync_memory( 2203 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr) 2204 { 2205 struct amdgpu_sync sync; 2206 int ret; 2207 2208 amdgpu_sync_create(&sync); 2209 2210 mutex_lock(&mem->lock); 2211 amdgpu_sync_clone(&mem->sync, &sync); 2212 mutex_unlock(&mem->lock); 2213 2214 ret = amdgpu_sync_wait(&sync, intr); 2215 amdgpu_sync_free(&sync); 2216 return ret; 2217 } 2218 2219 /** 2220 * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference count 2221 * @bo: Buffer object to be mapped 2222 * @bo_gart: Return bo reference 2223 * 2224 * Before return, bo reference count is incremented. To release the reference and unpin/ 2225 * unmap the BO, call amdgpu_amdkfd_free_kernel_mem. 2226 */ 2227 int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo, struct amdgpu_bo **bo_gart) 2228 { 2229 int ret; 2230 2231 ret = amdgpu_bo_reserve(bo, true); 2232 if (ret) { 2233 pr_err("Failed to reserve bo. ret %d\n", ret); 2234 goto err_reserve_bo_failed; 2235 } 2236 2237 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 2238 if (ret) { 2239 pr_err("Failed to pin bo. ret %d\n", ret); 2240 goto err_pin_bo_failed; 2241 } 2242 2243 ret = amdgpu_ttm_alloc_gart(&bo->tbo); 2244 if (ret) { 2245 pr_err("Failed to bind bo to GART. ret %d\n", ret); 2246 goto err_map_bo_gart_failed; 2247 } 2248 2249 amdgpu_amdkfd_remove_eviction_fence( 2250 bo, bo->vm_bo->vm->process_info->eviction_fence); 2251 2252 amdgpu_bo_unreserve(bo); 2253 2254 *bo_gart = amdgpu_bo_ref(bo); 2255 2256 return 0; 2257 2258 err_map_bo_gart_failed: 2259 amdgpu_bo_unpin(bo); 2260 err_pin_bo_failed: 2261 amdgpu_bo_unreserve(bo); 2262 err_reserve_bo_failed: 2263 2264 return ret; 2265 } 2266 2267 /** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Map a GTT BO for kernel CPU access 2268 * 2269 * @mem: Buffer object to be mapped for CPU access 2270 * @kptr[out]: pointer in kernel CPU address space 2271 * @size[out]: size of the buffer 2272 * 2273 * Pins the BO and maps it for kernel CPU access. The eviction fence is removed 2274 * from the BO, since pinned BOs cannot be evicted. The bo must remain on the 2275 * validate_list, so the GPU mapping can be restored after a page table was 2276 * evicted. 2277 * 2278 * Return: 0 on success, error code on failure 2279 */ 2280 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem, 2281 void **kptr, uint64_t *size) 2282 { 2283 int ret; 2284 struct amdgpu_bo *bo = mem->bo; 2285 2286 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) { 2287 pr_err("userptr can't be mapped to kernel\n"); 2288 return -EINVAL; 2289 } 2290 2291 mutex_lock(&mem->process_info->lock); 2292 2293 ret = amdgpu_bo_reserve(bo, true); 2294 if (ret) { 2295 pr_err("Failed to reserve bo. ret %d\n", ret); 2296 goto bo_reserve_failed; 2297 } 2298 2299 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 2300 if (ret) { 2301 pr_err("Failed to pin bo. ret %d\n", ret); 2302 goto pin_failed; 2303 } 2304 2305 ret = amdgpu_bo_kmap(bo, kptr); 2306 if (ret) { 2307 pr_err("Failed to map bo to kernel. ret %d\n", ret); 2308 goto kmap_failed; 2309 } 2310 2311 amdgpu_amdkfd_remove_eviction_fence( 2312 bo, mem->process_info->eviction_fence); 2313 2314 if (size) 2315 *size = amdgpu_bo_size(bo); 2316 2317 amdgpu_bo_unreserve(bo); 2318 2319 mutex_unlock(&mem->process_info->lock); 2320 return 0; 2321 2322 kmap_failed: 2323 amdgpu_bo_unpin(bo); 2324 pin_failed: 2325 amdgpu_bo_unreserve(bo); 2326 bo_reserve_failed: 2327 mutex_unlock(&mem->process_info->lock); 2328 2329 return ret; 2330 } 2331 2332 /** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Unmap a GTT BO for kernel CPU access 2333 * 2334 * @mem: Buffer object to be unmapped for CPU access 2335 * 2336 * Removes the kernel CPU mapping and unpins the BO. It does not restore the 2337 * eviction fence, so this function should only be used for cleanup before the 2338 * BO is destroyed. 2339 */ 2340 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem) 2341 { 2342 struct amdgpu_bo *bo = mem->bo; 2343 2344 (void)amdgpu_bo_reserve(bo, true); 2345 amdgpu_bo_kunmap(bo); 2346 amdgpu_bo_unpin(bo); 2347 amdgpu_bo_unreserve(bo); 2348 } 2349 2350 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, 2351 struct kfd_vm_fault_info *mem) 2352 { 2353 if (atomic_read_acquire(&adev->gmc.vm_fault_info_updated) == 1) { 2354 *mem = *adev->gmc.vm_fault_info; 2355 atomic_set_release(&adev->gmc.vm_fault_info_updated, 0); 2356 } 2357 return 0; 2358 } 2359 2360 static int import_obj_create(struct amdgpu_device *adev, 2361 struct dma_buf *dma_buf, 2362 struct drm_gem_object *obj, 2363 uint64_t va, void *drm_priv, 2364 struct kgd_mem **mem, uint64_t *size, 2365 uint64_t *mmap_offset) 2366 { 2367 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); 2368 struct amdgpu_bo *bo; 2369 int ret; 2370 2371 bo = gem_to_amdgpu_bo(obj); 2372 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | 2373 AMDGPU_GEM_DOMAIN_GTT))) 2374 /* Only VRAM and GTT BOs are supported */ 2375 return -EINVAL; 2376 2377 *mem = kzalloc_obj(struct kgd_mem, GFP_KERNEL); 2378 if (!*mem) 2379 return -ENOMEM; 2380 2381 ret = drm_vma_node_allow(&obj->vma_node, drm_priv); 2382 if (ret) 2383 goto err_free_mem; 2384 2385 if (size) 2386 *size = amdgpu_bo_size(bo); 2387 2388 if (mmap_offset) 2389 *mmap_offset = amdgpu_bo_mmap_offset(bo); 2390 2391 INIT_LIST_HEAD(&(*mem)->attachments); 2392 mutex_init(&(*mem)->lock); 2393 2394 (*mem)->alloc_flags = 2395 ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 2396 KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT) 2397 | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE 2398 | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE; 2399 2400 get_dma_buf(dma_buf); 2401 (*mem)->dmabuf = dma_buf; 2402 (*mem)->bo = bo; 2403 (*mem)->va = va; 2404 (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) && 2405 !adev->apu_prefer_gtt ? 2406 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT; 2407 2408 (*mem)->mapped_to_gpu_memory = 0; 2409 (*mem)->process_info = avm->process_info; 2410 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false); 2411 amdgpu_sync_create(&(*mem)->sync); 2412 (*mem)->is_imported = true; 2413 2414 mutex_lock(&avm->process_info->lock); 2415 if (avm->process_info->eviction_fence && 2416 !dma_fence_is_signaled(&avm->process_info->eviction_fence->base)) 2417 ret = amdgpu_amdkfd_bo_validate_and_fence(bo, (*mem)->domain, 2418 &avm->process_info->eviction_fence->base); 2419 mutex_unlock(&avm->process_info->lock); 2420 if (ret) 2421 goto err_remove_mem; 2422 2423 return 0; 2424 2425 err_remove_mem: 2426 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info); 2427 drm_vma_node_revoke(&obj->vma_node, drm_priv); 2428 err_free_mem: 2429 kfree(*mem); 2430 return ret; 2431 } 2432 2433 int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, 2434 uint64_t va, void *drm_priv, 2435 struct kgd_mem **mem, uint64_t *size, 2436 uint64_t *mmap_offset) 2437 { 2438 struct drm_gem_object *obj; 2439 uint32_t handle; 2440 int ret; 2441 2442 ret = drm_gem_prime_fd_to_handle(&adev->ddev, adev->kfd.client.file, fd, 2443 &handle); 2444 if (ret) 2445 return ret; 2446 obj = drm_gem_object_lookup(adev->kfd.client.file, handle); 2447 if (!obj) { 2448 ret = -EINVAL; 2449 goto err_release_handle; 2450 } 2451 2452 ret = import_obj_create(adev, obj->dma_buf, obj, va, drm_priv, mem, size, 2453 mmap_offset); 2454 if (ret) 2455 goto err_put_obj; 2456 2457 (*mem)->gem_handle = handle; 2458 2459 return 0; 2460 2461 err_put_obj: 2462 drm_gem_object_put(obj); 2463 err_release_handle: 2464 drm_gem_handle_delete(adev->kfd.client.file, handle); 2465 return ret; 2466 } 2467 2468 int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, 2469 struct dma_buf **dma_buf) 2470 { 2471 int ret; 2472 2473 mutex_lock(&mem->lock); 2474 ret = kfd_mem_export_dmabuf(mem); 2475 if (ret) 2476 goto out; 2477 2478 get_dma_buf(mem->dmabuf); 2479 *dma_buf = mem->dmabuf; 2480 out: 2481 mutex_unlock(&mem->lock); 2482 return ret; 2483 } 2484 2485 /* Evict a userptr BO by stopping the queues if necessary 2486 * 2487 * Runs in MMU notifier, may be in RECLAIM_FS context. This means it 2488 * cannot do any memory allocations, and cannot take any locks that 2489 * are held elsewhere while allocating memory. 2490 * 2491 * It doesn't do anything to the BO itself. The real work happens in 2492 * restore, where we get updated page addresses. This function only 2493 * ensures that GPU access to the BO is stopped. 2494 */ 2495 int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, 2496 unsigned long cur_seq, struct kgd_mem *mem) 2497 { 2498 struct amdkfd_process_info *process_info = mem->process_info; 2499 int r = 0; 2500 2501 /* Do not process MMU notifications during CRIU restore until 2502 * KFD_CRIU_OP_RESUME IOCTL is received 2503 */ 2504 if (READ_ONCE(process_info->block_mmu_notifications)) 2505 return 0; 2506 2507 mutex_lock(&process_info->notifier_lock); 2508 mmu_interval_set_seq(mni, cur_seq); 2509 2510 mem->invalid++; 2511 if (++process_info->evicted_bos == 1) { 2512 /* First eviction, stop the queues */ 2513 r = kgd2kfd_quiesce_mm(mni->mm, 2514 KFD_QUEUE_EVICTION_TRIGGER_USERPTR); 2515 2516 if (r && r != -ESRCH) 2517 pr_err("Failed to quiesce KFD\n"); 2518 2519 if (r != -ESRCH) 2520 queue_delayed_work(system_freezable_wq, 2521 &process_info->restore_userptr_work, 2522 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS)); 2523 } 2524 mutex_unlock(&process_info->notifier_lock); 2525 2526 return r; 2527 } 2528 2529 /* Update invalid userptr BOs 2530 * 2531 * Moves invalidated (evicted) userptr BOs from userptr_valid_list to 2532 * userptr_inval_list and updates user pages for all BOs that have 2533 * been invalidated since their last update. 2534 */ 2535 static int update_invalid_user_pages(struct amdkfd_process_info *process_info, 2536 struct mm_struct *mm) 2537 { 2538 struct kgd_mem *mem, *tmp_mem; 2539 struct amdgpu_bo *bo; 2540 struct ttm_operation_ctx ctx = { false, false }; 2541 uint32_t invalid; 2542 int ret = 0; 2543 2544 mutex_lock(&process_info->notifier_lock); 2545 2546 /* Move all invalidated BOs to the userptr_inval_list */ 2547 list_for_each_entry_safe(mem, tmp_mem, 2548 &process_info->userptr_valid_list, 2549 validate_list) 2550 if (mem->invalid) 2551 list_move_tail(&mem->validate_list, 2552 &process_info->userptr_inval_list); 2553 2554 /* Go through userptr_inval_list and update any invalid user_pages */ 2555 list_for_each_entry(mem, &process_info->userptr_inval_list, 2556 validate_list) { 2557 invalid = mem->invalid; 2558 if (!invalid) 2559 /* BO hasn't been invalidated since the last 2560 * revalidation attempt. Keep its page list. 2561 */ 2562 continue; 2563 2564 bo = mem->bo; 2565 2566 amdgpu_hmm_range_free(mem->range); 2567 mem->range = NULL; 2568 2569 /* BO reservations and getting user pages (hmm_range_fault) 2570 * must happen outside the notifier lock 2571 */ 2572 mutex_unlock(&process_info->notifier_lock); 2573 2574 /* Move the BO to system (CPU) domain if necessary to unmap 2575 * and free the SG table 2576 */ 2577 if (bo->tbo.resource->mem_type != TTM_PL_SYSTEM) { 2578 if (amdgpu_bo_reserve(bo, true)) 2579 return -EAGAIN; 2580 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 2581 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 2582 amdgpu_bo_unreserve(bo); 2583 if (ret) { 2584 pr_err("%s: Failed to invalidate userptr BO\n", 2585 __func__); 2586 return -EAGAIN; 2587 } 2588 } 2589 2590 mem->range = amdgpu_hmm_range_alloc(NULL); 2591 if (unlikely(!mem->range)) 2592 return -ENOMEM; 2593 /* Get updated user pages */ 2594 ret = amdgpu_ttm_tt_get_user_pages(bo, mem->range); 2595 if (ret) { 2596 amdgpu_hmm_range_free(mem->range); 2597 mem->range = NULL; 2598 pr_debug("Failed %d to get user pages\n", ret); 2599 2600 /* Return -EFAULT bad address error as success. It will 2601 * fail later with a VM fault if the GPU tries to access 2602 * it. Better than hanging indefinitely with stalled 2603 * user mode queues. 2604 * 2605 * Return other error -EBUSY or -ENOMEM to retry restore 2606 */ 2607 if (ret != -EFAULT) 2608 return ret; 2609 2610 /* If applications unmap memory before destroying the userptr 2611 * from the KFD, trigger a segmentation fault in VM debug mode. 2612 */ 2613 if (amdgpu_ttm_adev(bo->tbo.bdev)->debug_vm_userptr) { 2614 struct kfd_process *p; 2615 2616 pr_err("Pid %d unmapped memory before destroying userptr at GPU addr 0x%llx\n", 2617 pid_nr(process_info->pid), mem->va); 2618 2619 // Send GPU VM fault to user space 2620 p = kfd_lookup_process_by_pid(process_info->pid); 2621 if (p) { 2622 kfd_signal_vm_fault_event_with_userptr(p, mem->va); 2623 kfd_unref_process(p); 2624 } 2625 } 2626 2627 ret = 0; 2628 } 2629 2630 amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, mem->range); 2631 2632 mutex_lock(&process_info->notifier_lock); 2633 2634 /* Mark the BO as valid unless it was invalidated 2635 * again concurrently. 2636 */ 2637 if (mem->invalid != invalid) { 2638 ret = -EAGAIN; 2639 goto unlock_out; 2640 } 2641 /* set mem valid if mem has hmm range associated */ 2642 if (mem->range) 2643 mem->invalid = 0; 2644 } 2645 2646 unlock_out: 2647 mutex_unlock(&process_info->notifier_lock); 2648 2649 return ret; 2650 } 2651 2652 /* Validate invalid userptr BOs 2653 * 2654 * Validates BOs on the userptr_inval_list. Also updates GPUVM page tables 2655 * with new page addresses and waits for the page table updates to complete. 2656 */ 2657 static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) 2658 { 2659 struct ttm_operation_ctx ctx = { false, false }; 2660 struct amdgpu_sync sync; 2661 struct drm_exec exec; 2662 2663 struct amdgpu_vm *peer_vm; 2664 struct kgd_mem *mem, *tmp_mem; 2665 struct amdgpu_bo *bo; 2666 int ret; 2667 2668 amdgpu_sync_create(&sync); 2669 2670 drm_exec_init(&exec, 0, 0); 2671 /* Reserve all BOs and page tables for validation */ 2672 drm_exec_until_all_locked(&exec) { 2673 /* Reserve all the page directories */ 2674 list_for_each_entry(peer_vm, &process_info->vm_list_head, 2675 vm_list_node) { 2676 ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2); 2677 drm_exec_retry_on_contention(&exec); 2678 if (unlikely(ret)) 2679 goto unreserve_out; 2680 } 2681 2682 /* Reserve the userptr_inval_list entries to resv_list */ 2683 list_for_each_entry(mem, &process_info->userptr_inval_list, 2684 validate_list) { 2685 struct drm_gem_object *gobj; 2686 2687 gobj = &mem->bo->tbo.base; 2688 ret = drm_exec_prepare_obj(&exec, gobj, 1); 2689 drm_exec_retry_on_contention(&exec); 2690 if (unlikely(ret)) 2691 goto unreserve_out; 2692 } 2693 } 2694 2695 ret = process_validate_vms(process_info, NULL); 2696 if (ret) 2697 goto unreserve_out; 2698 2699 /* Validate BOs and update GPUVM page tables */ 2700 list_for_each_entry_safe(mem, tmp_mem, 2701 &process_info->userptr_inval_list, 2702 validate_list) { 2703 struct kfd_mem_attachment *attachment; 2704 2705 bo = mem->bo; 2706 2707 /* Validate the BO if we got user pages */ 2708 if (bo->tbo.ttm->pages[0]) { 2709 amdgpu_bo_placement_from_domain(bo, mem->domain); 2710 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 2711 if (ret) { 2712 pr_err("%s: failed to validate BO\n", __func__); 2713 goto unreserve_out; 2714 } 2715 } 2716 2717 /* Update mapping. If the BO was not validated 2718 * (because we couldn't get user pages), this will 2719 * clear the page table entries, which will result in 2720 * VM faults if the GPU tries to access the invalid 2721 * memory. 2722 */ 2723 list_for_each_entry(attachment, &mem->attachments, list) { 2724 if (!attachment->is_mapped) 2725 continue; 2726 2727 kfd_mem_dmaunmap_attachment(mem, attachment); 2728 ret = update_gpuvm_pte(mem, attachment, &sync); 2729 if (ret) { 2730 pr_err("%s: update PTE failed\n", __func__); 2731 /* make sure this gets validated again */ 2732 mutex_lock(&process_info->notifier_lock); 2733 mem->invalid++; 2734 mutex_unlock(&process_info->notifier_lock); 2735 goto unreserve_out; 2736 } 2737 } 2738 } 2739 2740 /* Update page directories */ 2741 ret = process_update_pds(process_info, &sync); 2742 2743 unreserve_out: 2744 drm_exec_fini(&exec); 2745 amdgpu_sync_wait(&sync, false); 2746 amdgpu_sync_free(&sync); 2747 2748 return ret; 2749 } 2750 2751 /* Confirm that all user pages are valid while holding the notifier lock 2752 * 2753 * Moves valid BOs from the userptr_inval_list back to userptr_val_list. 2754 */ 2755 static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_info) 2756 { 2757 struct kgd_mem *mem, *tmp_mem; 2758 int ret = 0; 2759 2760 list_for_each_entry_safe(mem, tmp_mem, 2761 &process_info->userptr_inval_list, 2762 validate_list) { 2763 bool valid; 2764 2765 /* keep mem without hmm range at userptr_inval_list */ 2766 if (!mem->range) 2767 continue; 2768 2769 /* Only check mem with hmm range associated */ 2770 valid = amdgpu_hmm_range_valid(mem->range); 2771 amdgpu_hmm_range_free(mem->range); 2772 2773 mem->range = NULL; 2774 if (!valid) { 2775 WARN(!mem->invalid, "Invalid BO not marked invalid"); 2776 ret = -EAGAIN; 2777 continue; 2778 } 2779 2780 if (mem->invalid) { 2781 WARN(1, "Valid BO is marked invalid"); 2782 ret = -EAGAIN; 2783 continue; 2784 } 2785 2786 list_move_tail(&mem->validate_list, 2787 &process_info->userptr_valid_list); 2788 } 2789 2790 return ret; 2791 } 2792 2793 /* Worker callback to restore evicted userptr BOs 2794 * 2795 * Tries to update and validate all userptr BOs. If successful and no 2796 * concurrent evictions happened, the queues are restarted. Otherwise, 2797 * reschedule for another attempt later. 2798 */ 2799 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work) 2800 { 2801 struct delayed_work *dwork = to_delayed_work(work); 2802 struct amdkfd_process_info *process_info = 2803 container_of(dwork, struct amdkfd_process_info, 2804 restore_userptr_work); 2805 struct task_struct *usertask; 2806 struct mm_struct *mm; 2807 uint32_t evicted_bos; 2808 2809 mutex_lock(&process_info->notifier_lock); 2810 evicted_bos = process_info->evicted_bos; 2811 mutex_unlock(&process_info->notifier_lock); 2812 if (!evicted_bos) 2813 return; 2814 2815 /* Reference task and mm in case of concurrent process termination */ 2816 usertask = get_pid_task(process_info->pid, PIDTYPE_PID); 2817 if (!usertask) 2818 return; 2819 mm = get_task_mm(usertask); 2820 if (!mm) { 2821 put_task_struct(usertask); 2822 return; 2823 } 2824 2825 mutex_lock(&process_info->lock); 2826 2827 if (update_invalid_user_pages(process_info, mm)) 2828 goto unlock_out; 2829 /* userptr_inval_list can be empty if all evicted userptr BOs 2830 * have been freed. In that case there is nothing to validate 2831 * and we can just restart the queues. 2832 */ 2833 if (!list_empty(&process_info->userptr_inval_list)) { 2834 if (validate_invalid_user_pages(process_info)) 2835 goto unlock_out; 2836 } 2837 /* Final check for concurrent evicton and atomic update. If 2838 * another eviction happens after successful update, it will 2839 * be a first eviction that calls quiesce_mm. The eviction 2840 * reference counting inside KFD will handle this case. 2841 */ 2842 mutex_lock(&process_info->notifier_lock); 2843 if (process_info->evicted_bos != evicted_bos) 2844 goto unlock_notifier_out; 2845 2846 if (confirm_valid_user_pages_locked(process_info)) { 2847 WARN(1, "User pages unexpectedly invalid"); 2848 goto unlock_notifier_out; 2849 } 2850 2851 process_info->evicted_bos = evicted_bos = 0; 2852 2853 if (kgd2kfd_resume_mm(mm)) { 2854 pr_err("%s: Failed to resume KFD\n", __func__); 2855 /* No recovery from this failure. Probably the CP is 2856 * hanging. No point trying again. 2857 */ 2858 } 2859 2860 unlock_notifier_out: 2861 mutex_unlock(&process_info->notifier_lock); 2862 unlock_out: 2863 mutex_unlock(&process_info->lock); 2864 2865 /* If validation failed, reschedule another attempt */ 2866 if (evicted_bos) { 2867 queue_delayed_work(system_freezable_wq, 2868 &process_info->restore_userptr_work, 2869 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS)); 2870 2871 kfd_smi_event_queue_restore_rescheduled(mm); 2872 } 2873 mmput(mm); 2874 put_task_struct(usertask); 2875 } 2876 2877 static void replace_eviction_fence(struct dma_fence __rcu **ef, 2878 struct dma_fence *new_ef) 2879 { 2880 struct dma_fence *old_ef = rcu_replace_pointer(*ef, new_ef, true 2881 /* protected by process_info->lock */); 2882 2883 /* If we're replacing an unsignaled eviction fence, that fence will 2884 * never be signaled, and if anyone is still waiting on that fence, 2885 * they will hang forever. This should never happen. We should only 2886 * replace the fence in restore_work that only gets scheduled after 2887 * eviction work signaled the fence. 2888 */ 2889 WARN_ONCE(!dma_fence_is_signaled(old_ef), 2890 "Replacing unsignaled eviction fence"); 2891 dma_fence_put(old_ef); 2892 } 2893 2894 /** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given 2895 * KFD process identified by process_info 2896 * 2897 * @process_info: amdkfd_process_info of the KFD process 2898 * 2899 * After memory eviction, restore thread calls this function. The function 2900 * should be called when the Process is still valid. BO restore involves - 2901 * 2902 * 1. Release old eviction fence and create new one 2903 * 2. Get two copies of PD BO list from all the VMs. Keep one copy as pd_list. 2904 * 3 Use the second PD list and kfd_bo_list to create a list (ctx.list) of 2905 * BOs that need to be reserved. 2906 * 4. Reserve all the BOs 2907 * 5. Validate of PD and PT BOs. 2908 * 6. Validate all KFD BOs using kfd_bo_list and Map them and add new fence 2909 * 7. Add fence to all PD and PT BOs. 2910 * 8. Unreserve all BOs 2911 */ 2912 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu **ef) 2913 { 2914 struct amdkfd_process_info *process_info = info; 2915 struct amdgpu_vm *peer_vm; 2916 struct kgd_mem *mem; 2917 struct list_head duplicate_save; 2918 struct amdgpu_sync sync_obj; 2919 unsigned long failed_size = 0; 2920 unsigned long total_size = 0; 2921 struct drm_exec exec; 2922 int ret; 2923 2924 INIT_LIST_HEAD(&duplicate_save); 2925 2926 mutex_lock(&process_info->lock); 2927 2928 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); 2929 drm_exec_until_all_locked(&exec) { 2930 list_for_each_entry(peer_vm, &process_info->vm_list_head, 2931 vm_list_node) { 2932 ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2); 2933 drm_exec_retry_on_contention(&exec); 2934 if (unlikely(ret)) { 2935 pr_err("Locking VM PD failed, ret: %d\n", ret); 2936 goto ttm_reserve_fail; 2937 } 2938 } 2939 2940 /* Reserve all BOs and page tables/directory. Add all BOs from 2941 * kfd_bo_list to ctx.list 2942 */ 2943 list_for_each_entry(mem, &process_info->kfd_bo_list, 2944 validate_list) { 2945 struct drm_gem_object *gobj; 2946 2947 gobj = &mem->bo->tbo.base; 2948 ret = drm_exec_prepare_obj(&exec, gobj, 1); 2949 drm_exec_retry_on_contention(&exec); 2950 if (unlikely(ret)) { 2951 pr_err("drm_exec_prepare_obj failed, ret: %d\n", ret); 2952 goto ttm_reserve_fail; 2953 } 2954 } 2955 } 2956 2957 amdgpu_sync_create(&sync_obj); 2958 2959 /* Validate BOs managed by KFD */ 2960 list_for_each_entry(mem, &process_info->kfd_bo_list, 2961 validate_list) { 2962 2963 struct amdgpu_bo *bo = mem->bo; 2964 uint32_t domain = mem->domain; 2965 struct dma_resv_iter cursor; 2966 struct dma_fence *fence; 2967 2968 total_size += amdgpu_bo_size(bo); 2969 2970 ret = amdgpu_amdkfd_bo_validate(bo, domain, false); 2971 if (ret) { 2972 pr_debug("Memory eviction: Validate BOs failed\n"); 2973 failed_size += amdgpu_bo_size(bo); 2974 ret = amdgpu_amdkfd_bo_validate(bo, 2975 AMDGPU_GEM_DOMAIN_GTT, false); 2976 if (ret) { 2977 pr_debug("Memory eviction: Try again\n"); 2978 goto validate_map_fail; 2979 } 2980 } 2981 dma_resv_for_each_fence(&cursor, bo->tbo.base.resv, 2982 DMA_RESV_USAGE_KERNEL, fence) { 2983 ret = amdgpu_sync_fence(&sync_obj, fence, GFP_KERNEL); 2984 if (ret) { 2985 pr_debug("Memory eviction: Sync BO fence failed. Try again\n"); 2986 goto validate_map_fail; 2987 } 2988 } 2989 } 2990 2991 if (failed_size) 2992 pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size); 2993 2994 /* Validate PDs, PTs and evicted DMABuf imports last. Otherwise BO 2995 * validations above would invalidate DMABuf imports again. 2996 */ 2997 ret = process_validate_vms(process_info, &exec.ticket); 2998 if (ret) { 2999 pr_debug("Validating VMs failed, ret: %d\n", ret); 3000 goto validate_map_fail; 3001 } 3002 3003 /* Update mappings managed by KFD. */ 3004 list_for_each_entry(mem, &process_info->kfd_bo_list, 3005 validate_list) { 3006 struct kfd_mem_attachment *attachment; 3007 3008 list_for_each_entry(attachment, &mem->attachments, list) { 3009 if (!attachment->is_mapped) 3010 continue; 3011 3012 kfd_mem_dmaunmap_attachment(mem, attachment); 3013 ret = update_gpuvm_pte(mem, attachment, &sync_obj); 3014 if (ret) { 3015 pr_debug("Memory eviction: update PTE failed. Try again\n"); 3016 goto validate_map_fail; 3017 } 3018 } 3019 } 3020 3021 /* Update mappings not managed by KFD */ 3022 list_for_each_entry(peer_vm, &process_info->vm_list_head, 3023 vm_list_node) { 3024 struct amdgpu_device *adev = amdgpu_ttm_adev( 3025 peer_vm->root.bo->tbo.bdev); 3026 3027 struct amdgpu_fpriv *fpriv = 3028 container_of(peer_vm, struct amdgpu_fpriv, vm); 3029 3030 ret = amdgpu_vm_bo_update(adev, fpriv->prt_va, false); 3031 if (ret) { 3032 dev_dbg(adev->dev, 3033 "Memory eviction: handle PRT moved failed, pid %8d. Try again.\n", 3034 pid_nr(process_info->pid)); 3035 goto validate_map_fail; 3036 } 3037 3038 ret = amdgpu_vm_handle_moved(adev, peer_vm, &exec.ticket); 3039 if (ret) { 3040 dev_dbg(adev->dev, 3041 "Memory eviction: handle moved failed, pid %8d. Try again.\n", 3042 pid_nr(process_info->pid)); 3043 goto validate_map_fail; 3044 } 3045 } 3046 3047 /* Update page directories */ 3048 ret = process_update_pds(process_info, &sync_obj); 3049 if (ret) { 3050 pr_debug("Memory eviction: update PDs failed. Try again\n"); 3051 goto validate_map_fail; 3052 } 3053 3054 /* Sync with fences on all the page tables. They implicitly depend on any 3055 * move fences from amdgpu_vm_handle_moved above. 3056 */ 3057 ret = process_sync_pds_resv(process_info, &sync_obj); 3058 if (ret) { 3059 pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n"); 3060 goto validate_map_fail; 3061 } 3062 3063 /* Wait for validate and PT updates to finish */ 3064 amdgpu_sync_wait(&sync_obj, false); 3065 3066 /* The old eviction fence may be unsignaled if restore happens 3067 * after a GPU reset or suspend/resume. Keep the old fence in that 3068 * case. Otherwise release the old eviction fence and create new 3069 * one, because fence only goes from unsignaled to signaled once 3070 * and cannot be reused. Use context and mm from the old fence. 3071 * 3072 * If an old eviction fence signals after this check, that's OK. 3073 * Anyone signaling an eviction fence must stop the queues first 3074 * and schedule another restore worker. 3075 */ 3076 if (dma_fence_is_signaled(&process_info->eviction_fence->base)) { 3077 struct amdgpu_amdkfd_fence *new_fence = 3078 amdgpu_amdkfd_fence_create( 3079 process_info->eviction_fence->base.context, 3080 process_info->eviction_fence->mm, 3081 NULL, process_info->context_id); 3082 3083 if (!new_fence) { 3084 pr_err("Failed to create eviction fence\n"); 3085 ret = -ENOMEM; 3086 goto validate_map_fail; 3087 } 3088 dma_fence_put(&process_info->eviction_fence->base); 3089 process_info->eviction_fence = new_fence; 3090 replace_eviction_fence(ef, dma_fence_get(&new_fence->base)); 3091 } else { 3092 WARN_ONCE(*ef != &process_info->eviction_fence->base, 3093 "KFD eviction fence doesn't match KGD process_info"); 3094 } 3095 3096 /* Attach new eviction fence to all BOs except pinned ones */ 3097 list_for_each_entry(mem, &process_info->kfd_bo_list, validate_list) { 3098 if (mem->bo->tbo.pin_count) 3099 continue; 3100 3101 dma_resv_add_fence(mem->bo->tbo.base.resv, 3102 &process_info->eviction_fence->base, 3103 DMA_RESV_USAGE_BOOKKEEP); 3104 } 3105 /* Attach eviction fence to PD / PT BOs and DMABuf imports */ 3106 list_for_each_entry(peer_vm, &process_info->vm_list_head, 3107 vm_list_node) { 3108 struct amdgpu_bo *bo = peer_vm->root.bo; 3109 3110 dma_resv_add_fence(bo->tbo.base.resv, 3111 &process_info->eviction_fence->base, 3112 DMA_RESV_USAGE_BOOKKEEP); 3113 } 3114 3115 validate_map_fail: 3116 amdgpu_sync_free(&sync_obj); 3117 ttm_reserve_fail: 3118 drm_exec_fini(&exec); 3119 mutex_unlock(&process_info->lock); 3120 return ret; 3121 } 3122 3123 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem) 3124 { 3125 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info; 3126 struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws; 3127 int ret; 3128 3129 if (!info || !gws) 3130 return -EINVAL; 3131 3132 *mem = kzalloc_obj(struct kgd_mem, GFP_KERNEL); 3133 if (!*mem) 3134 return -ENOMEM; 3135 3136 mutex_init(&(*mem)->lock); 3137 INIT_LIST_HEAD(&(*mem)->attachments); 3138 (*mem)->bo = amdgpu_bo_ref(gws_bo); 3139 (*mem)->domain = AMDGPU_GEM_DOMAIN_GWS; 3140 (*mem)->process_info = process_info; 3141 add_kgd_mem_to_kfd_bo_list(*mem, process_info, false); 3142 amdgpu_sync_create(&(*mem)->sync); 3143 3144 3145 /* Validate gws bo the first time it is added to process */ 3146 mutex_lock(&(*mem)->process_info->lock); 3147 ret = amdgpu_bo_reserve(gws_bo, false); 3148 if (unlikely(ret)) { 3149 pr_err("Reserve gws bo failed %d\n", ret); 3150 goto bo_reservation_failure; 3151 } 3152 3153 ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true); 3154 if (ret) { 3155 pr_err("GWS BO validate failed %d\n", ret); 3156 goto bo_validation_failure; 3157 } 3158 /* GWS resource is shared b/t amdgpu and amdkfd 3159 * Add process eviction fence to bo so they can 3160 * evict each other. 3161 */ 3162 ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1); 3163 if (ret) 3164 goto reserve_shared_fail; 3165 dma_resv_add_fence(gws_bo->tbo.base.resv, 3166 &process_info->eviction_fence->base, 3167 DMA_RESV_USAGE_BOOKKEEP); 3168 amdgpu_bo_unreserve(gws_bo); 3169 mutex_unlock(&(*mem)->process_info->lock); 3170 3171 return ret; 3172 3173 reserve_shared_fail: 3174 bo_validation_failure: 3175 amdgpu_bo_unreserve(gws_bo); 3176 bo_reservation_failure: 3177 mutex_unlock(&(*mem)->process_info->lock); 3178 amdgpu_sync_free(&(*mem)->sync); 3179 remove_kgd_mem_from_kfd_bo_list(*mem, process_info); 3180 amdgpu_bo_unref(&gws_bo); 3181 mutex_destroy(&(*mem)->lock); 3182 kfree(*mem); 3183 *mem = NULL; 3184 return ret; 3185 } 3186 3187 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem) 3188 { 3189 int ret; 3190 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info; 3191 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem; 3192 struct amdgpu_bo *gws_bo = kgd_mem->bo; 3193 3194 /* Remove BO from process's validate list so restore worker won't touch 3195 * it anymore 3196 */ 3197 remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info); 3198 3199 ret = amdgpu_bo_reserve(gws_bo, false); 3200 if (unlikely(ret)) { 3201 pr_err("Reserve gws bo failed %d\n", ret); 3202 //TODO add BO back to validate_list? 3203 return ret; 3204 } 3205 amdgpu_amdkfd_remove_eviction_fence(gws_bo, 3206 process_info->eviction_fence); 3207 amdgpu_bo_unreserve(gws_bo); 3208 amdgpu_sync_free(&kgd_mem->sync); 3209 amdgpu_bo_unref(&gws_bo); 3210 mutex_destroy(&kgd_mem->lock); 3211 kfree(mem); 3212 return 0; 3213 } 3214 3215 /* Returns GPU-specific tiling mode information */ 3216 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, 3217 struct tile_config *config) 3218 { 3219 config->gb_addr_config = adev->gfx.config.gb_addr_config; 3220 config->tile_config_ptr = adev->gfx.config.tile_mode_array; 3221 config->num_tile_configs = 3222 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 3223 config->macro_tile_config_ptr = 3224 adev->gfx.config.macrotile_mode_array; 3225 config->num_macro_tile_configs = 3226 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 3227 3228 /* Those values are not set from GFX9 onwards */ 3229 config->num_banks = adev->gfx.config.num_banks; 3230 config->num_ranks = adev->gfx.config.num_ranks; 3231 3232 return 0; 3233 } 3234 3235 bool amdgpu_amdkfd_bo_mapped_to_dev(void *drm_priv, struct kgd_mem *mem) 3236 { 3237 struct amdgpu_vm *vm = drm_priv_to_vm(drm_priv); 3238 struct kfd_mem_attachment *entry; 3239 3240 list_for_each_entry(entry, &mem->attachments, list) { 3241 if (entry->is_mapped && entry->bo_va->base.vm == vm) 3242 return true; 3243 } 3244 return false; 3245 } 3246 3247 #if defined(CONFIG_DEBUG_FS) 3248 3249 int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data) 3250 { 3251 3252 spin_lock(&kfd_mem_limit.mem_limit_lock); 3253 seq_printf(m, "System mem used %lldM out of %lluM\n", 3254 (kfd_mem_limit.system_mem_used >> 20), 3255 (kfd_mem_limit.max_system_mem_limit >> 20)); 3256 seq_printf(m, "TTM mem used %lldM out of %lluM\n", 3257 (kfd_mem_limit.ttm_mem_used >> 20), 3258 (kfd_mem_limit.max_ttm_mem_limit >> 20)); 3259 spin_unlock(&kfd_mem_limit.mem_limit_lock); 3260 3261 return 0; 3262 } 3263 3264 #endif 3265