1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/delay.h> 13 #include <linux/netdevice.h> 14 #include <linux/interrupt.h> 15 #include <linux/tcp.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/ethtool.h> 21 #include <linux/if_vlan.h> 22 #include <linux/cpu.h> 23 #include <linux/smp.h> 24 #include <linux/pm_qos.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/prefetch.h> 27 #include <linux/suspend.h> 28 29 #include "e1000.h" 30 #define CREATE_TRACE_POINTS 31 #include "e1000e_trace.h" 32 33 char e1000e_driver_name[] = "e1000e"; 34 35 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 36 static int debug = -1; 37 module_param(debug, int, 0); 38 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 39 40 static const struct e1000_info *e1000_info_tbl[] = { 41 [board_82571] = &e1000_82571_info, 42 [board_82572] = &e1000_82572_info, 43 [board_82573] = &e1000_82573_info, 44 [board_82574] = &e1000_82574_info, 45 [board_82583] = &e1000_82583_info, 46 [board_80003es2lan] = &e1000_es2_info, 47 [board_ich8lan] = &e1000_ich8_info, 48 [board_ich9lan] = &e1000_ich9_info, 49 [board_ich10lan] = &e1000_ich10_info, 50 [board_pchlan] = &e1000_pch_info, 51 [board_pch2lan] = &e1000_pch2_info, 52 [board_pch_lpt] = &e1000_pch_lpt_info, 53 [board_pch_spt] = &e1000_pch_spt_info, 54 [board_pch_cnp] = &e1000_pch_cnp_info, 55 [board_pch_tgp] = &e1000_pch_tgp_info, 56 [board_pch_adp] = &e1000_pch_adp_info, 57 [board_pch_mtp] = &e1000_pch_mtp_info, 58 }; 59 60 struct e1000_reg_info { 61 u32 ofs; 62 char *name; 63 }; 64 65 static const struct e1000_reg_info e1000_reg_info_tbl[] = { 66 /* General Registers */ 67 {E1000_CTRL, "CTRL"}, 68 {E1000_STATUS, "STATUS"}, 69 {E1000_CTRL_EXT, "CTRL_EXT"}, 70 71 /* Interrupt Registers */ 72 {E1000_ICR, "ICR"}, 73 74 /* Rx Registers */ 75 {E1000_RCTL, "RCTL"}, 76 {E1000_RDLEN(0), "RDLEN"}, 77 {E1000_RDH(0), "RDH"}, 78 {E1000_RDT(0), "RDT"}, 79 {E1000_RDTR, "RDTR"}, 80 {E1000_RXDCTL(0), "RXDCTL"}, 81 {E1000_ERT, "ERT"}, 82 {E1000_RDBAL(0), "RDBAL"}, 83 {E1000_RDBAH(0), "RDBAH"}, 84 {E1000_RDFH, "RDFH"}, 85 {E1000_RDFT, "RDFT"}, 86 {E1000_RDFHS, "RDFHS"}, 87 {E1000_RDFTS, "RDFTS"}, 88 {E1000_RDFPC, "RDFPC"}, 89 90 /* Tx Registers */ 91 {E1000_TCTL, "TCTL"}, 92 {E1000_TDBAL(0), "TDBAL"}, 93 {E1000_TDBAH(0), "TDBAH"}, 94 {E1000_TDLEN(0), "TDLEN"}, 95 {E1000_TDH(0), "TDH"}, 96 {E1000_TDT(0), "TDT"}, 97 {E1000_TIDV, "TIDV"}, 98 {E1000_TXDCTL(0), "TXDCTL"}, 99 {E1000_TADV, "TADV"}, 100 {E1000_TARC(0), "TARC"}, 101 {E1000_TDFH, "TDFH"}, 102 {E1000_TDFT, "TDFT"}, 103 {E1000_TDFHS, "TDFHS"}, 104 {E1000_TDFTS, "TDFTS"}, 105 {E1000_TDFPC, "TDFPC"}, 106 107 /* List Terminator */ 108 {0, NULL} 109 }; 110 111 /** 112 * __ew32_prepare - prepare to write to MAC CSR register on certain parts 113 * @hw: pointer to the HW structure 114 * 115 * When updating the MAC CSR registers, the Manageability Engine (ME) could 116 * be accessing the registers at the same time. Normally, this is handled in 117 * h/w by an arbiter but on some parts there is a bug that acknowledges Host 118 * accesses later than it should which could result in the register to have 119 * an incorrect value. Workaround this by checking the FWSM register which 120 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 121 * and try again a number of times. 122 **/ 123 static void __ew32_prepare(struct e1000_hw *hw) 124 { 125 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 126 127 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 128 udelay(50); 129 } 130 131 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 132 { 133 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 134 __ew32_prepare(hw); 135 136 writel(val, hw->hw_addr + reg); 137 } 138 139 /** 140 * e1000_regdump - register printout routine 141 * @hw: pointer to the HW structure 142 * @reginfo: pointer to the register info table 143 **/ 144 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo) 145 { 146 int n = 0; 147 char rname[16]; 148 u32 regs[8]; 149 150 switch (reginfo->ofs) { 151 case E1000_RXDCTL(0): 152 for (n = 0; n < 2; n++) 153 regs[n] = __er32(hw, E1000_RXDCTL(n)); 154 break; 155 case E1000_TXDCTL(0): 156 for (n = 0; n < 2; n++) 157 regs[n] = __er32(hw, E1000_TXDCTL(n)); 158 break; 159 case E1000_TARC(0): 160 for (n = 0; n < 2; n++) 161 regs[n] = __er32(hw, E1000_TARC(n)); 162 break; 163 default: 164 pr_info("%-15s %08x\n", 165 reginfo->name, __er32(hw, reginfo->ofs)); 166 return; 167 } 168 169 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]"); 170 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]); 171 } 172 173 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter, 174 struct e1000_buffer *bi) 175 { 176 int i; 177 struct e1000_ps_page *ps_page; 178 179 for (i = 0; i < adapter->rx_ps_pages; i++) { 180 ps_page = &bi->ps_pages[i]; 181 182 if (ps_page->page) { 183 pr_info("packet dump for ps_page %d:\n", i); 184 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 185 16, 1, page_address(ps_page->page), 186 PAGE_SIZE, true); 187 } 188 } 189 } 190 191 /** 192 * e1000e_dump - Print registers, Tx-ring and Rx-ring 193 * @adapter: board private structure 194 **/ 195 static void e1000e_dump(struct e1000_adapter *adapter) 196 { 197 struct net_device *netdev = adapter->netdev; 198 struct e1000_hw *hw = &adapter->hw; 199 struct e1000_reg_info *reginfo; 200 struct e1000_ring *tx_ring = adapter->tx_ring; 201 struct e1000_tx_desc *tx_desc; 202 struct my_u0 { 203 __le64 a; 204 __le64 b; 205 } *u0; 206 struct e1000_buffer *buffer_info; 207 struct e1000_ring *rx_ring = adapter->rx_ring; 208 union e1000_rx_desc_packet_split *rx_desc_ps; 209 union e1000_rx_desc_extended *rx_desc; 210 struct my_u1 { 211 __le64 a; 212 __le64 b; 213 __le64 c; 214 __le64 d; 215 } *u1; 216 u32 staterr; 217 int i = 0; 218 219 if (!netif_msg_hw(adapter)) 220 return; 221 222 /* Print netdevice Info */ 223 if (netdev) { 224 dev_info(&adapter->pdev->dev, "Net device Info\n"); 225 pr_info("Device Name state trans_start\n"); 226 pr_info("%-15s %016lX %016lX\n", netdev->name, 227 netdev->state, dev_trans_start(netdev)); 228 } 229 230 /* Print Registers */ 231 dev_info(&adapter->pdev->dev, "Register Dump\n"); 232 pr_info(" Register Name Value\n"); 233 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl; 234 reginfo->name; reginfo++) { 235 e1000_regdump(hw, reginfo); 236 } 237 238 /* Print Tx Ring Summary */ 239 if (!netdev || !netif_running(netdev)) 240 return; 241 242 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n"); 243 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 244 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean]; 245 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", 246 0, tx_ring->next_to_use, tx_ring->next_to_clean, 247 (unsigned long long)buffer_info->dma, 248 buffer_info->length, 249 buffer_info->next_to_watch, 250 (unsigned long long)buffer_info->time_stamp); 251 252 /* Print Tx Ring */ 253 if (!netif_msg_tx_done(adapter)) 254 goto rx_ring_summary; 255 256 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n"); 257 258 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended) 259 * 260 * Legacy Transmit Descriptor 261 * +--------------------------------------------------------------+ 262 * 0 | Buffer Address [63:0] (Reserved on Write Back) | 263 * +--------------------------------------------------------------+ 264 * 8 | Special | CSS | Status | CMD | CSO | Length | 265 * +--------------------------------------------------------------+ 266 * 63 48 47 36 35 32 31 24 23 16 15 0 267 * 268 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload 269 * 63 48 47 40 39 32 31 16 15 8 7 0 270 * +----------------------------------------------------------------+ 271 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS | 272 * +----------------------------------------------------------------+ 273 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN | 274 * +----------------------------------------------------------------+ 275 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 276 * 277 * Extended Data Descriptor (DTYP=0x1) 278 * +----------------------------------------------------------------+ 279 * 0 | Buffer Address [63:0] | 280 * +----------------------------------------------------------------+ 281 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN | 282 * +----------------------------------------------------------------+ 283 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 284 */ 285 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n"); 286 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n"); 287 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n"); 288 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 289 const char *next_desc; 290 tx_desc = E1000_TX_DESC(*tx_ring, i); 291 buffer_info = &tx_ring->buffer_info[i]; 292 u0 = (struct my_u0 *)tx_desc; 293 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean) 294 next_desc = " NTC/U"; 295 else if (i == tx_ring->next_to_use) 296 next_desc = " NTU"; 297 else if (i == tx_ring->next_to_clean) 298 next_desc = " NTC"; 299 else 300 next_desc = ""; 301 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", 302 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' : 303 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')), 304 i, 305 (unsigned long long)le64_to_cpu(u0->a), 306 (unsigned long long)le64_to_cpu(u0->b), 307 (unsigned long long)buffer_info->dma, 308 buffer_info->length, buffer_info->next_to_watch, 309 (unsigned long long)buffer_info->time_stamp, 310 buffer_info->skb, next_desc); 311 312 if (netif_msg_pktdata(adapter) && buffer_info->skb) 313 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 314 16, 1, buffer_info->skb->data, 315 buffer_info->skb->len, true); 316 } 317 318 /* Print Rx Ring Summary */ 319 rx_ring_summary: 320 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n"); 321 pr_info("Queue [NTU] [NTC]\n"); 322 pr_info(" %5d %5X %5X\n", 323 0, rx_ring->next_to_use, rx_ring->next_to_clean); 324 325 /* Print Rx Ring */ 326 if (!netif_msg_rx_status(adapter)) 327 return; 328 329 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n"); 330 switch (adapter->rx_ps_pages) { 331 case 1: 332 case 2: 333 case 3: 334 /* [Extended] Packet Split Receive Descriptor Format 335 * 336 * +-----------------------------------------------------+ 337 * 0 | Buffer Address 0 [63:0] | 338 * +-----------------------------------------------------+ 339 * 8 | Buffer Address 1 [63:0] | 340 * +-----------------------------------------------------+ 341 * 16 | Buffer Address 2 [63:0] | 342 * +-----------------------------------------------------+ 343 * 24 | Buffer Address 3 [63:0] | 344 * +-----------------------------------------------------+ 345 */ 346 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n"); 347 /* [Extended] Receive Descriptor (Write-Back) Format 348 * 349 * 63 48 47 32 31 13 12 8 7 4 3 0 350 * +------------------------------------------------------+ 351 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS | 352 * | Checksum | Ident | | Queue | | Type | 353 * +------------------------------------------------------+ 354 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 355 * +------------------------------------------------------+ 356 * 63 48 47 32 31 20 19 0 357 */ 358 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n"); 359 for (i = 0; i < rx_ring->count; i++) { 360 const char *next_desc; 361 buffer_info = &rx_ring->buffer_info[i]; 362 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i); 363 u1 = (struct my_u1 *)rx_desc_ps; 364 staterr = 365 le32_to_cpu(rx_desc_ps->wb.middle.status_error); 366 367 if (i == rx_ring->next_to_use) 368 next_desc = " NTU"; 369 else if (i == rx_ring->next_to_clean) 370 next_desc = " NTC"; 371 else 372 next_desc = ""; 373 374 if (staterr & E1000_RXD_STAT_DD) { 375 /* Descriptor Done */ 376 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n", 377 "RWB", i, 378 (unsigned long long)le64_to_cpu(u1->a), 379 (unsigned long long)le64_to_cpu(u1->b), 380 (unsigned long long)le64_to_cpu(u1->c), 381 (unsigned long long)le64_to_cpu(u1->d), 382 buffer_info->skb, next_desc); 383 } else { 384 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n", 385 "R ", i, 386 (unsigned long long)le64_to_cpu(u1->a), 387 (unsigned long long)le64_to_cpu(u1->b), 388 (unsigned long long)le64_to_cpu(u1->c), 389 (unsigned long long)le64_to_cpu(u1->d), 390 (unsigned long long)buffer_info->dma, 391 buffer_info->skb, next_desc); 392 393 if (netif_msg_pktdata(adapter)) 394 e1000e_dump_ps_pages(adapter, 395 buffer_info); 396 } 397 } 398 break; 399 default: 400 case 0: 401 /* Extended Receive Descriptor (Read) Format 402 * 403 * +-----------------------------------------------------+ 404 * 0 | Buffer Address [63:0] | 405 * +-----------------------------------------------------+ 406 * 8 | Reserved | 407 * +-----------------------------------------------------+ 408 */ 409 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n"); 410 /* Extended Receive Descriptor (Write-Back) Format 411 * 412 * 63 48 47 32 31 24 23 4 3 0 413 * +------------------------------------------------------+ 414 * | RSS Hash | | | | 415 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS | 416 * | Packet | IP | | | Type | 417 * | Checksum | Ident | | | | 418 * +------------------------------------------------------+ 419 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 420 * +------------------------------------------------------+ 421 * 63 48 47 32 31 20 19 0 422 */ 423 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n"); 424 425 for (i = 0; i < rx_ring->count; i++) { 426 const char *next_desc; 427 428 buffer_info = &rx_ring->buffer_info[i]; 429 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 430 u1 = (struct my_u1 *)rx_desc; 431 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 432 433 if (i == rx_ring->next_to_use) 434 next_desc = " NTU"; 435 else if (i == rx_ring->next_to_clean) 436 next_desc = " NTC"; 437 else 438 next_desc = ""; 439 440 if (staterr & E1000_RXD_STAT_DD) { 441 /* Descriptor Done */ 442 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n", 443 "RWB", i, 444 (unsigned long long)le64_to_cpu(u1->a), 445 (unsigned long long)le64_to_cpu(u1->b), 446 buffer_info->skb, next_desc); 447 } else { 448 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n", 449 "R ", i, 450 (unsigned long long)le64_to_cpu(u1->a), 451 (unsigned long long)le64_to_cpu(u1->b), 452 (unsigned long long)buffer_info->dma, 453 buffer_info->skb, next_desc); 454 455 if (netif_msg_pktdata(adapter) && 456 buffer_info->skb) 457 print_hex_dump(KERN_INFO, "", 458 DUMP_PREFIX_ADDRESS, 16, 459 1, 460 buffer_info->skb->data, 461 adapter->rx_buffer_len, 462 true); 463 } 464 } 465 } 466 } 467 468 /** 469 * e1000_desc_unused - calculate if we have unused descriptors 470 * @ring: pointer to ring struct to perform calculation on 471 **/ 472 static int e1000_desc_unused(struct e1000_ring *ring) 473 { 474 if (ring->next_to_clean > ring->next_to_use) 475 return ring->next_to_clean - ring->next_to_use - 1; 476 477 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 478 } 479 480 /** 481 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp 482 * @adapter: board private structure 483 * @hwtstamps: time stamp structure to update 484 * @systim: unsigned 64bit system time value. 485 * 486 * Convert the system time value stored in the RX/TXSTMP registers into a 487 * hwtstamp which can be used by the upper level time stamping functions. 488 * 489 * The 'systim_lock' spinlock is used to protect the consistency of the 490 * system time value. This is needed because reading the 64 bit time 491 * value involves reading two 32 bit registers. The first read latches the 492 * value. 493 **/ 494 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter, 495 struct skb_shared_hwtstamps *hwtstamps, 496 u64 systim) 497 { 498 u64 ns; 499 unsigned long flags; 500 501 spin_lock_irqsave(&adapter->systim_lock, flags); 502 ns = timecounter_cyc2time(&adapter->tc, systim); 503 spin_unlock_irqrestore(&adapter->systim_lock, flags); 504 505 memset(hwtstamps, 0, sizeof(*hwtstamps)); 506 hwtstamps->hwtstamp = ns_to_ktime(ns); 507 } 508 509 /** 510 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp 511 * @adapter: board private structure 512 * @status: descriptor extended error and status field 513 * @skb: particular skb to include time stamp 514 * 515 * If the time stamp is valid, convert it into the timecounter ns value 516 * and store that result into the shhwtstamps structure which is passed 517 * up the network stack. 518 **/ 519 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status, 520 struct sk_buff *skb) 521 { 522 struct e1000_hw *hw = &adapter->hw; 523 u64 rxstmp; 524 525 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) || 526 !(status & E1000_RXDEXT_STATERR_TST) || 527 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 528 return; 529 530 /* The Rx time stamp registers contain the time stamp. No other 531 * received packet will be time stamped until the Rx time stamp 532 * registers are read. Because only one packet can be time stamped 533 * at a time, the register values must belong to this packet and 534 * therefore none of the other additional attributes need to be 535 * compared. 536 */ 537 rxstmp = (u64)er32(RXSTMPL); 538 rxstmp |= (u64)er32(RXSTMPH) << 32; 539 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp); 540 541 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP; 542 } 543 544 /** 545 * e1000_receive_skb - helper function to handle Rx indications 546 * @adapter: board private structure 547 * @netdev: pointer to netdev struct 548 * @staterr: descriptor extended error and status field as written by hardware 549 * @vlan: descriptor vlan field as written by hardware (no le/be conversion) 550 * @skb: pointer to sk_buff to be indicated to stack 551 **/ 552 static void e1000_receive_skb(struct e1000_adapter *adapter, 553 struct net_device *netdev, struct sk_buff *skb, 554 u32 staterr, __le16 vlan) 555 { 556 u16 tag = le16_to_cpu(vlan); 557 558 e1000e_rx_hwtstamp(adapter, staterr, skb); 559 560 skb->protocol = eth_type_trans(skb, netdev); 561 562 if (staterr & E1000_RXD_STAT_VP) 563 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag); 564 565 napi_gro_receive(&adapter->napi, skb); 566 } 567 568 /** 569 * e1000_rx_checksum - Receive Checksum Offload 570 * @adapter: board private structure 571 * @status_err: receive descriptor status and error fields 572 * @skb: socket buffer with received data 573 **/ 574 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, 575 struct sk_buff *skb) 576 { 577 u16 status = (u16)status_err; 578 u8 errors = (u8)(status_err >> 24); 579 580 skb_checksum_none_assert(skb); 581 582 /* Rx checksum disabled */ 583 if (!(adapter->netdev->features & NETIF_F_RXCSUM)) 584 return; 585 586 /* Ignore Checksum bit is set */ 587 if (status & E1000_RXD_STAT_IXSM) 588 return; 589 590 /* TCP/UDP checksum error bit or IP checksum error bit is set */ 591 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) { 592 /* let the stack verify checksum errors */ 593 adapter->hw_csum_err++; 594 return; 595 } 596 597 /* TCP/UDP Checksum has not been calculated */ 598 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) 599 return; 600 601 /* It must be a TCP or UDP packet with a valid checksum */ 602 skb->ip_summed = CHECKSUM_UNNECESSARY; 603 adapter->hw_csum_good++; 604 } 605 606 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i) 607 { 608 struct e1000_adapter *adapter = rx_ring->adapter; 609 struct e1000_hw *hw = &adapter->hw; 610 611 __ew32_prepare(hw); 612 writel(i, rx_ring->tail); 613 614 if (unlikely(i != readl(rx_ring->tail))) { 615 u32 rctl = er32(RCTL); 616 617 ew32(RCTL, rctl & ~E1000_RCTL_EN); 618 e_err("ME firmware caused invalid RDT - resetting\n"); 619 schedule_work(&adapter->reset_task); 620 } 621 } 622 623 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i) 624 { 625 struct e1000_adapter *adapter = tx_ring->adapter; 626 struct e1000_hw *hw = &adapter->hw; 627 628 __ew32_prepare(hw); 629 writel(i, tx_ring->tail); 630 631 if (unlikely(i != readl(tx_ring->tail))) { 632 u32 tctl = er32(TCTL); 633 634 ew32(TCTL, tctl & ~E1000_TCTL_EN); 635 e_err("ME firmware caused invalid TDT - resetting\n"); 636 schedule_work(&adapter->reset_task); 637 } 638 } 639 640 /** 641 * e1000_alloc_rx_buffers - Replace used receive buffers 642 * @rx_ring: Rx descriptor ring 643 * @cleaned_count: number to reallocate 644 * @gfp: flags for allocation 645 **/ 646 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring, 647 int cleaned_count, gfp_t gfp) 648 { 649 struct e1000_adapter *adapter = rx_ring->adapter; 650 struct net_device *netdev = adapter->netdev; 651 struct pci_dev *pdev = adapter->pdev; 652 union e1000_rx_desc_extended *rx_desc; 653 struct e1000_buffer *buffer_info; 654 struct sk_buff *skb; 655 unsigned int i; 656 unsigned int bufsz = adapter->rx_buffer_len; 657 658 i = rx_ring->next_to_use; 659 buffer_info = &rx_ring->buffer_info[i]; 660 661 while (cleaned_count--) { 662 skb = buffer_info->skb; 663 if (skb) { 664 skb_trim(skb, 0); 665 goto map_skb; 666 } 667 668 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 669 if (!skb) { 670 /* Better luck next round */ 671 adapter->alloc_rx_buff_failed++; 672 break; 673 } 674 675 buffer_info->skb = skb; 676 map_skb: 677 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 678 adapter->rx_buffer_len, 679 DMA_FROM_DEVICE); 680 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 681 dev_err(&pdev->dev, "Rx DMA map failed\n"); 682 adapter->rx_dma_failed++; 683 break; 684 } 685 686 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 687 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 688 689 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 690 /* Force memory writes to complete before letting h/w 691 * know there are new descriptors to fetch. (Only 692 * applicable for weak-ordered memory model archs, 693 * such as IA-64). 694 */ 695 wmb(); 696 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 697 e1000e_update_rdt_wa(rx_ring, i); 698 else 699 writel(i, rx_ring->tail); 700 } 701 i++; 702 if (i == rx_ring->count) 703 i = 0; 704 buffer_info = &rx_ring->buffer_info[i]; 705 } 706 707 rx_ring->next_to_use = i; 708 } 709 710 /** 711 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split 712 * @rx_ring: Rx descriptor ring 713 * @cleaned_count: number to reallocate 714 * @gfp: flags for allocation 715 **/ 716 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring, 717 int cleaned_count, gfp_t gfp) 718 { 719 struct e1000_adapter *adapter = rx_ring->adapter; 720 struct net_device *netdev = adapter->netdev; 721 struct pci_dev *pdev = adapter->pdev; 722 union e1000_rx_desc_packet_split *rx_desc; 723 struct e1000_buffer *buffer_info; 724 struct e1000_ps_page *ps_page; 725 struct sk_buff *skb; 726 unsigned int i, j; 727 728 i = rx_ring->next_to_use; 729 buffer_info = &rx_ring->buffer_info[i]; 730 731 while (cleaned_count--) { 732 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 733 734 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 735 ps_page = &buffer_info->ps_pages[j]; 736 if (j >= adapter->rx_ps_pages) { 737 /* all unused desc entries get hw null ptr */ 738 rx_desc->read.buffer_addr[j + 1] = 739 ~cpu_to_le64(0); 740 continue; 741 } 742 if (!ps_page->page) { 743 ps_page->page = alloc_page(gfp); 744 if (!ps_page->page) { 745 adapter->alloc_rx_buff_failed++; 746 goto no_buffers; 747 } 748 ps_page->dma = dma_map_page(&pdev->dev, 749 ps_page->page, 750 0, PAGE_SIZE, 751 DMA_FROM_DEVICE); 752 if (dma_mapping_error(&pdev->dev, 753 ps_page->dma)) { 754 dev_err(&adapter->pdev->dev, 755 "Rx DMA page map failed\n"); 756 adapter->rx_dma_failed++; 757 goto no_buffers; 758 } 759 } 760 /* Refresh the desc even if buffer_addrs 761 * didn't change because each write-back 762 * erases this info. 763 */ 764 rx_desc->read.buffer_addr[j + 1] = 765 cpu_to_le64(ps_page->dma); 766 } 767 768 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0, 769 gfp); 770 771 if (!skb) { 772 adapter->alloc_rx_buff_failed++; 773 break; 774 } 775 776 buffer_info->skb = skb; 777 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 778 adapter->rx_ps_bsize0, 779 DMA_FROM_DEVICE); 780 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 781 dev_err(&pdev->dev, "Rx DMA map failed\n"); 782 adapter->rx_dma_failed++; 783 /* cleanup skb */ 784 dev_kfree_skb_any(skb); 785 buffer_info->skb = NULL; 786 break; 787 } 788 789 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); 790 791 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 792 /* Force memory writes to complete before letting h/w 793 * know there are new descriptors to fetch. (Only 794 * applicable for weak-ordered memory model archs, 795 * such as IA-64). 796 */ 797 wmb(); 798 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 799 e1000e_update_rdt_wa(rx_ring, i << 1); 800 else 801 writel(i << 1, rx_ring->tail); 802 } 803 804 i++; 805 if (i == rx_ring->count) 806 i = 0; 807 buffer_info = &rx_ring->buffer_info[i]; 808 } 809 810 no_buffers: 811 rx_ring->next_to_use = i; 812 } 813 814 /** 815 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers 816 * @rx_ring: Rx descriptor ring 817 * @cleaned_count: number of buffers to allocate this pass 818 * @gfp: flags for allocation 819 **/ 820 821 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring, 822 int cleaned_count, gfp_t gfp) 823 { 824 struct e1000_adapter *adapter = rx_ring->adapter; 825 struct net_device *netdev = adapter->netdev; 826 struct pci_dev *pdev = adapter->pdev; 827 union e1000_rx_desc_extended *rx_desc; 828 struct e1000_buffer *buffer_info; 829 struct sk_buff *skb; 830 unsigned int i; 831 unsigned int bufsz = 256 - 16; /* for skb_reserve */ 832 833 i = rx_ring->next_to_use; 834 buffer_info = &rx_ring->buffer_info[i]; 835 836 while (cleaned_count--) { 837 skb = buffer_info->skb; 838 if (skb) { 839 skb_trim(skb, 0); 840 goto check_page; 841 } 842 843 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 844 if (unlikely(!skb)) { 845 /* Better luck next round */ 846 adapter->alloc_rx_buff_failed++; 847 break; 848 } 849 850 buffer_info->skb = skb; 851 check_page: 852 /* allocate a new page if necessary */ 853 if (!buffer_info->page) { 854 buffer_info->page = alloc_page(gfp); 855 if (unlikely(!buffer_info->page)) { 856 adapter->alloc_rx_buff_failed++; 857 break; 858 } 859 } 860 861 if (!buffer_info->dma) { 862 buffer_info->dma = dma_map_page(&pdev->dev, 863 buffer_info->page, 0, 864 PAGE_SIZE, 865 DMA_FROM_DEVICE); 866 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 867 adapter->alloc_rx_buff_failed++; 868 break; 869 } 870 } 871 872 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 873 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 874 875 if (unlikely(++i == rx_ring->count)) 876 i = 0; 877 buffer_info = &rx_ring->buffer_info[i]; 878 } 879 880 if (likely(rx_ring->next_to_use != i)) { 881 rx_ring->next_to_use = i; 882 if (unlikely(i-- == 0)) 883 i = (rx_ring->count - 1); 884 885 /* Force memory writes to complete before letting h/w 886 * know there are new descriptors to fetch. (Only 887 * applicable for weak-ordered memory model archs, 888 * such as IA-64). 889 */ 890 wmb(); 891 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 892 e1000e_update_rdt_wa(rx_ring, i); 893 else 894 writel(i, rx_ring->tail); 895 } 896 } 897 898 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss, 899 struct sk_buff *skb) 900 { 901 if (netdev->features & NETIF_F_RXHASH) 902 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3); 903 } 904 905 /** 906 * e1000_clean_rx_irq - Send received data up the network stack 907 * @rx_ring: Rx descriptor ring 908 * @work_done: output parameter for indicating completed work 909 * @work_to_do: how many packets we can clean 910 * 911 * the return value indicates whether actual cleaning was done, there 912 * is no guarantee that everything was cleaned 913 **/ 914 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done, 915 int work_to_do) 916 { 917 struct e1000_adapter *adapter = rx_ring->adapter; 918 struct net_device *netdev = adapter->netdev; 919 struct pci_dev *pdev = adapter->pdev; 920 struct e1000_hw *hw = &adapter->hw; 921 union e1000_rx_desc_extended *rx_desc, *next_rxd; 922 struct e1000_buffer *buffer_info, *next_buffer; 923 u32 length, staterr; 924 unsigned int i; 925 int cleaned_count = 0; 926 bool cleaned = false; 927 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 928 929 i = rx_ring->next_to_clean; 930 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 931 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 932 buffer_info = &rx_ring->buffer_info[i]; 933 934 while (staterr & E1000_RXD_STAT_DD) { 935 struct sk_buff *skb; 936 937 if (*work_done >= work_to_do) 938 break; 939 (*work_done)++; 940 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 941 942 skb = buffer_info->skb; 943 buffer_info->skb = NULL; 944 945 prefetch(skb->data - NET_IP_ALIGN); 946 947 i++; 948 if (i == rx_ring->count) 949 i = 0; 950 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 951 prefetch(next_rxd); 952 953 next_buffer = &rx_ring->buffer_info[i]; 954 955 cleaned = true; 956 cleaned_count++; 957 dma_unmap_single(&pdev->dev, buffer_info->dma, 958 adapter->rx_buffer_len, DMA_FROM_DEVICE); 959 buffer_info->dma = 0; 960 961 length = le16_to_cpu(rx_desc->wb.upper.length); 962 963 /* !EOP means multiple descriptors were used to store a single 964 * packet, if that's the case we need to toss it. In fact, we 965 * need to toss every packet with the EOP bit clear and the 966 * next frame that _does_ have the EOP bit set, as it is by 967 * definition only a frame fragment 968 */ 969 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) 970 adapter->flags2 |= FLAG2_IS_DISCARDING; 971 972 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 973 /* All receives must fit into a single buffer */ 974 e_dbg("Receive packet consumed multiple buffers\n"); 975 /* recycle */ 976 buffer_info->skb = skb; 977 if (staterr & E1000_RXD_STAT_EOP) 978 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 979 goto next_desc; 980 } 981 982 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 983 !(netdev->features & NETIF_F_RXALL))) { 984 /* recycle */ 985 buffer_info->skb = skb; 986 goto next_desc; 987 } 988 989 /* adjust length to remove Ethernet CRC */ 990 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 991 /* If configured to store CRC, don't subtract FCS, 992 * but keep the FCS bytes out of the total_rx_bytes 993 * counter 994 */ 995 if (netdev->features & NETIF_F_RXFCS) 996 total_rx_bytes -= 4; 997 else 998 length -= 4; 999 } 1000 1001 total_rx_bytes += length; 1002 total_rx_packets++; 1003 1004 /* code added for copybreak, this should improve 1005 * performance for small packets with large amounts 1006 * of reassembly being done in the stack 1007 */ 1008 if (length < copybreak) { 1009 struct sk_buff *new_skb = 1010 napi_alloc_skb(&adapter->napi, length); 1011 if (new_skb) { 1012 skb_copy_to_linear_data_offset(new_skb, 1013 -NET_IP_ALIGN, 1014 (skb->data - 1015 NET_IP_ALIGN), 1016 (length + 1017 NET_IP_ALIGN)); 1018 /* save the skb in buffer_info as good */ 1019 buffer_info->skb = skb; 1020 skb = new_skb; 1021 } 1022 /* else just continue with the old one */ 1023 } 1024 /* end copybreak code */ 1025 skb_put(skb, length); 1026 1027 /* Receive Checksum Offload */ 1028 e1000_rx_checksum(adapter, staterr, skb); 1029 1030 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1031 1032 e1000_receive_skb(adapter, netdev, skb, staterr, 1033 rx_desc->wb.upper.vlan); 1034 1035 next_desc: 1036 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1037 1038 /* return some buffers to hardware, one at a time is too slow */ 1039 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1040 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1041 GFP_ATOMIC); 1042 cleaned_count = 0; 1043 } 1044 1045 /* use prefetched values */ 1046 rx_desc = next_rxd; 1047 buffer_info = next_buffer; 1048 1049 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1050 } 1051 rx_ring->next_to_clean = i; 1052 1053 cleaned_count = e1000_desc_unused(rx_ring); 1054 if (cleaned_count) 1055 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1056 1057 adapter->total_rx_bytes += total_rx_bytes; 1058 adapter->total_rx_packets += total_rx_packets; 1059 return cleaned; 1060 } 1061 1062 static void e1000_put_txbuf(struct e1000_ring *tx_ring, 1063 struct e1000_buffer *buffer_info, 1064 bool drop) 1065 { 1066 struct e1000_adapter *adapter = tx_ring->adapter; 1067 1068 if (buffer_info->dma) { 1069 if (buffer_info->mapped_as_page) 1070 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, 1071 buffer_info->length, DMA_TO_DEVICE); 1072 else 1073 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 1074 buffer_info->length, DMA_TO_DEVICE); 1075 buffer_info->dma = 0; 1076 } 1077 if (buffer_info->skb) { 1078 if (drop) 1079 dev_kfree_skb_any(buffer_info->skb); 1080 else 1081 dev_consume_skb_any(buffer_info->skb); 1082 buffer_info->skb = NULL; 1083 } 1084 buffer_info->time_stamp = 0; 1085 } 1086 1087 static void e1000_print_hw_hang(struct work_struct *work) 1088 { 1089 struct e1000_adapter *adapter = container_of(work, 1090 struct e1000_adapter, 1091 print_hang_task); 1092 struct net_device *netdev = adapter->netdev; 1093 struct e1000_ring *tx_ring = adapter->tx_ring; 1094 unsigned int i = tx_ring->next_to_clean; 1095 unsigned int eop = tx_ring->buffer_info[i].next_to_watch; 1096 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); 1097 struct e1000_hw *hw = &adapter->hw; 1098 u16 phy_status, phy_1000t_status, phy_ext_status; 1099 u16 pci_status; 1100 1101 if (test_bit(__E1000_DOWN, &adapter->state)) 1102 return; 1103 1104 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) { 1105 /* May be block on write-back, flush and detect again 1106 * flush pending descriptor writebacks to memory 1107 */ 1108 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1109 /* execute the writes immediately */ 1110 e1e_flush(); 1111 /* Due to rare timing issues, write to TIDV again to ensure 1112 * the write is successful 1113 */ 1114 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1115 /* execute the writes immediately */ 1116 e1e_flush(); 1117 adapter->tx_hang_recheck = true; 1118 return; 1119 } 1120 adapter->tx_hang_recheck = false; 1121 1122 if (er32(TDH(0)) == er32(TDT(0))) { 1123 e_dbg("false hang detected, ignoring\n"); 1124 return; 1125 } 1126 1127 /* Real hang detected */ 1128 netif_stop_queue(netdev); 1129 1130 e1e_rphy(hw, MII_BMSR, &phy_status); 1131 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status); 1132 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status); 1133 1134 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status); 1135 1136 /* detected Hardware unit hang */ 1137 e_err("Detected Hardware Unit Hang:\n" 1138 " TDH <%x>\n" 1139 " TDT <%x>\n" 1140 " next_to_use <%x>\n" 1141 " next_to_clean <%x>\n" 1142 "buffer_info[next_to_clean]:\n" 1143 " time_stamp <%lx>\n" 1144 " next_to_watch <%x>\n" 1145 " jiffies <%lx>\n" 1146 " next_to_watch.status <%x>\n" 1147 "MAC Status <%x>\n" 1148 "PHY Status <%x>\n" 1149 "PHY 1000BASE-T Status <%x>\n" 1150 "PHY Extended Status <%x>\n" 1151 "PCI Status <%x>\n", 1152 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use, 1153 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp, 1154 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS), 1155 phy_status, phy_1000t_status, phy_ext_status, pci_status); 1156 1157 e1000e_dump(adapter); 1158 1159 /* Suggest workaround for known h/w issue */ 1160 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE)) 1161 e_err("Try turning off Tx pause (flow control) via ethtool\n"); 1162 } 1163 1164 /** 1165 * e1000e_tx_hwtstamp_work - check for Tx time stamp 1166 * @work: pointer to work struct 1167 * 1168 * This work function polls the TSYNCTXCTL valid bit to determine when a 1169 * timestamp has been taken for the current stored skb. The timestamp must 1170 * be for this skb because only one such packet is allowed in the queue. 1171 */ 1172 static void e1000e_tx_hwtstamp_work(struct work_struct *work) 1173 { 1174 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, 1175 tx_hwtstamp_work); 1176 struct e1000_hw *hw = &adapter->hw; 1177 1178 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) { 1179 struct sk_buff *skb = adapter->tx_hwtstamp_skb; 1180 struct skb_shared_hwtstamps shhwtstamps; 1181 u64 txstmp; 1182 1183 txstmp = er32(TXSTMPL); 1184 txstmp |= (u64)er32(TXSTMPH) << 32; 1185 1186 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp); 1187 1188 /* Clear the global tx_hwtstamp_skb pointer and force writes 1189 * prior to notifying the stack of a Tx timestamp. 1190 */ 1191 adapter->tx_hwtstamp_skb = NULL; 1192 wmb(); /* force write prior to skb_tstamp_tx */ 1193 1194 skb_tstamp_tx(skb, &shhwtstamps); 1195 dev_consume_skb_any(skb); 1196 } else if (time_after(jiffies, adapter->tx_hwtstamp_start 1197 + adapter->tx_timeout_factor * HZ)) { 1198 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 1199 adapter->tx_hwtstamp_skb = NULL; 1200 adapter->tx_hwtstamp_timeouts++; 1201 e_warn("clearing Tx timestamp hang\n"); 1202 } else { 1203 /* reschedule to check later */ 1204 schedule_work(&adapter->tx_hwtstamp_work); 1205 } 1206 } 1207 1208 /** 1209 * e1000_clean_tx_irq - Reclaim resources after transmit completes 1210 * @tx_ring: Tx descriptor ring 1211 * 1212 * the return value indicates whether actual cleaning was done, there 1213 * is no guarantee that everything was cleaned 1214 **/ 1215 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring) 1216 { 1217 struct e1000_adapter *adapter = tx_ring->adapter; 1218 struct net_device *netdev = adapter->netdev; 1219 struct e1000_hw *hw = &adapter->hw; 1220 struct e1000_tx_desc *tx_desc, *eop_desc; 1221 struct e1000_buffer *buffer_info; 1222 unsigned int i, eop; 1223 unsigned int count = 0; 1224 unsigned int total_tx_bytes = 0, total_tx_packets = 0; 1225 unsigned int bytes_compl = 0, pkts_compl = 0; 1226 1227 i = tx_ring->next_to_clean; 1228 eop = tx_ring->buffer_info[i].next_to_watch; 1229 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1230 1231 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) && 1232 (count < tx_ring->count)) { 1233 bool cleaned = false; 1234 1235 dma_rmb(); /* read buffer_info after eop_desc */ 1236 for (; !cleaned; count++) { 1237 tx_desc = E1000_TX_DESC(*tx_ring, i); 1238 buffer_info = &tx_ring->buffer_info[i]; 1239 cleaned = (i == eop); 1240 1241 if (cleaned) { 1242 total_tx_packets += buffer_info->segs; 1243 total_tx_bytes += buffer_info->bytecount; 1244 if (buffer_info->skb) { 1245 bytes_compl += buffer_info->skb->len; 1246 pkts_compl++; 1247 } 1248 } 1249 1250 e1000_put_txbuf(tx_ring, buffer_info, false); 1251 tx_desc->upper.data = 0; 1252 1253 i++; 1254 if (i == tx_ring->count) 1255 i = 0; 1256 } 1257 1258 if (i == tx_ring->next_to_use) 1259 break; 1260 eop = tx_ring->buffer_info[i].next_to_watch; 1261 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1262 } 1263 1264 tx_ring->next_to_clean = i; 1265 1266 netdev_completed_queue(netdev, pkts_compl, bytes_compl); 1267 1268 #define TX_WAKE_THRESHOLD 32 1269 if (count && netif_carrier_ok(netdev) && 1270 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { 1271 /* Make sure that anybody stopping the queue after this 1272 * sees the new next_to_clean. 1273 */ 1274 smp_mb(); 1275 1276 if (netif_queue_stopped(netdev) && 1277 !(test_bit(__E1000_DOWN, &adapter->state))) { 1278 netif_wake_queue(netdev); 1279 ++adapter->restart_queue; 1280 } 1281 } 1282 1283 if (adapter->detect_tx_hung) { 1284 /* Detect a transmit hang in hardware, this serializes the 1285 * check with the clearing of time_stamp and movement of i 1286 */ 1287 adapter->detect_tx_hung = false; 1288 if (tx_ring->buffer_info[i].time_stamp && 1289 time_after(jiffies, tx_ring->buffer_info[i].time_stamp 1290 + (adapter->tx_timeout_factor * HZ)) && 1291 !(er32(STATUS) & E1000_STATUS_TXOFF)) 1292 schedule_work(&adapter->print_hang_task); 1293 else 1294 adapter->tx_hang_recheck = false; 1295 } 1296 adapter->total_tx_bytes += total_tx_bytes; 1297 adapter->total_tx_packets += total_tx_packets; 1298 return count < tx_ring->count; 1299 } 1300 1301 /** 1302 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split 1303 * @rx_ring: Rx descriptor ring 1304 * @work_done: output parameter for indicating completed work 1305 * @work_to_do: how many packets we can clean 1306 * 1307 * the return value indicates whether actual cleaning was done, there 1308 * is no guarantee that everything was cleaned 1309 **/ 1310 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done, 1311 int work_to_do) 1312 { 1313 struct e1000_adapter *adapter = rx_ring->adapter; 1314 struct e1000_hw *hw = &adapter->hw; 1315 union e1000_rx_desc_packet_split *rx_desc, *next_rxd; 1316 struct net_device *netdev = adapter->netdev; 1317 struct pci_dev *pdev = adapter->pdev; 1318 struct e1000_buffer *buffer_info, *next_buffer; 1319 struct e1000_ps_page *ps_page; 1320 struct sk_buff *skb; 1321 unsigned int i, j; 1322 u32 length, staterr; 1323 int cleaned_count = 0; 1324 bool cleaned = false; 1325 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1326 1327 i = rx_ring->next_to_clean; 1328 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 1329 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1330 buffer_info = &rx_ring->buffer_info[i]; 1331 1332 while (staterr & E1000_RXD_STAT_DD) { 1333 if (*work_done >= work_to_do) 1334 break; 1335 (*work_done)++; 1336 skb = buffer_info->skb; 1337 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1338 1339 /* in the packet split case this is header only */ 1340 prefetch(skb->data - NET_IP_ALIGN); 1341 1342 i++; 1343 if (i == rx_ring->count) 1344 i = 0; 1345 next_rxd = E1000_RX_DESC_PS(*rx_ring, i); 1346 prefetch(next_rxd); 1347 1348 next_buffer = &rx_ring->buffer_info[i]; 1349 1350 cleaned = true; 1351 cleaned_count++; 1352 dma_unmap_single(&pdev->dev, buffer_info->dma, 1353 adapter->rx_ps_bsize0, DMA_FROM_DEVICE); 1354 buffer_info->dma = 0; 1355 1356 /* see !EOP comment in other Rx routine */ 1357 if (!(staterr & E1000_RXD_STAT_EOP)) 1358 adapter->flags2 |= FLAG2_IS_DISCARDING; 1359 1360 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 1361 e_dbg("Packet Split buffers didn't pick up the full packet\n"); 1362 dev_kfree_skb_irq(skb); 1363 if (staterr & E1000_RXD_STAT_EOP) 1364 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1365 goto next_desc; 1366 } 1367 1368 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1369 !(netdev->features & NETIF_F_RXALL))) { 1370 dev_kfree_skb_irq(skb); 1371 goto next_desc; 1372 } 1373 1374 length = le16_to_cpu(rx_desc->wb.middle.length0); 1375 1376 if (!length) { 1377 e_dbg("Last part of the packet spanning multiple descriptors\n"); 1378 dev_kfree_skb_irq(skb); 1379 goto next_desc; 1380 } 1381 1382 /* Good Receive */ 1383 skb_put(skb, length); 1384 1385 { 1386 /* this looks ugly, but it seems compiler issues make 1387 * it more efficient than reusing j 1388 */ 1389 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); 1390 1391 /* page alloc/put takes too long and effects small 1392 * packet throughput, so unsplit small packets and 1393 * save the alloc/put 1394 */ 1395 if (l1 && (l1 <= copybreak) && 1396 ((length + l1) <= adapter->rx_ps_bsize0)) { 1397 ps_page = &buffer_info->ps_pages[0]; 1398 1399 dma_sync_single_for_cpu(&pdev->dev, 1400 ps_page->dma, 1401 PAGE_SIZE, 1402 DMA_FROM_DEVICE); 1403 memcpy(skb_tail_pointer(skb), 1404 page_address(ps_page->page), l1); 1405 dma_sync_single_for_device(&pdev->dev, 1406 ps_page->dma, 1407 PAGE_SIZE, 1408 DMA_FROM_DEVICE); 1409 1410 /* remove the CRC */ 1411 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1412 if (!(netdev->features & NETIF_F_RXFCS)) 1413 l1 -= 4; 1414 } 1415 1416 skb_put(skb, l1); 1417 goto copydone; 1418 } /* if */ 1419 } 1420 1421 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1422 length = le16_to_cpu(rx_desc->wb.upper.length[j]); 1423 if (!length) 1424 break; 1425 1426 ps_page = &buffer_info->ps_pages[j]; 1427 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1428 DMA_FROM_DEVICE); 1429 ps_page->dma = 0; 1430 skb_fill_page_desc(skb, j, ps_page->page, 0, length); 1431 ps_page->page = NULL; 1432 skb->len += length; 1433 skb->data_len += length; 1434 skb->truesize += PAGE_SIZE; 1435 } 1436 1437 /* strip the ethernet crc, problem is we're using pages now so 1438 * this whole operation can get a little cpu intensive 1439 */ 1440 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1441 if (!(netdev->features & NETIF_F_RXFCS)) 1442 pskb_trim(skb, skb->len - 4); 1443 } 1444 1445 copydone: 1446 total_rx_bytes += skb->len; 1447 total_rx_packets++; 1448 1449 e1000_rx_checksum(adapter, staterr, skb); 1450 1451 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1452 1453 if (rx_desc->wb.upper.header_status & 1454 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)) 1455 adapter->rx_hdr_split++; 1456 1457 e1000_receive_skb(adapter, netdev, skb, staterr, 1458 rx_desc->wb.middle.vlan); 1459 1460 next_desc: 1461 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); 1462 buffer_info->skb = NULL; 1463 1464 /* return some buffers to hardware, one at a time is too slow */ 1465 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1466 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1467 GFP_ATOMIC); 1468 cleaned_count = 0; 1469 } 1470 1471 /* use prefetched values */ 1472 rx_desc = next_rxd; 1473 buffer_info = next_buffer; 1474 1475 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1476 } 1477 rx_ring->next_to_clean = i; 1478 1479 cleaned_count = e1000_desc_unused(rx_ring); 1480 if (cleaned_count) 1481 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1482 1483 adapter->total_rx_bytes += total_rx_bytes; 1484 adapter->total_rx_packets += total_rx_packets; 1485 return cleaned; 1486 } 1487 1488 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb, 1489 u16 length) 1490 { 1491 bi->page = NULL; 1492 skb->len += length; 1493 skb->data_len += length; 1494 skb->truesize += PAGE_SIZE; 1495 } 1496 1497 /** 1498 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy 1499 * @rx_ring: Rx descriptor ring 1500 * @work_done: output parameter for indicating completed work 1501 * @work_to_do: how many packets we can clean 1502 * 1503 * the return value indicates whether actual cleaning was done, there 1504 * is no guarantee that everything was cleaned 1505 **/ 1506 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done, 1507 int work_to_do) 1508 { 1509 struct e1000_adapter *adapter = rx_ring->adapter; 1510 struct net_device *netdev = adapter->netdev; 1511 struct pci_dev *pdev = adapter->pdev; 1512 union e1000_rx_desc_extended *rx_desc, *next_rxd; 1513 struct e1000_buffer *buffer_info, *next_buffer; 1514 u32 length, staterr; 1515 unsigned int i; 1516 int cleaned_count = 0; 1517 bool cleaned = false; 1518 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1519 struct skb_shared_info *shinfo; 1520 1521 i = rx_ring->next_to_clean; 1522 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 1523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1524 buffer_info = &rx_ring->buffer_info[i]; 1525 1526 while (staterr & E1000_RXD_STAT_DD) { 1527 struct sk_buff *skb; 1528 1529 if (*work_done >= work_to_do) 1530 break; 1531 (*work_done)++; 1532 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1533 1534 skb = buffer_info->skb; 1535 buffer_info->skb = NULL; 1536 1537 ++i; 1538 if (i == rx_ring->count) 1539 i = 0; 1540 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 1541 prefetch(next_rxd); 1542 1543 next_buffer = &rx_ring->buffer_info[i]; 1544 1545 cleaned = true; 1546 cleaned_count++; 1547 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE, 1548 DMA_FROM_DEVICE); 1549 buffer_info->dma = 0; 1550 1551 length = le16_to_cpu(rx_desc->wb.upper.length); 1552 1553 /* errors is only valid for DD + EOP descriptors */ 1554 if (unlikely((staterr & E1000_RXD_STAT_EOP) && 1555 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1556 !(netdev->features & NETIF_F_RXALL)))) { 1557 /* recycle both page and skb */ 1558 buffer_info->skb = skb; 1559 /* an error means any chain goes out the window too */ 1560 if (rx_ring->rx_skb_top) 1561 dev_kfree_skb_irq(rx_ring->rx_skb_top); 1562 rx_ring->rx_skb_top = NULL; 1563 goto next_desc; 1564 } 1565 #define rxtop (rx_ring->rx_skb_top) 1566 if (!(staterr & E1000_RXD_STAT_EOP)) { 1567 /* this descriptor is only the beginning (or middle) */ 1568 if (!rxtop) { 1569 /* this is the beginning of a chain */ 1570 rxtop = skb; 1571 skb_fill_page_desc(rxtop, 0, buffer_info->page, 1572 0, length); 1573 } else { 1574 /* this is the middle of a chain */ 1575 shinfo = skb_shinfo(rxtop); 1576 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1577 buffer_info->page, 0, 1578 length); 1579 /* re-use the skb, only consumed the page */ 1580 buffer_info->skb = skb; 1581 } 1582 e1000_consume_page(buffer_info, rxtop, length); 1583 goto next_desc; 1584 } else { 1585 if (rxtop) { 1586 /* end of the chain */ 1587 shinfo = skb_shinfo(rxtop); 1588 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1589 buffer_info->page, 0, 1590 length); 1591 /* re-use the current skb, we only consumed the 1592 * page 1593 */ 1594 buffer_info->skb = skb; 1595 skb = rxtop; 1596 rxtop = NULL; 1597 e1000_consume_page(buffer_info, skb, length); 1598 } else { 1599 /* no chain, got EOP, this buf is the packet 1600 * copybreak to save the put_page/alloc_page 1601 */ 1602 if (length <= copybreak && 1603 skb_tailroom(skb) >= length) { 1604 memcpy(skb_tail_pointer(skb), 1605 page_address(buffer_info->page), 1606 length); 1607 /* re-use the page, so don't erase 1608 * buffer_info->page 1609 */ 1610 skb_put(skb, length); 1611 } else { 1612 skb_fill_page_desc(skb, 0, 1613 buffer_info->page, 0, 1614 length); 1615 e1000_consume_page(buffer_info, skb, 1616 length); 1617 } 1618 } 1619 } 1620 1621 /* Receive Checksum Offload */ 1622 e1000_rx_checksum(adapter, staterr, skb); 1623 1624 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1625 1626 /* probably a little skewed due to removing CRC */ 1627 total_rx_bytes += skb->len; 1628 total_rx_packets++; 1629 1630 /* eth type trans needs skb->data to point to something */ 1631 if (!pskb_may_pull(skb, ETH_HLEN)) { 1632 e_err("pskb_may_pull failed.\n"); 1633 dev_kfree_skb_irq(skb); 1634 goto next_desc; 1635 } 1636 1637 e1000_receive_skb(adapter, netdev, skb, staterr, 1638 rx_desc->wb.upper.vlan); 1639 1640 next_desc: 1641 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1642 1643 /* return some buffers to hardware, one at a time is too slow */ 1644 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { 1645 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1646 GFP_ATOMIC); 1647 cleaned_count = 0; 1648 } 1649 1650 /* use prefetched values */ 1651 rx_desc = next_rxd; 1652 buffer_info = next_buffer; 1653 1654 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1655 } 1656 rx_ring->next_to_clean = i; 1657 1658 cleaned_count = e1000_desc_unused(rx_ring); 1659 if (cleaned_count) 1660 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1661 1662 adapter->total_rx_bytes += total_rx_bytes; 1663 adapter->total_rx_packets += total_rx_packets; 1664 return cleaned; 1665 } 1666 1667 /** 1668 * e1000_clean_rx_ring - Free Rx Buffers per Queue 1669 * @rx_ring: Rx descriptor ring 1670 **/ 1671 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring) 1672 { 1673 struct e1000_adapter *adapter = rx_ring->adapter; 1674 struct e1000_buffer *buffer_info; 1675 struct e1000_ps_page *ps_page; 1676 struct pci_dev *pdev = adapter->pdev; 1677 unsigned int i, j; 1678 1679 /* Free all the Rx ring sk_buffs */ 1680 for (i = 0; i < rx_ring->count; i++) { 1681 buffer_info = &rx_ring->buffer_info[i]; 1682 if (buffer_info->dma) { 1683 if (adapter->clean_rx == e1000_clean_rx_irq) 1684 dma_unmap_single(&pdev->dev, buffer_info->dma, 1685 adapter->rx_buffer_len, 1686 DMA_FROM_DEVICE); 1687 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq) 1688 dma_unmap_page(&pdev->dev, buffer_info->dma, 1689 PAGE_SIZE, DMA_FROM_DEVICE); 1690 else if (adapter->clean_rx == e1000_clean_rx_irq_ps) 1691 dma_unmap_single(&pdev->dev, buffer_info->dma, 1692 adapter->rx_ps_bsize0, 1693 DMA_FROM_DEVICE); 1694 buffer_info->dma = 0; 1695 } 1696 1697 if (buffer_info->page) { 1698 put_page(buffer_info->page); 1699 buffer_info->page = NULL; 1700 } 1701 1702 if (buffer_info->skb) { 1703 dev_kfree_skb(buffer_info->skb); 1704 buffer_info->skb = NULL; 1705 } 1706 1707 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1708 ps_page = &buffer_info->ps_pages[j]; 1709 if (!ps_page->page) 1710 break; 1711 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1712 DMA_FROM_DEVICE); 1713 ps_page->dma = 0; 1714 put_page(ps_page->page); 1715 ps_page->page = NULL; 1716 } 1717 } 1718 1719 /* there also may be some cached data from a chained receive */ 1720 if (rx_ring->rx_skb_top) { 1721 dev_kfree_skb(rx_ring->rx_skb_top); 1722 rx_ring->rx_skb_top = NULL; 1723 } 1724 1725 /* Zero out the descriptor ring */ 1726 memset(rx_ring->desc, 0, rx_ring->size); 1727 1728 rx_ring->next_to_clean = 0; 1729 rx_ring->next_to_use = 0; 1730 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1731 } 1732 1733 static void e1000e_downshift_workaround(struct work_struct *work) 1734 { 1735 struct e1000_adapter *adapter = container_of(work, 1736 struct e1000_adapter, 1737 downshift_task); 1738 1739 if (test_bit(__E1000_DOWN, &adapter->state)) 1740 return; 1741 1742 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw); 1743 } 1744 1745 /** 1746 * e1000_intr_msi - Interrupt Handler 1747 * @irq: interrupt number 1748 * @data: pointer to a network interface device structure 1749 **/ 1750 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data) 1751 { 1752 struct net_device *netdev = data; 1753 struct e1000_adapter *adapter = netdev_priv(netdev); 1754 struct e1000_hw *hw = &adapter->hw; 1755 u32 icr = er32(ICR); 1756 1757 /* read ICR disables interrupts using IAM */ 1758 if (icr & E1000_ICR_LSC) { 1759 hw->mac.get_link_status = true; 1760 /* ICH8 workaround-- Call gig speed drop workaround on cable 1761 * disconnect (LSC) before accessing any PHY registers 1762 */ 1763 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1764 (!(er32(STATUS) & E1000_STATUS_LU))) 1765 schedule_work(&adapter->downshift_task); 1766 1767 /* 80003ES2LAN workaround-- For packet buffer work-around on 1768 * link down event; disable receives here in the ISR and reset 1769 * adapter in watchdog 1770 */ 1771 if (netif_carrier_ok(netdev) && 1772 adapter->flags & FLAG_RX_NEEDS_RESTART) { 1773 /* disable receives */ 1774 u32 rctl = er32(RCTL); 1775 1776 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1777 adapter->flags |= FLAG_RESTART_NOW; 1778 } 1779 /* guard against interrupt when we're going down */ 1780 if (!test_bit(__E1000_DOWN, &adapter->state)) 1781 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1782 } 1783 1784 /* Reset on uncorrectable ECC error */ 1785 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1786 u32 pbeccsts = er32(PBECCSTS); 1787 1788 adapter->corr_errors += 1789 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1790 adapter->uncorr_errors += 1791 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts); 1792 1793 /* Do the reset outside of interrupt context */ 1794 schedule_work(&adapter->reset_task); 1795 1796 /* return immediately since reset is imminent */ 1797 return IRQ_HANDLED; 1798 } 1799 1800 if (napi_schedule_prep(&adapter->napi)) { 1801 adapter->total_tx_bytes = 0; 1802 adapter->total_tx_packets = 0; 1803 adapter->total_rx_bytes = 0; 1804 adapter->total_rx_packets = 0; 1805 __napi_schedule(&adapter->napi); 1806 } 1807 1808 return IRQ_HANDLED; 1809 } 1810 1811 /** 1812 * e1000_intr - Interrupt Handler 1813 * @irq: interrupt number 1814 * @data: pointer to a network interface device structure 1815 **/ 1816 static irqreturn_t e1000_intr(int __always_unused irq, void *data) 1817 { 1818 struct net_device *netdev = data; 1819 struct e1000_adapter *adapter = netdev_priv(netdev); 1820 struct e1000_hw *hw = &adapter->hw; 1821 u32 rctl, icr = er32(ICR); 1822 1823 if (!icr || test_bit(__E1000_DOWN, &adapter->state)) 1824 return IRQ_NONE; /* Not our interrupt */ 1825 1826 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 1827 * not set, then the adapter didn't send an interrupt 1828 */ 1829 if (!(icr & E1000_ICR_INT_ASSERTED)) 1830 return IRQ_NONE; 1831 1832 /* Interrupt Auto-Mask...upon reading ICR, 1833 * interrupts are masked. No need for the 1834 * IMC write 1835 */ 1836 1837 if (icr & E1000_ICR_LSC) { 1838 hw->mac.get_link_status = true; 1839 /* ICH8 workaround-- Call gig speed drop workaround on cable 1840 * disconnect (LSC) before accessing any PHY registers 1841 */ 1842 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1843 (!(er32(STATUS) & E1000_STATUS_LU))) 1844 schedule_work(&adapter->downshift_task); 1845 1846 /* 80003ES2LAN workaround-- 1847 * For packet buffer work-around on link down event; 1848 * disable receives here in the ISR and 1849 * reset adapter in watchdog 1850 */ 1851 if (netif_carrier_ok(netdev) && 1852 (adapter->flags & FLAG_RX_NEEDS_RESTART)) { 1853 /* disable receives */ 1854 rctl = er32(RCTL); 1855 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1856 adapter->flags |= FLAG_RESTART_NOW; 1857 } 1858 /* guard against interrupt when we're going down */ 1859 if (!test_bit(__E1000_DOWN, &adapter->state)) 1860 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1861 } 1862 1863 /* Reset on uncorrectable ECC error */ 1864 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1865 u32 pbeccsts = er32(PBECCSTS); 1866 1867 adapter->corr_errors += 1868 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1869 adapter->uncorr_errors += 1870 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts); 1871 1872 /* Do the reset outside of interrupt context */ 1873 schedule_work(&adapter->reset_task); 1874 1875 /* return immediately since reset is imminent */ 1876 return IRQ_HANDLED; 1877 } 1878 1879 if (napi_schedule_prep(&adapter->napi)) { 1880 adapter->total_tx_bytes = 0; 1881 adapter->total_tx_packets = 0; 1882 adapter->total_rx_bytes = 0; 1883 adapter->total_rx_packets = 0; 1884 __napi_schedule(&adapter->napi); 1885 } 1886 1887 return IRQ_HANDLED; 1888 } 1889 1890 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data) 1891 { 1892 struct net_device *netdev = data; 1893 struct e1000_adapter *adapter = netdev_priv(netdev); 1894 struct e1000_hw *hw = &adapter->hw; 1895 u32 icr = er32(ICR); 1896 1897 if (icr & adapter->eiac_mask) 1898 ew32(ICS, (icr & adapter->eiac_mask)); 1899 1900 if (icr & E1000_ICR_LSC) { 1901 hw->mac.get_link_status = true; 1902 /* guard against interrupt when we're going down */ 1903 if (!test_bit(__E1000_DOWN, &adapter->state)) 1904 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1905 } 1906 1907 if (!test_bit(__E1000_DOWN, &adapter->state)) 1908 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK); 1909 1910 return IRQ_HANDLED; 1911 } 1912 1913 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data) 1914 { 1915 struct net_device *netdev = data; 1916 struct e1000_adapter *adapter = netdev_priv(netdev); 1917 struct e1000_hw *hw = &adapter->hw; 1918 struct e1000_ring *tx_ring = adapter->tx_ring; 1919 1920 adapter->total_tx_bytes = 0; 1921 adapter->total_tx_packets = 0; 1922 1923 if (!e1000_clean_tx_irq(tx_ring)) 1924 /* Ring was not completely cleaned, so fire another interrupt */ 1925 ew32(ICS, tx_ring->ims_val); 1926 1927 if (!test_bit(__E1000_DOWN, &adapter->state)) 1928 ew32(IMS, adapter->tx_ring->ims_val); 1929 1930 return IRQ_HANDLED; 1931 } 1932 1933 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data) 1934 { 1935 struct net_device *netdev = data; 1936 struct e1000_adapter *adapter = netdev_priv(netdev); 1937 struct e1000_ring *rx_ring = adapter->rx_ring; 1938 1939 /* Write the ITR value calculated at the end of the 1940 * previous interrupt. 1941 */ 1942 if (rx_ring->set_itr) { 1943 u32 itr = rx_ring->itr_val ? 1944 1000000000 / (rx_ring->itr_val * 256) : 0; 1945 1946 writel(itr, rx_ring->itr_register); 1947 rx_ring->set_itr = 0; 1948 } 1949 1950 if (napi_schedule_prep(&adapter->napi)) { 1951 adapter->total_rx_bytes = 0; 1952 adapter->total_rx_packets = 0; 1953 __napi_schedule(&adapter->napi); 1954 } 1955 return IRQ_HANDLED; 1956 } 1957 1958 /** 1959 * e1000_configure_msix - Configure MSI-X hardware 1960 * @adapter: board private structure 1961 * 1962 * e1000_configure_msix sets up the hardware to properly 1963 * generate MSI-X interrupts. 1964 **/ 1965 static void e1000_configure_msix(struct e1000_adapter *adapter) 1966 { 1967 struct e1000_hw *hw = &adapter->hw; 1968 struct e1000_ring *rx_ring = adapter->rx_ring; 1969 struct e1000_ring *tx_ring = adapter->tx_ring; 1970 int vector = 0; 1971 u32 ctrl_ext, ivar = 0; 1972 1973 adapter->eiac_mask = 0; 1974 1975 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */ 1976 if (hw->mac.type == e1000_82574) { 1977 u32 rfctl = er32(RFCTL); 1978 1979 rfctl |= E1000_RFCTL_ACK_DIS; 1980 ew32(RFCTL, rfctl); 1981 } 1982 1983 /* Configure Rx vector */ 1984 rx_ring->ims_val = E1000_IMS_RXQ0; 1985 adapter->eiac_mask |= rx_ring->ims_val; 1986 if (rx_ring->itr_val) 1987 writel(1000000000 / (rx_ring->itr_val * 256), 1988 rx_ring->itr_register); 1989 else 1990 writel(1, rx_ring->itr_register); 1991 ivar = E1000_IVAR_INT_ALLOC_VALID | vector; 1992 1993 /* Configure Tx vector */ 1994 tx_ring->ims_val = E1000_IMS_TXQ0; 1995 vector++; 1996 if (tx_ring->itr_val) 1997 writel(1000000000 / (tx_ring->itr_val * 256), 1998 tx_ring->itr_register); 1999 else 2000 writel(1, tx_ring->itr_register); 2001 adapter->eiac_mask |= tx_ring->ims_val; 2002 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8); 2003 2004 /* set vector for Other Causes, e.g. link changes */ 2005 vector++; 2006 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16); 2007 if (rx_ring->itr_val) 2008 writel(1000000000 / (rx_ring->itr_val * 256), 2009 hw->hw_addr + E1000_EITR_82574(vector)); 2010 else 2011 writel(1, hw->hw_addr + E1000_EITR_82574(vector)); 2012 2013 /* Cause Tx interrupts on every write back */ 2014 ivar |= BIT(31); 2015 2016 ew32(IVAR, ivar); 2017 2018 /* enable MSI-X PBA support */ 2019 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME; 2020 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME; 2021 ew32(CTRL_EXT, ctrl_ext); 2022 e1e_flush(); 2023 } 2024 2025 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter) 2026 { 2027 if (adapter->msix_entries) { 2028 pci_disable_msix(adapter->pdev); 2029 kfree(adapter->msix_entries); 2030 adapter->msix_entries = NULL; 2031 } else if (adapter->flags & FLAG_MSI_ENABLED) { 2032 pci_disable_msi(adapter->pdev); 2033 adapter->flags &= ~FLAG_MSI_ENABLED; 2034 } 2035 } 2036 2037 /** 2038 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported 2039 * @adapter: board private structure 2040 * 2041 * Attempt to configure interrupts using the best available 2042 * capabilities of the hardware and kernel. 2043 **/ 2044 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter) 2045 { 2046 int err; 2047 int i; 2048 2049 switch (adapter->int_mode) { 2050 case E1000E_INT_MODE_MSIX: 2051 if (adapter->flags & FLAG_HAS_MSIX) { 2052 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */ 2053 adapter->msix_entries = kzalloc_objs(struct msix_entry, 2054 adapter->num_vectors, 2055 GFP_KERNEL); 2056 if (adapter->msix_entries) { 2057 struct e1000_adapter *a = adapter; 2058 2059 for (i = 0; i < adapter->num_vectors; i++) 2060 adapter->msix_entries[i].entry = i; 2061 2062 err = pci_enable_msix_range(a->pdev, 2063 a->msix_entries, 2064 a->num_vectors, 2065 a->num_vectors); 2066 if (err > 0) 2067 return; 2068 } 2069 /* MSI-X failed, so fall through and try MSI */ 2070 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n"); 2071 e1000e_reset_interrupt_capability(adapter); 2072 } 2073 adapter->int_mode = E1000E_INT_MODE_MSI; 2074 fallthrough; 2075 case E1000E_INT_MODE_MSI: 2076 if (!pci_enable_msi(adapter->pdev)) { 2077 adapter->flags |= FLAG_MSI_ENABLED; 2078 } else { 2079 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2080 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n"); 2081 } 2082 fallthrough; 2083 case E1000E_INT_MODE_LEGACY: 2084 /* Don't do anything; this is the system default */ 2085 break; 2086 } 2087 2088 /* store the number of vectors being used */ 2089 adapter->num_vectors = 1; 2090 } 2091 2092 /** 2093 * e1000_request_msix - Initialize MSI-X interrupts 2094 * @adapter: board private structure 2095 * 2096 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the 2097 * kernel. 2098 **/ 2099 static int e1000_request_msix(struct e1000_adapter *adapter) 2100 { 2101 struct net_device *netdev = adapter->netdev; 2102 int err = 0, vector = 0; 2103 2104 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2105 snprintf(adapter->rx_ring->name, 2106 sizeof(adapter->rx_ring->name) - 1, 2107 "%.14s-rx-0", netdev->name); 2108 else 2109 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); 2110 err = request_irq(adapter->msix_entries[vector].vector, 2111 e1000_intr_msix_rx, 0, adapter->rx_ring->name, 2112 netdev); 2113 if (err) 2114 return err; 2115 adapter->rx_ring->itr_register = adapter->hw.hw_addr + 2116 E1000_EITR_82574(vector); 2117 adapter->rx_ring->itr_val = adapter->itr; 2118 vector++; 2119 2120 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2121 snprintf(adapter->tx_ring->name, 2122 sizeof(adapter->tx_ring->name) - 1, 2123 "%.14s-tx-0", netdev->name); 2124 else 2125 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); 2126 err = request_irq(adapter->msix_entries[vector].vector, 2127 e1000_intr_msix_tx, 0, adapter->tx_ring->name, 2128 netdev); 2129 if (err) 2130 return err; 2131 adapter->tx_ring->itr_register = adapter->hw.hw_addr + 2132 E1000_EITR_82574(vector); 2133 adapter->tx_ring->itr_val = adapter->itr; 2134 vector++; 2135 2136 err = request_irq(adapter->msix_entries[vector].vector, 2137 e1000_msix_other, 0, netdev->name, netdev); 2138 if (err) 2139 return err; 2140 2141 e1000_configure_msix(adapter); 2142 2143 return 0; 2144 } 2145 2146 /** 2147 * e1000_request_irq - initialize interrupts 2148 * @adapter: board private structure 2149 * 2150 * Attempts to configure interrupts using the best available 2151 * capabilities of the hardware and kernel. 2152 **/ 2153 static int e1000_request_irq(struct e1000_adapter *adapter) 2154 { 2155 struct net_device *netdev = adapter->netdev; 2156 int err; 2157 2158 if (adapter->msix_entries) { 2159 err = e1000_request_msix(adapter); 2160 if (!err) 2161 return err; 2162 /* fall back to MSI */ 2163 e1000e_reset_interrupt_capability(adapter); 2164 adapter->int_mode = E1000E_INT_MODE_MSI; 2165 e1000e_set_interrupt_capability(adapter); 2166 } 2167 if (adapter->flags & FLAG_MSI_ENABLED) { 2168 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0, 2169 netdev->name, netdev); 2170 if (!err) 2171 return err; 2172 2173 /* fall back to legacy interrupt */ 2174 e1000e_reset_interrupt_capability(adapter); 2175 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2176 } 2177 2178 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED, 2179 netdev->name, netdev); 2180 if (err) 2181 e_err("Unable to allocate interrupt, Error: %d\n", err); 2182 2183 return err; 2184 } 2185 2186 static void e1000_free_irq(struct e1000_adapter *adapter) 2187 { 2188 struct net_device *netdev = adapter->netdev; 2189 2190 if (adapter->msix_entries) { 2191 int vector = 0; 2192 2193 free_irq(adapter->msix_entries[vector].vector, netdev); 2194 vector++; 2195 2196 free_irq(adapter->msix_entries[vector].vector, netdev); 2197 vector++; 2198 2199 /* Other Causes interrupt vector */ 2200 free_irq(adapter->msix_entries[vector].vector, netdev); 2201 return; 2202 } 2203 2204 free_irq(adapter->pdev->irq, netdev); 2205 } 2206 2207 /** 2208 * e1000_irq_disable - Mask off interrupt generation on the NIC 2209 * @adapter: board private structure 2210 **/ 2211 static void e1000_irq_disable(struct e1000_adapter *adapter) 2212 { 2213 struct e1000_hw *hw = &adapter->hw; 2214 2215 ew32(IMC, ~0); 2216 if (adapter->msix_entries) 2217 ew32(EIAC_82574, 0); 2218 e1e_flush(); 2219 2220 if (adapter->msix_entries) { 2221 int i; 2222 2223 for (i = 0; i < adapter->num_vectors; i++) 2224 synchronize_irq(adapter->msix_entries[i].vector); 2225 } else { 2226 synchronize_irq(adapter->pdev->irq); 2227 } 2228 } 2229 2230 /** 2231 * e1000_irq_enable - Enable default interrupt generation settings 2232 * @adapter: board private structure 2233 **/ 2234 static void e1000_irq_enable(struct e1000_adapter *adapter) 2235 { 2236 struct e1000_hw *hw = &adapter->hw; 2237 2238 if (adapter->msix_entries) { 2239 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); 2240 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | 2241 IMS_OTHER_MASK); 2242 } else if (hw->mac.type >= e1000_pch_lpt) { 2243 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER); 2244 } else { 2245 ew32(IMS, IMS_ENABLE_MASK); 2246 } 2247 e1e_flush(); 2248 } 2249 2250 /** 2251 * e1000e_get_hw_control - get control of the h/w from f/w 2252 * @adapter: address of board private structure 2253 * 2254 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2255 * For ASF and Pass Through versions of f/w this means that 2256 * the driver is loaded. For AMT version (only with 82573) 2257 * of the f/w this means that the network i/f is open. 2258 **/ 2259 void e1000e_get_hw_control(struct e1000_adapter *adapter) 2260 { 2261 struct e1000_hw *hw = &adapter->hw; 2262 u32 ctrl_ext; 2263 u32 swsm; 2264 2265 /* Let firmware know the driver has taken over */ 2266 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2267 swsm = er32(SWSM); 2268 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); 2269 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2270 ctrl_ext = er32(CTRL_EXT); 2271 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 2272 } 2273 } 2274 2275 /** 2276 * e1000e_release_hw_control - release control of the h/w to f/w 2277 * @adapter: address of board private structure 2278 * 2279 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2280 * For ASF and Pass Through versions of f/w this means that the 2281 * driver is no longer loaded. For AMT version (only with 82573) i 2282 * of the f/w this means that the network i/f is closed. 2283 * 2284 **/ 2285 void e1000e_release_hw_control(struct e1000_adapter *adapter) 2286 { 2287 struct e1000_hw *hw = &adapter->hw; 2288 u32 ctrl_ext; 2289 u32 swsm; 2290 2291 /* Let firmware taken over control of h/w */ 2292 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2293 swsm = er32(SWSM); 2294 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 2295 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2296 ctrl_ext = er32(CTRL_EXT); 2297 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 2298 } 2299 } 2300 2301 /** 2302 * e1000_alloc_ring_dma - allocate memory for a ring structure 2303 * @adapter: board private structure 2304 * @ring: ring struct for which to allocate dma 2305 **/ 2306 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, 2307 struct e1000_ring *ring) 2308 { 2309 struct pci_dev *pdev = adapter->pdev; 2310 2311 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma, 2312 GFP_KERNEL); 2313 if (!ring->desc) 2314 return -ENOMEM; 2315 2316 return 0; 2317 } 2318 2319 /** 2320 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) 2321 * @tx_ring: Tx descriptor ring 2322 * 2323 * Return 0 on success, negative on failure 2324 **/ 2325 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring) 2326 { 2327 struct e1000_adapter *adapter = tx_ring->adapter; 2328 int err = -ENOMEM, size; 2329 2330 size = sizeof(struct e1000_buffer) * tx_ring->count; 2331 tx_ring->buffer_info = vzalloc(size); 2332 if (!tx_ring->buffer_info) 2333 goto err; 2334 2335 /* round up to nearest 4K */ 2336 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); 2337 tx_ring->size = ALIGN(tx_ring->size, 4096); 2338 2339 err = e1000_alloc_ring_dma(adapter, tx_ring); 2340 if (err) 2341 goto err; 2342 2343 tx_ring->next_to_use = 0; 2344 tx_ring->next_to_clean = 0; 2345 2346 return 0; 2347 err: 2348 vfree(tx_ring->buffer_info); 2349 e_err("Unable to allocate memory for the transmit descriptor ring\n"); 2350 return err; 2351 } 2352 2353 /** 2354 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors) 2355 * @rx_ring: Rx descriptor ring 2356 * 2357 * Returns 0 on success, negative on failure 2358 **/ 2359 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring) 2360 { 2361 struct e1000_adapter *adapter = rx_ring->adapter; 2362 struct e1000_buffer *buffer_info; 2363 int i, size, desc_len, err = -ENOMEM; 2364 2365 size = sizeof(struct e1000_buffer) * rx_ring->count; 2366 rx_ring->buffer_info = vzalloc(size); 2367 if (!rx_ring->buffer_info) 2368 goto err; 2369 2370 for (i = 0; i < rx_ring->count; i++) { 2371 buffer_info = &rx_ring->buffer_info[i]; 2372 buffer_info->ps_pages = kzalloc_objs(struct e1000_ps_page, 2373 PS_PAGE_BUFFERS, 2374 GFP_KERNEL); 2375 if (!buffer_info->ps_pages) 2376 goto err_pages; 2377 } 2378 2379 desc_len = sizeof(union e1000_rx_desc_packet_split); 2380 2381 /* Round up to nearest 4K */ 2382 rx_ring->size = rx_ring->count * desc_len; 2383 rx_ring->size = ALIGN(rx_ring->size, 4096); 2384 2385 err = e1000_alloc_ring_dma(adapter, rx_ring); 2386 if (err) 2387 goto err_pages; 2388 2389 rx_ring->next_to_clean = 0; 2390 rx_ring->next_to_use = 0; 2391 rx_ring->rx_skb_top = NULL; 2392 2393 return 0; 2394 2395 err_pages: 2396 for (i = 0; i < rx_ring->count; i++) { 2397 buffer_info = &rx_ring->buffer_info[i]; 2398 kfree(buffer_info->ps_pages); 2399 } 2400 err: 2401 vfree(rx_ring->buffer_info); 2402 e_err("Unable to allocate memory for the receive descriptor ring\n"); 2403 return err; 2404 } 2405 2406 /** 2407 * e1000_clean_tx_ring - Free Tx Buffers 2408 * @tx_ring: Tx descriptor ring 2409 **/ 2410 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring) 2411 { 2412 struct e1000_adapter *adapter = tx_ring->adapter; 2413 struct e1000_buffer *buffer_info; 2414 unsigned long size; 2415 unsigned int i; 2416 2417 for (i = 0; i < tx_ring->count; i++) { 2418 buffer_info = &tx_ring->buffer_info[i]; 2419 e1000_put_txbuf(tx_ring, buffer_info, false); 2420 } 2421 2422 netdev_reset_queue(adapter->netdev); 2423 size = sizeof(struct e1000_buffer) * tx_ring->count; 2424 memset(tx_ring->buffer_info, 0, size); 2425 2426 memset(tx_ring->desc, 0, tx_ring->size); 2427 2428 tx_ring->next_to_use = 0; 2429 tx_ring->next_to_clean = 0; 2430 } 2431 2432 /** 2433 * e1000e_free_tx_resources - Free Tx Resources per Queue 2434 * @tx_ring: Tx descriptor ring 2435 * 2436 * Free all transmit software resources 2437 **/ 2438 void e1000e_free_tx_resources(struct e1000_ring *tx_ring) 2439 { 2440 struct e1000_adapter *adapter = tx_ring->adapter; 2441 struct pci_dev *pdev = adapter->pdev; 2442 2443 e1000_clean_tx_ring(tx_ring); 2444 2445 vfree(tx_ring->buffer_info); 2446 tx_ring->buffer_info = NULL; 2447 2448 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, 2449 tx_ring->dma); 2450 tx_ring->desc = NULL; 2451 } 2452 2453 /** 2454 * e1000e_free_rx_resources - Free Rx Resources 2455 * @rx_ring: Rx descriptor ring 2456 * 2457 * Free all receive software resources 2458 **/ 2459 void e1000e_free_rx_resources(struct e1000_ring *rx_ring) 2460 { 2461 struct e1000_adapter *adapter = rx_ring->adapter; 2462 struct pci_dev *pdev = adapter->pdev; 2463 int i; 2464 2465 e1000_clean_rx_ring(rx_ring); 2466 2467 for (i = 0; i < rx_ring->count; i++) 2468 kfree(rx_ring->buffer_info[i].ps_pages); 2469 2470 vfree(rx_ring->buffer_info); 2471 rx_ring->buffer_info = NULL; 2472 2473 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, 2474 rx_ring->dma); 2475 rx_ring->desc = NULL; 2476 } 2477 2478 /** 2479 * e1000_update_itr - update the dynamic ITR value based on statistics 2480 * @itr_setting: current adapter->itr 2481 * @packets: the number of packets during this measurement interval 2482 * @bytes: the number of bytes during this measurement interval 2483 * 2484 * Stores a new ITR value based on packets and byte 2485 * counts during the last interrupt. The advantage of per interrupt 2486 * computation is faster updates and more accurate ITR for the current 2487 * traffic pattern. Constants in this function were computed 2488 * based on theoretical maximum wire speed and thresholds were set based 2489 * on testing data as well as attempting to minimize response time 2490 * while increasing bulk throughput. This functionality is controlled 2491 * by the InterruptThrottleRate module parameter. 2492 **/ 2493 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes) 2494 { 2495 unsigned int retval = itr_setting; 2496 2497 if (packets == 0) 2498 return itr_setting; 2499 2500 switch (itr_setting) { 2501 case lowest_latency: 2502 /* handle TSO and jumbo frames */ 2503 if (bytes / packets > 8000) 2504 retval = bulk_latency; 2505 else if ((packets < 5) && (bytes > 512)) 2506 retval = low_latency; 2507 break; 2508 case low_latency: /* 50 usec aka 20000 ints/s */ 2509 if (bytes > 10000) { 2510 /* this if handles the TSO accounting */ 2511 if (bytes / packets > 8000) 2512 retval = bulk_latency; 2513 else if ((packets < 10) || ((bytes / packets) > 1200)) 2514 retval = bulk_latency; 2515 else if ((packets > 35)) 2516 retval = lowest_latency; 2517 } else if (bytes / packets > 2000) { 2518 retval = bulk_latency; 2519 } else if (packets <= 2 && bytes < 512) { 2520 retval = lowest_latency; 2521 } 2522 break; 2523 case bulk_latency: /* 250 usec aka 4000 ints/s */ 2524 if (bytes > 25000) { 2525 if (packets > 35) 2526 retval = low_latency; 2527 } else if (bytes < 6000) { 2528 retval = low_latency; 2529 } 2530 break; 2531 } 2532 2533 return retval; 2534 } 2535 2536 static void e1000_set_itr(struct e1000_adapter *adapter) 2537 { 2538 u16 current_itr; 2539 u32 new_itr = adapter->itr; 2540 2541 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 2542 if (adapter->link_speed != SPEED_1000) { 2543 new_itr = 4000; 2544 goto set_itr_now; 2545 } 2546 2547 if (adapter->flags2 & FLAG2_DISABLE_AIM) { 2548 new_itr = 0; 2549 goto set_itr_now; 2550 } 2551 2552 adapter->tx_itr = e1000_update_itr(adapter->tx_itr, 2553 adapter->total_tx_packets, 2554 adapter->total_tx_bytes); 2555 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2556 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency) 2557 adapter->tx_itr = low_latency; 2558 2559 adapter->rx_itr = e1000_update_itr(adapter->rx_itr, 2560 adapter->total_rx_packets, 2561 adapter->total_rx_bytes); 2562 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2563 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency) 2564 adapter->rx_itr = low_latency; 2565 2566 current_itr = max(adapter->rx_itr, adapter->tx_itr); 2567 2568 /* counts and packets in update_itr are dependent on these numbers */ 2569 switch (current_itr) { 2570 case lowest_latency: 2571 new_itr = 70000; 2572 break; 2573 case low_latency: 2574 new_itr = 20000; /* aka hwitr = ~200 */ 2575 break; 2576 case bulk_latency: 2577 new_itr = 4000; 2578 break; 2579 default: 2580 break; 2581 } 2582 2583 set_itr_now: 2584 if (new_itr != adapter->itr) { 2585 /* this attempts to bias the interrupt rate towards Bulk 2586 * by adding intermediate steps when interrupt rate is 2587 * increasing 2588 */ 2589 new_itr = new_itr > adapter->itr ? 2590 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr; 2591 adapter->itr = new_itr; 2592 adapter->rx_ring->itr_val = new_itr; 2593 if (adapter->msix_entries) 2594 adapter->rx_ring->set_itr = 1; 2595 else 2596 e1000e_write_itr(adapter, new_itr); 2597 } 2598 } 2599 2600 /** 2601 * e1000e_write_itr - write the ITR value to the appropriate registers 2602 * @adapter: address of board private structure 2603 * @itr: new ITR value to program 2604 * 2605 * e1000e_write_itr determines if the adapter is in MSI-X mode 2606 * and, if so, writes the EITR registers with the ITR value. 2607 * Otherwise, it writes the ITR value into the ITR register. 2608 **/ 2609 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr) 2610 { 2611 struct e1000_hw *hw = &adapter->hw; 2612 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0; 2613 2614 if (adapter->msix_entries) { 2615 int vector; 2616 2617 for (vector = 0; vector < adapter->num_vectors; vector++) 2618 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector)); 2619 } else { 2620 ew32(ITR, new_itr); 2621 } 2622 } 2623 2624 /** 2625 * e1000_alloc_queues - Allocate memory for all rings 2626 * @adapter: board private structure to initialize 2627 **/ 2628 static int e1000_alloc_queues(struct e1000_adapter *adapter) 2629 { 2630 int size = sizeof(struct e1000_ring); 2631 2632 adapter->tx_ring = kzalloc(size, GFP_KERNEL); 2633 if (!adapter->tx_ring) 2634 goto err; 2635 adapter->tx_ring->count = adapter->tx_ring_count; 2636 adapter->tx_ring->adapter = adapter; 2637 2638 adapter->rx_ring = kzalloc(size, GFP_KERNEL); 2639 if (!adapter->rx_ring) 2640 goto err; 2641 adapter->rx_ring->count = adapter->rx_ring_count; 2642 adapter->rx_ring->adapter = adapter; 2643 2644 return 0; 2645 err: 2646 e_err("Unable to allocate memory for queues\n"); 2647 kfree(adapter->rx_ring); 2648 kfree(adapter->tx_ring); 2649 return -ENOMEM; 2650 } 2651 2652 /** 2653 * e1000e_poll - NAPI Rx polling callback 2654 * @napi: struct associated with this polling callback 2655 * @budget: number of packets driver is allowed to process this poll 2656 **/ 2657 static int e1000e_poll(struct napi_struct *napi, int budget) 2658 { 2659 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, 2660 napi); 2661 struct e1000_hw *hw = &adapter->hw; 2662 struct net_device *poll_dev = adapter->netdev; 2663 int tx_cleaned = 1, work_done = 0; 2664 2665 adapter = netdev_priv(poll_dev); 2666 2667 if (!adapter->msix_entries || 2668 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) 2669 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring); 2670 2671 adapter->clean_rx(adapter->rx_ring, &work_done, budget); 2672 2673 if (!tx_cleaned || work_done == budget) 2674 return budget; 2675 2676 /* Exit the polling mode, but don't re-enable interrupts if stack might 2677 * poll us due to busy-polling 2678 */ 2679 if (likely(napi_complete_done(napi, work_done))) { 2680 if (adapter->itr_setting & 3) 2681 e1000_set_itr(adapter); 2682 if (!test_bit(__E1000_DOWN, &adapter->state)) { 2683 if (adapter->msix_entries) 2684 ew32(IMS, adapter->rx_ring->ims_val); 2685 else 2686 e1000_irq_enable(adapter); 2687 } 2688 } 2689 2690 return work_done; 2691 } 2692 2693 static int e1000_vlan_rx_add_vid(struct net_device *netdev, 2694 __always_unused __be16 proto, u16 vid) 2695 { 2696 struct e1000_adapter *adapter = netdev_priv(netdev); 2697 struct e1000_hw *hw = &adapter->hw; 2698 u32 vfta, index; 2699 2700 /* don't update vlan cookie if already programmed */ 2701 if ((adapter->hw.mng_cookie.status & 2702 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2703 (vid == adapter->mng_vlan_id)) 2704 return 0; 2705 2706 /* add VID to filter table */ 2707 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2708 index = (vid >> 5) & 0x7F; 2709 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2710 vfta |= BIT((vid & 0x1F)); 2711 hw->mac.ops.write_vfta(hw, index, vfta); 2712 } 2713 2714 set_bit(vid, adapter->active_vlans); 2715 2716 return 0; 2717 } 2718 2719 static int e1000_vlan_rx_kill_vid(struct net_device *netdev, 2720 __always_unused __be16 proto, u16 vid) 2721 { 2722 struct e1000_adapter *adapter = netdev_priv(netdev); 2723 struct e1000_hw *hw = &adapter->hw; 2724 u32 vfta, index; 2725 2726 if ((adapter->hw.mng_cookie.status & 2727 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2728 (vid == adapter->mng_vlan_id)) { 2729 /* release control to f/w */ 2730 e1000e_release_hw_control(adapter); 2731 return 0; 2732 } 2733 2734 /* remove VID from filter table */ 2735 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2736 index = (vid >> 5) & 0x7F; 2737 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2738 vfta &= ~BIT((vid & 0x1F)); 2739 hw->mac.ops.write_vfta(hw, index, vfta); 2740 } 2741 2742 clear_bit(vid, adapter->active_vlans); 2743 2744 return 0; 2745 } 2746 2747 /** 2748 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering 2749 * @adapter: board private structure to initialize 2750 **/ 2751 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter) 2752 { 2753 struct net_device *netdev = adapter->netdev; 2754 struct e1000_hw *hw = &adapter->hw; 2755 u32 rctl; 2756 2757 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2758 /* disable VLAN receive filtering */ 2759 rctl = er32(RCTL); 2760 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 2761 ew32(RCTL, rctl); 2762 2763 if (adapter->mng_vlan_id != E1000_MNG_VLAN_NONE) { 2764 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 2765 adapter->mng_vlan_id); 2766 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 2767 } 2768 } 2769 } 2770 2771 /** 2772 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering 2773 * @adapter: board private structure to initialize 2774 **/ 2775 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter) 2776 { 2777 struct e1000_hw *hw = &adapter->hw; 2778 u32 rctl; 2779 2780 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2781 /* enable VLAN receive filtering */ 2782 rctl = er32(RCTL); 2783 rctl |= E1000_RCTL_VFE; 2784 rctl &= ~E1000_RCTL_CFIEN; 2785 ew32(RCTL, rctl); 2786 } 2787 } 2788 2789 /** 2790 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping 2791 * @adapter: board private structure to initialize 2792 **/ 2793 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter) 2794 { 2795 struct e1000_hw *hw = &adapter->hw; 2796 u32 ctrl; 2797 2798 /* disable VLAN tag insert/strip */ 2799 ctrl = er32(CTRL); 2800 ctrl &= ~E1000_CTRL_VME; 2801 ew32(CTRL, ctrl); 2802 } 2803 2804 /** 2805 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping 2806 * @adapter: board private structure to initialize 2807 **/ 2808 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter) 2809 { 2810 struct e1000_hw *hw = &adapter->hw; 2811 u32 ctrl; 2812 2813 /* enable VLAN tag insert/strip */ 2814 ctrl = er32(CTRL); 2815 ctrl |= E1000_CTRL_VME; 2816 ew32(CTRL, ctrl); 2817 } 2818 2819 static void e1000_update_mng_vlan(struct e1000_adapter *adapter) 2820 { 2821 struct net_device *netdev = adapter->netdev; 2822 u16 vid = adapter->hw.mng_cookie.vlan_id; 2823 u16 old_vid = adapter->mng_vlan_id; 2824 2825 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 2826 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 2827 adapter->mng_vlan_id = vid; 2828 } 2829 2830 if (old_vid != E1000_MNG_VLAN_NONE && vid != old_vid) 2831 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid); 2832 } 2833 2834 static void e1000_restore_vlan(struct e1000_adapter *adapter) 2835 { 2836 u16 vid; 2837 2838 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 2839 2840 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2841 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 2842 } 2843 2844 static void e1000_init_manageability_pt(struct e1000_adapter *adapter) 2845 { 2846 struct e1000_hw *hw = &adapter->hw; 2847 u32 manc, manc2h, mdef, i, j; 2848 2849 if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) 2850 return; 2851 2852 manc = er32(MANC); 2853 2854 /* enable receiving management packets to the host. this will probably 2855 * generate destination unreachable messages from the host OS, but 2856 * the packets will be handled on SMBUS 2857 */ 2858 manc |= E1000_MANC_EN_MNG2HOST; 2859 manc2h = er32(MANC2H); 2860 2861 switch (hw->mac.type) { 2862 default: 2863 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664); 2864 break; 2865 case e1000_82574: 2866 case e1000_82583: 2867 /* Check if IPMI pass-through decision filter already exists; 2868 * if so, enable it. 2869 */ 2870 for (i = 0, j = 0; i < 8; i++) { 2871 mdef = er32(MDEF(i)); 2872 2873 /* Ignore filters with anything other than IPMI ports */ 2874 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2875 continue; 2876 2877 /* Enable this decision filter in MANC2H */ 2878 if (mdef) 2879 manc2h |= BIT(i); 2880 2881 j |= mdef; 2882 } 2883 2884 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2885 break; 2886 2887 /* Create new decision filter in an empty filter */ 2888 for (i = 0, j = 0; i < 8; i++) 2889 if (er32(MDEF(i)) == 0) { 2890 ew32(MDEF(i), (E1000_MDEF_PORT_623 | 2891 E1000_MDEF_PORT_664)); 2892 manc2h |= BIT(1); 2893 j++; 2894 break; 2895 } 2896 2897 if (!j) 2898 e_warn("Unable to create IPMI pass-through filter\n"); 2899 break; 2900 } 2901 2902 ew32(MANC2H, manc2h); 2903 ew32(MANC, manc); 2904 } 2905 2906 /** 2907 * e1000_configure_tx - Configure Transmit Unit after Reset 2908 * @adapter: board private structure 2909 * 2910 * Configure the Tx unit of the MAC after a reset. 2911 **/ 2912 static void e1000_configure_tx(struct e1000_adapter *adapter) 2913 { 2914 struct e1000_hw *hw = &adapter->hw; 2915 struct e1000_ring *tx_ring = adapter->tx_ring; 2916 u64 tdba; 2917 u32 tdlen, tctl, tarc; 2918 2919 /* Setup the HW Tx Head and Tail descriptor pointers */ 2920 tdba = tx_ring->dma; 2921 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); 2922 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); 2923 ew32(TDBAH(0), (tdba >> 32)); 2924 ew32(TDLEN(0), tdlen); 2925 ew32(TDH(0), 0); 2926 ew32(TDT(0), 0); 2927 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0); 2928 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0); 2929 2930 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 2931 e1000e_update_tdt_wa(tx_ring, 0); 2932 2933 /* Set the Tx Interrupt Delay register */ 2934 ew32(TIDV, adapter->tx_int_delay); 2935 /* Tx irq moderation */ 2936 ew32(TADV, adapter->tx_abs_int_delay); 2937 2938 if (adapter->flags2 & FLAG2_DMA_BURST) { 2939 u32 txdctl = er32(TXDCTL(0)); 2940 2941 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | 2942 E1000_TXDCTL_WTHRESH); 2943 /* set up some performance related parameters to encourage the 2944 * hardware to use the bus more efficiently in bursts, depends 2945 * on the tx_int_delay to be enabled, 2946 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls 2947 * hthresh = 1 ==> prefetch when one or more available 2948 * pthresh = 0x1f ==> prefetch if internal cache 31 or less 2949 * BEWARE: this seems to work but should be considered first if 2950 * there are Tx hangs or other Tx related bugs 2951 */ 2952 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE; 2953 ew32(TXDCTL(0), txdctl); 2954 } 2955 /* erratum work around: set txdctl the same for both queues */ 2956 ew32(TXDCTL(1), er32(TXDCTL(0))); 2957 2958 /* Program the Transmit Control Register */ 2959 tctl = er32(TCTL); 2960 tctl &= ~E1000_TCTL_CT; 2961 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2962 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2963 2964 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { 2965 tarc = er32(TARC(0)); 2966 /* set the speed mode bit, we'll clear it if we're not at 2967 * gigabit link later 2968 */ 2969 #define SPEED_MODE_BIT BIT(21) 2970 tarc |= SPEED_MODE_BIT; 2971 ew32(TARC(0), tarc); 2972 } 2973 2974 /* errata: program both queues to unweighted RR */ 2975 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { 2976 tarc = er32(TARC(0)); 2977 tarc |= 1; 2978 ew32(TARC(0), tarc); 2979 tarc = er32(TARC(1)); 2980 tarc |= 1; 2981 ew32(TARC(1), tarc); 2982 } 2983 2984 /* Setup Transmit Descriptor Settings for eop descriptor */ 2985 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 2986 2987 /* only set IDE if we are delaying interrupts using the timers */ 2988 if (adapter->tx_int_delay) 2989 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 2990 2991 /* enable Report Status bit */ 2992 adapter->txd_cmd |= E1000_TXD_CMD_RS; 2993 2994 ew32(TCTL, tctl); 2995 2996 hw->mac.ops.config_collision_dist(hw); 2997 2998 /* SPT and KBL Si errata workaround to avoid data corruption */ 2999 if (hw->mac.type == e1000_pch_spt) { 3000 u32 reg_val; 3001 3002 reg_val = er32(IOSFPC); 3003 reg_val |= E1000_RCTL_RDMTS_HEX; 3004 ew32(IOSFPC, reg_val); 3005 3006 reg_val = er32(TARC(0)); 3007 /* SPT and KBL Si errata workaround to avoid Tx hang. 3008 * Dropping the number of outstanding requests from 3009 * 3 to 2 in order to avoid a buffer overrun. 3010 */ 3011 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3012 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ; 3013 ew32(TARC(0), reg_val); 3014 } 3015 } 3016 3017 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ 3018 (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) 3019 3020 /** 3021 * e1000_setup_rctl - configure the receive control registers 3022 * @adapter: Board private structure 3023 **/ 3024 static void e1000_setup_rctl(struct e1000_adapter *adapter) 3025 { 3026 struct e1000_hw *hw = &adapter->hw; 3027 u32 rctl, rfctl; 3028 u32 pages = 0; 3029 3030 /* Workaround Si errata on PCHx - configure jumbo frame flow. 3031 * If jumbo frames not set, program related MAC/PHY registers 3032 * to h/w defaults 3033 */ 3034 if (hw->mac.type >= e1000_pch2lan) { 3035 s32 ret_val; 3036 3037 if (adapter->netdev->mtu > ETH_DATA_LEN) 3038 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true); 3039 else 3040 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false); 3041 3042 if (ret_val) 3043 e_dbg("failed to enable|disable jumbo frame workaround mode\n"); 3044 } 3045 3046 /* Program MC offset vector base */ 3047 rctl = er32(RCTL); 3048 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3049 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3050 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3051 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3052 3053 /* Do not Store bad packets */ 3054 rctl &= ~E1000_RCTL_SBP; 3055 3056 /* Enable Long Packet receive */ 3057 if (adapter->netdev->mtu <= ETH_DATA_LEN) 3058 rctl &= ~E1000_RCTL_LPE; 3059 else 3060 rctl |= E1000_RCTL_LPE; 3061 3062 /* Some systems expect that the CRC is included in SMBUS traffic. The 3063 * hardware strips the CRC before sending to both SMBUS (BMC) and to 3064 * host memory when this is enabled 3065 */ 3066 if (adapter->flags2 & FLAG2_CRC_STRIPPING) 3067 rctl |= E1000_RCTL_SECRC; 3068 3069 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */ 3070 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) { 3071 u16 phy_data; 3072 3073 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); 3074 phy_data &= 0xfff8; 3075 phy_data |= BIT(2); 3076 e1e_wphy(hw, PHY_REG(770, 26), phy_data); 3077 3078 e1e_rphy(hw, 22, &phy_data); 3079 phy_data &= 0x0fff; 3080 phy_data |= BIT(14); 3081 e1e_wphy(hw, 0x10, 0x2823); 3082 e1e_wphy(hw, 0x11, 0x0003); 3083 e1e_wphy(hw, 22, phy_data); 3084 } 3085 3086 /* Setup buffer sizes */ 3087 rctl &= ~E1000_RCTL_SZ_4096; 3088 rctl |= E1000_RCTL_BSEX; 3089 switch (adapter->rx_buffer_len) { 3090 case 2048: 3091 default: 3092 rctl |= E1000_RCTL_SZ_2048; 3093 rctl &= ~E1000_RCTL_BSEX; 3094 break; 3095 case 4096: 3096 rctl |= E1000_RCTL_SZ_4096; 3097 break; 3098 case 8192: 3099 rctl |= E1000_RCTL_SZ_8192; 3100 break; 3101 case 16384: 3102 rctl |= E1000_RCTL_SZ_16384; 3103 break; 3104 } 3105 3106 /* Enable Extended Status in all Receive Descriptors */ 3107 rfctl = er32(RFCTL); 3108 rfctl |= E1000_RFCTL_EXTEN; 3109 ew32(RFCTL, rfctl); 3110 3111 /* 82571 and greater support packet-split where the protocol 3112 * header is placed in skb->data and the packet data is 3113 * placed in pages hanging off of skb_shinfo(skb)->nr_frags. 3114 * In the case of a non-split, skb->data is linearly filled, 3115 * followed by the page buffers. Therefore, skb->data is 3116 * sized to hold the largest protocol header. 3117 * 3118 * allocations using alloc_page take too long for regular MTU 3119 * so only enable packet split for jumbo frames 3120 * 3121 * Using pages when the page size is greater than 16k wastes 3122 * a lot of memory, since we allocate 3 pages at all times 3123 * per packet. 3124 */ 3125 pages = PAGE_USE_COUNT(adapter->netdev->mtu); 3126 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE)) 3127 adapter->rx_ps_pages = pages; 3128 else 3129 adapter->rx_ps_pages = 0; 3130 3131 if (adapter->rx_ps_pages) { 3132 u32 psrctl = 0; 3133 3134 /* Enable Packet split descriptors */ 3135 rctl |= E1000_RCTL_DTYP_PS; 3136 3137 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT; 3138 3139 switch (adapter->rx_ps_pages) { 3140 case 3: 3141 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT; 3142 fallthrough; 3143 case 2: 3144 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT; 3145 fallthrough; 3146 case 1: 3147 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT; 3148 break; 3149 } 3150 3151 ew32(PSRCTL, psrctl); 3152 } 3153 3154 /* This is useful for sniffing bad packets. */ 3155 if (adapter->netdev->features & NETIF_F_RXALL) { 3156 /* UPE and MPE will be handled by normal PROMISC logic 3157 * in e1000e_set_rx_mode 3158 */ 3159 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3160 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3161 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3162 3163 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3164 E1000_RCTL_DPF | /* Allow filtered pause */ 3165 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3166 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3167 * and that breaks VLANs. 3168 */ 3169 } 3170 3171 ew32(RCTL, rctl); 3172 /* just started the receive unit, no need to restart */ 3173 adapter->flags &= ~FLAG_RESTART_NOW; 3174 } 3175 3176 /** 3177 * e1000_configure_rx - Configure Receive Unit after Reset 3178 * @adapter: board private structure 3179 * 3180 * Configure the Rx unit of the MAC after a reset. 3181 **/ 3182 static void e1000_configure_rx(struct e1000_adapter *adapter) 3183 { 3184 struct e1000_hw *hw = &adapter->hw; 3185 struct e1000_ring *rx_ring = adapter->rx_ring; 3186 u64 rdba; 3187 u32 rdlen, rctl, rxcsum, ctrl_ext; 3188 3189 if (adapter->rx_ps_pages) { 3190 /* this is a 32 byte descriptor */ 3191 rdlen = rx_ring->count * 3192 sizeof(union e1000_rx_desc_packet_split); 3193 adapter->clean_rx = e1000_clean_rx_irq_ps; 3194 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; 3195 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) { 3196 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3197 adapter->clean_rx = e1000_clean_jumbo_rx_irq; 3198 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; 3199 } else { 3200 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3201 adapter->clean_rx = e1000_clean_rx_irq; 3202 adapter->alloc_rx_buf = e1000_alloc_rx_buffers; 3203 } 3204 3205 /* disable receives while setting up the descriptors */ 3206 rctl = er32(RCTL); 3207 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 3208 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3209 e1e_flush(); 3210 usleep_range(10000, 11000); 3211 3212 if (adapter->flags2 & FLAG2_DMA_BURST) { 3213 /* set the writeback threshold (only takes effect if the RDTR 3214 * is set). set GRAN=1 and write back up to 0x4 worth, and 3215 * enable prefetching of 0x20 Rx descriptors 3216 * granularity = 01 3217 * wthresh = 04, 3218 * hthresh = 04, 3219 * pthresh = 0x20 3220 */ 3221 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); 3222 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE); 3223 } 3224 3225 /* set the Receive Delay Timer Register */ 3226 ew32(RDTR, adapter->rx_int_delay); 3227 3228 /* irq moderation */ 3229 ew32(RADV, adapter->rx_abs_int_delay); 3230 if ((adapter->itr_setting != 0) && (adapter->itr != 0)) 3231 e1000e_write_itr(adapter, adapter->itr); 3232 3233 ctrl_ext = er32(CTRL_EXT); 3234 /* Auto-Mask interrupts upon ICR access */ 3235 ctrl_ext |= E1000_CTRL_EXT_IAME; 3236 ew32(IAM, 0xffffffff); 3237 ew32(CTRL_EXT, ctrl_ext); 3238 e1e_flush(); 3239 3240 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3241 * the Base and Length of the Rx Descriptor Ring 3242 */ 3243 rdba = rx_ring->dma; 3244 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); 3245 ew32(RDBAH(0), (rdba >> 32)); 3246 ew32(RDLEN(0), rdlen); 3247 ew32(RDH(0), 0); 3248 ew32(RDT(0), 0); 3249 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0); 3250 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0); 3251 3252 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 3253 e1000e_update_rdt_wa(rx_ring, 0); 3254 3255 /* Enable Receive Checksum Offload for TCP and UDP */ 3256 rxcsum = er32(RXCSUM); 3257 if (adapter->netdev->features & NETIF_F_RXCSUM) 3258 rxcsum |= E1000_RXCSUM_TUOFL; 3259 else 3260 rxcsum &= ~E1000_RXCSUM_TUOFL; 3261 ew32(RXCSUM, rxcsum); 3262 3263 /* With jumbo frames, excessive C-state transition latencies result 3264 * in dropped transactions. 3265 */ 3266 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3267 u32 lat = 3268 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 - 3269 adapter->max_frame_size) * 8 / 1000; 3270 3271 if (adapter->flags & FLAG_IS_ICH) { 3272 u32 rxdctl = er32(RXDCTL(0)); 3273 3274 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8)); 3275 } 3276 3277 dev_info(&adapter->pdev->dev, 3278 "Some CPU C-states have been disabled in order to enable jumbo frames\n"); 3279 cpu_latency_qos_update_request(&adapter->pm_qos_req, lat); 3280 } else { 3281 cpu_latency_qos_update_request(&adapter->pm_qos_req, 3282 PM_QOS_DEFAULT_VALUE); 3283 } 3284 3285 /* Enable Receives */ 3286 ew32(RCTL, rctl); 3287 } 3288 3289 /** 3290 * e1000e_write_mc_addr_list - write multicast addresses to MTA 3291 * @netdev: network interface device structure 3292 * 3293 * Writes multicast address list to the MTA hash table. 3294 * Returns: -ENOMEM on failure 3295 * 0 on no addresses written 3296 * X on writing X addresses to MTA 3297 */ 3298 static int e1000e_write_mc_addr_list(struct net_device *netdev) 3299 { 3300 struct e1000_adapter *adapter = netdev_priv(netdev); 3301 struct e1000_hw *hw = &adapter->hw; 3302 struct netdev_hw_addr *ha; 3303 u8 *mta_list; 3304 int i; 3305 3306 if (netdev_mc_empty(netdev)) { 3307 /* nothing to program, so clear mc list */ 3308 hw->mac.ops.update_mc_addr_list(hw, NULL, 0); 3309 return 0; 3310 } 3311 3312 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC); 3313 if (!mta_list) 3314 return -ENOMEM; 3315 3316 /* update_mc_addr_list expects a packed array of only addresses. */ 3317 i = 0; 3318 netdev_for_each_mc_addr(ha, netdev) 3319 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3320 3321 hw->mac.ops.update_mc_addr_list(hw, mta_list, i); 3322 kfree(mta_list); 3323 3324 return netdev_mc_count(netdev); 3325 } 3326 3327 /** 3328 * e1000e_write_uc_addr_list - write unicast addresses to RAR table 3329 * @netdev: network interface device structure 3330 * 3331 * Writes unicast address list to the RAR table. 3332 * Returns: -ENOMEM on failure/insufficient address space 3333 * 0 on no addresses written 3334 * X on writing X addresses to the RAR table 3335 **/ 3336 static int e1000e_write_uc_addr_list(struct net_device *netdev) 3337 { 3338 struct e1000_adapter *adapter = netdev_priv(netdev); 3339 struct e1000_hw *hw = &adapter->hw; 3340 unsigned int rar_entries; 3341 int count = 0; 3342 3343 rar_entries = hw->mac.ops.rar_get_count(hw); 3344 3345 /* save a rar entry for our hardware address */ 3346 rar_entries--; 3347 3348 /* save a rar entry for the LAA workaround */ 3349 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) 3350 rar_entries--; 3351 3352 /* return ENOMEM indicating insufficient memory for addresses */ 3353 if (netdev_uc_count(netdev) > rar_entries) 3354 return -ENOMEM; 3355 3356 if (!netdev_uc_empty(netdev) && rar_entries) { 3357 struct netdev_hw_addr *ha; 3358 3359 /* write the addresses in reverse order to avoid write 3360 * combining 3361 */ 3362 netdev_for_each_uc_addr(ha, netdev) { 3363 int ret_val; 3364 3365 if (!rar_entries) 3366 break; 3367 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); 3368 if (ret_val < 0) 3369 return -ENOMEM; 3370 count++; 3371 } 3372 } 3373 3374 /* zero out the remaining RAR entries not used above */ 3375 for (; rar_entries > 0; rar_entries--) { 3376 ew32(RAH(rar_entries), 0); 3377 ew32(RAL(rar_entries), 0); 3378 } 3379 e1e_flush(); 3380 3381 return count; 3382 } 3383 3384 /** 3385 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set 3386 * @netdev: network interface device structure 3387 * 3388 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast 3389 * address list or the network interface flags are updated. This routine is 3390 * responsible for configuring the hardware for proper unicast, multicast, 3391 * promiscuous mode, and all-multi behavior. 3392 **/ 3393 static void e1000e_set_rx_mode(struct net_device *netdev) 3394 { 3395 struct e1000_adapter *adapter = netdev_priv(netdev); 3396 struct e1000_hw *hw = &adapter->hw; 3397 u32 rctl; 3398 3399 if (pm_runtime_suspended(netdev->dev.parent)) 3400 return; 3401 3402 /* Check for Promiscuous and All Multicast modes */ 3403 rctl = er32(RCTL); 3404 3405 /* clear the affected bits */ 3406 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 3407 3408 if (netdev->flags & IFF_PROMISC) { 3409 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3410 /* Do not hardware filter VLANs in promisc mode */ 3411 e1000e_vlan_filter_disable(adapter); 3412 } else { 3413 int count; 3414 3415 if (netdev->flags & IFF_ALLMULTI) { 3416 rctl |= E1000_RCTL_MPE; 3417 } else { 3418 /* Write addresses to the MTA, if the attempt fails 3419 * then we should just turn on promiscuous mode so 3420 * that we can at least receive multicast traffic 3421 */ 3422 count = e1000e_write_mc_addr_list(netdev); 3423 if (count < 0) 3424 rctl |= E1000_RCTL_MPE; 3425 } 3426 e1000e_vlan_filter_enable(adapter); 3427 /* Write addresses to available RAR registers, if there is not 3428 * sufficient space to store all the addresses then enable 3429 * unicast promiscuous mode 3430 */ 3431 count = e1000e_write_uc_addr_list(netdev); 3432 if (count < 0) 3433 rctl |= E1000_RCTL_UPE; 3434 } 3435 3436 ew32(RCTL, rctl); 3437 3438 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 3439 e1000e_vlan_strip_enable(adapter); 3440 else 3441 e1000e_vlan_strip_disable(adapter); 3442 } 3443 3444 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter) 3445 { 3446 struct e1000_hw *hw = &adapter->hw; 3447 u32 mrqc, rxcsum; 3448 u32 rss_key[10]; 3449 int i; 3450 3451 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3452 for (i = 0; i < 10; i++) 3453 ew32(RSSRK(i), rss_key[i]); 3454 3455 /* Direct all traffic to queue 0 */ 3456 for (i = 0; i < 32; i++) 3457 ew32(RETA(i), 0); 3458 3459 /* Disable raw packet checksumming so that RSS hash is placed in 3460 * descriptor on writeback. 3461 */ 3462 rxcsum = er32(RXCSUM); 3463 rxcsum |= E1000_RXCSUM_PCSD; 3464 3465 ew32(RXCSUM, rxcsum); 3466 3467 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 | 3468 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3469 E1000_MRQC_RSS_FIELD_IPV6 | 3470 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3471 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3472 3473 ew32(MRQC, mrqc); 3474 } 3475 3476 /** 3477 * e1000e_get_base_timinca - get default SYSTIM time increment attributes 3478 * @adapter: board private structure 3479 * @timinca: pointer to returned time increment attributes 3480 * 3481 * Get attributes for incrementing the System Time Register SYSTIML/H at 3482 * the default base frequency, and set the cyclecounter shift value. 3483 **/ 3484 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca) 3485 { 3486 struct e1000_hw *hw = &adapter->hw; 3487 u32 incvalue, incperiod, shift; 3488 3489 /* Make sure clock is enabled on I217/I218/I219 before checking 3490 * the frequency 3491 */ 3492 if ((hw->mac.type >= e1000_pch_lpt) && 3493 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) && 3494 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { 3495 u32 fextnvm7 = er32(FEXTNVM7); 3496 3497 if (!(fextnvm7 & BIT(0))) { 3498 ew32(FEXTNVM7, fextnvm7 | BIT(0)); 3499 e1e_flush(); 3500 } 3501 } 3502 3503 switch (hw->mac.type) { 3504 case e1000_pch2lan: 3505 /* Stable 96MHz frequency */ 3506 incperiod = INCPERIOD_96MHZ; 3507 incvalue = INCVALUE_96MHZ; 3508 shift = INCVALUE_SHIFT_96MHZ; 3509 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3510 break; 3511 case e1000_pch_lpt: 3512 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3513 /* Stable 96MHz frequency */ 3514 incperiod = INCPERIOD_96MHZ; 3515 incvalue = INCVALUE_96MHZ; 3516 shift = INCVALUE_SHIFT_96MHZ; 3517 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3518 } else { 3519 /* Stable 25MHz frequency */ 3520 incperiod = INCPERIOD_25MHZ; 3521 incvalue = INCVALUE_25MHZ; 3522 shift = INCVALUE_SHIFT_25MHZ; 3523 adapter->cc.shift = shift; 3524 } 3525 break; 3526 case e1000_pch_spt: 3527 /* Stable 24MHz frequency */ 3528 incperiod = INCPERIOD_24MHZ; 3529 incvalue = INCVALUE_24MHZ; 3530 shift = INCVALUE_SHIFT_24MHZ; 3531 adapter->cc.shift = shift; 3532 break; 3533 case e1000_pch_cnp: 3534 case e1000_pch_tgp: 3535 case e1000_pch_adp: 3536 case e1000_pch_nvp: 3537 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3538 /* Stable 24MHz frequency */ 3539 incperiod = INCPERIOD_24MHZ; 3540 incvalue = INCVALUE_24MHZ; 3541 shift = INCVALUE_SHIFT_24MHZ; 3542 adapter->cc.shift = shift; 3543 } else { 3544 /* Stable 38400KHz frequency */ 3545 incperiod = INCPERIOD_38400KHZ; 3546 incvalue = INCVALUE_38400KHZ; 3547 shift = INCVALUE_SHIFT_38400KHZ; 3548 adapter->cc.shift = shift; 3549 } 3550 break; 3551 case e1000_pch_mtp: 3552 case e1000_pch_lnp: 3553 case e1000_pch_ptp: 3554 /* System firmware can misreport this value, so set it to a 3555 * stable 38400KHz frequency. 3556 */ 3557 incperiod = INCPERIOD_38400KHZ; 3558 incvalue = INCVALUE_38400KHZ; 3559 shift = INCVALUE_SHIFT_38400KHZ; 3560 adapter->cc.shift = shift; 3561 break; 3562 case e1000_82574: 3563 case e1000_82583: 3564 /* Stable 25MHz frequency */ 3565 incperiod = INCPERIOD_25MHZ; 3566 incvalue = INCVALUE_25MHZ; 3567 shift = INCVALUE_SHIFT_25MHZ; 3568 adapter->cc.shift = shift; 3569 break; 3570 default: 3571 return -EINVAL; 3572 } 3573 3574 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) | 3575 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK)); 3576 3577 return 0; 3578 } 3579 3580 /** 3581 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable 3582 * @adapter: board private structure 3583 * @config: timestamp configuration 3584 * @extack: netlink extended ACK for error report 3585 * 3586 * Outgoing time stamping can be enabled and disabled. Play nice and 3587 * disable it when requested, although it shouldn't cause any overhead 3588 * when no packet needs it. At most one packet in the queue may be 3589 * marked for time stamping, otherwise it would be impossible to tell 3590 * for sure to which packet the hardware time stamp belongs. 3591 * 3592 * Incoming time stamping has to be configured via the hardware filters. 3593 * Not all combinations are supported, in particular event type has to be 3594 * specified. Matching the kind of event packet is not supported, with the 3595 * exception of "all V2 events regardless of level 2 or 4". 3596 **/ 3597 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter, 3598 struct kernel_hwtstamp_config *config, 3599 struct netlink_ext_ack *extack) 3600 { 3601 struct e1000_hw *hw = &adapter->hw; 3602 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 3603 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 3604 u32 rxmtrl = 0; 3605 u16 rxudp = 0; 3606 bool is_l4 = false; 3607 bool is_l2 = false; 3608 u32 regval; 3609 3610 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) { 3611 NL_SET_ERR_MSG(extack, "No HW timestamp support"); 3612 return -EINVAL; 3613 } 3614 3615 switch (config->tx_type) { 3616 case HWTSTAMP_TX_OFF: 3617 tsync_tx_ctl = 0; 3618 break; 3619 case HWTSTAMP_TX_ON: 3620 break; 3621 default: 3622 NL_SET_ERR_MSG(extack, "Unsupported TX HW timestamp type"); 3623 return -ERANGE; 3624 } 3625 3626 switch (config->rx_filter) { 3627 case HWTSTAMP_FILTER_NONE: 3628 tsync_rx_ctl = 0; 3629 break; 3630 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3631 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3632 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE; 3633 is_l4 = true; 3634 break; 3635 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3636 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3637 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE; 3638 is_l4 = true; 3639 break; 3640 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3641 /* Also time stamps V2 L2 Path Delay Request/Response */ 3642 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3643 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3644 is_l2 = true; 3645 break; 3646 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3647 /* Also time stamps V2 L2 Path Delay Request/Response. */ 3648 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3649 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3650 is_l2 = true; 3651 break; 3652 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3653 /* Hardware cannot filter just V2 L4 Sync messages */ 3654 fallthrough; 3655 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3656 /* Also time stamps V2 Path Delay Request/Response. */ 3657 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3658 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3659 is_l2 = true; 3660 is_l4 = true; 3661 break; 3662 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3663 /* Hardware cannot filter just V2 L4 Delay Request messages */ 3664 fallthrough; 3665 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3666 /* Also time stamps V2 Path Delay Request/Response. */ 3667 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3668 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3669 is_l2 = true; 3670 is_l4 = true; 3671 break; 3672 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3673 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3674 /* Hardware cannot filter just V2 L4 or L2 Event messages */ 3675 fallthrough; 3676 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3677 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 3678 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 3679 is_l2 = true; 3680 is_l4 = true; 3681 break; 3682 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3683 /* For V1, the hardware can only filter Sync messages or 3684 * Delay Request messages but not both so fall-through to 3685 * time stamp all packets. 3686 */ 3687 fallthrough; 3688 case HWTSTAMP_FILTER_NTP_ALL: 3689 case HWTSTAMP_FILTER_ALL: 3690 is_l2 = true; 3691 is_l4 = true; 3692 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 3693 config->rx_filter = HWTSTAMP_FILTER_ALL; 3694 break; 3695 default: 3696 NL_SET_ERR_MSG(extack, "Unsupported RX HW timestamp filter"); 3697 return -ERANGE; 3698 } 3699 3700 adapter->hwtstamp_config = *config; 3701 3702 /* enable/disable Tx h/w time stamping */ 3703 regval = er32(TSYNCTXCTL); 3704 regval &= ~E1000_TSYNCTXCTL_ENABLED; 3705 regval |= tsync_tx_ctl; 3706 ew32(TSYNCTXCTL, regval); 3707 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) != 3708 (regval & E1000_TSYNCTXCTL_ENABLED)) { 3709 NL_SET_ERR_MSG(extack, 3710 "Timesync Tx Control register not set as expected"); 3711 return -EAGAIN; 3712 } 3713 3714 /* enable/disable Rx h/w time stamping */ 3715 regval = er32(TSYNCRXCTL); 3716 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 3717 regval |= tsync_rx_ctl; 3718 ew32(TSYNCRXCTL, regval); 3719 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED | 3720 E1000_TSYNCRXCTL_TYPE_MASK)) != 3721 (regval & (E1000_TSYNCRXCTL_ENABLED | 3722 E1000_TSYNCRXCTL_TYPE_MASK))) { 3723 NL_SET_ERR_MSG(extack, 3724 "Timesync Rx Control register not set as expected"); 3725 return -EAGAIN; 3726 } 3727 3728 /* L2: define ethertype filter for time stamped packets */ 3729 if (is_l2) 3730 rxmtrl |= ETH_P_1588; 3731 3732 /* define which PTP packets get time stamped */ 3733 ew32(RXMTRL, rxmtrl); 3734 3735 /* Filter by destination port */ 3736 if (is_l4) { 3737 rxudp = PTP_EV_PORT; 3738 cpu_to_be16s(&rxudp); 3739 } 3740 ew32(RXUDP, rxudp); 3741 3742 e1e_flush(); 3743 3744 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */ 3745 er32(RXSTMPH); 3746 er32(TXSTMPH); 3747 3748 return 0; 3749 } 3750 3751 /** 3752 * e1000_configure - configure the hardware for Rx and Tx 3753 * @adapter: private board structure 3754 **/ 3755 static void e1000_configure(struct e1000_adapter *adapter) 3756 { 3757 struct e1000_ring *rx_ring = adapter->rx_ring; 3758 3759 e1000e_set_rx_mode(adapter->netdev); 3760 3761 e1000_restore_vlan(adapter); 3762 e1000_init_manageability_pt(adapter); 3763 3764 e1000_configure_tx(adapter); 3765 3766 if (adapter->netdev->features & NETIF_F_RXHASH) 3767 e1000e_setup_rss_hash(adapter); 3768 e1000_setup_rctl(adapter); 3769 e1000_configure_rx(adapter); 3770 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL); 3771 } 3772 3773 /** 3774 * e1000e_power_up_phy - restore link in case the phy was powered down 3775 * @adapter: address of board private structure 3776 * 3777 * The phy may be powered down to save power and turn off link when the 3778 * driver is unloaded and wake on lan is not enabled (among others) 3779 * *** this routine MUST be followed by a call to e1000e_reset *** 3780 **/ 3781 void e1000e_power_up_phy(struct e1000_adapter *adapter) 3782 { 3783 if (adapter->hw.phy.ops.power_up) 3784 adapter->hw.phy.ops.power_up(&adapter->hw); 3785 3786 adapter->hw.mac.ops.setup_link(&adapter->hw); 3787 } 3788 3789 /** 3790 * e1000_power_down_phy - Power down the PHY 3791 * @adapter: board private structure 3792 * 3793 * Power down the PHY so no link is implied when interface is down. 3794 * The PHY cannot be powered down if management or WoL is active. 3795 */ 3796 static void e1000_power_down_phy(struct e1000_adapter *adapter) 3797 { 3798 if (adapter->hw.phy.ops.power_down) 3799 adapter->hw.phy.ops.power_down(&adapter->hw); 3800 } 3801 3802 /** 3803 * e1000_flush_tx_ring - remove all descriptors from the tx_ring 3804 * @adapter: board private structure 3805 * 3806 * We want to clear all pending descriptors from the TX ring. 3807 * zeroing happens when the HW reads the regs. We assign the ring itself as 3808 * the data of the next descriptor. We don't care about the data we are about 3809 * to reset the HW. 3810 */ 3811 static void e1000_flush_tx_ring(struct e1000_adapter *adapter) 3812 { 3813 struct e1000_hw *hw = &adapter->hw; 3814 struct e1000_ring *tx_ring = adapter->tx_ring; 3815 struct e1000_tx_desc *tx_desc = NULL; 3816 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS; 3817 u16 size = 512; 3818 3819 tctl = er32(TCTL); 3820 ew32(TCTL, tctl | E1000_TCTL_EN); 3821 tdt = er32(TDT(0)); 3822 BUG_ON(tdt != tx_ring->next_to_use); 3823 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use); 3824 tx_desc->buffer_addr = cpu_to_le64(tx_ring->dma); 3825 3826 tx_desc->lower.data = cpu_to_le32(txd_lower | size); 3827 tx_desc->upper.data = 0; 3828 /* flush descriptors to memory before notifying the HW */ 3829 wmb(); 3830 tx_ring->next_to_use++; 3831 if (tx_ring->next_to_use == tx_ring->count) 3832 tx_ring->next_to_use = 0; 3833 ew32(TDT(0), tx_ring->next_to_use); 3834 usleep_range(200, 250); 3835 } 3836 3837 /** 3838 * e1000_flush_rx_ring - remove all descriptors from the rx_ring 3839 * @adapter: board private structure 3840 * 3841 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3842 */ 3843 static void e1000_flush_rx_ring(struct e1000_adapter *adapter) 3844 { 3845 u32 rctl, rxdctl; 3846 struct e1000_hw *hw = &adapter->hw; 3847 3848 rctl = er32(RCTL); 3849 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3850 e1e_flush(); 3851 usleep_range(100, 150); 3852 3853 rxdctl = er32(RXDCTL(0)); 3854 /* zero the lower 14 bits (prefetch and host thresholds) */ 3855 rxdctl &= 0xffffc000; 3856 3857 /* update thresholds: prefetch threshold to 31, host threshold to 1 3858 * and make sure the granularity is "descriptors" and not "cache lines" 3859 */ 3860 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3861 3862 ew32(RXDCTL(0), rxdctl); 3863 /* momentarily enable the RX ring for the changes to take effect */ 3864 ew32(RCTL, rctl | E1000_RCTL_EN); 3865 e1e_flush(); 3866 usleep_range(100, 150); 3867 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3868 } 3869 3870 /** 3871 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings 3872 * @adapter: board private structure 3873 * 3874 * In i219, the descriptor rings must be emptied before resetting the HW 3875 * or before changing the device state to D3 during runtime (runtime PM). 3876 * 3877 * Failure to do this will cause the HW to enter a unit hang state which can 3878 * only be released by PCI reset on the device 3879 * 3880 */ 3881 3882 static void e1000_flush_desc_rings(struct e1000_adapter *adapter) 3883 { 3884 u16 hang_state; 3885 u32 fext_nvm11, tdlen; 3886 struct e1000_hw *hw = &adapter->hw; 3887 3888 /* First, disable MULR fix in FEXTNVM11 */ 3889 fext_nvm11 = er32(FEXTNVM11); 3890 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3891 ew32(FEXTNVM11, fext_nvm11); 3892 /* do nothing if we're not in faulty state, or if the queue is empty */ 3893 tdlen = er32(TDLEN(0)); 3894 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3895 &hang_state); 3896 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3897 return; 3898 e1000_flush_tx_ring(adapter); 3899 /* recheck, maybe the fault is caused by the rx ring */ 3900 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3901 &hang_state); 3902 if (hang_state & FLUSH_DESC_REQUIRED) 3903 e1000_flush_rx_ring(adapter); 3904 } 3905 3906 /** 3907 * e1000e_systim_reset - reset the timesync registers after a hardware reset 3908 * @adapter: board private structure 3909 * 3910 * When the MAC is reset, all hardware bits for timesync will be reset to the 3911 * default values. This function will restore the settings last in place. 3912 * Since the clock SYSTIME registers are reset, we will simply restore the 3913 * cyclecounter to the kernel real clock time. 3914 **/ 3915 static void e1000e_systim_reset(struct e1000_adapter *adapter) 3916 { 3917 struct ptp_clock_info *info = &adapter->ptp_clock_info; 3918 struct e1000_hw *hw = &adapter->hw; 3919 struct netlink_ext_ack extack = {}; 3920 unsigned long flags; 3921 u32 timinca; 3922 s32 ret_val; 3923 3924 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3925 return; 3926 3927 if (info->adjfine) { 3928 /* restore the previous ptp frequency delta */ 3929 ret_val = info->adjfine(info, adapter->ptp_delta); 3930 } else { 3931 /* set the default base frequency if no adjustment possible */ 3932 ret_val = e1000e_get_base_timinca(adapter, &timinca); 3933 if (!ret_val) 3934 ew32(TIMINCA, timinca); 3935 } 3936 3937 if (ret_val) { 3938 dev_warn(&adapter->pdev->dev, 3939 "Failed to restore TIMINCA clock rate delta: %d\n", 3940 ret_val); 3941 return; 3942 } 3943 3944 /* reset the systim ns time counter */ 3945 spin_lock_irqsave(&adapter->systim_lock, flags); 3946 timecounter_init(&adapter->tc, &adapter->cc, 3947 ktime_to_ns(ktime_get_real())); 3948 spin_unlock_irqrestore(&adapter->systim_lock, flags); 3949 3950 /* restore the previous hwtstamp configuration settings */ 3951 ret_val = e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config, 3952 &extack); 3953 if (ret_val) { 3954 if (extack._msg) 3955 e_err("%s\n", extack._msg); 3956 } 3957 } 3958 3959 /** 3960 * e1000e_reset - bring the hardware into a known good state 3961 * @adapter: board private structure 3962 * 3963 * This function boots the hardware and enables some settings that 3964 * require a configuration cycle of the hardware - those cannot be 3965 * set/changed during runtime. After reset the device needs to be 3966 * properly configured for Rx, Tx etc. 3967 */ 3968 void e1000e_reset(struct e1000_adapter *adapter) 3969 { 3970 struct e1000_mac_info *mac = &adapter->hw.mac; 3971 struct e1000_fc_info *fc = &adapter->hw.fc; 3972 struct e1000_hw *hw = &adapter->hw; 3973 u32 tx_space, min_tx_space, min_rx_space; 3974 u32 pba = adapter->pba; 3975 u16 hwm; 3976 3977 /* reset Packet Buffer Allocation to default */ 3978 ew32(PBA, pba); 3979 3980 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) { 3981 /* To maintain wire speed transmits, the Tx FIFO should be 3982 * large enough to accommodate two full transmit packets, 3983 * rounded up to the next 1KB and expressed in KB. Likewise, 3984 * the Rx FIFO should be large enough to accommodate at least 3985 * one full receive packet and is similarly rounded up and 3986 * expressed in KB. 3987 */ 3988 pba = er32(PBA); 3989 /* upper 16 bits has Tx packet buffer allocation size in KB */ 3990 tx_space = pba >> 16; 3991 /* lower 16 bits has Rx packet buffer allocation size in KB */ 3992 pba &= 0xffff; 3993 /* the Tx fifo also stores 16 bytes of information about the Tx 3994 * but don't include ethernet FCS because hardware appends it 3995 */ 3996 min_tx_space = (adapter->max_frame_size + 3997 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2; 3998 min_tx_space = ALIGN(min_tx_space, 1024); 3999 min_tx_space >>= 10; 4000 /* software strips receive CRC, so leave room for it */ 4001 min_rx_space = adapter->max_frame_size; 4002 min_rx_space = ALIGN(min_rx_space, 1024); 4003 min_rx_space >>= 10; 4004 4005 /* If current Tx allocation is less than the min Tx FIFO size, 4006 * and the min Tx FIFO size is less than the current Rx FIFO 4007 * allocation, take space away from current Rx allocation 4008 */ 4009 if ((tx_space < min_tx_space) && 4010 ((min_tx_space - tx_space) < pba)) { 4011 pba -= min_tx_space - tx_space; 4012 4013 /* if short on Rx space, Rx wins and must trump Tx 4014 * adjustment 4015 */ 4016 if (pba < min_rx_space) 4017 pba = min_rx_space; 4018 } 4019 4020 ew32(PBA, pba); 4021 } 4022 4023 /* flow control settings 4024 * 4025 * The high water mark must be low enough to fit one full frame 4026 * (or the size used for early receive) above it in the Rx FIFO. 4027 * Set it to the lower of: 4028 * - 90% of the Rx FIFO size, and 4029 * - the full Rx FIFO size minus one full frame 4030 */ 4031 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) 4032 fc->pause_time = 0xFFFF; 4033 else 4034 fc->pause_time = E1000_FC_PAUSE_TIME; 4035 fc->send_xon = true; 4036 fc->current_mode = fc->requested_mode; 4037 4038 switch (hw->mac.type) { 4039 case e1000_ich9lan: 4040 case e1000_ich10lan: 4041 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4042 pba = 14; 4043 ew32(PBA, pba); 4044 fc->high_water = 0x2800; 4045 fc->low_water = fc->high_water - 8; 4046 break; 4047 } 4048 fallthrough; 4049 default: 4050 hwm = min(((pba << 10) * 9 / 10), 4051 ((pba << 10) - adapter->max_frame_size)); 4052 4053 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ 4054 fc->low_water = fc->high_water - 8; 4055 break; 4056 case e1000_pchlan: 4057 /* Workaround PCH LOM adapter hangs with certain network 4058 * loads. If hangs persist, try disabling Tx flow control. 4059 */ 4060 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4061 fc->high_water = 0x3500; 4062 fc->low_water = 0x1500; 4063 } else { 4064 fc->high_water = 0x5000; 4065 fc->low_water = 0x3000; 4066 } 4067 fc->refresh_time = 0x1000; 4068 break; 4069 case e1000_pch2lan: 4070 case e1000_pch_lpt: 4071 case e1000_pch_spt: 4072 case e1000_pch_cnp: 4073 case e1000_pch_tgp: 4074 case e1000_pch_adp: 4075 case e1000_pch_mtp: 4076 case e1000_pch_lnp: 4077 case e1000_pch_ptp: 4078 case e1000_pch_nvp: 4079 fc->refresh_time = 0xFFFF; 4080 fc->pause_time = 0xFFFF; 4081 4082 if (adapter->netdev->mtu <= ETH_DATA_LEN) { 4083 fc->high_water = 0x05C20; 4084 fc->low_water = 0x05048; 4085 break; 4086 } 4087 4088 pba = 14; 4089 ew32(PBA, pba); 4090 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH; 4091 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL; 4092 break; 4093 } 4094 4095 /* Alignment of Tx data is on an arbitrary byte boundary with the 4096 * maximum size per Tx descriptor limited only to the transmit 4097 * allocation of the packet buffer minus 96 bytes with an upper 4098 * limit of 24KB due to receive synchronization limitations. 4099 */ 4100 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96, 4101 24 << 10); 4102 4103 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot 4104 * fit in receive buffer. 4105 */ 4106 if (adapter->itr_setting & 0x3) { 4107 if ((adapter->max_frame_size * 2) > (pba << 10)) { 4108 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) { 4109 dev_info(&adapter->pdev->dev, 4110 "Interrupt Throttle Rate off\n"); 4111 adapter->flags2 |= FLAG2_DISABLE_AIM; 4112 e1000e_write_itr(adapter, 0); 4113 } 4114 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) { 4115 dev_info(&adapter->pdev->dev, 4116 "Interrupt Throttle Rate on\n"); 4117 adapter->flags2 &= ~FLAG2_DISABLE_AIM; 4118 adapter->itr = 20000; 4119 e1000e_write_itr(adapter, adapter->itr); 4120 } 4121 } 4122 4123 if (hw->mac.type >= e1000_pch_spt) 4124 e1000_flush_desc_rings(adapter); 4125 /* Allow time for pending master requests to run */ 4126 mac->ops.reset_hw(hw); 4127 4128 /* For parts with AMT enabled, let the firmware know 4129 * that the network interface is in control 4130 */ 4131 if (adapter->flags & FLAG_HAS_AMT) 4132 e1000e_get_hw_control(adapter); 4133 4134 ew32(WUC, 0); 4135 4136 if (mac->ops.init_hw(hw)) 4137 e_err("Hardware Error\n"); 4138 4139 e1000_update_mng_vlan(adapter); 4140 4141 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 4142 ew32(VET, ETH_P_8021Q); 4143 4144 e1000e_reset_adaptive(hw); 4145 4146 /* restore systim and hwtstamp settings */ 4147 e1000e_systim_reset(adapter); 4148 4149 /* Set EEE advertisement as appropriate */ 4150 if (adapter->flags2 & FLAG2_HAS_EEE) { 4151 s32 ret_val; 4152 u16 adv_addr; 4153 4154 switch (hw->phy.type) { 4155 case e1000_phy_82579: 4156 adv_addr = I82579_EEE_ADVERTISEMENT; 4157 break; 4158 case e1000_phy_i217: 4159 adv_addr = I217_EEE_ADVERTISEMENT; 4160 break; 4161 default: 4162 dev_err(&adapter->pdev->dev, 4163 "Invalid PHY type setting EEE advertisement\n"); 4164 return; 4165 } 4166 4167 ret_val = hw->phy.ops.acquire(hw); 4168 if (ret_val) { 4169 dev_err(&adapter->pdev->dev, 4170 "EEE advertisement - unable to acquire PHY\n"); 4171 return; 4172 } 4173 4174 e1000_write_emi_reg_locked(hw, adv_addr, 4175 hw->dev_spec.ich8lan.eee_disable ? 4176 0 : adapter->eee_advert); 4177 4178 hw->phy.ops.release(hw); 4179 } 4180 4181 if (!netif_running(adapter->netdev) && 4182 !test_bit(__E1000_TESTING, &adapter->state)) 4183 e1000_power_down_phy(adapter); 4184 4185 e1000_get_phy_info(hw); 4186 4187 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && 4188 !(adapter->flags & FLAG_SMART_POWER_DOWN)) { 4189 u16 phy_data = 0; 4190 /* speed up time to link by disabling smart power down, ignore 4191 * the return value of this function because there is nothing 4192 * different we would do if it failed 4193 */ 4194 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 4195 phy_data &= ~IGP02E1000_PM_SPD; 4196 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 4197 } 4198 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) { 4199 u32 reg; 4200 4201 /* Fextnvm7 @ 0xe4[2] = 1 */ 4202 reg = er32(FEXTNVM7); 4203 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; 4204 ew32(FEXTNVM7, reg); 4205 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */ 4206 reg = er32(FEXTNVM9); 4207 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | 4208 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; 4209 ew32(FEXTNVM9, reg); 4210 } 4211 4212 } 4213 4214 /** 4215 * e1000e_trigger_lsc - trigger an LSC interrupt 4216 * @adapter: board private structure 4217 * 4218 * Fire a link status change interrupt to start the watchdog. 4219 **/ 4220 static void e1000e_trigger_lsc(struct e1000_adapter *adapter) 4221 { 4222 struct e1000_hw *hw = &adapter->hw; 4223 4224 if (adapter->msix_entries) 4225 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER); 4226 else 4227 ew32(ICS, E1000_ICS_LSC); 4228 } 4229 4230 void e1000e_up(struct e1000_adapter *adapter) 4231 { 4232 /* hardware has been reset, we need to reload some things */ 4233 e1000_configure(adapter); 4234 4235 clear_bit(__E1000_DOWN, &adapter->state); 4236 4237 if (adapter->msix_entries) 4238 e1000_configure_msix(adapter); 4239 e1000_irq_enable(adapter); 4240 4241 /* Tx queue started by watchdog timer when link is up */ 4242 4243 e1000e_trigger_lsc(adapter); 4244 } 4245 4246 static void e1000e_flush_descriptors(struct e1000_adapter *adapter) 4247 { 4248 struct e1000_hw *hw = &adapter->hw; 4249 4250 if (!(adapter->flags2 & FLAG2_DMA_BURST)) 4251 return; 4252 4253 /* flush pending descriptor writebacks to memory */ 4254 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4255 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4256 4257 /* execute the writes immediately */ 4258 e1e_flush(); 4259 4260 /* due to rare timing issues, write to TIDV/RDTR again to ensure the 4261 * write is successful 4262 */ 4263 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4264 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4265 4266 /* execute the writes immediately */ 4267 e1e_flush(); 4268 } 4269 4270 static void e1000e_update_stats(struct e1000_adapter *adapter); 4271 4272 /** 4273 * e1000e_down - quiesce the device and optionally reset the hardware 4274 * @adapter: board private structure 4275 * @reset: boolean flag to reset the hardware or not 4276 */ 4277 void e1000e_down(struct e1000_adapter *adapter, bool reset) 4278 { 4279 struct net_device *netdev = adapter->netdev; 4280 struct e1000_hw *hw = &adapter->hw; 4281 u32 tctl, rctl; 4282 4283 /* signal that we're down so the interrupt handler does not 4284 * reschedule our watchdog timer 4285 */ 4286 set_bit(__E1000_DOWN, &adapter->state); 4287 4288 netif_carrier_off(netdev); 4289 4290 /* disable receives in the hardware */ 4291 rctl = er32(RCTL); 4292 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 4293 ew32(RCTL, rctl & ~E1000_RCTL_EN); 4294 /* flush and sleep below */ 4295 4296 netif_stop_queue(netdev); 4297 4298 /* disable transmits in the hardware */ 4299 tctl = er32(TCTL); 4300 tctl &= ~E1000_TCTL_EN; 4301 ew32(TCTL, tctl); 4302 4303 /* flush both disables and wait for them to finish */ 4304 e1e_flush(); 4305 usleep_range(10000, 11000); 4306 4307 e1000_irq_disable(adapter); 4308 4309 napi_synchronize(&adapter->napi); 4310 4311 timer_delete_sync(&adapter->watchdog_timer); 4312 timer_delete_sync(&adapter->phy_info_timer); 4313 4314 spin_lock(&adapter->stats64_lock); 4315 e1000e_update_stats(adapter); 4316 spin_unlock(&adapter->stats64_lock); 4317 4318 e1000e_flush_descriptors(adapter); 4319 4320 adapter->link_speed = 0; 4321 adapter->link_duplex = 0; 4322 4323 /* Disable Si errata workaround on PCHx for jumbo frame flow */ 4324 if ((hw->mac.type >= e1000_pch2lan) && 4325 (adapter->netdev->mtu > ETH_DATA_LEN) && 4326 e1000_lv_jumbo_workaround_ich8lan(hw, false)) 4327 e_dbg("failed to disable jumbo frame workaround mode\n"); 4328 4329 if (!pci_channel_offline(adapter->pdev)) { 4330 if (reset) 4331 e1000e_reset(adapter); 4332 else if (hw->mac.type >= e1000_pch_spt) 4333 e1000_flush_desc_rings(adapter); 4334 } 4335 e1000_clean_tx_ring(adapter->tx_ring); 4336 e1000_clean_rx_ring(adapter->rx_ring); 4337 } 4338 4339 void e1000e_reinit_locked(struct e1000_adapter *adapter) 4340 { 4341 might_sleep(); 4342 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 4343 usleep_range(1000, 1100); 4344 e1000e_down(adapter, true); 4345 e1000e_up(adapter); 4346 clear_bit(__E1000_RESETTING, &adapter->state); 4347 } 4348 4349 /** 4350 * e1000e_sanitize_systim - sanitize raw cycle counter reads 4351 * @hw: pointer to the HW structure 4352 * @systim: PHC time value read, sanitized and returned 4353 * @sts: structure to hold system time before and after reading SYSTIML, 4354 * may be NULL 4355 * 4356 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L: 4357 * check to see that the time is incrementing at a reasonable 4358 * rate and is a multiple of incvalue. 4359 **/ 4360 static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim, 4361 struct ptp_system_timestamp *sts) 4362 { 4363 u64 time_delta, rem, temp; 4364 u64 systim_next; 4365 u32 incvalue; 4366 int i; 4367 4368 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK; 4369 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) { 4370 /* latch SYSTIMH on read of SYSTIML */ 4371 ptp_read_system_prets(sts); 4372 systim_next = (u64)er32(SYSTIML); 4373 ptp_read_system_postts(sts); 4374 systim_next |= (u64)er32(SYSTIMH) << 32; 4375 4376 time_delta = systim_next - systim; 4377 temp = time_delta; 4378 /* VMWare users have seen incvalue of zero, don't div / 0 */ 4379 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0); 4380 4381 systim = systim_next; 4382 4383 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0)) 4384 break; 4385 } 4386 4387 return systim; 4388 } 4389 4390 /** 4391 * e1000e_read_systim - read SYSTIM register 4392 * @adapter: board private structure 4393 * @sts: structure which will contain system time before and after reading 4394 * SYSTIML, may be NULL 4395 **/ 4396 u64 e1000e_read_systim(struct e1000_adapter *adapter, 4397 struct ptp_system_timestamp *sts) 4398 { 4399 struct e1000_hw *hw = &adapter->hw; 4400 u32 systimel, systimel_2, systimeh; 4401 u64 systim; 4402 /* SYSTIMH latching upon SYSTIML read does not work well. 4403 * This means that if SYSTIML overflows after we read it but before 4404 * we read SYSTIMH, the value of SYSTIMH has been incremented and we 4405 * will experience a huge non linear increment in the systime value 4406 * to fix that we test for overflow and if true, we re-read systime. 4407 */ 4408 ptp_read_system_prets(sts); 4409 systimel = er32(SYSTIML); 4410 ptp_read_system_postts(sts); 4411 systimeh = er32(SYSTIMH); 4412 /* Is systimel is so large that overflow is possible? */ 4413 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) { 4414 ptp_read_system_prets(sts); 4415 systimel_2 = er32(SYSTIML); 4416 ptp_read_system_postts(sts); 4417 if (systimel > systimel_2) { 4418 /* There was an overflow, read again SYSTIMH, and use 4419 * systimel_2 4420 */ 4421 systimeh = er32(SYSTIMH); 4422 systimel = systimel_2; 4423 } 4424 } 4425 systim = (u64)systimel; 4426 systim |= (u64)systimeh << 32; 4427 4428 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW) 4429 systim = e1000e_sanitize_systim(hw, systim, sts); 4430 4431 return systim; 4432 } 4433 4434 /** 4435 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter) 4436 * @cc: cyclecounter structure 4437 **/ 4438 static u64 e1000e_cyclecounter_read(struct cyclecounter *cc) 4439 { 4440 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter, 4441 cc); 4442 4443 return e1000e_read_systim(adapter, NULL); 4444 } 4445 4446 /** 4447 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4448 * @adapter: board private structure to initialize 4449 * 4450 * e1000_sw_init initializes the Adapter private data structure. 4451 * Fields are initialized based on PCI device information and 4452 * OS network device settings (MTU size). 4453 **/ 4454 static int e1000_sw_init(struct e1000_adapter *adapter) 4455 { 4456 struct net_device *netdev = adapter->netdev; 4457 4458 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 4459 adapter->rx_ps_bsize0 = 128; 4460 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 4461 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4462 adapter->tx_ring_count = E1000_DEFAULT_TXD; 4463 adapter->rx_ring_count = E1000_DEFAULT_RXD; 4464 4465 spin_lock_init(&adapter->stats64_lock); 4466 4467 e1000e_set_interrupt_capability(adapter); 4468 4469 if (e1000_alloc_queues(adapter)) 4470 return -ENOMEM; 4471 4472 /* Setup hardware time stamping cyclecounter */ 4473 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 4474 adapter->cc.read = e1000e_cyclecounter_read; 4475 adapter->cc.mask = CYCLECOUNTER_MASK(64); 4476 adapter->cc.mult = 1; 4477 /* cc.shift set in e1000e_get_base_tininca() */ 4478 4479 spin_lock_init(&adapter->systim_lock); 4480 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work); 4481 } 4482 4483 /* Explicitly disable IRQ since the NIC can be in any state. */ 4484 e1000_irq_disable(adapter); 4485 4486 set_bit(__E1000_DOWN, &adapter->state); 4487 return 0; 4488 } 4489 4490 /** 4491 * e1000_intr_msi_test - Interrupt Handler 4492 * @irq: interrupt number 4493 * @data: pointer to a network interface device structure 4494 **/ 4495 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data) 4496 { 4497 struct net_device *netdev = data; 4498 struct e1000_adapter *adapter = netdev_priv(netdev); 4499 struct e1000_hw *hw = &adapter->hw; 4500 u32 icr = er32(ICR); 4501 4502 e_dbg("icr is %08X\n", icr); 4503 if (icr & E1000_ICR_RXSEQ) { 4504 adapter->flags &= ~FLAG_MSI_TEST_FAILED; 4505 /* Force memory writes to complete before acknowledging the 4506 * interrupt is handled. 4507 */ 4508 wmb(); 4509 } 4510 4511 return IRQ_HANDLED; 4512 } 4513 4514 /** 4515 * e1000_test_msi_interrupt - Returns 0 for successful test 4516 * @adapter: board private struct 4517 * 4518 * code flow taken from tg3.c 4519 **/ 4520 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter) 4521 { 4522 struct net_device *netdev = adapter->netdev; 4523 struct e1000_hw *hw = &adapter->hw; 4524 int err; 4525 4526 /* poll_enable hasn't been called yet, so don't need disable */ 4527 /* clear any pending events */ 4528 er32(ICR); 4529 4530 /* free the real vector and request a test handler */ 4531 e1000_free_irq(adapter); 4532 e1000e_reset_interrupt_capability(adapter); 4533 4534 /* Assume that the test fails, if it succeeds then the test 4535 * MSI irq handler will unset this flag 4536 */ 4537 adapter->flags |= FLAG_MSI_TEST_FAILED; 4538 4539 err = pci_enable_msi(adapter->pdev); 4540 if (err) 4541 goto msi_test_failed; 4542 4543 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0, 4544 netdev->name, netdev); 4545 if (err) { 4546 pci_disable_msi(adapter->pdev); 4547 goto msi_test_failed; 4548 } 4549 4550 /* Force memory writes to complete before enabling and firing an 4551 * interrupt. 4552 */ 4553 wmb(); 4554 4555 e1000_irq_enable(adapter); 4556 4557 /* fire an unusual interrupt on the test handler */ 4558 ew32(ICS, E1000_ICS_RXSEQ); 4559 e1e_flush(); 4560 msleep(100); 4561 4562 e1000_irq_disable(adapter); 4563 4564 rmb(); /* read flags after interrupt has been fired */ 4565 4566 if (adapter->flags & FLAG_MSI_TEST_FAILED) { 4567 adapter->int_mode = E1000E_INT_MODE_LEGACY; 4568 e_info("MSI interrupt test failed, using legacy interrupt.\n"); 4569 } else { 4570 e_dbg("MSI interrupt test succeeded!\n"); 4571 } 4572 4573 free_irq(adapter->pdev->irq, netdev); 4574 pci_disable_msi(adapter->pdev); 4575 4576 msi_test_failed: 4577 e1000e_set_interrupt_capability(adapter); 4578 return e1000_request_irq(adapter); 4579 } 4580 4581 /** 4582 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored 4583 * @adapter: board private struct 4584 * 4585 * code flow taken from tg3.c, called with e1000 interrupts disabled. 4586 **/ 4587 static int e1000_test_msi(struct e1000_adapter *adapter) 4588 { 4589 int err; 4590 u16 pci_cmd; 4591 4592 if (!(adapter->flags & FLAG_MSI_ENABLED)) 4593 return 0; 4594 4595 /* disable SERR in case the MSI write causes a master abort */ 4596 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4597 if (pci_cmd & PCI_COMMAND_SERR) 4598 pci_write_config_word(adapter->pdev, PCI_COMMAND, 4599 pci_cmd & ~PCI_COMMAND_SERR); 4600 4601 err = e1000_test_msi_interrupt(adapter); 4602 4603 /* re-enable SERR */ 4604 if (pci_cmd & PCI_COMMAND_SERR) { 4605 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4606 pci_cmd |= PCI_COMMAND_SERR; 4607 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd); 4608 } 4609 4610 return err; 4611 } 4612 4613 /** 4614 * e1000e_open - Called when a network interface is made active 4615 * @netdev: network interface device structure 4616 * 4617 * Returns 0 on success, negative value on failure 4618 * 4619 * The open entry point is called when a network interface is made 4620 * active by the system (IFF_UP). At this point all resources needed 4621 * for transmit and receive operations are allocated, the interrupt 4622 * handler is registered with the OS, the watchdog timer is started, 4623 * and the stack is notified that the interface is ready. 4624 **/ 4625 int e1000e_open(struct net_device *netdev) 4626 { 4627 struct e1000_adapter *adapter = netdev_priv(netdev); 4628 struct e1000_hw *hw = &adapter->hw; 4629 struct pci_dev *pdev = adapter->pdev; 4630 int err; 4631 int irq; 4632 4633 /* disallow open during test */ 4634 if (test_bit(__E1000_TESTING, &adapter->state)) 4635 return -EBUSY; 4636 4637 pm_runtime_get_sync(&pdev->dev); 4638 4639 netif_carrier_off(netdev); 4640 netif_stop_queue(netdev); 4641 4642 /* allocate transmit descriptors */ 4643 err = e1000e_setup_tx_resources(adapter->tx_ring); 4644 if (err) 4645 goto err_setup_tx; 4646 4647 /* allocate receive descriptors */ 4648 err = e1000e_setup_rx_resources(adapter->rx_ring); 4649 if (err) 4650 goto err_setup_rx; 4651 4652 /* If AMT is enabled, let the firmware know that the network 4653 * interface is now open and reset the part to a known state. 4654 */ 4655 if (adapter->flags & FLAG_HAS_AMT) { 4656 e1000e_get_hw_control(adapter); 4657 e1000e_reset(adapter); 4658 } 4659 4660 e1000e_power_up_phy(adapter); 4661 4662 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4663 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) 4664 e1000_update_mng_vlan(adapter); 4665 4666 /* DMA latency requirement to workaround jumbo issue */ 4667 cpu_latency_qos_add_request(&adapter->pm_qos_req, PM_QOS_DEFAULT_VALUE); 4668 4669 /* before we allocate an interrupt, we must be ready to handle it. 4670 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4671 * as soon as we call pci_request_irq, so we have to setup our 4672 * clean_rx handler before we do so. 4673 */ 4674 e1000_configure(adapter); 4675 4676 err = e1000_request_irq(adapter); 4677 if (err) 4678 goto err_req_irq; 4679 4680 /* Work around PCIe errata with MSI interrupts causing some chipsets to 4681 * ignore e1000e MSI messages, which means we need to test our MSI 4682 * interrupt now 4683 */ 4684 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) { 4685 err = e1000_test_msi(adapter); 4686 if (err) { 4687 e_err("Interrupt allocation failed\n"); 4688 goto err_req_irq; 4689 } 4690 } 4691 4692 /* From here on the code is the same as e1000e_up() */ 4693 clear_bit(__E1000_DOWN, &adapter->state); 4694 4695 if (adapter->int_mode == E1000E_INT_MODE_MSIX) 4696 irq = adapter->msix_entries[0].vector; 4697 else 4698 irq = adapter->pdev->irq; 4699 4700 netif_napi_set_irq(&adapter->napi, irq); 4701 napi_enable(&adapter->napi); 4702 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_RX, &adapter->napi); 4703 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_TX, &adapter->napi); 4704 4705 e1000_irq_enable(adapter); 4706 4707 adapter->tx_hang_recheck = false; 4708 4709 hw->mac.get_link_status = true; 4710 pm_runtime_put(&pdev->dev); 4711 4712 e1000e_trigger_lsc(adapter); 4713 4714 return 0; 4715 4716 err_req_irq: 4717 cpu_latency_qos_remove_request(&adapter->pm_qos_req); 4718 e1000e_release_hw_control(adapter); 4719 e1000_power_down_phy(adapter); 4720 e1000e_free_rx_resources(adapter->rx_ring); 4721 err_setup_rx: 4722 e1000e_free_tx_resources(adapter->tx_ring); 4723 err_setup_tx: 4724 e1000e_reset(adapter); 4725 pm_runtime_put_sync(&pdev->dev); 4726 4727 return err; 4728 } 4729 4730 /** 4731 * e1000e_close - Disables a network interface 4732 * @netdev: network interface device structure 4733 * 4734 * Returns 0, this is not allowed to fail 4735 * 4736 * The close entry point is called when an interface is de-activated 4737 * by the OS. The hardware is still under the drivers control, but 4738 * needs to be disabled. A global MAC reset is issued to stop the 4739 * hardware, and all transmit and receive resources are freed. 4740 **/ 4741 int e1000e_close(struct net_device *netdev) 4742 { 4743 struct e1000_adapter *adapter = netdev_priv(netdev); 4744 struct pci_dev *pdev = adapter->pdev; 4745 int count = E1000_CHECK_RESET_COUNT; 4746 4747 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 4748 usleep_range(10000, 11000); 4749 4750 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 4751 4752 pm_runtime_get_sync(&pdev->dev); 4753 4754 if (netif_device_present(netdev)) { 4755 e1000e_down(adapter, true); 4756 e1000_free_irq(adapter); 4757 4758 /* Link status message must follow this format */ 4759 netdev_info(netdev, "NIC Link is Down\n"); 4760 } 4761 4762 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_RX, NULL); 4763 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_TX, NULL); 4764 napi_disable(&adapter->napi); 4765 4766 e1000e_free_tx_resources(adapter->tx_ring); 4767 e1000e_free_rx_resources(adapter->rx_ring); 4768 4769 /* kill manageability vlan ID if supported, but not if a vlan with 4770 * the same ID is registered on the host OS (let 8021q kill it) 4771 */ 4772 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) 4773 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 4774 adapter->mng_vlan_id); 4775 4776 /* If AMT is enabled, let the firmware know that the network 4777 * interface is now closed 4778 */ 4779 if ((adapter->flags & FLAG_HAS_AMT) && 4780 !test_bit(__E1000_TESTING, &adapter->state)) 4781 e1000e_release_hw_control(adapter); 4782 4783 cpu_latency_qos_remove_request(&adapter->pm_qos_req); 4784 4785 pm_runtime_put_sync(&pdev->dev); 4786 4787 return 0; 4788 } 4789 4790 /** 4791 * e1000_set_mac - Change the Ethernet Address of the NIC 4792 * @netdev: network interface device structure 4793 * @p: pointer to an address structure 4794 * 4795 * Returns 0 on success, negative on failure 4796 **/ 4797 static int e1000_set_mac(struct net_device *netdev, void *p) 4798 { 4799 struct e1000_adapter *adapter = netdev_priv(netdev); 4800 struct e1000_hw *hw = &adapter->hw; 4801 struct sockaddr *addr = p; 4802 4803 if (!is_valid_ether_addr(addr->sa_data)) 4804 return -EADDRNOTAVAIL; 4805 4806 eth_hw_addr_set(netdev, addr->sa_data); 4807 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); 4808 4809 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 4810 4811 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { 4812 /* activate the work around */ 4813 e1000e_set_laa_state_82571(&adapter->hw, 1); 4814 4815 /* Hold a copy of the LAA in RAR[14] This is done so that 4816 * between the time RAR[0] gets clobbered and the time it 4817 * gets fixed (in e1000_watchdog), the actual LAA is in one 4818 * of the RARs and no incoming packets directed to this port 4819 * are dropped. Eventually the LAA will be in RAR[0] and 4820 * RAR[14] 4821 */ 4822 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 4823 adapter->hw.mac.rar_entry_count - 1); 4824 } 4825 4826 return 0; 4827 } 4828 4829 /** 4830 * e1000e_update_phy_task - work thread to update phy 4831 * @work: pointer to our work struct 4832 * 4833 * this worker thread exists because we must acquire a 4834 * semaphore to read the phy, which we could msleep while 4835 * waiting for it, and we can't msleep in a timer. 4836 **/ 4837 static void e1000e_update_phy_task(struct work_struct *work) 4838 { 4839 struct e1000_adapter *adapter = container_of(work, 4840 struct e1000_adapter, 4841 update_phy_task); 4842 struct e1000_hw *hw = &adapter->hw; 4843 4844 if (test_bit(__E1000_DOWN, &adapter->state)) 4845 return; 4846 4847 e1000_get_phy_info(hw); 4848 4849 /* Enable EEE on 82579 after link up */ 4850 if (hw->phy.type >= e1000_phy_82579) 4851 e1000_set_eee_pchlan(hw); 4852 } 4853 4854 /** 4855 * e1000_update_phy_info - timre call-back to update PHY info 4856 * @t: pointer to timer_list containing private info adapter 4857 * 4858 * Need to wait a few seconds after link up to get diagnostic information from 4859 * the phy 4860 **/ 4861 static void e1000_update_phy_info(struct timer_list *t) 4862 { 4863 struct e1000_adapter *adapter = timer_container_of(adapter, t, 4864 phy_info_timer); 4865 4866 if (test_bit(__E1000_DOWN, &adapter->state)) 4867 return; 4868 4869 schedule_work(&adapter->update_phy_task); 4870 } 4871 4872 /** 4873 * e1000e_update_phy_stats - Update the PHY statistics counters 4874 * @adapter: board private structure 4875 * 4876 * Read/clear the upper 16-bit PHY registers and read/accumulate lower 4877 **/ 4878 static void e1000e_update_phy_stats(struct e1000_adapter *adapter) 4879 { 4880 struct e1000_hw *hw = &adapter->hw; 4881 s32 ret_val; 4882 u16 phy_data; 4883 4884 ret_val = hw->phy.ops.acquire(hw); 4885 if (ret_val) 4886 return; 4887 4888 /* A page set is expensive so check if already on desired page. 4889 * If not, set to the page with the PHY status registers. 4890 */ 4891 hw->phy.addr = 1; 4892 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4893 &phy_data); 4894 if (ret_val) 4895 goto release; 4896 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) { 4897 ret_val = hw->phy.ops.set_page(hw, 4898 HV_STATS_PAGE << IGP_PAGE_SHIFT); 4899 if (ret_val) 4900 goto release; 4901 } 4902 4903 /* Single Collision Count */ 4904 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 4905 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 4906 if (!ret_val) 4907 adapter->stats.scc += phy_data; 4908 4909 /* Excessive Collision Count */ 4910 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 4911 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 4912 if (!ret_val) 4913 adapter->stats.ecol += phy_data; 4914 4915 /* Multiple Collision Count */ 4916 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 4917 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 4918 if (!ret_val) 4919 adapter->stats.mcc += phy_data; 4920 4921 /* Late Collision Count */ 4922 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 4923 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 4924 if (!ret_val) 4925 adapter->stats.latecol += phy_data; 4926 4927 /* Collision Count - also used for adaptive IFS */ 4928 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 4929 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 4930 if (!ret_val) 4931 hw->mac.collision_delta = phy_data; 4932 4933 /* Defer Count */ 4934 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 4935 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 4936 if (!ret_val) 4937 adapter->stats.dc += phy_data; 4938 4939 /* Transmit with no CRS */ 4940 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 4941 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 4942 if (!ret_val) 4943 adapter->stats.tncrs += phy_data; 4944 4945 release: 4946 hw->phy.ops.release(hw); 4947 } 4948 4949 /** 4950 * e1000e_update_stats - Update the board statistics counters 4951 * @adapter: board private structure 4952 **/ 4953 static void e1000e_update_stats(struct e1000_adapter *adapter) 4954 { 4955 struct net_device *netdev = adapter->netdev; 4956 struct e1000_hw *hw = &adapter->hw; 4957 struct pci_dev *pdev = adapter->pdev; 4958 4959 /* Prevent stats update while adapter is being reset, or if the pci 4960 * connection is down. 4961 */ 4962 if (adapter->link_speed == 0) 4963 return; 4964 if (pci_channel_offline(pdev)) 4965 return; 4966 4967 adapter->stats.crcerrs += er32(CRCERRS); 4968 adapter->stats.gprc += er32(GPRC); 4969 adapter->stats.gorc += er32(GORCL); 4970 er32(GORCH); /* Clear gorc */ 4971 adapter->stats.bprc += er32(BPRC); 4972 adapter->stats.mprc += er32(MPRC); 4973 adapter->stats.roc += er32(ROC); 4974 4975 adapter->stats.mpc += er32(MPC); 4976 4977 /* Half-duplex statistics */ 4978 if (adapter->link_duplex == HALF_DUPLEX) { 4979 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) { 4980 e1000e_update_phy_stats(adapter); 4981 } else { 4982 adapter->stats.scc += er32(SCC); 4983 adapter->stats.ecol += er32(ECOL); 4984 adapter->stats.mcc += er32(MCC); 4985 adapter->stats.latecol += er32(LATECOL); 4986 adapter->stats.dc += er32(DC); 4987 4988 hw->mac.collision_delta = er32(COLC); 4989 4990 if ((hw->mac.type != e1000_82574) && 4991 (hw->mac.type != e1000_82583)) 4992 adapter->stats.tncrs += er32(TNCRS); 4993 } 4994 adapter->stats.colc += hw->mac.collision_delta; 4995 } 4996 4997 adapter->stats.xonrxc += er32(XONRXC); 4998 adapter->stats.xontxc += er32(XONTXC); 4999 adapter->stats.xoffrxc += er32(XOFFRXC); 5000 adapter->stats.xofftxc += er32(XOFFTXC); 5001 adapter->stats.gptc += er32(GPTC); 5002 adapter->stats.gotc += er32(GOTCL); 5003 er32(GOTCH); /* Clear gotc */ 5004 adapter->stats.rnbc += er32(RNBC); 5005 adapter->stats.ruc += er32(RUC); 5006 5007 adapter->stats.mptc += er32(MPTC); 5008 adapter->stats.bptc += er32(BPTC); 5009 5010 /* used for adaptive IFS */ 5011 5012 hw->mac.tx_packet_delta = er32(TPT); 5013 adapter->stats.tpt += hw->mac.tx_packet_delta; 5014 5015 adapter->stats.algnerrc += er32(ALGNERRC); 5016 adapter->stats.rxerrc += er32(RXERRC); 5017 adapter->stats.cexterr += er32(CEXTERR); 5018 adapter->stats.tsctc += er32(TSCTC); 5019 adapter->stats.tsctfc += er32(TSCTFC); 5020 5021 /* Fill out the OS statistics structure */ 5022 netdev->stats.multicast = adapter->stats.mprc; 5023 netdev->stats.collisions = adapter->stats.colc; 5024 5025 /* Rx Errors */ 5026 5027 /* RLEC on some newer hardware can be incorrect so build 5028 * our own version based on RUC and ROC 5029 */ 5030 netdev->stats.rx_errors = adapter->stats.rxerrc + 5031 adapter->stats.crcerrs + adapter->stats.algnerrc + 5032 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 5033 netdev->stats.rx_length_errors = adapter->stats.ruc + 5034 adapter->stats.roc; 5035 netdev->stats.rx_crc_errors = adapter->stats.crcerrs; 5036 netdev->stats.rx_frame_errors = adapter->stats.algnerrc; 5037 netdev->stats.rx_missed_errors = adapter->stats.mpc; 5038 5039 /* Tx Errors */ 5040 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol; 5041 netdev->stats.tx_aborted_errors = adapter->stats.ecol; 5042 netdev->stats.tx_window_errors = adapter->stats.latecol; 5043 netdev->stats.tx_carrier_errors = adapter->stats.tncrs; 5044 5045 /* Tx Dropped needs to be maintained elsewhere */ 5046 5047 /* Management Stats */ 5048 adapter->stats.mgptc += er32(MGTPTC); 5049 adapter->stats.mgprc += er32(MGTPRC); 5050 adapter->stats.mgpdc += er32(MGTPDC); 5051 5052 /* Correctable ECC Errors */ 5053 if (hw->mac.type >= e1000_pch_lpt) { 5054 u32 pbeccsts = er32(PBECCSTS); 5055 5056 adapter->corr_errors += 5057 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 5058 adapter->uncorr_errors += 5059 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts); 5060 } 5061 } 5062 5063 /** 5064 * e1000_phy_read_status - Update the PHY register status snapshot 5065 * @adapter: board private structure 5066 **/ 5067 static void e1000_phy_read_status(struct e1000_adapter *adapter) 5068 { 5069 struct e1000_hw *hw = &adapter->hw; 5070 struct e1000_phy_regs *phy = &adapter->phy_regs; 5071 5072 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) && 5073 (er32(STATUS) & E1000_STATUS_LU) && 5074 (adapter->hw.phy.media_type == e1000_media_type_copper)) { 5075 int ret_val; 5076 5077 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr); 5078 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr); 5079 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise); 5080 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa); 5081 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion); 5082 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000); 5083 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000); 5084 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus); 5085 if (ret_val) 5086 e_warn("Error reading PHY register\n"); 5087 } else { 5088 /* Do not read PHY registers if link is not up 5089 * Set values to typical power-on defaults 5090 */ 5091 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); 5092 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | 5093 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE | 5094 BMSR_ERCAP); 5095 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP | 5096 ADVERTISE_ALL | ADVERTISE_CSMA); 5097 phy->lpa = 0; 5098 phy->expansion = EXPANSION_ENABLENPAGE; 5099 phy->ctrl1000 = ADVERTISE_1000FULL; 5100 phy->stat1000 = 0; 5101 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF); 5102 } 5103 } 5104 5105 static void e1000_print_link_info(struct e1000_adapter *adapter) 5106 { 5107 struct e1000_hw *hw = &adapter->hw; 5108 u32 ctrl = er32(CTRL); 5109 5110 /* Link status message must follow this format for user tools */ 5111 netdev_info(adapter->netdev, 5112 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5113 adapter->link_speed, 5114 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half", 5115 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" : 5116 (ctrl & E1000_CTRL_RFCE) ? "Rx" : 5117 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None"); 5118 } 5119 5120 static bool e1000e_has_link(struct e1000_adapter *adapter) 5121 { 5122 struct e1000_hw *hw = &adapter->hw; 5123 bool link_active = false; 5124 s32 ret_val = 0; 5125 5126 /* get_link_status is set on LSC (link status) interrupt or 5127 * Rx sequence error interrupt. get_link_status will stay 5128 * true until the check_for_link establishes link 5129 * for copper adapters ONLY 5130 */ 5131 switch (hw->phy.media_type) { 5132 case e1000_media_type_copper: 5133 if (hw->mac.get_link_status) { 5134 ret_val = hw->mac.ops.check_for_link(hw); 5135 link_active = !hw->mac.get_link_status; 5136 } else { 5137 link_active = true; 5138 } 5139 break; 5140 case e1000_media_type_fiber: 5141 ret_val = hw->mac.ops.check_for_link(hw); 5142 link_active = !!(er32(STATUS) & E1000_STATUS_LU); 5143 break; 5144 case e1000_media_type_internal_serdes: 5145 ret_val = hw->mac.ops.check_for_link(hw); 5146 link_active = hw->mac.serdes_has_link; 5147 break; 5148 default: 5149 case e1000_media_type_unknown: 5150 break; 5151 } 5152 5153 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && 5154 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { 5155 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ 5156 e_info("Gigabit has been disabled, downgrading speed\n"); 5157 } 5158 5159 return link_active; 5160 } 5161 5162 static void e1000e_enable_receives(struct e1000_adapter *adapter) 5163 { 5164 /* make sure the receive unit is started */ 5165 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) && 5166 (adapter->flags & FLAG_RESTART_NOW)) { 5167 struct e1000_hw *hw = &adapter->hw; 5168 u32 rctl = er32(RCTL); 5169 5170 ew32(RCTL, rctl | E1000_RCTL_EN); 5171 adapter->flags &= ~FLAG_RESTART_NOW; 5172 } 5173 } 5174 5175 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter) 5176 { 5177 struct e1000_hw *hw = &adapter->hw; 5178 5179 /* With 82574 controllers, PHY needs to be checked periodically 5180 * for hung state and reset, if two calls return true 5181 */ 5182 if (e1000_check_phy_82574(hw)) 5183 adapter->phy_hang_count++; 5184 else 5185 adapter->phy_hang_count = 0; 5186 5187 if (adapter->phy_hang_count > 1) { 5188 adapter->phy_hang_count = 0; 5189 e_dbg("PHY appears hung - resetting\n"); 5190 schedule_work(&adapter->reset_task); 5191 } 5192 } 5193 5194 /** 5195 * e1000_watchdog - Timer Call-back 5196 * @t: pointer to timer_list containing private info adapter 5197 **/ 5198 static void e1000_watchdog(struct timer_list *t) 5199 { 5200 struct e1000_adapter *adapter = timer_container_of(adapter, t, 5201 watchdog_timer); 5202 5203 /* Do the rest outside of interrupt context */ 5204 schedule_work(&adapter->watchdog_task); 5205 5206 /* TODO: make this use queue_delayed_work() */ 5207 } 5208 5209 static void e1000_watchdog_task(struct work_struct *work) 5210 { 5211 struct e1000_adapter *adapter = container_of(work, 5212 struct e1000_adapter, 5213 watchdog_task); 5214 struct net_device *netdev = adapter->netdev; 5215 struct e1000_mac_info *mac = &adapter->hw.mac; 5216 struct e1000_phy_info *phy = &adapter->hw.phy; 5217 struct e1000_ring *tx_ring = adapter->tx_ring; 5218 u32 dmoff_exit_timeout = 100, tries = 0; 5219 struct e1000_hw *hw = &adapter->hw; 5220 u32 link, tctl, pcim_state; 5221 5222 if (test_bit(__E1000_DOWN, &adapter->state)) 5223 return; 5224 5225 link = e1000e_has_link(adapter); 5226 if ((netif_carrier_ok(netdev)) && link) { 5227 /* Cancel scheduled suspend requests. */ 5228 pm_runtime_resume(netdev->dev.parent); 5229 5230 e1000e_enable_receives(adapter); 5231 goto link_up; 5232 } 5233 5234 if ((e1000e_enable_tx_pkt_filtering(hw)) && 5235 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) 5236 e1000_update_mng_vlan(adapter); 5237 5238 if (link) { 5239 if (!netif_carrier_ok(netdev)) { 5240 bool txb2b = true; 5241 5242 /* Cancel scheduled suspend requests. */ 5243 pm_runtime_resume(netdev->dev.parent); 5244 5245 /* Checking if MAC is in DMoff state*/ 5246 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 5247 pcim_state = er32(STATUS); 5248 while (pcim_state & E1000_STATUS_PCIM_STATE) { 5249 if (tries++ == dmoff_exit_timeout) { 5250 e_dbg("Error in exiting dmoff\n"); 5251 break; 5252 } 5253 usleep_range(10000, 20000); 5254 pcim_state = er32(STATUS); 5255 5256 /* Checking if MAC exited DMoff state */ 5257 if (!(pcim_state & E1000_STATUS_PCIM_STATE)) 5258 e1000_phy_hw_reset(&adapter->hw); 5259 } 5260 } 5261 5262 /* update snapshot of PHY registers on LSC */ 5263 e1000_phy_read_status(adapter); 5264 mac->ops.get_link_up_info(&adapter->hw, 5265 &adapter->link_speed, 5266 &adapter->link_duplex); 5267 e1000_print_link_info(adapter); 5268 5269 /* check if SmartSpeed worked */ 5270 e1000e_check_downshift(hw); 5271 if (phy->speed_downgraded) 5272 netdev_warn(netdev, 5273 "Link Speed was downgraded by SmartSpeed\n"); 5274 5275 /* On supported PHYs, check for duplex mismatch only 5276 * if link has autonegotiated at 10/100 half 5277 */ 5278 if ((hw->phy.type == e1000_phy_igp_3 || 5279 hw->phy.type == e1000_phy_bm) && 5280 hw->mac.autoneg && 5281 (adapter->link_speed == SPEED_10 || 5282 adapter->link_speed == SPEED_100) && 5283 (adapter->link_duplex == HALF_DUPLEX)) { 5284 u16 autoneg_exp; 5285 5286 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp); 5287 5288 if (!(autoneg_exp & EXPANSION_NWAY)) 5289 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n"); 5290 } 5291 5292 /* adjust timeout factor according to speed/duplex */ 5293 adapter->tx_timeout_factor = 1; 5294 switch (adapter->link_speed) { 5295 case SPEED_10: 5296 txb2b = false; 5297 adapter->tx_timeout_factor = 16; 5298 break; 5299 case SPEED_100: 5300 txb2b = false; 5301 adapter->tx_timeout_factor = 10; 5302 break; 5303 } 5304 5305 /* workaround: re-program speed mode bit after 5306 * link-up event 5307 */ 5308 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && 5309 !txb2b) { 5310 u32 tarc0; 5311 5312 tarc0 = er32(TARC(0)); 5313 tarc0 &= ~SPEED_MODE_BIT; 5314 ew32(TARC(0), tarc0); 5315 } 5316 5317 /* enable transmits in the hardware, need to do this 5318 * after setting TARC(0) 5319 */ 5320 tctl = er32(TCTL); 5321 tctl |= E1000_TCTL_EN; 5322 ew32(TCTL, tctl); 5323 5324 /* Perform any post-link-up configuration before 5325 * reporting link up. 5326 */ 5327 if (phy->ops.cfg_on_link_up) 5328 phy->ops.cfg_on_link_up(hw); 5329 5330 netif_wake_queue(netdev); 5331 netif_carrier_on(netdev); 5332 5333 if (!test_bit(__E1000_DOWN, &adapter->state)) 5334 mod_timer(&adapter->phy_info_timer, 5335 round_jiffies(jiffies + 2 * HZ)); 5336 } 5337 } else { 5338 if (netif_carrier_ok(netdev)) { 5339 adapter->link_speed = 0; 5340 adapter->link_duplex = 0; 5341 /* Link status message must follow this format */ 5342 netdev_info(netdev, "NIC Link is Down\n"); 5343 netif_carrier_off(netdev); 5344 netif_stop_queue(netdev); 5345 if (!test_bit(__E1000_DOWN, &adapter->state)) 5346 mod_timer(&adapter->phy_info_timer, 5347 round_jiffies(jiffies + 2 * HZ)); 5348 5349 /* 8000ES2LAN requires a Rx packet buffer work-around 5350 * on link down event; reset the controller to flush 5351 * the Rx packet buffer. 5352 */ 5353 if (adapter->flags & FLAG_RX_NEEDS_RESTART) 5354 adapter->flags |= FLAG_RESTART_NOW; 5355 else 5356 pm_schedule_suspend(netdev->dev.parent, 5357 LINK_TIMEOUT); 5358 } 5359 } 5360 5361 link_up: 5362 spin_lock(&adapter->stats64_lock); 5363 e1000e_update_stats(adapter); 5364 5365 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; 5366 adapter->tpt_old = adapter->stats.tpt; 5367 mac->collision_delta = adapter->stats.colc - adapter->colc_old; 5368 adapter->colc_old = adapter->stats.colc; 5369 5370 adapter->gorc = adapter->stats.gorc - adapter->gorc_old; 5371 adapter->gorc_old = adapter->stats.gorc; 5372 adapter->gotc = adapter->stats.gotc - adapter->gotc_old; 5373 adapter->gotc_old = adapter->stats.gotc; 5374 spin_unlock(&adapter->stats64_lock); 5375 5376 /* If the link is lost the controller stops DMA, but 5377 * if there is queued Tx work it cannot be done. So 5378 * reset the controller to flush the Tx packet buffers. 5379 */ 5380 if (!netif_carrier_ok(netdev) && 5381 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) 5382 adapter->flags |= FLAG_RESTART_NOW; 5383 5384 /* If reset is necessary, do it outside of interrupt context. */ 5385 if (adapter->flags & FLAG_RESTART_NOW) { 5386 schedule_work(&adapter->reset_task); 5387 /* return immediately since reset is imminent */ 5388 return; 5389 } 5390 5391 e1000e_update_adaptive(&adapter->hw); 5392 5393 /* Simple mode for Interrupt Throttle Rate (ITR) */ 5394 if (adapter->itr_setting == 4) { 5395 /* Symmetric Tx/Rx gets a reduced ITR=2000; 5396 * Total asymmetrical Tx or Rx gets ITR=8000; 5397 * everyone else is between 2000-8000. 5398 */ 5399 u32 goc = (adapter->gotc + adapter->gorc) / 10000; 5400 u32 dif = (adapter->gotc > adapter->gorc ? 5401 adapter->gotc - adapter->gorc : 5402 adapter->gorc - adapter->gotc) / 10000; 5403 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000; 5404 5405 e1000e_write_itr(adapter, itr); 5406 } 5407 5408 /* Cause software interrupt to ensure Rx ring is cleaned */ 5409 if (adapter->msix_entries) 5410 ew32(ICS, adapter->rx_ring->ims_val); 5411 else 5412 ew32(ICS, E1000_ICS_RXDMT0); 5413 5414 /* flush pending descriptors to memory before detecting Tx hang */ 5415 e1000e_flush_descriptors(adapter); 5416 5417 /* Force detection of hung controller every watchdog period */ 5418 adapter->detect_tx_hung = true; 5419 5420 /* With 82571 controllers, LAA may be overwritten due to controller 5421 * reset from the other port. Set the appropriate LAA in RAR[0] 5422 */ 5423 if (e1000e_get_laa_state_82571(hw)) 5424 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0); 5425 5426 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG) 5427 e1000e_check_82574_phy_workaround(adapter); 5428 5429 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */ 5430 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) { 5431 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) && 5432 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) { 5433 er32(RXSTMPH); 5434 adapter->rx_hwtstamp_cleared++; 5435 } else { 5436 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP; 5437 } 5438 } 5439 5440 /* Reset the timer */ 5441 if (!test_bit(__E1000_DOWN, &adapter->state)) 5442 mod_timer(&adapter->watchdog_timer, 5443 round_jiffies(jiffies + 2 * HZ)); 5444 } 5445 5446 #define E1000_TX_FLAGS_CSUM 0x00000001 5447 #define E1000_TX_FLAGS_VLAN 0x00000002 5448 #define E1000_TX_FLAGS_TSO 0x00000004 5449 #define E1000_TX_FLAGS_IPV4 0x00000008 5450 #define E1000_TX_FLAGS_NO_FCS 0x00000010 5451 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020 5452 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 5453 #define E1000_TX_FLAGS_VLAN_SHIFT 16 5454 5455 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb, 5456 __be16 protocol) 5457 { 5458 struct e1000_context_desc *context_desc; 5459 struct e1000_buffer *buffer_info; 5460 unsigned int i; 5461 u32 cmd_length = 0; 5462 u16 ipcse = 0, mss; 5463 u8 ipcss, ipcso, tucss, tucso, hdr_len; 5464 int err; 5465 5466 if (!skb_is_gso(skb)) 5467 return 0; 5468 5469 err = skb_cow_head(skb, 0); 5470 if (err < 0) 5471 return err; 5472 5473 hdr_len = skb_tcp_all_headers(skb); 5474 mss = skb_shinfo(skb)->gso_size; 5475 if (protocol == htons(ETH_P_IP)) { 5476 struct iphdr *iph = ip_hdr(skb); 5477 iph->tot_len = 0; 5478 iph->check = 0; 5479 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 5480 0, IPPROTO_TCP, 0); 5481 cmd_length = E1000_TXD_CMD_IP; 5482 ipcse = skb_transport_offset(skb) - 1; 5483 } else if (skb_is_gso_v6(skb)) { 5484 tcp_v6_gso_csum_prep(skb); 5485 ipcse = 0; 5486 } 5487 ipcss = skb_network_offset(skb); 5488 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; 5489 tucss = skb_transport_offset(skb); 5490 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; 5491 5492 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | 5493 E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); 5494 5495 i = tx_ring->next_to_use; 5496 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5497 buffer_info = &tx_ring->buffer_info[i]; 5498 5499 context_desc->lower_setup.ip_fields.ipcss = ipcss; 5500 context_desc->lower_setup.ip_fields.ipcso = ipcso; 5501 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); 5502 context_desc->upper_setup.tcp_fields.tucss = tucss; 5503 context_desc->upper_setup.tcp_fields.tucso = tucso; 5504 context_desc->upper_setup.tcp_fields.tucse = 0; 5505 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); 5506 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; 5507 context_desc->cmd_and_length = cpu_to_le32(cmd_length); 5508 5509 buffer_info->time_stamp = jiffies; 5510 buffer_info->next_to_watch = i; 5511 5512 i++; 5513 if (i == tx_ring->count) 5514 i = 0; 5515 tx_ring->next_to_use = i; 5516 5517 return 1; 5518 } 5519 5520 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb, 5521 __be16 protocol) 5522 { 5523 struct e1000_adapter *adapter = tx_ring->adapter; 5524 struct e1000_context_desc *context_desc; 5525 struct e1000_buffer *buffer_info; 5526 unsigned int i; 5527 u8 css; 5528 u32 cmd_len = E1000_TXD_CMD_DEXT; 5529 5530 if (skb->ip_summed != CHECKSUM_PARTIAL) 5531 return false; 5532 5533 switch (protocol) { 5534 case cpu_to_be16(ETH_P_IP): 5535 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 5536 cmd_len |= E1000_TXD_CMD_TCP; 5537 break; 5538 case cpu_to_be16(ETH_P_IPV6): 5539 /* XXX not handling all IPV6 headers */ 5540 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) 5541 cmd_len |= E1000_TXD_CMD_TCP; 5542 break; 5543 default: 5544 if (unlikely(net_ratelimit())) 5545 e_warn("checksum_partial proto=%x!\n", 5546 be16_to_cpu(protocol)); 5547 break; 5548 } 5549 5550 css = skb_checksum_start_offset(skb); 5551 5552 i = tx_ring->next_to_use; 5553 buffer_info = &tx_ring->buffer_info[i]; 5554 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5555 5556 context_desc->lower_setup.ip_config = 0; 5557 context_desc->upper_setup.tcp_fields.tucss = css; 5558 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset; 5559 context_desc->upper_setup.tcp_fields.tucse = 0; 5560 context_desc->tcp_seg_setup.data = 0; 5561 context_desc->cmd_and_length = cpu_to_le32(cmd_len); 5562 5563 buffer_info->time_stamp = jiffies; 5564 buffer_info->next_to_watch = i; 5565 5566 i++; 5567 if (i == tx_ring->count) 5568 i = 0; 5569 tx_ring->next_to_use = i; 5570 5571 return true; 5572 } 5573 5574 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb, 5575 unsigned int first, unsigned int max_per_txd, 5576 unsigned int nr_frags) 5577 { 5578 struct e1000_adapter *adapter = tx_ring->adapter; 5579 struct pci_dev *pdev = adapter->pdev; 5580 struct e1000_buffer *buffer_info; 5581 unsigned int len = skb_headlen(skb); 5582 unsigned int offset = 0, size, count = 0, i; 5583 unsigned int f, bytecount, segs; 5584 5585 i = tx_ring->next_to_use; 5586 5587 while (len) { 5588 buffer_info = &tx_ring->buffer_info[i]; 5589 size = min(len, max_per_txd); 5590 5591 buffer_info->length = size; 5592 buffer_info->time_stamp = jiffies; 5593 buffer_info->next_to_watch = i; 5594 buffer_info->dma = dma_map_single(&pdev->dev, 5595 skb->data + offset, 5596 size, DMA_TO_DEVICE); 5597 buffer_info->mapped_as_page = false; 5598 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5599 goto dma_error; 5600 5601 len -= size; 5602 offset += size; 5603 count++; 5604 5605 if (len) { 5606 i++; 5607 if (i == tx_ring->count) 5608 i = 0; 5609 } 5610 } 5611 5612 for (f = 0; f < nr_frags; f++) { 5613 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 5614 5615 len = skb_frag_size(frag); 5616 offset = 0; 5617 5618 while (len) { 5619 i++; 5620 if (i == tx_ring->count) 5621 i = 0; 5622 5623 buffer_info = &tx_ring->buffer_info[i]; 5624 size = min(len, max_per_txd); 5625 5626 buffer_info->length = size; 5627 buffer_info->time_stamp = jiffies; 5628 buffer_info->next_to_watch = i; 5629 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag, 5630 offset, size, 5631 DMA_TO_DEVICE); 5632 buffer_info->mapped_as_page = true; 5633 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5634 goto dma_error; 5635 5636 len -= size; 5637 offset += size; 5638 count++; 5639 } 5640 } 5641 5642 segs = skb_shinfo(skb)->gso_segs ? : 1; 5643 /* multiply data chunks by size of headers */ 5644 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len; 5645 5646 tx_ring->buffer_info[i].skb = skb; 5647 tx_ring->buffer_info[i].segs = segs; 5648 tx_ring->buffer_info[i].bytecount = bytecount; 5649 tx_ring->buffer_info[first].next_to_watch = i; 5650 5651 return count; 5652 5653 dma_error: 5654 dev_err(&pdev->dev, "Tx DMA map failed\n"); 5655 buffer_info->dma = 0; 5656 if (count) 5657 count--; 5658 5659 while (count--) { 5660 if (i == 0) 5661 i += tx_ring->count; 5662 i--; 5663 buffer_info = &tx_ring->buffer_info[i]; 5664 e1000_put_txbuf(tx_ring, buffer_info, true); 5665 } 5666 5667 return 0; 5668 } 5669 5670 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count) 5671 { 5672 struct e1000_adapter *adapter = tx_ring->adapter; 5673 struct e1000_tx_desc *tx_desc = NULL; 5674 struct e1000_buffer *buffer_info; 5675 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; 5676 unsigned int i; 5677 5678 if (tx_flags & E1000_TX_FLAGS_TSO) { 5679 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | 5680 E1000_TXD_CMD_TSE; 5681 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5682 5683 if (tx_flags & E1000_TX_FLAGS_IPV4) 5684 txd_upper |= E1000_TXD_POPTS_IXSM << 8; 5685 } 5686 5687 if (tx_flags & E1000_TX_FLAGS_CSUM) { 5688 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5689 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5690 } 5691 5692 if (tx_flags & E1000_TX_FLAGS_VLAN) { 5693 txd_lower |= E1000_TXD_CMD_VLE; 5694 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK); 5695 } 5696 5697 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5698 txd_lower &= ~(E1000_TXD_CMD_IFCS); 5699 5700 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) { 5701 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5702 txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 5703 } 5704 5705 i = tx_ring->next_to_use; 5706 5707 do { 5708 buffer_info = &tx_ring->buffer_info[i]; 5709 tx_desc = E1000_TX_DESC(*tx_ring, i); 5710 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 5711 tx_desc->lower.data = cpu_to_le32(txd_lower | 5712 buffer_info->length); 5713 tx_desc->upper.data = cpu_to_le32(txd_upper); 5714 5715 i++; 5716 if (i == tx_ring->count) 5717 i = 0; 5718 } while (--count > 0); 5719 5720 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); 5721 5722 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */ 5723 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5724 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS)); 5725 5726 /* Force memory writes to complete before letting h/w 5727 * know there are new descriptors to fetch. (Only 5728 * applicable for weak-ordered memory model archs, 5729 * such as IA-64). 5730 */ 5731 wmb(); 5732 5733 tx_ring->next_to_use = i; 5734 } 5735 5736 #define MINIMUM_DHCP_PACKET_SIZE 282 5737 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, 5738 struct sk_buff *skb) 5739 { 5740 struct e1000_hw *hw = &adapter->hw; 5741 u16 length, offset; 5742 5743 if (skb_vlan_tag_present(skb) && 5744 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && 5745 (adapter->hw.mng_cookie.status & 5746 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))) 5747 return 0; 5748 5749 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE) 5750 return 0; 5751 5752 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP)) 5753 return 0; 5754 5755 { 5756 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14); 5757 struct udphdr *udp; 5758 5759 if (ip->protocol != IPPROTO_UDP) 5760 return 0; 5761 5762 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); 5763 if (ntohs(udp->dest) != 67) 5764 return 0; 5765 5766 offset = (u8 *)udp + 8 - skb->data; 5767 length = skb->len - offset; 5768 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); 5769 } 5770 5771 return 0; 5772 } 5773 5774 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5775 { 5776 struct e1000_adapter *adapter = tx_ring->adapter; 5777 5778 netif_stop_queue(adapter->netdev); 5779 /* Herbert's original patch had: 5780 * smp_mb__after_netif_stop_queue(); 5781 * but since that doesn't exist yet, just open code it. 5782 */ 5783 smp_mb(); 5784 5785 /* We need to check again in a case another CPU has just 5786 * made room available. 5787 */ 5788 if (e1000_desc_unused(tx_ring) < size) 5789 return -EBUSY; 5790 5791 /* A reprieve! */ 5792 netif_start_queue(adapter->netdev); 5793 ++adapter->restart_queue; 5794 return 0; 5795 } 5796 5797 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5798 { 5799 BUG_ON(size > tx_ring->count); 5800 5801 if (e1000_desc_unused(tx_ring) >= size) 5802 return 0; 5803 return __e1000_maybe_stop_tx(tx_ring, size); 5804 } 5805 5806 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, 5807 struct net_device *netdev) 5808 { 5809 struct e1000_adapter *adapter = netdev_priv(netdev); 5810 struct e1000_ring *tx_ring = adapter->tx_ring; 5811 unsigned int first; 5812 unsigned int tx_flags = 0; 5813 unsigned int len = skb_headlen(skb); 5814 unsigned int nr_frags; 5815 unsigned int mss; 5816 int count = 0; 5817 int tso; 5818 unsigned int f; 5819 __be16 protocol = vlan_get_protocol(skb); 5820 5821 if (test_bit(__E1000_DOWN, &adapter->state)) { 5822 dev_kfree_skb_any(skb); 5823 return NETDEV_TX_OK; 5824 } 5825 5826 if (skb->len <= 0) { 5827 dev_kfree_skb_any(skb); 5828 return NETDEV_TX_OK; 5829 } 5830 5831 /* The minimum packet size with TCTL.PSP set is 17 bytes so 5832 * pad skb in order to meet this minimum size requirement 5833 */ 5834 if (skb_put_padto(skb, 17)) 5835 return NETDEV_TX_OK; 5836 5837 mss = skb_shinfo(skb)->gso_size; 5838 if (mss) { 5839 u8 hdr_len; 5840 5841 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data 5842 * points to just header, pull a few bytes of payload from 5843 * frags into skb->data 5844 */ 5845 hdr_len = skb_tcp_all_headers(skb); 5846 /* we do this workaround for ES2LAN, but it is un-necessary, 5847 * avoiding it could save a lot of cycles 5848 */ 5849 if (skb->data_len && (hdr_len == len)) { 5850 unsigned int pull_size; 5851 5852 pull_size = min_t(unsigned int, 4, skb->data_len); 5853 if (!__pskb_pull_tail(skb, pull_size)) { 5854 e_err("__pskb_pull_tail failed.\n"); 5855 dev_kfree_skb_any(skb); 5856 return NETDEV_TX_OK; 5857 } 5858 len = skb_headlen(skb); 5859 } 5860 } 5861 5862 /* reserve a descriptor for the offload context */ 5863 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) 5864 count++; 5865 count++; 5866 5867 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit); 5868 5869 nr_frags = skb_shinfo(skb)->nr_frags; 5870 for (f = 0; f < nr_frags; f++) 5871 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]), 5872 adapter->tx_fifo_limit); 5873 5874 if (adapter->hw.mac.tx_pkt_filtering) 5875 e1000_transfer_dhcp_info(adapter, skb); 5876 5877 /* need: count + 2 desc gap to keep tail from touching 5878 * head, otherwise try next time 5879 */ 5880 if (e1000_maybe_stop_tx(tx_ring, count + 2)) 5881 return NETDEV_TX_BUSY; 5882 5883 if (skb_vlan_tag_present(skb)) { 5884 tx_flags |= E1000_TX_FLAGS_VLAN; 5885 tx_flags |= (skb_vlan_tag_get(skb) << 5886 E1000_TX_FLAGS_VLAN_SHIFT); 5887 } 5888 5889 first = tx_ring->next_to_use; 5890 5891 tso = e1000_tso(tx_ring, skb, protocol); 5892 if (tso < 0) { 5893 dev_kfree_skb_any(skb); 5894 return NETDEV_TX_OK; 5895 } 5896 5897 if (tso) 5898 tx_flags |= E1000_TX_FLAGS_TSO; 5899 else if (e1000_tx_csum(tx_ring, skb, protocol)) 5900 tx_flags |= E1000_TX_FLAGS_CSUM; 5901 5902 /* Old method was to assume IPv4 packet by default if TSO was enabled. 5903 * 82571 hardware supports TSO capabilities for IPv6 as well... 5904 * no longer assume, we must. 5905 */ 5906 if (protocol == htons(ETH_P_IP)) 5907 tx_flags |= E1000_TX_FLAGS_IPV4; 5908 5909 if (unlikely(skb->no_fcs)) 5910 tx_flags |= E1000_TX_FLAGS_NO_FCS; 5911 5912 /* if count is 0 then mapping error has occurred */ 5913 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit, 5914 nr_frags); 5915 if (count) { 5916 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 5917 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) { 5918 if (!adapter->tx_hwtstamp_skb) { 5919 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5920 tx_flags |= E1000_TX_FLAGS_HWTSTAMP; 5921 adapter->tx_hwtstamp_skb = skb_get(skb); 5922 adapter->tx_hwtstamp_start = jiffies; 5923 schedule_work(&adapter->tx_hwtstamp_work); 5924 } else { 5925 adapter->tx_hwtstamp_skipped++; 5926 } 5927 } 5928 5929 skb_tx_timestamp(skb); 5930 5931 netdev_sent_queue(netdev, skb->len); 5932 e1000_tx_queue(tx_ring, tx_flags, count); 5933 /* Make sure there is space in the ring for the next send. */ 5934 e1000_maybe_stop_tx(tx_ring, 5935 ((MAX_SKB_FRAGS + 1) * 5936 DIV_ROUND_UP(PAGE_SIZE, 5937 adapter->tx_fifo_limit) + 4)); 5938 5939 if (!netdev_xmit_more() || 5940 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) { 5941 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 5942 e1000e_update_tdt_wa(tx_ring, 5943 tx_ring->next_to_use); 5944 else 5945 writel(tx_ring->next_to_use, tx_ring->tail); 5946 } 5947 } else { 5948 dev_kfree_skb_any(skb); 5949 tx_ring->buffer_info[first].time_stamp = 0; 5950 tx_ring->next_to_use = first; 5951 } 5952 5953 return NETDEV_TX_OK; 5954 } 5955 5956 /** 5957 * e1000_tx_timeout - Respond to a Tx Hang 5958 * @netdev: network interface device structure 5959 * @txqueue: index of the hung queue (unused) 5960 **/ 5961 static void e1000_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 5962 { 5963 struct e1000_adapter *adapter = netdev_priv(netdev); 5964 5965 /* Do the reset outside of interrupt context */ 5966 adapter->tx_timeout_count++; 5967 schedule_work(&adapter->reset_task); 5968 } 5969 5970 static void e1000_reset_task(struct work_struct *work) 5971 { 5972 struct e1000_adapter *adapter; 5973 adapter = container_of(work, struct e1000_adapter, reset_task); 5974 5975 rtnl_lock(); 5976 /* don't run the task if already down */ 5977 if (test_bit(__E1000_DOWN, &adapter->state)) { 5978 rtnl_unlock(); 5979 return; 5980 } 5981 5982 if (!(adapter->flags & FLAG_RESTART_NOW)) { 5983 e1000e_dump(adapter); 5984 e_err("Reset adapter unexpectedly\n"); 5985 } 5986 e1000e_reinit_locked(adapter); 5987 rtnl_unlock(); 5988 } 5989 5990 /** 5991 * e1000e_get_stats64 - Get System Network Statistics 5992 * @netdev: network interface device structure 5993 * @stats: rtnl_link_stats64 pointer 5994 * 5995 * Returns the address of the device statistics structure. 5996 **/ 5997 void e1000e_get_stats64(struct net_device *netdev, 5998 struct rtnl_link_stats64 *stats) 5999 { 6000 struct e1000_adapter *adapter = netdev_priv(netdev); 6001 6002 spin_lock(&adapter->stats64_lock); 6003 e1000e_update_stats(adapter); 6004 /* Fill out the OS statistics structure */ 6005 stats->rx_bytes = adapter->stats.gorc; 6006 stats->rx_packets = adapter->stats.gprc; 6007 stats->tx_bytes = adapter->stats.gotc; 6008 stats->tx_packets = adapter->stats.gptc; 6009 stats->multicast = adapter->stats.mprc; 6010 stats->collisions = adapter->stats.colc; 6011 6012 /* Rx Errors */ 6013 6014 /* RLEC on some newer hardware can be incorrect so build 6015 * our own version based on RUC and ROC 6016 */ 6017 stats->rx_errors = adapter->stats.rxerrc + 6018 adapter->stats.crcerrs + adapter->stats.algnerrc + 6019 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 6020 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc; 6021 stats->rx_crc_errors = adapter->stats.crcerrs; 6022 stats->rx_frame_errors = adapter->stats.algnerrc; 6023 stats->rx_missed_errors = adapter->stats.mpc; 6024 6025 /* Tx Errors */ 6026 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol; 6027 stats->tx_aborted_errors = adapter->stats.ecol; 6028 stats->tx_window_errors = adapter->stats.latecol; 6029 stats->tx_carrier_errors = adapter->stats.tncrs; 6030 6031 /* Tx Dropped needs to be maintained elsewhere */ 6032 6033 spin_unlock(&adapter->stats64_lock); 6034 } 6035 6036 /** 6037 * e1000_change_mtu - Change the Maximum Transfer Unit 6038 * @netdev: network interface device structure 6039 * @new_mtu: new value for maximum frame size 6040 * 6041 * Returns 0 on success, negative on failure 6042 **/ 6043 static int e1000_change_mtu(struct net_device *netdev, int new_mtu) 6044 { 6045 struct e1000_adapter *adapter = netdev_priv(netdev); 6046 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 6047 6048 /* Jumbo frame support */ 6049 if ((new_mtu > ETH_DATA_LEN) && 6050 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { 6051 e_err("Jumbo Frames not supported.\n"); 6052 return -EINVAL; 6053 } 6054 6055 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 6056 if ((adapter->hw.mac.type >= e1000_pch2lan) && 6057 !(adapter->flags2 & FLAG2_CRC_STRIPPING) && 6058 (new_mtu > ETH_DATA_LEN)) { 6059 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n"); 6060 return -EINVAL; 6061 } 6062 6063 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 6064 usleep_range(1000, 1100); 6065 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ 6066 adapter->max_frame_size = max_frame; 6067 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6068 netdev->mtu, new_mtu); 6069 WRITE_ONCE(netdev->mtu, new_mtu); 6070 6071 pm_runtime_get_sync(netdev->dev.parent); 6072 6073 if (netif_running(netdev)) 6074 e1000e_down(adapter, true); 6075 6076 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN 6077 * means we reserve 2 more, this pushes us to allocate from the next 6078 * larger slab size. 6079 * i.e. RXBUFFER_2048 --> size-4096 slab 6080 * However with the new *_jumbo_rx* routines, jumbo receives will use 6081 * fragmented skbs 6082 */ 6083 6084 if (max_frame <= 2048) 6085 adapter->rx_buffer_len = 2048; 6086 else 6087 adapter->rx_buffer_len = 4096; 6088 6089 /* adjust allocation if LPE protects us, and we aren't using SBP */ 6090 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) 6091 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 6092 6093 if (netif_running(netdev)) 6094 e1000e_up(adapter); 6095 else 6096 e1000e_reset(adapter); 6097 6098 pm_runtime_put_sync(netdev->dev.parent); 6099 6100 clear_bit(__E1000_RESETTING, &adapter->state); 6101 6102 return 0; 6103 } 6104 6105 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6106 { 6107 struct e1000_adapter *adapter = netdev_priv(netdev); 6108 struct mii_ioctl_data *data = if_mii(ifr); 6109 6110 if (adapter->hw.phy.media_type != e1000_media_type_copper) 6111 return -EOPNOTSUPP; 6112 6113 switch (cmd) { 6114 case SIOCGMIIPHY: 6115 data->phy_id = adapter->hw.phy.addr; 6116 break; 6117 case SIOCGMIIREG: 6118 e1000_phy_read_status(adapter); 6119 6120 switch (data->reg_num & 0x1F) { 6121 case MII_BMCR: 6122 data->val_out = adapter->phy_regs.bmcr; 6123 break; 6124 case MII_BMSR: 6125 data->val_out = adapter->phy_regs.bmsr; 6126 break; 6127 case MII_PHYSID1: 6128 data->val_out = (adapter->hw.phy.id >> 16); 6129 break; 6130 case MII_PHYSID2: 6131 data->val_out = (adapter->hw.phy.id & 0xFFFF); 6132 break; 6133 case MII_ADVERTISE: 6134 data->val_out = adapter->phy_regs.advertise; 6135 break; 6136 case MII_LPA: 6137 data->val_out = adapter->phy_regs.lpa; 6138 break; 6139 case MII_EXPANSION: 6140 data->val_out = adapter->phy_regs.expansion; 6141 break; 6142 case MII_CTRL1000: 6143 data->val_out = adapter->phy_regs.ctrl1000; 6144 break; 6145 case MII_STAT1000: 6146 data->val_out = adapter->phy_regs.stat1000; 6147 break; 6148 case MII_ESTATUS: 6149 data->val_out = adapter->phy_regs.estatus; 6150 break; 6151 default: 6152 return -EIO; 6153 } 6154 break; 6155 case SIOCSMIIREG: 6156 default: 6157 return -EOPNOTSUPP; 6158 } 6159 return 0; 6160 } 6161 6162 /** 6163 * e1000e_hwtstamp_set - control hardware time stamping 6164 * @netdev: network interface device structure 6165 * @config: timestamp configuration 6166 * @extack: netlink extended ACK report 6167 * 6168 * Outgoing time stamping can be enabled and disabled. Play nice and 6169 * disable it when requested, although it shouldn't cause any overhead 6170 * when no packet needs it. At most one packet in the queue may be 6171 * marked for time stamping, otherwise it would be impossible to tell 6172 * for sure to which packet the hardware time stamp belongs. 6173 * 6174 * Incoming time stamping has to be configured via the hardware filters. 6175 * Not all combinations are supported, in particular event type has to be 6176 * specified. Matching the kind of event packet is not supported, with the 6177 * exception of "all V2 events regardless of level 2 or 4". 6178 **/ 6179 static int e1000e_hwtstamp_set(struct net_device *netdev, 6180 struct kernel_hwtstamp_config *config, 6181 struct netlink_ext_ack *extack) 6182 { 6183 struct e1000_adapter *adapter = netdev_priv(netdev); 6184 int ret_val; 6185 6186 ret_val = e1000e_config_hwtstamp(adapter, config, extack); 6187 if (ret_val) 6188 return ret_val; 6189 6190 switch (config->rx_filter) { 6191 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 6192 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 6193 case HWTSTAMP_FILTER_PTP_V2_SYNC: 6194 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 6195 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 6196 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 6197 /* With V2 type filters which specify a Sync or Delay Request, 6198 * Path Delay Request/Response messages are also time stamped 6199 * by hardware so notify the caller the requested packets plus 6200 * some others are time stamped. 6201 */ 6202 config->rx_filter = HWTSTAMP_FILTER_SOME; 6203 break; 6204 default: 6205 break; 6206 } 6207 6208 return 0; 6209 } 6210 6211 static int e1000e_hwtstamp_get(struct net_device *netdev, 6212 struct kernel_hwtstamp_config *kernel_config) 6213 { 6214 struct e1000_adapter *adapter = netdev_priv(netdev); 6215 6216 *kernel_config = adapter->hwtstamp_config; 6217 6218 return 0; 6219 } 6220 6221 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) 6222 { 6223 struct e1000_hw *hw = &adapter->hw; 6224 u32 i, mac_reg, wuc; 6225 u16 phy_reg, wuc_enable; 6226 int retval; 6227 6228 /* copy MAC RARs to PHY RARs */ 6229 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 6230 6231 retval = hw->phy.ops.acquire(hw); 6232 if (retval) { 6233 e_err("Could not acquire PHY\n"); 6234 return retval; 6235 } 6236 6237 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */ 6238 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6239 if (retval) 6240 goto release; 6241 6242 /* copy MAC MTA to PHY MTA - only needed for pchlan */ 6243 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 6244 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 6245 hw->phy.ops.write_reg_page(hw, BM_MTA(i), 6246 (u16)(mac_reg & 0xFFFF)); 6247 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1, 6248 (u16)((mac_reg >> 16) & 0xFFFF)); 6249 } 6250 6251 /* configure PHY Rx Control register */ 6252 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); 6253 mac_reg = er32(RCTL); 6254 if (mac_reg & E1000_RCTL_UPE) 6255 phy_reg |= BM_RCTL_UPE; 6256 if (mac_reg & E1000_RCTL_MPE) 6257 phy_reg |= BM_RCTL_MPE; 6258 phy_reg &= ~(BM_RCTL_MO_MASK); 6259 if (mac_reg & E1000_RCTL_MO_3) 6260 phy_reg |= (FIELD_GET(E1000_RCTL_MO_3, mac_reg) 6261 << BM_RCTL_MO_SHIFT); 6262 if (mac_reg & E1000_RCTL_BAM) 6263 phy_reg |= BM_RCTL_BAM; 6264 if (mac_reg & E1000_RCTL_PMCF) 6265 phy_reg |= BM_RCTL_PMCF; 6266 mac_reg = er32(CTRL); 6267 if (mac_reg & E1000_CTRL_RFCE) 6268 phy_reg |= BM_RCTL_RFCE; 6269 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg); 6270 6271 wuc = E1000_WUC_PME_EN; 6272 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC)) 6273 wuc |= E1000_WUC_APME; 6274 6275 /* enable PHY wakeup in MAC register */ 6276 ew32(WUFC, wufc); 6277 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME | 6278 E1000_WUC_PME_STATUS | wuc)); 6279 6280 /* configure and enable PHY wakeup in PHY registers */ 6281 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc); 6282 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc); 6283 6284 /* activate PHY wakeup */ 6285 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 6286 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6287 if (retval) 6288 e_err("Could not set PHY Host Wakeup bit\n"); 6289 release: 6290 hw->phy.ops.release(hw); 6291 6292 return retval; 6293 } 6294 6295 static void e1000e_flush_lpic(struct pci_dev *pdev) 6296 { 6297 struct net_device *netdev = pci_get_drvdata(pdev); 6298 struct e1000_adapter *adapter = netdev_priv(netdev); 6299 struct e1000_hw *hw = &adapter->hw; 6300 u32 ret_val; 6301 6302 pm_runtime_get_sync(netdev->dev.parent); 6303 6304 ret_val = hw->phy.ops.acquire(hw); 6305 if (ret_val) 6306 goto fl_out; 6307 6308 pr_info("EEE TX LPI TIMER: %08X\n", 6309 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT); 6310 6311 hw->phy.ops.release(hw); 6312 6313 fl_out: 6314 pm_runtime_put_sync(netdev->dev.parent); 6315 } 6316 6317 /* S0ix implementation */ 6318 static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter) 6319 { 6320 struct e1000_hw *hw = &adapter->hw; 6321 u32 mac_data; 6322 u16 phy_data; 6323 6324 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID && 6325 hw->mac.type >= e1000_pch_adp) { 6326 /* Request ME configure the device for S0ix */ 6327 mac_data = er32(H2ME); 6328 mac_data |= E1000_H2ME_START_DPG; 6329 mac_data &= ~E1000_H2ME_EXIT_DPG; 6330 trace_e1000e_trace_mac_register(mac_data); 6331 ew32(H2ME, mac_data); 6332 } else { 6333 /* Request driver configure the device to S0ix */ 6334 /* Disable the periodic inband message, 6335 * don't request PCIe clock in K1 page770_17[10:9] = 10b 6336 */ 6337 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6338 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ; 6339 phy_data |= BIT(10); 6340 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6341 6342 /* Make sure we don't exit K1 every time a new packet arrives 6343 * 772_29[5] = 1 CS_Mode_Stay_In_K1 6344 */ 6345 e1e_rphy(hw, I217_CGFREG, &phy_data); 6346 phy_data |= BIT(5); 6347 e1e_wphy(hw, I217_CGFREG, phy_data); 6348 6349 /* Change the MAC/PHY interface to SMBus 6350 * Force the SMBus in PHY page769_23[0] = 1 6351 * Force the SMBus in MAC CTRL_EXT[11] = 1 6352 */ 6353 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6354 phy_data |= CV_SMB_CTRL_FORCE_SMBUS; 6355 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6356 mac_data = er32(CTRL_EXT); 6357 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS; 6358 ew32(CTRL_EXT, mac_data); 6359 6360 /* DFT control: PHY bit: page769_20[0] = 1 6361 * page769_20[7] - PHY PLL stop 6362 * page769_20[8] - PHY go to the electrical idle 6363 * page769_20[9] - PHY serdes disable 6364 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1 6365 */ 6366 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data); 6367 phy_data |= BIT(0); 6368 phy_data |= BIT(7); 6369 phy_data |= BIT(8); 6370 phy_data |= BIT(9); 6371 e1e_wphy(hw, I82579_DFT_CTRL, phy_data); 6372 6373 mac_data = er32(EXTCNF_CTRL); 6374 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 6375 ew32(EXTCNF_CTRL, mac_data); 6376 6377 /* Disable disconnected cable conditioning for Power Gating */ 6378 mac_data = er32(DPGFR); 6379 mac_data |= BIT(2); 6380 ew32(DPGFR, mac_data); 6381 6382 /* Enable the Dynamic Clock Gating in the DMA and MAC */ 6383 mac_data = er32(CTRL_EXT); 6384 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN; 6385 ew32(CTRL_EXT, mac_data); 6386 } 6387 6388 /* Enable the Dynamic Power Gating in the MAC */ 6389 mac_data = er32(FEXTNVM7); 6390 mac_data |= BIT(22); 6391 ew32(FEXTNVM7, mac_data); 6392 6393 /* Don't wake from dynamic Power Gating with clock request */ 6394 mac_data = er32(FEXTNVM12); 6395 mac_data |= BIT(12); 6396 ew32(FEXTNVM12, mac_data); 6397 6398 /* Ungate PGCB clock */ 6399 mac_data = er32(FEXTNVM9); 6400 mac_data &= ~BIT(28); 6401 ew32(FEXTNVM9, mac_data); 6402 6403 /* Enable K1 off to enable mPHY Power Gating */ 6404 mac_data = er32(FEXTNVM6); 6405 mac_data |= BIT(31); 6406 ew32(FEXTNVM6, mac_data); 6407 6408 /* Enable mPHY power gating for any link and speed */ 6409 mac_data = er32(FEXTNVM8); 6410 mac_data |= BIT(9); 6411 ew32(FEXTNVM8, mac_data); 6412 6413 /* No MAC DPG gating SLP_S0 in modern standby 6414 * Switch the logic of the lanphypc to use PMC counter 6415 */ 6416 mac_data = er32(FEXTNVM5); 6417 mac_data |= BIT(7); 6418 ew32(FEXTNVM5, mac_data); 6419 6420 /* Disable the time synchronization clock */ 6421 mac_data = er32(FEXTNVM7); 6422 mac_data |= BIT(31); 6423 mac_data &= ~BIT(0); 6424 ew32(FEXTNVM7, mac_data); 6425 6426 /* Dynamic Power Gating Enable */ 6427 mac_data = er32(CTRL_EXT); 6428 mac_data |= BIT(3); 6429 ew32(CTRL_EXT, mac_data); 6430 6431 /* Check MAC Tx/Rx packet buffer pointers. 6432 * Reset MAC Tx/Rx packet buffer pointers to suppress any 6433 * pending traffic indication that would prevent power gating. 6434 */ 6435 mac_data = er32(TDFH); 6436 if (mac_data) 6437 ew32(TDFH, 0); 6438 mac_data = er32(TDFT); 6439 if (mac_data) 6440 ew32(TDFT, 0); 6441 mac_data = er32(TDFHS); 6442 if (mac_data) 6443 ew32(TDFHS, 0); 6444 mac_data = er32(TDFTS); 6445 if (mac_data) 6446 ew32(TDFTS, 0); 6447 mac_data = er32(TDFPC); 6448 if (mac_data) 6449 ew32(TDFPC, 0); 6450 mac_data = er32(RDFH); 6451 if (mac_data) 6452 ew32(RDFH, 0); 6453 mac_data = er32(RDFT); 6454 if (mac_data) 6455 ew32(RDFT, 0); 6456 mac_data = er32(RDFHS); 6457 if (mac_data) 6458 ew32(RDFHS, 0); 6459 mac_data = er32(RDFTS); 6460 if (mac_data) 6461 ew32(RDFTS, 0); 6462 mac_data = er32(RDFPC); 6463 if (mac_data) 6464 ew32(RDFPC, 0); 6465 } 6466 6467 static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter) 6468 { 6469 struct e1000_hw *hw = &adapter->hw; 6470 bool firmware_bug = false; 6471 u32 mac_data; 6472 u16 phy_data; 6473 u32 i = 0; 6474 6475 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID && 6476 hw->mac.type >= e1000_pch_adp) { 6477 /* Keep the GPT clock enabled for CSME */ 6478 mac_data = er32(FEXTNVM); 6479 mac_data |= BIT(3); 6480 ew32(FEXTNVM, mac_data); 6481 /* Request ME unconfigure the device from S0ix */ 6482 mac_data = er32(H2ME); 6483 mac_data &= ~E1000_H2ME_START_DPG; 6484 mac_data |= E1000_H2ME_EXIT_DPG; 6485 trace_e1000e_trace_mac_register(mac_data); 6486 ew32(H2ME, mac_data); 6487 6488 /* Poll up to 2.5 seconds for ME to unconfigure DPG. 6489 * If this takes more than 1 second, show a warning indicating a 6490 * firmware bug 6491 */ 6492 while (!(er32(EXFWSM) & E1000_EXFWSM_DPG_EXIT_DONE)) { 6493 if (i > 100 && !firmware_bug) 6494 firmware_bug = true; 6495 6496 if (i++ == 250) { 6497 e_dbg("Timeout (firmware bug): %d msec\n", 6498 i * 10); 6499 break; 6500 } 6501 6502 usleep_range(10000, 11000); 6503 } 6504 if (firmware_bug) 6505 e_warn("DPG_EXIT_DONE took %d msec. This is a firmware bug\n", 6506 i * 10); 6507 else 6508 e_dbg("DPG_EXIT_DONE cleared after %d msec\n", i * 10); 6509 } else { 6510 /* Request driver unconfigure the device from S0ix */ 6511 6512 /* Cancel disable disconnected cable conditioning 6513 * for Power Gating 6514 */ 6515 mac_data = er32(DPGFR); 6516 mac_data &= ~BIT(2); 6517 ew32(DPGFR, mac_data); 6518 6519 /* Disable the Dynamic Clock Gating in the DMA and MAC */ 6520 mac_data = er32(CTRL_EXT); 6521 mac_data &= 0xFFF7FFFF; 6522 ew32(CTRL_EXT, mac_data); 6523 6524 /* Enable the periodic inband message, 6525 * Request PCIe clock in K1 page770_17[10:9] =01b 6526 */ 6527 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6528 phy_data &= 0xFBFF; 6529 phy_data |= HV_PM_CTRL_K1_CLK_REQ; 6530 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6531 6532 /* Return back configuration 6533 * 772_29[5] = 0 CS_Mode_Stay_In_K1 6534 */ 6535 e1e_rphy(hw, I217_CGFREG, &phy_data); 6536 phy_data &= 0xFFDF; 6537 e1e_wphy(hw, I217_CGFREG, phy_data); 6538 6539 /* Change the MAC/PHY interface to Kumeran 6540 * Unforce the SMBus in PHY page769_23[0] = 0 6541 * Unforce the SMBus in MAC CTRL_EXT[11] = 0 6542 */ 6543 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6544 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS; 6545 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6546 mac_data = er32(CTRL_EXT); 6547 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS; 6548 ew32(CTRL_EXT, mac_data); 6549 } 6550 6551 /* Disable Dynamic Power Gating */ 6552 mac_data = er32(CTRL_EXT); 6553 mac_data &= 0xFFFFFFF7; 6554 ew32(CTRL_EXT, mac_data); 6555 6556 /* Enable the time synchronization clock */ 6557 mac_data = er32(FEXTNVM7); 6558 mac_data &= ~BIT(31); 6559 mac_data |= BIT(0); 6560 ew32(FEXTNVM7, mac_data); 6561 6562 /* Disable the Dynamic Power Gating in the MAC */ 6563 mac_data = er32(FEXTNVM7); 6564 mac_data &= 0xFFBFFFFF; 6565 ew32(FEXTNVM7, mac_data); 6566 6567 /* Disable mPHY power gating for any link and speed */ 6568 mac_data = er32(FEXTNVM8); 6569 mac_data &= ~BIT(9); 6570 ew32(FEXTNVM8, mac_data); 6571 6572 /* Disable K1 off */ 6573 mac_data = er32(FEXTNVM6); 6574 mac_data &= ~BIT(31); 6575 ew32(FEXTNVM6, mac_data); 6576 6577 /* Disable Ungate PGCB clock */ 6578 mac_data = er32(FEXTNVM9); 6579 mac_data |= BIT(28); 6580 ew32(FEXTNVM9, mac_data); 6581 6582 /* Cancel not waking from dynamic 6583 * Power Gating with clock request 6584 */ 6585 mac_data = er32(FEXTNVM12); 6586 mac_data &= ~BIT(12); 6587 ew32(FEXTNVM12, mac_data); 6588 6589 /* Revert the lanphypc logic to use the internal Gbe counter 6590 * and not the PMC counter 6591 */ 6592 mac_data = er32(FEXTNVM5); 6593 mac_data &= 0xFFFFFF7F; 6594 ew32(FEXTNVM5, mac_data); 6595 } 6596 6597 static int e1000e_pm_freeze(struct device *dev) 6598 { 6599 struct net_device *netdev = dev_get_drvdata(dev); 6600 struct e1000_adapter *adapter = netdev_priv(netdev); 6601 bool present; 6602 6603 rtnl_lock(); 6604 6605 present = netif_device_present(netdev); 6606 netif_device_detach(netdev); 6607 6608 if (present && netif_running(netdev)) { 6609 int count = E1000_CHECK_RESET_COUNT; 6610 6611 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6612 usleep_range(10000, 11000); 6613 6614 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6615 6616 /* Quiesce the device without resetting the hardware */ 6617 e1000e_down(adapter, false); 6618 e1000_free_irq(adapter); 6619 } 6620 rtnl_unlock(); 6621 6622 e1000e_reset_interrupt_capability(adapter); 6623 6624 /* Allow time for pending master requests to run */ 6625 e1000e_disable_pcie_master(&adapter->hw); 6626 6627 return 0; 6628 } 6629 6630 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime) 6631 { 6632 struct net_device *netdev = pci_get_drvdata(pdev); 6633 struct e1000_adapter *adapter = netdev_priv(netdev); 6634 struct e1000_hw *hw = &adapter->hw; 6635 u32 ctrl, ctrl_ext, rctl, status, wufc; 6636 int retval = 0; 6637 6638 /* Runtime suspend should only enable wakeup for link changes */ 6639 if (runtime) 6640 wufc = E1000_WUFC_LNKC; 6641 else if (device_may_wakeup(&pdev->dev)) 6642 wufc = adapter->wol; 6643 else 6644 wufc = 0; 6645 6646 status = er32(STATUS); 6647 if (status & E1000_STATUS_LU) 6648 wufc &= ~E1000_WUFC_LNKC; 6649 6650 if (wufc) { 6651 e1000_setup_rctl(adapter); 6652 e1000e_set_rx_mode(netdev); 6653 6654 /* turn on all-multi mode if wake on multicast is enabled */ 6655 if (wufc & E1000_WUFC_MC) { 6656 rctl = er32(RCTL); 6657 rctl |= E1000_RCTL_MPE; 6658 ew32(RCTL, rctl); 6659 } 6660 6661 ctrl = er32(CTRL); 6662 ctrl |= E1000_CTRL_ADVD3WUC; 6663 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) 6664 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; 6665 ew32(CTRL, ctrl); 6666 6667 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 6668 adapter->hw.phy.media_type == 6669 e1000_media_type_internal_serdes) { 6670 /* keep the laser running in D3 */ 6671 ctrl_ext = er32(CTRL_EXT); 6672 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 6673 ew32(CTRL_EXT, ctrl_ext); 6674 } 6675 6676 if (!runtime) 6677 e1000e_power_up_phy(adapter); 6678 6679 if (adapter->flags & FLAG_IS_ICH) 6680 e1000_suspend_workarounds_ich8lan(&adapter->hw); 6681 6682 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6683 /* enable wakeup by the PHY */ 6684 retval = e1000_init_phy_wakeup(adapter, wufc); 6685 if (retval) { 6686 e_err("Failed to enable wakeup\n"); 6687 goto skip_phy_configurations; 6688 } 6689 } else { 6690 /* enable wakeup by the MAC */ 6691 ew32(WUFC, wufc); 6692 ew32(WUC, E1000_WUC_PME_EN); 6693 } 6694 } else { 6695 ew32(WUC, 0); 6696 ew32(WUFC, 0); 6697 6698 e1000_power_down_phy(adapter); 6699 } 6700 6701 if (adapter->hw.phy.type == e1000_phy_igp_3) { 6702 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 6703 } else if (hw->mac.type >= e1000_pch_lpt) { 6704 if (wufc && !(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) { 6705 /* ULP does not support wake from unicast, multicast 6706 * or broadcast. 6707 */ 6708 retval = e1000_enable_ulp_lpt_lp(hw, !runtime); 6709 if (retval) { 6710 e_err("Failed to enable ULP\n"); 6711 goto skip_phy_configurations; 6712 } 6713 } 6714 } 6715 6716 /* Ensure that the appropriate bits are set in LPI_CTRL 6717 * for EEE in Sx 6718 */ 6719 if ((hw->phy.type >= e1000_phy_i217) && 6720 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) { 6721 u16 lpi_ctrl = 0; 6722 6723 retval = hw->phy.ops.acquire(hw); 6724 if (!retval) { 6725 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL, 6726 &lpi_ctrl); 6727 if (!retval) { 6728 if (adapter->eee_advert & 6729 hw->dev_spec.ich8lan.eee_lp_ability & 6730 I82579_EEE_100_SUPPORTED) 6731 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 6732 if (adapter->eee_advert & 6733 hw->dev_spec.ich8lan.eee_lp_ability & 6734 I82579_EEE_1000_SUPPORTED) 6735 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 6736 6737 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL, 6738 lpi_ctrl); 6739 } 6740 } 6741 hw->phy.ops.release(hw); 6742 } 6743 6744 skip_phy_configurations: 6745 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6746 * would have already happened in close and is redundant. 6747 */ 6748 e1000e_release_hw_control(adapter); 6749 6750 pci_clear_master(pdev); 6751 6752 /* The pci-e switch on some quad port adapters will report a 6753 * correctable error when the MAC transitions from D0 to D3. To 6754 * prevent this we need to mask off the correctable errors on the 6755 * downstream port of the pci-e switch. 6756 * 6757 * We don't have the associated upstream bridge while assigning 6758 * the PCI device into guest. For example, the KVM on power is 6759 * one of the cases. 6760 */ 6761 if (adapter->flags & FLAG_IS_QUAD_PORT) { 6762 struct pci_dev *us_dev = pdev->bus->self; 6763 u16 devctl; 6764 6765 if (!us_dev) 6766 return 0; 6767 6768 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl); 6769 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, 6770 (devctl & ~PCI_EXP_DEVCTL_CERE)); 6771 6772 pci_save_state(pdev); 6773 pci_prepare_to_sleep(pdev); 6774 6775 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl); 6776 } 6777 6778 return 0; 6779 } 6780 6781 /** 6782 * __e1000e_disable_aspm - Disable ASPM states 6783 * @pdev: pointer to PCI device struct 6784 * @state: bit-mask of ASPM states to disable 6785 * @locked: indication if this context holds pci_bus_sem locked. 6786 * 6787 * Some devices *must* have certain ASPM states disabled per hardware errata. 6788 **/ 6789 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked) 6790 { 6791 struct pci_dev *parent = pdev->bus->self; 6792 u16 aspm_dis_mask = 0; 6793 u16 pdev_aspmc, parent_aspmc; 6794 6795 switch (state) { 6796 case PCIE_LINK_STATE_L0S: 6797 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1: 6798 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S; 6799 fallthrough; /* can't have L1 without L0s */ 6800 case PCIE_LINK_STATE_L1: 6801 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1; 6802 break; 6803 default: 6804 return; 6805 } 6806 6807 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6808 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6809 6810 if (parent) { 6811 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, 6812 &parent_aspmc); 6813 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6814 } 6815 6816 /* Nothing to do if the ASPM states to be disabled already are */ 6817 if (!(pdev_aspmc & aspm_dis_mask) && 6818 (!parent || !(parent_aspmc & aspm_dis_mask))) 6819 return; 6820 6821 dev_info(&pdev->dev, "Disabling ASPM %s %s\n", 6822 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ? 6823 "L0s" : "", 6824 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ? 6825 "L1" : ""); 6826 6827 #ifdef CONFIG_PCIEASPM 6828 if (locked) 6829 pci_disable_link_state_locked(pdev, state); 6830 else 6831 pci_disable_link_state(pdev, state); 6832 6833 /* Double-check ASPM control. If not disabled by the above, the 6834 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is 6835 * not enabled); override by writing PCI config space directly. 6836 */ 6837 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6838 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6839 6840 if (!(aspm_dis_mask & pdev_aspmc)) 6841 return; 6842 #endif 6843 6844 /* Both device and parent should have the same ASPM setting. 6845 * Disable ASPM in downstream component first and then upstream. 6846 */ 6847 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask); 6848 6849 if (parent) 6850 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 6851 aspm_dis_mask); 6852 } 6853 6854 /** 6855 * e1000e_disable_aspm - Disable ASPM states. 6856 * @pdev: pointer to PCI device struct 6857 * @state: bit-mask of ASPM states to disable 6858 * 6859 * This function acquires the pci_bus_sem! 6860 * Some devices *must* have certain ASPM states disabled per hardware errata. 6861 **/ 6862 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state) 6863 { 6864 __e1000e_disable_aspm(pdev, state, 0); 6865 } 6866 6867 /** 6868 * e1000e_disable_aspm_locked - Disable ASPM states. 6869 * @pdev: pointer to PCI device struct 6870 * @state: bit-mask of ASPM states to disable 6871 * 6872 * This function must be called with pci_bus_sem acquired! 6873 * Some devices *must* have certain ASPM states disabled per hardware errata. 6874 **/ 6875 static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state) 6876 { 6877 __e1000e_disable_aspm(pdev, state, 1); 6878 } 6879 6880 static int e1000e_pm_thaw(struct device *dev) 6881 { 6882 struct net_device *netdev = dev_get_drvdata(dev); 6883 struct e1000_adapter *adapter = netdev_priv(netdev); 6884 int rc = 0; 6885 6886 e1000e_set_interrupt_capability(adapter); 6887 6888 rtnl_lock(); 6889 if (netif_running(netdev)) { 6890 rc = e1000_request_irq(adapter); 6891 if (rc) 6892 goto err_irq; 6893 6894 e1000e_up(adapter); 6895 } 6896 6897 netif_device_attach(netdev); 6898 err_irq: 6899 rtnl_unlock(); 6900 6901 return rc; 6902 } 6903 6904 static int __e1000_resume(struct pci_dev *pdev) 6905 { 6906 struct net_device *netdev = pci_get_drvdata(pdev); 6907 struct e1000_adapter *adapter = netdev_priv(netdev); 6908 struct e1000_hw *hw = &adapter->hw; 6909 u16 aspm_disable_flag = 0; 6910 6911 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6912 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6913 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6914 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6915 if (aspm_disable_flag) 6916 e1000e_disable_aspm(pdev, aspm_disable_flag); 6917 6918 pci_set_master(pdev); 6919 6920 if (hw->mac.type >= e1000_pch2lan) 6921 e1000_resume_workarounds_pchlan(&adapter->hw); 6922 6923 e1000e_power_up_phy(adapter); 6924 6925 /* report the system wakeup cause from S3/S4 */ 6926 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6927 u16 phy_data; 6928 6929 e1e_rphy(&adapter->hw, BM_WUS, &phy_data); 6930 if (phy_data) { 6931 e_info("PHY Wakeup cause - %s\n", 6932 phy_data & E1000_WUS_EX ? "Unicast Packet" : 6933 phy_data & E1000_WUS_MC ? "Multicast Packet" : 6934 phy_data & E1000_WUS_BC ? "Broadcast Packet" : 6935 phy_data & E1000_WUS_MAG ? "Magic Packet" : 6936 phy_data & E1000_WUS_LNKC ? 6937 "Link Status Change" : "other"); 6938 } 6939 e1e_wphy(&adapter->hw, BM_WUS, ~0); 6940 } else { 6941 u32 wus = er32(WUS); 6942 6943 if (wus) { 6944 e_info("MAC Wakeup cause - %s\n", 6945 wus & E1000_WUS_EX ? "Unicast Packet" : 6946 wus & E1000_WUS_MC ? "Multicast Packet" : 6947 wus & E1000_WUS_BC ? "Broadcast Packet" : 6948 wus & E1000_WUS_MAG ? "Magic Packet" : 6949 wus & E1000_WUS_LNKC ? "Link Status Change" : 6950 "other"); 6951 } 6952 ew32(WUS, ~0); 6953 } 6954 6955 e1000e_reset(adapter); 6956 6957 e1000_init_manageability_pt(adapter); 6958 6959 /* If the controller has AMT, do not set DRV_LOAD until the interface 6960 * is up. For all other cases, let the f/w know that the h/w is now 6961 * under the control of the driver. 6962 */ 6963 if (!(adapter->flags & FLAG_HAS_AMT)) 6964 e1000e_get_hw_control(adapter); 6965 6966 return 0; 6967 } 6968 6969 static int e1000e_pm_prepare(struct device *dev) 6970 { 6971 return pm_runtime_suspended(dev) && 6972 pm_suspend_via_firmware(); 6973 } 6974 6975 static int e1000e_pm_suspend(struct device *dev) 6976 { 6977 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6978 struct e1000_adapter *adapter = netdev_priv(netdev); 6979 struct pci_dev *pdev = to_pci_dev(dev); 6980 int rc; 6981 6982 e1000e_flush_lpic(pdev); 6983 6984 e1000e_pm_freeze(dev); 6985 6986 rc = __e1000_shutdown(pdev, false); 6987 if (!rc) { 6988 /* Introduce S0ix implementation */ 6989 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS) 6990 e1000e_s0ix_entry_flow(adapter); 6991 } 6992 6993 return 0; 6994 } 6995 6996 static int e1000e_pm_resume(struct device *dev) 6997 { 6998 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6999 struct e1000_adapter *adapter = netdev_priv(netdev); 7000 struct pci_dev *pdev = to_pci_dev(dev); 7001 int rc; 7002 7003 /* Introduce S0ix implementation */ 7004 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS) 7005 e1000e_s0ix_exit_flow(adapter); 7006 7007 rc = __e1000_resume(pdev); 7008 if (rc) 7009 return rc; 7010 7011 return e1000e_pm_thaw(dev); 7012 } 7013 7014 static __maybe_unused int e1000e_pm_runtime_idle(struct device *dev) 7015 { 7016 struct net_device *netdev = dev_get_drvdata(dev); 7017 struct e1000_adapter *adapter = netdev_priv(netdev); 7018 u16 eee_lp; 7019 7020 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability; 7021 7022 if (!e1000e_has_link(adapter)) { 7023 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp; 7024 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC); 7025 } 7026 7027 return -EBUSY; 7028 } 7029 7030 static int e1000e_pm_runtime_resume(struct device *dev) 7031 { 7032 struct pci_dev *pdev = to_pci_dev(dev); 7033 struct net_device *netdev = pci_get_drvdata(pdev); 7034 struct e1000_adapter *adapter = netdev_priv(netdev); 7035 int rc; 7036 7037 pdev->pme_poll = true; 7038 7039 rc = __e1000_resume(pdev); 7040 if (rc) 7041 return rc; 7042 7043 if (netdev->flags & IFF_UP) 7044 e1000e_up(adapter); 7045 7046 return rc; 7047 } 7048 7049 static int e1000e_pm_runtime_suspend(struct device *dev) 7050 { 7051 struct pci_dev *pdev = to_pci_dev(dev); 7052 struct net_device *netdev = pci_get_drvdata(pdev); 7053 struct e1000_adapter *adapter = netdev_priv(netdev); 7054 7055 if (netdev->flags & IFF_UP) { 7056 int count = E1000_CHECK_RESET_COUNT; 7057 7058 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 7059 usleep_range(10000, 11000); 7060 7061 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 7062 7063 /* Down the device without resetting the hardware */ 7064 e1000e_down(adapter, false); 7065 } 7066 7067 if (__e1000_shutdown(pdev, true)) { 7068 e1000e_pm_runtime_resume(dev); 7069 return -EBUSY; 7070 } 7071 7072 return 0; 7073 } 7074 7075 static void e1000_shutdown(struct pci_dev *pdev) 7076 { 7077 e1000e_flush_lpic(pdev); 7078 7079 e1000e_pm_freeze(&pdev->dev); 7080 7081 __e1000_shutdown(pdev, false); 7082 } 7083 7084 #ifdef CONFIG_NET_POLL_CONTROLLER 7085 7086 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data) 7087 { 7088 struct net_device *netdev = data; 7089 struct e1000_adapter *adapter = netdev_priv(netdev); 7090 7091 if (adapter->msix_entries) { 7092 int vector, msix_irq; 7093 7094 vector = 0; 7095 msix_irq = adapter->msix_entries[vector].vector; 7096 if (disable_hardirq(msix_irq)) 7097 e1000_intr_msix_rx(msix_irq, netdev); 7098 enable_irq(msix_irq); 7099 7100 vector++; 7101 msix_irq = adapter->msix_entries[vector].vector; 7102 if (disable_hardirq(msix_irq)) 7103 e1000_intr_msix_tx(msix_irq, netdev); 7104 enable_irq(msix_irq); 7105 7106 vector++; 7107 msix_irq = adapter->msix_entries[vector].vector; 7108 if (disable_hardirq(msix_irq)) 7109 e1000_msix_other(msix_irq, netdev); 7110 enable_irq(msix_irq); 7111 } 7112 7113 return IRQ_HANDLED; 7114 } 7115 7116 /** 7117 * e1000_netpoll 7118 * @netdev: network interface device structure 7119 * 7120 * Polling 'interrupt' - used by things like netconsole to send skbs 7121 * without having to re-enable interrupts. It's not called while 7122 * the interrupt routine is executing. 7123 */ 7124 static void e1000_netpoll(struct net_device *netdev) 7125 { 7126 struct e1000_adapter *adapter = netdev_priv(netdev); 7127 7128 switch (adapter->int_mode) { 7129 case E1000E_INT_MODE_MSIX: 7130 e1000_intr_msix(adapter->pdev->irq, netdev); 7131 break; 7132 case E1000E_INT_MODE_MSI: 7133 if (disable_hardirq(adapter->pdev->irq)) 7134 e1000_intr_msi(adapter->pdev->irq, netdev); 7135 enable_irq(adapter->pdev->irq); 7136 break; 7137 default: /* E1000E_INT_MODE_LEGACY */ 7138 if (disable_hardirq(adapter->pdev->irq)) 7139 e1000_intr(adapter->pdev->irq, netdev); 7140 enable_irq(adapter->pdev->irq); 7141 break; 7142 } 7143 } 7144 #endif 7145 7146 /** 7147 * e1000_io_error_detected - called when PCI error is detected 7148 * @pdev: Pointer to PCI device 7149 * @state: The current pci connection state 7150 * 7151 * This function is called after a PCI bus error affecting 7152 * this device has been detected. 7153 */ 7154 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, 7155 pci_channel_state_t state) 7156 { 7157 e1000e_pm_freeze(&pdev->dev); 7158 7159 if (state == pci_channel_io_perm_failure) 7160 return PCI_ERS_RESULT_DISCONNECT; 7161 7162 pci_disable_device(pdev); 7163 7164 /* Request a slot reset. */ 7165 return PCI_ERS_RESULT_NEED_RESET; 7166 } 7167 7168 /** 7169 * e1000_io_slot_reset - called after the pci bus has been reset. 7170 * @pdev: Pointer to PCI device 7171 * 7172 * Restart the card from scratch, as if from a cold-boot. Implementation 7173 * resembles the first-half of the e1000e_pm_resume routine. 7174 */ 7175 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) 7176 { 7177 struct net_device *netdev = pci_get_drvdata(pdev); 7178 struct e1000_adapter *adapter = netdev_priv(netdev); 7179 struct e1000_hw *hw = &adapter->hw; 7180 u16 aspm_disable_flag = 0; 7181 int err; 7182 pci_ers_result_t result; 7183 7184 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 7185 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7186 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 7187 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7188 if (aspm_disable_flag) 7189 e1000e_disable_aspm_locked(pdev, aspm_disable_flag); 7190 7191 err = pci_enable_device_mem(pdev); 7192 if (err) { 7193 dev_err(&pdev->dev, 7194 "Cannot re-enable PCI device after reset.\n"); 7195 result = PCI_ERS_RESULT_DISCONNECT; 7196 } else { 7197 pci_restore_state(pdev); 7198 pci_set_master(pdev); 7199 7200 pci_enable_wake(pdev, PCI_D3hot, 0); 7201 pci_enable_wake(pdev, PCI_D3cold, 0); 7202 7203 e1000e_reset(adapter); 7204 ew32(WUS, ~0); 7205 result = PCI_ERS_RESULT_RECOVERED; 7206 } 7207 7208 return result; 7209 } 7210 7211 /** 7212 * e1000_io_resume - called when traffic can start flowing again. 7213 * @pdev: Pointer to PCI device 7214 * 7215 * This callback is called when the error recovery driver tells us that 7216 * its OK to resume normal operation. Implementation resembles the 7217 * second-half of the e1000e_pm_resume routine. 7218 */ 7219 static void e1000_io_resume(struct pci_dev *pdev) 7220 { 7221 struct net_device *netdev = pci_get_drvdata(pdev); 7222 struct e1000_adapter *adapter = netdev_priv(netdev); 7223 7224 e1000_init_manageability_pt(adapter); 7225 7226 e1000e_pm_thaw(&pdev->dev); 7227 7228 /* If the controller has AMT, do not set DRV_LOAD until the interface 7229 * is up. For all other cases, let the f/w know that the h/w is now 7230 * under the control of the driver. 7231 */ 7232 if (!(adapter->flags & FLAG_HAS_AMT)) 7233 e1000e_get_hw_control(adapter); 7234 } 7235 7236 static void e1000_print_device_info(struct e1000_adapter *adapter) 7237 { 7238 struct e1000_hw *hw = &adapter->hw; 7239 struct net_device *netdev = adapter->netdev; 7240 u32 ret_val; 7241 u8 pba_str[E1000_PBANUM_LENGTH]; 7242 7243 /* print bus type/speed/width info */ 7244 e_info("(PCI Express:2.5GT/s:%s) %pM\n", 7245 /* bus width */ 7246 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 7247 "Width x1"), 7248 /* MAC address */ 7249 netdev->dev_addr); 7250 e_info("Intel(R) PRO/%s Network Connection\n", 7251 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); 7252 ret_val = e1000_read_pba_string_generic(hw, pba_str, 7253 E1000_PBANUM_LENGTH); 7254 if (ret_val) 7255 strscpy((char *)pba_str, "Unknown", sizeof(pba_str)); 7256 e_info("MAC: %d, PHY: %d, PBA No: %s\n", 7257 hw->mac.type, hw->phy.type, pba_str); 7258 } 7259 7260 static void e1000_eeprom_checks(struct e1000_adapter *adapter) 7261 { 7262 struct e1000_hw *hw = &adapter->hw; 7263 int ret_val; 7264 u16 buf = 0; 7265 7266 if (hw->mac.type != e1000_82573) 7267 return; 7268 7269 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); 7270 le16_to_cpus(&buf); 7271 if (!ret_val && (!(buf & BIT(0)))) { 7272 /* Deep Smart Power Down (DSPD) */ 7273 dev_warn(&adapter->pdev->dev, 7274 "Warning: detected DSPD enabled in EEPROM\n"); 7275 } 7276 } 7277 7278 static netdev_features_t e1000_fix_features(struct net_device *netdev, 7279 netdev_features_t features) 7280 { 7281 struct e1000_adapter *adapter = netdev_priv(netdev); 7282 struct e1000_hw *hw = &adapter->hw; 7283 7284 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 7285 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN)) 7286 features &= ~NETIF_F_RXFCS; 7287 7288 /* Since there is no support for separate Rx/Tx vlan accel 7289 * enable/disable make sure Tx flag is always in same state as Rx. 7290 */ 7291 if (features & NETIF_F_HW_VLAN_CTAG_RX) 7292 features |= NETIF_F_HW_VLAN_CTAG_TX; 7293 else 7294 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 7295 7296 return features; 7297 } 7298 7299 static int e1000_set_features(struct net_device *netdev, 7300 netdev_features_t features) 7301 { 7302 struct e1000_adapter *adapter = netdev_priv(netdev); 7303 netdev_features_t changed = features ^ netdev->features; 7304 7305 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) 7306 adapter->flags |= FLAG_TSO_FORCE; 7307 7308 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 7309 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS | 7310 NETIF_F_RXALL))) 7311 return 0; 7312 7313 if (changed & NETIF_F_RXFCS) { 7314 if (features & NETIF_F_RXFCS) { 7315 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7316 } else { 7317 /* We need to take it back to defaults, which might mean 7318 * stripping is still disabled at the adapter level. 7319 */ 7320 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING) 7321 adapter->flags2 |= FLAG2_CRC_STRIPPING; 7322 else 7323 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7324 } 7325 } 7326 7327 netdev->features = features; 7328 7329 if (netif_running(netdev)) 7330 e1000e_reinit_locked(adapter); 7331 else 7332 e1000e_reset(adapter); 7333 7334 return 1; 7335 } 7336 7337 static const struct net_device_ops e1000e_netdev_ops = { 7338 .ndo_open = e1000e_open, 7339 .ndo_stop = e1000e_close, 7340 .ndo_start_xmit = e1000_xmit_frame, 7341 .ndo_get_stats64 = e1000e_get_stats64, 7342 .ndo_set_rx_mode = e1000e_set_rx_mode, 7343 .ndo_set_mac_address = e1000_set_mac, 7344 .ndo_change_mtu = e1000_change_mtu, 7345 .ndo_eth_ioctl = e1000_ioctl, 7346 .ndo_tx_timeout = e1000_tx_timeout, 7347 .ndo_validate_addr = eth_validate_addr, 7348 7349 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, 7350 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, 7351 #ifdef CONFIG_NET_POLL_CONTROLLER 7352 .ndo_poll_controller = e1000_netpoll, 7353 #endif 7354 .ndo_set_features = e1000_set_features, 7355 .ndo_fix_features = e1000_fix_features, 7356 .ndo_features_check = passthru_features_check, 7357 .ndo_hwtstamp_get = e1000e_hwtstamp_get, 7358 .ndo_hwtstamp_set = e1000e_hwtstamp_set, 7359 }; 7360 7361 /** 7362 * e1000_probe - Device Initialization Routine 7363 * @pdev: PCI device information struct 7364 * @ent: entry in e1000_pci_tbl 7365 * 7366 * Returns 0 on success, negative on failure 7367 * 7368 * e1000_probe initializes an adapter identified by a pci_dev structure. 7369 * The OS initialization, configuring of the adapter private structure, 7370 * and a hardware reset occur. 7371 **/ 7372 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 7373 { 7374 struct net_device *netdev; 7375 struct e1000_adapter *adapter; 7376 struct e1000_hw *hw; 7377 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; 7378 resource_size_t mmio_start, mmio_len; 7379 resource_size_t flash_start, flash_len; 7380 static int cards_found; 7381 u16 aspm_disable_flag = 0; 7382 u16 eeprom_data = 0; 7383 u16 eeprom_apme_mask = E1000_EEPROM_APME; 7384 int bars, i, err; 7385 s32 ret_val = 0; 7386 7387 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S) 7388 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7389 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1) 7390 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7391 if (aspm_disable_flag) 7392 e1000e_disable_aspm(pdev, aspm_disable_flag); 7393 7394 err = pci_enable_device_mem(pdev); 7395 if (err) 7396 return err; 7397 7398 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 7399 if (err) { 7400 dev_err(&pdev->dev, 7401 "No usable DMA configuration, aborting\n"); 7402 goto err_dma; 7403 } 7404 7405 bars = pci_select_bars(pdev, IORESOURCE_MEM); 7406 err = pci_request_selected_regions_exclusive(pdev, bars, 7407 e1000e_driver_name); 7408 if (err) 7409 goto err_pci_reg; 7410 7411 pci_set_master(pdev); 7412 /* PCI config space info */ 7413 err = pci_save_state(pdev); 7414 if (err) 7415 goto err_alloc_etherdev; 7416 7417 err = -ENOMEM; 7418 netdev = alloc_etherdev(sizeof(struct e1000_adapter)); 7419 if (!netdev) 7420 goto err_alloc_etherdev; 7421 7422 SET_NETDEV_DEV(netdev, &pdev->dev); 7423 7424 netdev->irq = pdev->irq; 7425 7426 pci_set_drvdata(pdev, netdev); 7427 adapter = netdev_priv(netdev); 7428 hw = &adapter->hw; 7429 adapter->netdev = netdev; 7430 adapter->pdev = pdev; 7431 adapter->ei = ei; 7432 adapter->pba = ei->pba; 7433 adapter->flags = ei->flags; 7434 adapter->flags2 = ei->flags2; 7435 adapter->hw.adapter = adapter; 7436 adapter->hw.mac.type = ei->mac; 7437 adapter->max_hw_frame_size = ei->max_hw_frame_size; 7438 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 7439 7440 mmio_start = pci_resource_start(pdev, 0); 7441 mmio_len = pci_resource_len(pdev, 0); 7442 7443 err = -EIO; 7444 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 7445 if (!adapter->hw.hw_addr) 7446 goto err_ioremap; 7447 7448 if ((adapter->flags & FLAG_HAS_FLASH) && 7449 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) && 7450 (hw->mac.type < e1000_pch_spt)) { 7451 flash_start = pci_resource_start(pdev, 1); 7452 flash_len = pci_resource_len(pdev, 1); 7453 adapter->hw.flash_address = ioremap(flash_start, flash_len); 7454 if (!adapter->hw.flash_address) 7455 goto err_flashmap; 7456 } 7457 7458 /* Set default EEE advertisement */ 7459 if (adapter->flags2 & FLAG2_HAS_EEE) 7460 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 7461 7462 /* construct the net_device struct */ 7463 netdev->netdev_ops = &e1000e_netdev_ops; 7464 e1000e_set_ethtool_ops(netdev); 7465 netdev->watchdog_timeo = 5 * HZ; 7466 netif_napi_add(netdev, &adapter->napi, e1000e_poll); 7467 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 7468 7469 netdev->mem_start = mmio_start; 7470 netdev->mem_end = mmio_start + mmio_len; 7471 7472 adapter->bd_number = cards_found++; 7473 7474 e1000e_check_options(adapter); 7475 7476 /* setup adapter struct */ 7477 err = e1000_sw_init(adapter); 7478 if (err) 7479 goto err_sw_init; 7480 7481 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 7482 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 7483 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 7484 7485 err = ei->get_variants(adapter); 7486 if (err) 7487 goto err_hw_init; 7488 7489 if ((adapter->flags & FLAG_IS_ICH) && 7490 (adapter->flags & FLAG_READ_ONLY_NVM) && 7491 (hw->mac.type < e1000_pch_spt)) 7492 e1000e_write_protect_nvm_ich8lan(&adapter->hw); 7493 7494 hw->mac.ops.get_bus_info(&adapter->hw); 7495 7496 adapter->hw.phy.autoneg_wait_to_complete = 0; 7497 7498 /* Copper options */ 7499 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 7500 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7501 adapter->hw.phy.disable_polarity_correction = 0; 7502 adapter->hw.phy.ms_type = e1000_ms_hw_default; 7503 } 7504 7505 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 7506 dev_info(&pdev->dev, 7507 "PHY reset is blocked due to SOL/IDER session.\n"); 7508 7509 /* Set initial default active device features */ 7510 netdev->features = (NETIF_F_SG | 7511 NETIF_F_HW_VLAN_CTAG_RX | 7512 NETIF_F_HW_VLAN_CTAG_TX | 7513 NETIF_F_TSO | 7514 NETIF_F_TSO6 | 7515 NETIF_F_RXHASH | 7516 NETIF_F_RXCSUM | 7517 NETIF_F_HW_CSUM); 7518 7519 /* disable TSO for pcie and 10/100 speeds to avoid 7520 * some hardware issues and for i219 to fix transfer 7521 * speed being capped at 60% 7522 */ 7523 if (!(adapter->flags & FLAG_TSO_FORCE)) { 7524 switch (adapter->link_speed) { 7525 case SPEED_10: 7526 case SPEED_100: 7527 e_info("10/100 speed: disabling TSO\n"); 7528 netdev->features &= ~NETIF_F_TSO; 7529 netdev->features &= ~NETIF_F_TSO6; 7530 break; 7531 case SPEED_1000: 7532 netdev->features |= NETIF_F_TSO; 7533 netdev->features |= NETIF_F_TSO6; 7534 break; 7535 default: 7536 /* oops */ 7537 break; 7538 } 7539 if (hw->mac.type == e1000_pch_spt) { 7540 netdev->features &= ~NETIF_F_TSO; 7541 netdev->features &= ~NETIF_F_TSO6; 7542 } 7543 } 7544 7545 /* Set user-changeable features (subset of all device features) */ 7546 netdev->hw_features = netdev->features; 7547 netdev->hw_features |= NETIF_F_RXFCS; 7548 netdev->priv_flags |= IFF_SUPP_NOFCS; 7549 netdev->hw_features |= NETIF_F_RXALL; 7550 7551 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) 7552 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7553 7554 netdev->vlan_features |= (NETIF_F_SG | 7555 NETIF_F_TSO | 7556 NETIF_F_TSO6 | 7557 NETIF_F_HW_CSUM); 7558 7559 netdev->priv_flags |= IFF_UNICAST_FLT; 7560 7561 netdev->features |= NETIF_F_HIGHDMA; 7562 netdev->vlan_features |= NETIF_F_HIGHDMA; 7563 7564 /* MTU range: 68 - max_hw_frame_size */ 7565 netdev->min_mtu = ETH_MIN_MTU; 7566 netdev->max_mtu = adapter->max_hw_frame_size - 7567 (VLAN_ETH_HLEN + ETH_FCS_LEN); 7568 7569 if (e1000e_enable_mng_pass_thru(&adapter->hw)) 7570 adapter->flags |= FLAG_MNG_PT_ENABLED; 7571 7572 /* before reading the NVM, reset the controller to 7573 * put the device in a known good starting state 7574 */ 7575 adapter->hw.mac.ops.reset_hw(&adapter->hw); 7576 7577 /* systems with ASPM and others may see the checksum fail on the first 7578 * attempt. Let's give it a few tries 7579 */ 7580 for (i = 0;; i++) { 7581 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) 7582 break; 7583 if (i == 2) { 7584 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 7585 err = -EIO; 7586 goto err_eeprom; 7587 } 7588 } 7589 7590 e1000_eeprom_checks(adapter); 7591 7592 /* copy the MAC address */ 7593 if (e1000e_read_mac_addr(&adapter->hw)) 7594 dev_err(&pdev->dev, 7595 "NVM Read Error while reading MAC address\n"); 7596 7597 eth_hw_addr_set(netdev, adapter->hw.mac.addr); 7598 7599 if (!is_valid_ether_addr(netdev->dev_addr)) { 7600 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n", 7601 netdev->dev_addr); 7602 err = -EIO; 7603 goto err_eeprom; 7604 } 7605 7606 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0); 7607 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0); 7608 7609 INIT_WORK(&adapter->reset_task, e1000_reset_task); 7610 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); 7611 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround); 7612 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task); 7613 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang); 7614 7615 /* Initialize link parameters. User can change them with ethtool */ 7616 adapter->hw.mac.autoneg = 1; 7617 adapter->fc_autoneg = true; 7618 adapter->hw.fc.requested_mode = e1000_fc_default; 7619 adapter->hw.fc.current_mode = e1000_fc_default; 7620 adapter->hw.phy.autoneg_advertised = 0x2f; 7621 7622 /* Initial Wake on LAN setting - If APM wake is enabled in 7623 * the EEPROM, enable the ACPI Magic Packet filter 7624 */ 7625 if (adapter->flags & FLAG_APME_IN_WUC) { 7626 /* APME bit in EEPROM is mapped to WUC.APME */ 7627 eeprom_data = er32(WUC); 7628 eeprom_apme_mask = E1000_WUC_APME; 7629 if ((hw->mac.type > e1000_ich10lan) && 7630 (eeprom_data & E1000_WUC_PHY_WAKE)) 7631 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP; 7632 } else if (adapter->flags & FLAG_APME_IN_CTRL3) { 7633 if (adapter->flags & FLAG_APME_CHECK_PORT_B && 7634 (adapter->hw.bus.func == 1)) 7635 ret_val = e1000_read_nvm(&adapter->hw, 7636 NVM_INIT_CONTROL3_PORT_B, 7637 1, &eeprom_data); 7638 else 7639 ret_val = e1000_read_nvm(&adapter->hw, 7640 NVM_INIT_CONTROL3_PORT_A, 7641 1, &eeprom_data); 7642 } 7643 7644 /* fetch WoL from EEPROM */ 7645 if (ret_val) 7646 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val); 7647 else if (eeprom_data & eeprom_apme_mask) 7648 adapter->eeprom_wol |= E1000_WUFC_MAG; 7649 7650 /* now that we have the eeprom settings, apply the special cases 7651 * where the eeprom may be wrong or the board simply won't support 7652 * wake on lan on a particular port 7653 */ 7654 if (!(adapter->flags & FLAG_HAS_WOL)) 7655 adapter->eeprom_wol = 0; 7656 7657 /* initialize the wol settings based on the eeprom settings */ 7658 adapter->wol = adapter->eeprom_wol; 7659 7660 /* make sure adapter isn't asleep if manageability is enabled */ 7661 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) || 7662 (hw->mac.ops.check_mng_mode(hw))) 7663 device_wakeup_enable(&pdev->dev); 7664 7665 /* save off EEPROM version number */ 7666 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); 7667 7668 if (ret_val) { 7669 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val); 7670 adapter->eeprom_vers = 0; 7671 } 7672 7673 /* init PTP hardware clock */ 7674 e1000e_ptp_init(adapter); 7675 7676 if (hw->mac.type >= e1000_pch_mtp) 7677 adapter->flags2 |= FLAG2_DISABLE_K1; 7678 7679 /* reset the hardware with the new settings */ 7680 e1000e_reset(adapter); 7681 7682 /* If the controller has AMT, do not set DRV_LOAD until the interface 7683 * is up. For all other cases, let the f/w know that the h/w is now 7684 * under the control of the driver. 7685 */ 7686 if (!(adapter->flags & FLAG_HAS_AMT)) 7687 e1000e_get_hw_control(adapter); 7688 7689 if (hw->mac.type >= e1000_pch_cnp) 7690 adapter->flags2 |= FLAG2_ENABLE_S0IX_FLOWS; 7691 7692 strscpy(netdev->name, "eth%d", sizeof(netdev->name)); 7693 err = register_netdev(netdev); 7694 if (err) 7695 goto err_register; 7696 7697 /* carrier off reporting is important to ethtool even BEFORE open */ 7698 netif_carrier_off(netdev); 7699 7700 e1000_print_device_info(adapter); 7701 7702 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_SMART_PREPARE); 7703 7704 if (pci_dev_run_wake(pdev)) 7705 pm_runtime_put_noidle(&pdev->dev); 7706 7707 return 0; 7708 7709 err_register: 7710 if (!(adapter->flags & FLAG_HAS_AMT)) 7711 e1000e_release_hw_control(adapter); 7712 err_eeprom: 7713 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw)) 7714 e1000_phy_hw_reset(&adapter->hw); 7715 err_hw_init: 7716 kfree(adapter->tx_ring); 7717 kfree(adapter->rx_ring); 7718 err_sw_init: 7719 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt)) 7720 iounmap(adapter->hw.flash_address); 7721 e1000e_reset_interrupt_capability(adapter); 7722 err_flashmap: 7723 iounmap(adapter->hw.hw_addr); 7724 err_ioremap: 7725 free_netdev(netdev); 7726 err_alloc_etherdev: 7727 pci_release_mem_regions(pdev); 7728 err_pci_reg: 7729 err_dma: 7730 pci_disable_device(pdev); 7731 return err; 7732 } 7733 7734 /** 7735 * e1000_remove - Device Removal Routine 7736 * @pdev: PCI device information struct 7737 * 7738 * e1000_remove is called by the PCI subsystem to alert the driver 7739 * that it should release a PCI device. This could be caused by a 7740 * Hot-Plug event, or because the driver is going to be removed from 7741 * memory. 7742 **/ 7743 static void e1000_remove(struct pci_dev *pdev) 7744 { 7745 struct net_device *netdev = pci_get_drvdata(pdev); 7746 struct e1000_adapter *adapter = netdev_priv(netdev); 7747 7748 e1000e_ptp_remove(adapter); 7749 7750 /* The timers may be rescheduled, so explicitly disable them 7751 * from being rescheduled. 7752 */ 7753 set_bit(__E1000_DOWN, &adapter->state); 7754 timer_delete_sync(&adapter->watchdog_timer); 7755 timer_delete_sync(&adapter->phy_info_timer); 7756 7757 cancel_work_sync(&adapter->reset_task); 7758 cancel_work_sync(&adapter->watchdog_task); 7759 cancel_work_sync(&adapter->downshift_task); 7760 cancel_work_sync(&adapter->update_phy_task); 7761 cancel_work_sync(&adapter->print_hang_task); 7762 7763 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 7764 cancel_work_sync(&adapter->tx_hwtstamp_work); 7765 if (adapter->tx_hwtstamp_skb) { 7766 dev_consume_skb_any(adapter->tx_hwtstamp_skb); 7767 adapter->tx_hwtstamp_skb = NULL; 7768 } 7769 } 7770 7771 unregister_netdev(netdev); 7772 7773 if (pci_dev_run_wake(pdev)) 7774 pm_runtime_get_noresume(&pdev->dev); 7775 7776 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7777 * would have already happened in close and is redundant. 7778 */ 7779 e1000e_release_hw_control(adapter); 7780 7781 e1000e_reset_interrupt_capability(adapter); 7782 kfree(adapter->tx_ring); 7783 kfree(adapter->rx_ring); 7784 7785 iounmap(adapter->hw.hw_addr); 7786 if ((adapter->hw.flash_address) && 7787 (adapter->hw.mac.type < e1000_pch_spt)) 7788 iounmap(adapter->hw.flash_address); 7789 pci_release_mem_regions(pdev); 7790 7791 free_netdev(netdev); 7792 7793 pci_disable_device(pdev); 7794 } 7795 7796 /* PCI Error Recovery (ERS) */ 7797 static const struct pci_error_handlers e1000_err_handler = { 7798 .error_detected = e1000_io_error_detected, 7799 .slot_reset = e1000_io_slot_reset, 7800 .resume = e1000_io_resume, 7801 }; 7802 7803 static const struct pci_device_id e1000_pci_tbl[] = { 7804 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, 7805 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, 7806 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, 7807 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), 7808 board_82571 }, 7809 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 }, 7810 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 }, 7811 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 }, 7812 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 }, 7813 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 }, 7814 7815 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 }, 7816 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 }, 7817 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 }, 7818 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 }, 7819 7820 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 }, 7821 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 }, 7822 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, 7823 7824 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 }, 7825 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 }, 7826 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 }, 7827 7828 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), 7829 board_80003es2lan }, 7830 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), 7831 board_80003es2lan }, 7832 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), 7833 board_80003es2lan }, 7834 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), 7835 board_80003es2lan }, 7836 7837 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan }, 7838 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan }, 7839 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan }, 7840 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan }, 7841 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan }, 7842 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan }, 7843 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan }, 7844 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan }, 7845 7846 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan }, 7847 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan }, 7848 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan }, 7849 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan }, 7850 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan }, 7851 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan }, 7852 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan }, 7853 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan }, 7854 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan }, 7855 7856 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan }, 7857 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, 7858 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, 7859 7860 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, 7861 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, 7862 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan }, 7863 7864 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan }, 7865 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan }, 7866 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, 7867 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, 7868 7869 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan }, 7870 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan }, 7871 7872 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt }, 7873 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt }, 7874 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt }, 7875 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt }, 7876 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt }, 7877 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt }, 7878 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt }, 7879 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt }, 7880 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt }, 7881 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt }, 7882 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt }, 7883 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt }, 7884 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt }, 7885 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt }, 7886 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt }, 7887 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt }, 7888 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt }, 7889 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp }, 7890 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp }, 7891 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp }, 7892 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp }, 7893 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp }, 7894 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp }, 7895 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp }, 7896 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp }, 7897 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10), board_pch_cnp }, 7898 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10), board_pch_cnp }, 7899 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11), board_pch_cnp }, 7900 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp }, 7901 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt }, 7902 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt }, 7903 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_tgp }, 7904 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_tgp }, 7905 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_tgp }, 7906 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_tgp }, 7907 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_tgp }, 7908 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_tgp }, 7909 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM23), board_pch_adp }, 7910 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V23), board_pch_adp }, 7911 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_adp }, 7912 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_adp }, 7913 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_adp }, 7914 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_adp }, 7915 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM22), board_pch_adp }, 7916 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V22), board_pch_adp }, 7917 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM19), board_pch_adp }, 7918 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V19), board_pch_adp }, 7919 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18), board_pch_mtp }, 7920 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18), board_pch_mtp }, 7921 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM20), board_pch_mtp }, 7922 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V20), board_pch_mtp }, 7923 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM21), board_pch_mtp }, 7924 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V21), board_pch_mtp }, 7925 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_LM24), board_pch_mtp }, 7926 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_V24), board_pch_mtp }, 7927 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM25), board_pch_mtp }, 7928 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V25), board_pch_mtp }, 7929 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM26), board_pch_mtp }, 7930 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V26), board_pch_mtp }, 7931 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM27), board_pch_mtp }, 7932 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V27), board_pch_mtp }, 7933 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_LM29), board_pch_mtp }, 7934 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_V29), board_pch_mtp }, 7935 7936 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ 7937 }; 7938 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); 7939 7940 static const struct dev_pm_ops e1000e_pm_ops = { 7941 .prepare = e1000e_pm_prepare, 7942 .suspend = e1000e_pm_suspend, 7943 .resume = e1000e_pm_resume, 7944 .freeze = e1000e_pm_freeze, 7945 .thaw = e1000e_pm_thaw, 7946 .poweroff = e1000e_pm_suspend, 7947 .restore = e1000e_pm_resume, 7948 RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume, 7949 e1000e_pm_runtime_idle) 7950 }; 7951 7952 /* PCI Device API Driver */ 7953 static struct pci_driver e1000_driver = { 7954 .name = e1000e_driver_name, 7955 .id_table = e1000_pci_tbl, 7956 .probe = e1000_probe, 7957 .remove = e1000_remove, 7958 .driver.pm = pm_ptr(&e1000e_pm_ops), 7959 .shutdown = e1000_shutdown, 7960 .err_handler = &e1000_err_handler 7961 }; 7962 7963 /** 7964 * e1000_init_module - Driver Registration Routine 7965 * 7966 * e1000_init_module is the first routine called when the driver is 7967 * loaded. All it does is register with the PCI subsystem. 7968 **/ 7969 static int __init e1000_init_module(void) 7970 { 7971 pr_info("Intel(R) PRO/1000 Network Driver\n"); 7972 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n"); 7973 7974 return pci_register_driver(&e1000_driver); 7975 } 7976 module_init(e1000_init_module); 7977 7978 /** 7979 * e1000_exit_module - Driver Exit Cleanup Routine 7980 * 7981 * e1000_exit_module is called just before the driver is removed 7982 * from memory. 7983 **/ 7984 static void __exit e1000_exit_module(void) 7985 { 7986 pci_unregister_driver(&e1000_driver); 7987 } 7988 module_exit(e1000_exit_module); 7989 7990 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver"); 7991 MODULE_LICENSE("GPL v2"); 7992 7993 /* netdev.c */ 7994