1 /*
2 * Copyright © 2006-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/debugfs.h>
25 #include <linux/iopoll.h>
26 #include <linux/time.h>
27
28 #include <drm/drm_fixed.h>
29 #include <drm/drm_print.h>
30
31 #include "hsw_ips.h"
32 #include "i915_reg.h"
33 #include "intel_atomic.h"
34 #include "intel_audio.h"
35 #include "intel_cdclk.h"
36 #include "intel_crtc.h"
37 #include "intel_dbuf_bw.h"
38 #include "intel_de.h"
39 #include "intel_display_regs.h"
40 #include "intel_display_types.h"
41 #include "intel_display_utils.h"
42 #include "intel_display_wa.h"
43 #include "intel_dram.h"
44 #include "intel_mchbar_regs.h"
45 #include "intel_pci_config.h"
46 #include "intel_pcode.h"
47 #include "intel_plane.h"
48 #include "intel_psr.h"
49 #include "intel_step.h"
50 #include "intel_vdsc.h"
51 #include "skl_watermark.h"
52 #include "skl_watermark_regs.h"
53 #include "vlv_clock.h"
54 #include "vlv_dsi.h"
55 #include "vlv_sideband.h"
56
57 /**
58 * DOC: CDCLK / RAWCLK
59 *
60 * The display engine uses several different clocks to do its work. There
61 * are two main clocks involved that aren't directly related to the actual
62 * pixel clock or any symbol/bit clock of the actual output port. These
63 * are the core display clock (CDCLK) and RAWCLK.
64 *
65 * CDCLK clocks most of the display pipe logic, and thus its frequency
66 * must be high enough to support the rate at which pixels are flowing
67 * through the pipes. Downscaling must also be accounted as that increases
68 * the effective pixel rate.
69 *
70 * On several platforms the CDCLK frequency can be changed dynamically
71 * to minimize power consumption for a given display configuration.
72 * Typically changes to the CDCLK frequency require all the display pipes
73 * to be shut down while the frequency is being changed.
74 *
75 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
76 * DMC will not change the active CDCLK frequency however, so that part
77 * will still be performed by the driver directly.
78 *
79 * There are multiple components involved in the generation of the CDCLK
80 * frequency:
81 *
82 * - We have the CDCLK PLL, which generates an output clock based on a
83 * reference clock and a ratio parameter.
84 * - The CD2X Divider, which divides the output of the PLL based on a
85 * divisor selected from a set of pre-defined choices.
86 * - The CD2X Squasher, which further divides the output based on a
87 * waveform represented as a sequence of bits where each zero
88 * "squashes out" a clock cycle.
89 * - And, finally, a fixed divider that divides the output frequency by 2.
90 *
91 * As such, the resulting CDCLK frequency can be calculated with the
92 * following formula:
93 *
94 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2
95 *
96 * , where vco is the frequency generated by the PLL; cd2x_div
97 * represents the CD2X Divider; sq_len and sq_div are the bit length
98 * and the number of high bits for the CD2X Squasher waveform, respectively;
99 * and 2 represents the fixed divider.
100 *
101 * Note that some older platforms do not contain the CD2X Divider
102 * and/or CD2X Squasher, in which case we can ignore their respective
103 * factors in the formula above.
104 *
105 * Several methods exist to change the CDCLK frequency, which ones are
106 * supported depends on the platform:
107 *
108 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
109 * - CD2X divider update. Single pipe can be active as the divider update
110 * can be synchronized with the pipe's start of vblank.
111 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active.
112 * - Squash waveform update. Pipes can be active.
113 * - Crawl and squash can also be done back to back. Pipes can be active.
114 *
115 * RAWCLK is a fixed frequency clock, often used by various auxiliary
116 * blocks such as AUX CH or backlight PWM. Hence the only thing we
117 * really need to know about RAWCLK is its frequency so that various
118 * dividers can be programmed correctly.
119 */
120
121 struct intel_cdclk_state {
122 struct intel_global_state base;
123
124 /*
125 * Logical configuration of cdclk (used for all scaling,
126 * watermark, etc. calculations and checks). This is
127 * computed as if all enabled crtcs were active.
128 */
129 struct intel_cdclk_config logical;
130
131 /*
132 * Actual configuration of cdclk, can be different from the
133 * logical configuration only when all crtc's are DPMS off.
134 */
135 struct intel_cdclk_config actual;
136
137 /* minimum acceptable cdclk to satisfy DBUF bandwidth requirements */
138 int dbuf_bw_min_cdclk;
139 /* minimum acceptable cdclk for each pipe */
140 int min_cdclk[I915_MAX_PIPES];
141 /* minimum acceptable voltage level for each pipe */
142 u8 min_voltage_level[I915_MAX_PIPES];
143
144 /* pipe to which cd2x update is synchronized */
145 enum pipe pipe;
146
147 /* forced minimum cdclk for glk+ audio w/a */
148 int force_min_cdclk;
149
150 /* bitmask of enabled pipes */
151 u8 enabled_pipes;
152
153 /* bitmask of active pipes */
154 u8 active_pipes;
155
156 /* update cdclk with pipes disabled */
157 bool disable_pipes;
158 };
159
160 struct intel_cdclk_funcs {
161 void (*get_cdclk)(struct intel_display *display,
162 struct intel_cdclk_config *cdclk_config);
163 void (*set_cdclk)(struct intel_display *display,
164 const struct intel_cdclk_config *cdclk_config,
165 enum pipe pipe);
166 int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
167 u8 (*calc_voltage_level)(int cdclk);
168 };
169
intel_cdclk_get_cdclk(struct intel_display * display,struct intel_cdclk_config * cdclk_config)170 void intel_cdclk_get_cdclk(struct intel_display *display,
171 struct intel_cdclk_config *cdclk_config)
172 {
173 display->funcs.cdclk->get_cdclk(display, cdclk_config);
174 }
175
intel_cdclk_set_cdclk(struct intel_display * display,const struct intel_cdclk_config * cdclk_config,enum pipe pipe)176 static void intel_cdclk_set_cdclk(struct intel_display *display,
177 const struct intel_cdclk_config *cdclk_config,
178 enum pipe pipe)
179 {
180 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe);
181 }
182
intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state * state)183 static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state)
184 {
185 struct intel_display *display = to_intel_display(state);
186
187 return display->funcs.cdclk->modeset_calc_cdclk(state);
188 }
189
intel_cdclk_calc_voltage_level(struct intel_display * display,int cdclk)190 static u8 intel_cdclk_calc_voltage_level(struct intel_display *display,
191 int cdclk)
192 {
193 return display->funcs.cdclk->calc_voltage_level(cdclk);
194 }
195
fixed_133mhz_get_cdclk(struct intel_display * display,struct intel_cdclk_config * cdclk_config)196 static void fixed_133mhz_get_cdclk(struct intel_display *display,
197 struct intel_cdclk_config *cdclk_config)
198 {
199 cdclk_config->cdclk = 133333;
200 }
201
fixed_200mhz_get_cdclk(struct intel_display * display,struct intel_cdclk_config * cdclk_config)202 static void fixed_200mhz_get_cdclk(struct intel_display *display,
203 struct intel_cdclk_config *cdclk_config)
204 {
205 cdclk_config->cdclk = 200000;
206 }
207
fixed_266mhz_get_cdclk(struct intel_display * display,struct intel_cdclk_config * cdclk_config)208 static void fixed_266mhz_get_cdclk(struct intel_display *display,
209 struct intel_cdclk_config *cdclk_config)
210 {
211 cdclk_config->cdclk = 266667;
212 }
213
fixed_333mhz_get_cdclk(struct intel_display * display,struct intel_cdclk_config * cdclk_config)214 static void fixed_333mhz_get_cdclk(struct intel_display *display,
215 struct intel_cdclk_config *cdclk_config)
216 {
217 cdclk_config->cdclk = 333333;
218 }
219
fixed_400mhz_get_cdclk(struct intel_display * display,struct intel_cdclk_config * cdclk_config)220 static void fixed_400mhz_get_cdclk(struct intel_display *display,
221 struct intel_cdclk_config *cdclk_config)
222 {
223 cdclk_config->cdclk = 400000;
224 }
225
fixed_450mhz_get_cdclk(struct intel_display * display,struct intel_cdclk_config * cdclk_config)226 static void fixed_450mhz_get_cdclk(struct intel_display *display,
227 struct intel_cdclk_config *cdclk_config)
228 {
229 cdclk_config->cdclk = 450000;
230 }
231
i85x_get_cdclk(struct intel_display * display,struct intel_cdclk_config * cdclk_config)232 static void i85x_get_cdclk(struct intel_display *display,
233 struct intel_cdclk_config *cdclk_config)
234 {
235 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
236 u16 hpllcc = 0;
237
238 /*
239 * 852GM/852GMV only supports 133 MHz and the HPLLCC
240 * encoding is different :(
241 * FIXME is this the right way to detect 852GM/852GMV?
242 */
243 if (pdev->revision == 0x1) {
244 cdclk_config->cdclk = 133333;
245 return;
246 }
247
248 pci_bus_read_config_word(pdev->bus,
249 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
250
251 /* Assume that the hardware is in the high speed state. This
252 * should be the default.
253 */
254 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
255 case GC_CLOCK_133_200:
256 case GC_CLOCK_133_200_2:
257 case GC_CLOCK_100_200:
258 cdclk_config->cdclk = 200000;
259 break;
260 case GC_CLOCK_166_250:
261 cdclk_config->cdclk = 250000;
262 break;
263 case GC_CLOCK_100_133:
264 cdclk_config->cdclk = 133333;
265 break;
266 case GC_CLOCK_133_266:
267 case GC_CLOCK_133_266_2:
268 case GC_CLOCK_166_266:
269 cdclk_config->cdclk = 266667;
270 break;
271 }
272 }
273
i915gm_get_cdclk(struct intel_display * display,struct intel_cdclk_config * cdclk_config)274 static void i915gm_get_cdclk(struct intel_display *display,
275 struct intel_cdclk_config *cdclk_config)
276 {
277 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
278 u16 gcfgc = 0;
279
280 pci_read_config_word(pdev, GCFGC, &gcfgc);
281
282 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
283 cdclk_config->cdclk = 133333;
284 return;
285 }
286
287 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
288 case GC_DISPLAY_CLOCK_333_320_MHZ:
289 cdclk_config->cdclk = 333333;
290 break;
291 default:
292 case GC_DISPLAY_CLOCK_190_200_MHZ:
293 cdclk_config->cdclk = 190000;
294 break;
295 }
296 }
297
i945gm_get_cdclk(struct intel_display * display,struct intel_cdclk_config * cdclk_config)298 static void i945gm_get_cdclk(struct intel_display *display,
299 struct intel_cdclk_config *cdclk_config)
300 {
301 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
302 u16 gcfgc = 0;
303
304 pci_read_config_word(pdev, GCFGC, &gcfgc);
305
306 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
307 cdclk_config->cdclk = 133333;
308 return;
309 }
310
311 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
312 case GC_DISPLAY_CLOCK_333_320_MHZ:
313 cdclk_config->cdclk = 320000;
314 break;
315 default:
316 case GC_DISPLAY_CLOCK_190_200_MHZ:
317 cdclk_config->cdclk = 200000;
318 break;
319 }
320 }
321
intel_hpll_vco(struct intel_display * display)322 static unsigned int intel_hpll_vco(struct intel_display *display)
323 {
324 static const unsigned int blb_vco[8] = {
325 [0] = 3200000,
326 [1] = 4000000,
327 [2] = 5333333,
328 [3] = 4800000,
329 [4] = 6400000,
330 };
331 static const unsigned int pnv_vco[8] = {
332 [0] = 3200000,
333 [1] = 4000000,
334 [2] = 5333333,
335 [3] = 4800000,
336 [4] = 2666667,
337 };
338 static const unsigned int cl_vco[8] = {
339 [0] = 3200000,
340 [1] = 4000000,
341 [2] = 5333333,
342 [3] = 6400000,
343 [4] = 3333333,
344 [5] = 3566667,
345 [6] = 4266667,
346 };
347 static const unsigned int elk_vco[8] = {
348 [0] = 3200000,
349 [1] = 4000000,
350 [2] = 5333333,
351 [3] = 4800000,
352 };
353 static const unsigned int ctg_vco[8] = {
354 [0] = 3200000,
355 [1] = 4000000,
356 [2] = 5333333,
357 [3] = 6400000,
358 [4] = 2666667,
359 [5] = 4266667,
360 };
361 const unsigned int *vco_table;
362 unsigned int vco;
363 u8 tmp = 0;
364
365 /* FIXME other chipsets? */
366 if (display->platform.gm45)
367 vco_table = ctg_vco;
368 else if (display->platform.g45)
369 vco_table = elk_vco;
370 else if (display->platform.i965gm)
371 vco_table = cl_vco;
372 else if (display->platform.pineview)
373 vco_table = pnv_vco;
374 else if (display->platform.g33)
375 vco_table = blb_vco;
376 else
377 return 0;
378
379 tmp = intel_de_read(display, display->platform.pineview ||
380 display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO);
381
382 vco = vco_table[tmp & 0x7];
383 if (vco == 0)
384 drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
385 tmp);
386 else
387 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco);
388
389 return vco;
390 }
391
g33_get_cdclk(struct intel_display * display,struct intel_cdclk_config * cdclk_config)392 static void g33_get_cdclk(struct intel_display *display,
393 struct intel_cdclk_config *cdclk_config)
394 {
395 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
396 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 };
397 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 };
398 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
399 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
400 const u8 *div_table;
401 unsigned int cdclk_sel;
402 u16 tmp = 0;
403
404 cdclk_config->vco = intel_hpll_vco(display);
405
406 pci_read_config_word(pdev, GCFGC, &tmp);
407
408 cdclk_sel = (tmp >> 4) & 0x7;
409
410 if (cdclk_sel >= ARRAY_SIZE(div_3200))
411 goto fail;
412
413 switch (cdclk_config->vco) {
414 case 3200000:
415 div_table = div_3200;
416 break;
417 case 4000000:
418 div_table = div_4000;
419 break;
420 case 4800000:
421 div_table = div_4800;
422 break;
423 case 5333333:
424 div_table = div_5333;
425 break;
426 default:
427 goto fail;
428 }
429
430 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
431 div_table[cdclk_sel]);
432 return;
433
434 fail:
435 drm_err(display->drm,
436 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
437 cdclk_config->vco, tmp);
438 cdclk_config->cdclk = 190476;
439 }
440
pnv_get_cdclk(struct intel_display * display,struct intel_cdclk_config * cdclk_config)441 static void pnv_get_cdclk(struct intel_display *display,
442 struct intel_cdclk_config *cdclk_config)
443 {
444 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
445 u16 gcfgc = 0;
446
447 pci_read_config_word(pdev, GCFGC, &gcfgc);
448
449 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
450 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
451 cdclk_config->cdclk = 266667;
452 break;
453 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
454 cdclk_config->cdclk = 333333;
455 break;
456 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
457 cdclk_config->cdclk = 444444;
458 break;
459 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
460 cdclk_config->cdclk = 200000;
461 break;
462 default:
463 drm_err(display->drm,
464 "Unknown pnv display core clock 0x%04x\n", gcfgc);
465 fallthrough;
466 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
467 cdclk_config->cdclk = 133333;
468 break;
469 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
470 cdclk_config->cdclk = 166667;
471 break;
472 }
473 }
474
i965gm_get_cdclk(struct intel_display * display,struct intel_cdclk_config * cdclk_config)475 static void i965gm_get_cdclk(struct intel_display *display,
476 struct intel_cdclk_config *cdclk_config)
477 {
478 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
479 static const u8 div_3200[] = { 16, 10, 8 };
480 static const u8 div_4000[] = { 20, 12, 10 };
481 static const u8 div_5333[] = { 24, 16, 14 };
482 const u8 *div_table;
483 unsigned int cdclk_sel;
484 u16 tmp = 0;
485
486 cdclk_config->vco = intel_hpll_vco(display);
487
488 pci_read_config_word(pdev, GCFGC, &tmp);
489
490 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
491
492 if (cdclk_sel >= ARRAY_SIZE(div_3200))
493 goto fail;
494
495 switch (cdclk_config->vco) {
496 case 3200000:
497 div_table = div_3200;
498 break;
499 case 4000000:
500 div_table = div_4000;
501 break;
502 case 5333333:
503 div_table = div_5333;
504 break;
505 default:
506 goto fail;
507 }
508
509 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
510 div_table[cdclk_sel]);
511 return;
512
513 fail:
514 drm_err(display->drm,
515 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
516 cdclk_config->vco, tmp);
517 cdclk_config->cdclk = 200000;
518 }
519
gm45_get_cdclk(struct intel_display * display,struct intel_cdclk_config * cdclk_config)520 static void gm45_get_cdclk(struct intel_display *display,
521 struct intel_cdclk_config *cdclk_config)
522 {
523 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
524 unsigned int cdclk_sel;
525 u16 tmp = 0;
526
527 cdclk_config->vco = intel_hpll_vco(display);
528
529 pci_read_config_word(pdev, GCFGC, &tmp);
530
531 cdclk_sel = (tmp >> 12) & 0x1;
532
533 switch (cdclk_config->vco) {
534 case 2666667:
535 case 4000000:
536 case 5333333:
537 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222;
538 break;
539 case 3200000:
540 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
541 break;
542 default:
543 drm_err(display->drm,
544 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
545 cdclk_config->vco, tmp);
546 cdclk_config->cdclk = 222222;
547 break;
548 }
549 }
550
hsw_get_cdclk(struct intel_display * display,struct intel_cdclk_config * cdclk_config)551 static void hsw_get_cdclk(struct intel_display *display,
552 struct intel_cdclk_config *cdclk_config)
553 {
554 u32 lcpll = intel_de_read(display, LCPLL_CTL);
555 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
556
557 if (lcpll & LCPLL_CD_SOURCE_FCLK)
558 cdclk_config->cdclk = 800000;
559 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
560 cdclk_config->cdclk = 450000;
561 else if (freq == LCPLL_CLK_FREQ_450)
562 cdclk_config->cdclk = 450000;
563 else if (display->platform.haswell_ult)
564 cdclk_config->cdclk = 337500;
565 else
566 cdclk_config->cdclk = 540000;
567 }
568
vlv_calc_cdclk(struct intel_display * display,int min_cdclk)569 static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk)
570 {
571 int freq_320 = (vlv_clock_get_hpll_vco(display->drm) << 1) % 320000 != 0 ?
572 333333 : 320000;
573
574 /*
575 * We seem to get an unstable or solid color picture at 200MHz.
576 * Not sure what's wrong. For now use 200MHz only when all pipes
577 * are off.
578 */
579 if (display->platform.valleyview && min_cdclk > freq_320)
580 return 400000;
581 else if (min_cdclk > 266667)
582 return freq_320;
583 else if (min_cdclk > 0)
584 return 266667;
585 else
586 return 200000;
587 }
588
vlv_calc_voltage_level(struct intel_display * display,int cdclk)589 static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk)
590 {
591 if (display->platform.valleyview) {
592 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
593 return 2;
594 else if (cdclk >= 266667)
595 return 1;
596 else
597 return 0;
598 } else {
599 /*
600 * Specs are full of misinformation, but testing on actual
601 * hardware has shown that we just need to write the desired
602 * CCK divider into the Punit register.
603 */
604 return DIV_ROUND_CLOSEST(vlv_clock_get_hpll_vco(display->drm) << 1, cdclk) - 1;
605 }
606 }
607
vlv_get_cdclk(struct intel_display * display,struct intel_cdclk_config * cdclk_config)608 static void vlv_get_cdclk(struct intel_display *display,
609 struct intel_cdclk_config *cdclk_config)
610 {
611 u32 val;
612
613 cdclk_config->vco = vlv_clock_get_hpll_vco(display->drm);
614 cdclk_config->cdclk = vlv_clock_get_cdclk(display->drm);
615
616 vlv_punit_get(display->drm);
617 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
618 vlv_punit_put(display->drm);
619
620 if (display->platform.valleyview)
621 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >>
622 DSPFREQGUAR_SHIFT;
623 else
624 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
625 DSPFREQGUAR_SHIFT_CHV;
626 }
627
vlv_program_pfi_credits(struct intel_display * display)628 static void vlv_program_pfi_credits(struct intel_display *display)
629 {
630 unsigned int credits, default_credits;
631
632 if (display->platform.cherryview)
633 default_credits = PFI_CREDIT(12);
634 else
635 default_credits = PFI_CREDIT(8);
636
637 if (display->cdclk.hw.cdclk >= vlv_clock_get_czclk(display->drm)) {
638 /* CHV suggested value is 31 or 63 */
639 if (display->platform.cherryview)
640 credits = PFI_CREDIT_63;
641 else
642 credits = PFI_CREDIT(15);
643 } else {
644 credits = default_credits;
645 }
646
647 /*
648 * WA - write default credits before re-programming
649 * FIXME: should we also set the resend bit here?
650 */
651 intel_de_write(display, GCI_CONTROL,
652 VGA_FAST_MODE_DISABLE | default_credits);
653
654 intel_de_write(display, GCI_CONTROL,
655 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND);
656
657 /*
658 * FIXME is this guaranteed to clear
659 * immediately or should we poll for it?
660 */
661 drm_WARN_ON(display->drm,
662 intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND);
663 }
664
vlv_set_cdclk(struct intel_display * display,const struct intel_cdclk_config * cdclk_config,enum pipe pipe)665 static void vlv_set_cdclk(struct intel_display *display,
666 const struct intel_cdclk_config *cdclk_config,
667 enum pipe pipe)
668 {
669 int cdclk = cdclk_config->cdclk;
670 u32 val, cmd = cdclk_config->voltage_level;
671 struct ref_tracker *wakeref;
672 int ret;
673
674 switch (cdclk) {
675 case 400000:
676 case 333333:
677 case 320000:
678 case 266667:
679 case 200000:
680 break;
681 default:
682 MISSING_CASE(cdclk);
683 return;
684 }
685
686 /* There are cases where we can end up here with power domains
687 * off and a CDCLK frequency other than the minimum, like when
688 * issuing a modeset without actually changing any display after
689 * a system suspend. So grab the display core domain, which covers
690 * the HW blocks needed for the following programming.
691 */
692 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE);
693
694 vlv_iosf_sb_get(display->drm,
695 BIT(VLV_IOSF_SB_CCK) |
696 BIT(VLV_IOSF_SB_BUNIT) |
697 BIT(VLV_IOSF_SB_PUNIT));
698
699 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
700 val &= ~DSPFREQGUAR_MASK;
701 val |= (cmd << DSPFREQGUAR_SHIFT);
702 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val);
703
704 ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),
705 (val & DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
706 500, 50 * 1000, false);
707 if (ret)
708 drm_err(display->drm, "timed out waiting for CDCLK change\n");
709
710 if (cdclk == 400000) {
711 u32 divider;
712
713 divider = DIV_ROUND_CLOSEST(vlv_clock_get_hpll_vco(display->drm) << 1,
714 cdclk) - 1;
715
716 /* adjust cdclk divider */
717 val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL);
718 val &= ~CCK_FREQUENCY_VALUES;
719 val |= divider;
720 vlv_cck_write(display->drm, CCK_DISPLAY_CLOCK_CONTROL, val);
721
722 ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL),
723 (val & CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
724 500, 50 * 1000, false);
725 if (ret)
726 drm_err(display->drm, "timed out waiting for CDCLK change\n");
727 }
728
729 /* adjust self-refresh exit latency value */
730 val = vlv_bunit_read(display->drm, BUNIT_REG_BISOC);
731 val &= ~0x7f;
732
733 /*
734 * For high bandwidth configs, we set a higher latency in the bunit
735 * so that the core display fetch happens in time to avoid underruns.
736 */
737 if (cdclk == 400000)
738 val |= 4500 / 250; /* 4.5 usec */
739 else
740 val |= 3000 / 250; /* 3.0 usec */
741 vlv_bunit_write(display->drm, BUNIT_REG_BISOC, val);
742
743 vlv_iosf_sb_put(display->drm,
744 BIT(VLV_IOSF_SB_CCK) |
745 BIT(VLV_IOSF_SB_BUNIT) |
746 BIT(VLV_IOSF_SB_PUNIT));
747
748 intel_update_cdclk(display);
749
750 vlv_program_pfi_credits(display);
751
752 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
753 }
754
chv_set_cdclk(struct intel_display * display,const struct intel_cdclk_config * cdclk_config,enum pipe pipe)755 static void chv_set_cdclk(struct intel_display *display,
756 const struct intel_cdclk_config *cdclk_config,
757 enum pipe pipe)
758 {
759 int cdclk = cdclk_config->cdclk;
760 u32 val, cmd = cdclk_config->voltage_level;
761 struct ref_tracker *wakeref;
762 int ret;
763
764 switch (cdclk) {
765 case 333333:
766 case 320000:
767 case 266667:
768 case 200000:
769 break;
770 default:
771 MISSING_CASE(cdclk);
772 return;
773 }
774
775 /* There are cases where we can end up here with power domains
776 * off and a CDCLK frequency other than the minimum, like when
777 * issuing a modeset without actually changing any display after
778 * a system suspend. So grab the display core domain, which covers
779 * the HW blocks needed for the following programming.
780 */
781 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE);
782
783 vlv_punit_get(display->drm);
784 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
785 val &= ~DSPFREQGUAR_MASK_CHV;
786 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
787 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val);
788
789 ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),
790 (val & DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
791 500, 50 * 1000, false);
792 if (ret)
793 drm_err(display->drm, "timed out waiting for CDCLK change\n");
794
795 vlv_punit_put(display->drm);
796
797 intel_update_cdclk(display);
798
799 vlv_program_pfi_credits(display);
800
801 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
802 }
803
bdw_calc_cdclk(int min_cdclk)804 static int bdw_calc_cdclk(int min_cdclk)
805 {
806 if (min_cdclk > 540000)
807 return 675000;
808 else if (min_cdclk > 450000)
809 return 540000;
810 else if (min_cdclk > 337500)
811 return 450000;
812 else
813 return 337500;
814 }
815
bdw_calc_voltage_level(int cdclk)816 static u8 bdw_calc_voltage_level(int cdclk)
817 {
818 switch (cdclk) {
819 default:
820 case 337500:
821 return 2;
822 case 450000:
823 return 0;
824 case 540000:
825 return 1;
826 case 675000:
827 return 3;
828 }
829 }
830
bdw_get_cdclk(struct intel_display * display,struct intel_cdclk_config * cdclk_config)831 static void bdw_get_cdclk(struct intel_display *display,
832 struct intel_cdclk_config *cdclk_config)
833 {
834 u32 lcpll = intel_de_read(display, LCPLL_CTL);
835 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
836
837 if (lcpll & LCPLL_CD_SOURCE_FCLK)
838 cdclk_config->cdclk = 800000;
839 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
840 cdclk_config->cdclk = 450000;
841 else if (freq == LCPLL_CLK_FREQ_450)
842 cdclk_config->cdclk = 450000;
843 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
844 cdclk_config->cdclk = 540000;
845 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
846 cdclk_config->cdclk = 337500;
847 else
848 cdclk_config->cdclk = 675000;
849
850 /*
851 * Can't read this out :( Let's assume it's
852 * at least what the CDCLK frequency requires.
853 */
854 cdclk_config->voltage_level =
855 bdw_calc_voltage_level(cdclk_config->cdclk);
856 }
857
bdw_cdclk_freq_sel(int cdclk)858 static u32 bdw_cdclk_freq_sel(int cdclk)
859 {
860 switch (cdclk) {
861 default:
862 MISSING_CASE(cdclk);
863 fallthrough;
864 case 337500:
865 return LCPLL_CLK_FREQ_337_5_BDW;
866 case 450000:
867 return LCPLL_CLK_FREQ_450;
868 case 540000:
869 return LCPLL_CLK_FREQ_54O_BDW;
870 case 675000:
871 return LCPLL_CLK_FREQ_675_BDW;
872 }
873 }
874
bdw_set_cdclk(struct intel_display * display,const struct intel_cdclk_config * cdclk_config,enum pipe pipe)875 static void bdw_set_cdclk(struct intel_display *display,
876 const struct intel_cdclk_config *cdclk_config,
877 enum pipe pipe)
878 {
879 int cdclk = cdclk_config->cdclk;
880 int ret;
881
882 if (drm_WARN(display->drm,
883 (intel_de_read(display, LCPLL_CTL) &
884 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
885 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
886 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
887 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
888 "trying to change cdclk frequency with cdclk not enabled\n"))
889 return;
890
891 ret = intel_pcode_write(display->drm, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
892 if (ret) {
893 drm_err(display->drm,
894 "failed to inform pcode about cdclk change\n");
895 return;
896 }
897
898 intel_de_rmw(display, LCPLL_CTL,
899 0, LCPLL_CD_SOURCE_FCLK);
900
901 /*
902 * According to the spec, it should be enough to poll for this 1 us.
903 * However, extensive testing shows that this can take longer.
904 */
905 ret = intel_de_wait_for_set_us(display, LCPLL_CTL,
906 LCPLL_CD_SOURCE_FCLK_DONE, 100);
907 if (ret)
908 drm_err(display->drm, "Switching to FCLK failed\n");
909
910 intel_de_rmw(display, LCPLL_CTL,
911 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk));
912
913 intel_de_rmw(display, LCPLL_CTL,
914 LCPLL_CD_SOURCE_FCLK, 0);
915
916 ret = intel_de_wait_for_clear_us(display, LCPLL_CTL,
917 LCPLL_CD_SOURCE_FCLK_DONE, 1);
918 if (ret)
919 drm_err(display->drm, "Switching back to LCPLL failed\n");
920
921 intel_pcode_write(display->drm, HSW_PCODE_DE_WRITE_FREQ_REQ,
922 cdclk_config->voltage_level);
923
924 intel_de_write(display, CDCLK_FREQ,
925 DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
926
927 intel_update_cdclk(display);
928 }
929
skl_calc_cdclk(int min_cdclk,int vco)930 static int skl_calc_cdclk(int min_cdclk, int vco)
931 {
932 if (vco == 8640000) {
933 if (min_cdclk > 540000)
934 return 617143;
935 else if (min_cdclk > 432000)
936 return 540000;
937 else if (min_cdclk > 308571)
938 return 432000;
939 else
940 return 308571;
941 } else {
942 if (min_cdclk > 540000)
943 return 675000;
944 else if (min_cdclk > 450000)
945 return 540000;
946 else if (min_cdclk > 337500)
947 return 450000;
948 else
949 return 337500;
950 }
951 }
952
skl_calc_voltage_level(int cdclk)953 static u8 skl_calc_voltage_level(int cdclk)
954 {
955 if (cdclk > 540000)
956 return 3;
957 else if (cdclk > 450000)
958 return 2;
959 else if (cdclk > 337500)
960 return 1;
961 else
962 return 0;
963 }
964
skl_dpll0_update(struct intel_display * display,struct intel_cdclk_config * cdclk_config)965 static void skl_dpll0_update(struct intel_display *display,
966 struct intel_cdclk_config *cdclk_config)
967 {
968 u32 val;
969
970 cdclk_config->ref = 24000;
971 cdclk_config->vco = 0;
972
973 val = intel_de_read(display, LCPLL1_CTL);
974 if ((val & LCPLL_PLL_ENABLE) == 0)
975 return;
976
977 if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0))
978 return;
979
980 val = intel_de_read(display, DPLL_CTRL1);
981
982 if (drm_WARN_ON(display->drm,
983 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
984 DPLL_CTRL1_SSC(SKL_DPLL0) |
985 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
986 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
987 return;
988
989 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
990 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
991 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
992 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
993 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
994 cdclk_config->vco = 8100000;
995 break;
996 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
997 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
998 cdclk_config->vco = 8640000;
999 break;
1000 default:
1001 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
1002 break;
1003 }
1004 }
1005
skl_get_cdclk(struct intel_display * display,struct intel_cdclk_config * cdclk_config)1006 static void skl_get_cdclk(struct intel_display *display,
1007 struct intel_cdclk_config *cdclk_config)
1008 {
1009 u32 cdctl;
1010
1011 skl_dpll0_update(display, cdclk_config);
1012
1013 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
1014
1015 if (cdclk_config->vco == 0)
1016 goto out;
1017
1018 cdctl = intel_de_read(display, CDCLK_CTL);
1019
1020 if (cdclk_config->vco == 8640000) {
1021 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1022 case CDCLK_FREQ_450_432:
1023 cdclk_config->cdclk = 432000;
1024 break;
1025 case CDCLK_FREQ_337_308:
1026 cdclk_config->cdclk = 308571;
1027 break;
1028 case CDCLK_FREQ_540:
1029 cdclk_config->cdclk = 540000;
1030 break;
1031 case CDCLK_FREQ_675_617:
1032 cdclk_config->cdclk = 617143;
1033 break;
1034 default:
1035 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
1036 break;
1037 }
1038 } else {
1039 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1040 case CDCLK_FREQ_450_432:
1041 cdclk_config->cdclk = 450000;
1042 break;
1043 case CDCLK_FREQ_337_308:
1044 cdclk_config->cdclk = 337500;
1045 break;
1046 case CDCLK_FREQ_540:
1047 cdclk_config->cdclk = 540000;
1048 break;
1049 case CDCLK_FREQ_675_617:
1050 cdclk_config->cdclk = 675000;
1051 break;
1052 default:
1053 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
1054 break;
1055 }
1056 }
1057
1058 out:
1059 /*
1060 * Can't read this out :( Let's assume it's
1061 * at least what the CDCLK frequency requires.
1062 */
1063 cdclk_config->voltage_level =
1064 skl_calc_voltage_level(cdclk_config->cdclk);
1065 }
1066
1067 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
skl_cdclk_decimal(int cdclk)1068 static int skl_cdclk_decimal(int cdclk)
1069 {
1070 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
1071 }
1072
skl_set_preferred_cdclk_vco(struct intel_display * display,int vco)1073 static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco)
1074 {
1075 bool changed = display->cdclk.skl_preferred_vco_freq != vco;
1076
1077 display->cdclk.skl_preferred_vco_freq = vco;
1078
1079 if (changed)
1080 intel_update_max_cdclk(display);
1081 }
1082
skl_dpll0_link_rate(struct intel_display * display,int vco)1083 static u32 skl_dpll0_link_rate(struct intel_display *display, int vco)
1084 {
1085 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
1086
1087 /*
1088 * We always enable DPLL0 with the lowest link rate possible, but still
1089 * taking into account the VCO required to operate the eDP panel at the
1090 * desired frequency. The usual DP link rates operate with a VCO of
1091 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
1092 * The modeset code is responsible for the selection of the exact link
1093 * rate later on, with the constraint of choosing a frequency that
1094 * works with vco.
1095 */
1096 if (vco == 8640000)
1097 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0);
1098 else
1099 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0);
1100 }
1101
skl_dpll0_enable(struct intel_display * display,int vco)1102 static void skl_dpll0_enable(struct intel_display *display, int vco)
1103 {
1104 intel_de_rmw(display, DPLL_CTRL1,
1105 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
1106 DPLL_CTRL1_SSC(SKL_DPLL0) |
1107 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0),
1108 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) |
1109 skl_dpll0_link_rate(display, vco));
1110 intel_de_posting_read(display, DPLL_CTRL1);
1111
1112 intel_de_rmw(display, LCPLL1_CTL,
1113 0, LCPLL_PLL_ENABLE);
1114
1115 if (intel_de_wait_for_set_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
1116 drm_err(display->drm, "DPLL0 not locked\n");
1117
1118 display->cdclk.hw.vco = vco;
1119
1120 /* We'll want to keep using the current vco from now on. */
1121 skl_set_preferred_cdclk_vco(display, vco);
1122 }
1123
skl_dpll0_disable(struct intel_display * display)1124 static void skl_dpll0_disable(struct intel_display *display)
1125 {
1126 intel_de_rmw(display, LCPLL1_CTL,
1127 LCPLL_PLL_ENABLE, 0);
1128
1129 if (intel_de_wait_for_clear_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
1130 drm_err(display->drm, "Couldn't disable DPLL0\n");
1131
1132 display->cdclk.hw.vco = 0;
1133 }
1134
skl_cdclk_freq_sel(struct intel_display * display,int cdclk,int vco)1135 static u32 skl_cdclk_freq_sel(struct intel_display *display,
1136 int cdclk, int vco)
1137 {
1138 switch (cdclk) {
1139 default:
1140 drm_WARN_ON(display->drm,
1141 cdclk != display->cdclk.hw.bypass);
1142 drm_WARN_ON(display->drm, vco != 0);
1143 fallthrough;
1144 case 308571:
1145 case 337500:
1146 return CDCLK_FREQ_337_308;
1147 case 450000:
1148 case 432000:
1149 return CDCLK_FREQ_450_432;
1150 case 540000:
1151 return CDCLK_FREQ_540;
1152 case 617143:
1153 case 675000:
1154 return CDCLK_FREQ_675_617;
1155 }
1156 }
1157
skl_set_cdclk(struct intel_display * display,const struct intel_cdclk_config * cdclk_config,enum pipe pipe)1158 static void skl_set_cdclk(struct intel_display *display,
1159 const struct intel_cdclk_config *cdclk_config,
1160 enum pipe pipe)
1161 {
1162 int cdclk = cdclk_config->cdclk;
1163 int vco = cdclk_config->vco;
1164 u32 freq_select, cdclk_ctl;
1165 int ret;
1166
1167 /*
1168 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
1169 * unsupported on SKL. In theory this should never happen since only
1170 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
1171 * supported on SKL either, see the above WA. WARN whenever trying to
1172 * use the corresponding VCO freq as that always leads to using the
1173 * minimum 308MHz CDCLK.
1174 */
1175 drm_WARN_ON_ONCE(display->drm,
1176 display->platform.skylake && vco == 8640000);
1177
1178 ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL,
1179 SKL_CDCLK_PREPARE_FOR_CHANGE,
1180 SKL_CDCLK_READY_FOR_CHANGE,
1181 SKL_CDCLK_READY_FOR_CHANGE, 3);
1182 if (ret) {
1183 drm_err(display->drm,
1184 "Failed to inform PCU about cdclk change (%d)\n", ret);
1185 return;
1186 }
1187
1188 freq_select = skl_cdclk_freq_sel(display, cdclk, vco);
1189
1190 if (display->cdclk.hw.vco != 0 &&
1191 display->cdclk.hw.vco != vco)
1192 skl_dpll0_disable(display);
1193
1194 cdclk_ctl = intel_de_read(display, CDCLK_CTL);
1195
1196 if (display->cdclk.hw.vco != vco) {
1197 /* Wa Display #1183: skl,kbl,cfl */
1198 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1199 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1200 intel_de_write(display, CDCLK_CTL, cdclk_ctl);
1201 }
1202
1203 /* Wa Display #1183: skl,kbl,cfl */
1204 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1205 intel_de_write(display, CDCLK_CTL, cdclk_ctl);
1206 intel_de_posting_read(display, CDCLK_CTL);
1207
1208 if (display->cdclk.hw.vco != vco)
1209 skl_dpll0_enable(display, vco);
1210
1211 /* Wa Display #1183: skl,kbl,cfl */
1212 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1213 intel_de_write(display, CDCLK_CTL, cdclk_ctl);
1214
1215 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1216 intel_de_write(display, CDCLK_CTL, cdclk_ctl);
1217
1218 /* Wa Display #1183: skl,kbl,cfl */
1219 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1220 intel_de_write(display, CDCLK_CTL, cdclk_ctl);
1221 intel_de_posting_read(display, CDCLK_CTL);
1222
1223 /* inform PCU of the change */
1224 intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL,
1225 cdclk_config->voltage_level);
1226
1227 intel_update_cdclk(display);
1228 }
1229
skl_sanitize_cdclk(struct intel_display * display)1230 static void skl_sanitize_cdclk(struct intel_display *display)
1231 {
1232 u32 cdctl, expected;
1233
1234 /*
1235 * check if the pre-os initialized the display
1236 * There is SWF18 scratchpad register defined which is set by the
1237 * pre-os which can be used by the OS drivers to check the status
1238 */
1239 if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1240 goto sanitize;
1241
1242 intel_update_cdclk(display);
1243 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
1244
1245 /* Is PLL enabled and locked ? */
1246 if (display->cdclk.hw.vco == 0 ||
1247 display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
1248 goto sanitize;
1249
1250 /* DPLL okay; verify the cdclock
1251 *
1252 * Noticed in some instances that the freq selection is correct but
1253 * decimal part is programmed wrong from BIOS where pre-os does not
1254 * enable display. Verify the same as well.
1255 */
1256 cdctl = intel_de_read(display, CDCLK_CTL);
1257 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1258 skl_cdclk_decimal(display->cdclk.hw.cdclk);
1259 if (cdctl == expected)
1260 /* All well; nothing to sanitize */
1261 return;
1262
1263 sanitize:
1264 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
1265
1266 /* force cdclk programming */
1267 display->cdclk.hw.cdclk = 0;
1268 /* force full PLL disable + enable */
1269 display->cdclk.hw.vco = ~0;
1270 }
1271
skl_cdclk_init_hw(struct intel_display * display)1272 static void skl_cdclk_init_hw(struct intel_display *display)
1273 {
1274 struct intel_cdclk_config cdclk_config;
1275
1276 skl_sanitize_cdclk(display);
1277
1278 if (display->cdclk.hw.cdclk != 0 &&
1279 display->cdclk.hw.vco != 0) {
1280 /*
1281 * Use the current vco as our initial
1282 * guess as to what the preferred vco is.
1283 */
1284 if (display->cdclk.skl_preferred_vco_freq == 0)
1285 skl_set_preferred_cdclk_vco(display,
1286 display->cdclk.hw.vco);
1287 return;
1288 }
1289
1290 cdclk_config = display->cdclk.hw;
1291
1292 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq;
1293 if (cdclk_config.vco == 0)
1294 cdclk_config.vco = 8100000;
1295 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
1296 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1297
1298 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
1299 }
1300
skl_cdclk_uninit_hw(struct intel_display * display)1301 static void skl_cdclk_uninit_hw(struct intel_display *display)
1302 {
1303 struct intel_cdclk_config cdclk_config = display->cdclk.hw;
1304
1305 cdclk_config.cdclk = cdclk_config.bypass;
1306 cdclk_config.vco = 0;
1307 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1308
1309 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
1310 }
1311
1312 struct intel_cdclk_vals {
1313 u32 cdclk;
1314 u16 refclk;
1315 u16 waveform;
1316 u8 ratio;
1317 };
1318
1319 static const struct intel_cdclk_vals bxt_cdclk_table[] = {
1320 { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
1321 { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
1322 { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
1323 { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
1324 { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
1325 {}
1326 };
1327
1328 static const struct intel_cdclk_vals glk_cdclk_table[] = {
1329 { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
1330 { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
1331 { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
1332 {}
1333 };
1334
1335 static const struct intel_cdclk_vals icl_cdclk_table[] = {
1336 { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
1337 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1338 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1339 { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
1340 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1341 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1342
1343 { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
1344 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1345 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1346 { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
1347 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1348 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1349
1350 { .refclk = 38400, .cdclk = 172800, .ratio = 9 },
1351 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1352 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1353 { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
1354 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1355 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1356 {}
1357 };
1358
1359 static const struct intel_cdclk_vals rkl_cdclk_table[] = {
1360 { .refclk = 19200, .cdclk = 172800, .ratio = 36 },
1361 { .refclk = 19200, .cdclk = 192000, .ratio = 40 },
1362 { .refclk = 19200, .cdclk = 307200, .ratio = 64 },
1363 { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
1364 { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
1365 { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
1366
1367 { .refclk = 24000, .cdclk = 180000, .ratio = 30 },
1368 { .refclk = 24000, .cdclk = 192000, .ratio = 32 },
1369 { .refclk = 24000, .cdclk = 312000, .ratio = 52 },
1370 { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
1371 { .refclk = 24000, .cdclk = 552000, .ratio = 92 },
1372 { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
1373
1374 { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
1375 { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
1376 { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
1377 { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
1378 { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
1379 { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
1380 {}
1381 };
1382
1383 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
1384 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1385 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1386 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1387
1388 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1389 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1390 { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
1391
1392 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1393 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1394 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1395 {}
1396 };
1397
1398 static const struct intel_cdclk_vals adlp_cdclk_table[] = {
1399 { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1400 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1401 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1402 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1403 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1404
1405 { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1406 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1407 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1408 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1409 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1410
1411 { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1412 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1413 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1414 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1415 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1416 {}
1417 };
1418
1419 static const struct intel_cdclk_vals rplu_cdclk_table[] = {
1420 { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1421 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1422 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1423 { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
1424 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1425 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1426
1427 { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1428 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1429 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1430 { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
1431 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1432 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1433
1434 { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1435 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1436 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1437 { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
1438 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1439 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1440 {}
1441 };
1442
1443 static const struct intel_cdclk_vals dg2_cdclk_table[] = {
1444 { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
1445 { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
1446 { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
1447 { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
1448 { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
1449 { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
1450 { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
1451 { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
1452 { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
1453 { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
1454 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1455 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1456 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1457 {}
1458 };
1459
1460 static const struct intel_cdclk_vals mtl_cdclk_table[] = {
1461 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1462 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1463 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
1464 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
1465 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
1466 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
1467 {}
1468 };
1469
1470 static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = {
1471 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1472 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1473 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1474 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1475 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1476 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1477 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1478 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1479 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1480 { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
1481 { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
1482 { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
1483 { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
1484 { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
1485 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1486 { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
1487 { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
1488 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1489 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1490 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1491 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1492 {}
1493 };
1494
1495 /*
1496 * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771
1497 */
1498 static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = {
1499 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1500 {}
1501 };
1502
1503 static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = {
1504 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1505 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1506 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1507 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1508 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1509 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1510 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1511 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1512 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1513 { .refclk = 38400, .cdclk = 326400, .ratio = 17, .waveform = 0xffff },
1514 { .refclk = 38400, .cdclk = 345600, .ratio = 18, .waveform = 0xffff },
1515 { .refclk = 38400, .cdclk = 364800, .ratio = 19, .waveform = 0xffff },
1516 { .refclk = 38400, .cdclk = 384000, .ratio = 20, .waveform = 0xffff },
1517 { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff },
1518 { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff },
1519 { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff },
1520 { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff },
1521 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1522 { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff },
1523 { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff },
1524 { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff },
1525 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1526 { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff },
1527 { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff },
1528 { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff },
1529 { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff },
1530 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1531 { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff },
1532 { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff },
1533 {}
1534 };
1535
1536 static const struct intel_cdclk_vals xe3p_lpd_cdclk_table[] = {
1537 { .refclk = 38400, .cdclk = 151200, .ratio = 21, .waveform = 0xa4a4 },
1538 { .refclk = 38400, .cdclk = 176400, .ratio = 21, .waveform = 0xaa54 },
1539 { .refclk = 38400, .cdclk = 201600, .ratio = 21, .waveform = 0xaaaa },
1540 { .refclk = 38400, .cdclk = 226800, .ratio = 21, .waveform = 0xad5a },
1541 { .refclk = 38400, .cdclk = 252000, .ratio = 21, .waveform = 0xb6b6 },
1542 { .refclk = 38400, .cdclk = 277200, .ratio = 21, .waveform = 0xdbb6 },
1543 { .refclk = 38400, .cdclk = 302400, .ratio = 21, .waveform = 0xeeee },
1544 { .refclk = 38400, .cdclk = 327600, .ratio = 21, .waveform = 0xf7de },
1545 { .refclk = 38400, .cdclk = 352800, .ratio = 21, .waveform = 0xfefe },
1546 { .refclk = 38400, .cdclk = 378000, .ratio = 21, .waveform = 0xfffe },
1547 { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff },
1548 { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff },
1549 { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff },
1550 { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff },
1551 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1552 { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff },
1553 { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff },
1554 { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff },
1555 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1556 { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff },
1557 { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff },
1558 { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff },
1559 { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff },
1560 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1561 { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff },
1562 { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff },
1563 { .refclk = 38400, .cdclk = 710400, .ratio = 37, .waveform = 0xffff },
1564 { .refclk = 38400, .cdclk = 729600, .ratio = 38, .waveform = 0xffff },
1565 { .refclk = 38400, .cdclk = 748800, .ratio = 39, .waveform = 0xffff },
1566 { .refclk = 38400, .cdclk = 768000, .ratio = 40, .waveform = 0xffff },
1567 { .refclk = 38400, .cdclk = 787200, .ratio = 41, .waveform = 0xffff },
1568 {}
1569 };
1570
1571 static const int cdclk_squash_len = 16;
1572
cdclk_squash_divider(u16 waveform)1573 static int cdclk_squash_divider(u16 waveform)
1574 {
1575 return hweight16(waveform ?: 0xffff);
1576 }
1577
cdclk_divider(int cdclk,int vco,u16 waveform)1578 static int cdclk_divider(int cdclk, int vco, u16 waveform)
1579 {
1580 /* 2 * cd2x divider */
1581 return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform),
1582 cdclk * cdclk_squash_len);
1583 }
1584
bxt_calc_cdclk(struct intel_display * display,int min_cdclk)1585 static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk)
1586 {
1587 const struct intel_cdclk_vals *table = display->cdclk.table;
1588 int i;
1589
1590 for (i = 0; table[i].refclk; i++)
1591 if (table[i].refclk == display->cdclk.hw.ref &&
1592 table[i].cdclk >= min_cdclk)
1593 return table[i].cdclk;
1594
1595 drm_WARN(display->drm, 1,
1596 "Cannot satisfy minimum cdclk %d with refclk %u\n",
1597 min_cdclk, display->cdclk.hw.ref);
1598 return display->cdclk.max_cdclk_freq;
1599 }
1600
bxt_calc_cdclk_pll_vco(struct intel_display * display,int cdclk)1601 static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk)
1602 {
1603 const struct intel_cdclk_vals *table = display->cdclk.table;
1604 int i;
1605
1606 if (cdclk == display->cdclk.hw.bypass)
1607 return 0;
1608
1609 for (i = 0; table[i].refclk; i++)
1610 if (table[i].refclk == display->cdclk.hw.ref &&
1611 table[i].cdclk == cdclk)
1612 return display->cdclk.hw.ref * table[i].ratio;
1613
1614 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",
1615 cdclk, display->cdclk.hw.ref);
1616 return 0;
1617 }
1618
bxt_calc_voltage_level(int cdclk)1619 static u8 bxt_calc_voltage_level(int cdclk)
1620 {
1621 return DIV_ROUND_UP(cdclk, 25000);
1622 }
1623
calc_voltage_level(int cdclk,int num_voltage_levels,const int voltage_level_max_cdclk[])1624 static u8 calc_voltage_level(int cdclk, int num_voltage_levels,
1625 const int voltage_level_max_cdclk[])
1626 {
1627 int voltage_level;
1628
1629 for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) {
1630 if (cdclk <= voltage_level_max_cdclk[voltage_level])
1631 return voltage_level;
1632 }
1633
1634 MISSING_CASE(cdclk);
1635 return num_voltage_levels - 1;
1636 }
1637
icl_calc_voltage_level(int cdclk)1638 static u8 icl_calc_voltage_level(int cdclk)
1639 {
1640 static const int icl_voltage_level_max_cdclk[] = {
1641 [0] = 312000,
1642 [1] = 556800,
1643 [2] = 652800,
1644 };
1645
1646 return calc_voltage_level(cdclk,
1647 ARRAY_SIZE(icl_voltage_level_max_cdclk),
1648 icl_voltage_level_max_cdclk);
1649 }
1650
ehl_calc_voltage_level(int cdclk)1651 static u8 ehl_calc_voltage_level(int cdclk)
1652 {
1653 static const int ehl_voltage_level_max_cdclk[] = {
1654 [0] = 180000,
1655 [1] = 312000,
1656 [2] = 326400,
1657 /*
1658 * Bspec lists the limit as 556.8 MHz, but some JSL
1659 * development boards (at least) boot with 652.8 MHz
1660 */
1661 [3] = 652800,
1662 };
1663
1664 return calc_voltage_level(cdclk,
1665 ARRAY_SIZE(ehl_voltage_level_max_cdclk),
1666 ehl_voltage_level_max_cdclk);
1667 }
1668
tgl_calc_voltage_level(int cdclk)1669 static u8 tgl_calc_voltage_level(int cdclk)
1670 {
1671 static const int tgl_voltage_level_max_cdclk[] = {
1672 [0] = 312000,
1673 [1] = 326400,
1674 [2] = 556800,
1675 [3] = 652800,
1676 };
1677
1678 return calc_voltage_level(cdclk,
1679 ARRAY_SIZE(tgl_voltage_level_max_cdclk),
1680 tgl_voltage_level_max_cdclk);
1681 }
1682
rplu_calc_voltage_level(int cdclk)1683 static u8 rplu_calc_voltage_level(int cdclk)
1684 {
1685 static const int rplu_voltage_level_max_cdclk[] = {
1686 [0] = 312000,
1687 [1] = 480000,
1688 [2] = 556800,
1689 [3] = 652800,
1690 };
1691
1692 return calc_voltage_level(cdclk,
1693 ARRAY_SIZE(rplu_voltage_level_max_cdclk),
1694 rplu_voltage_level_max_cdclk);
1695 }
1696
xe3lpd_calc_voltage_level(int cdclk)1697 static u8 xe3lpd_calc_voltage_level(int cdclk)
1698 {
1699 /*
1700 * Starting with xe3lpd power controller does not need the voltage
1701 * index when doing the modeset update. This function is best left
1702 * defined but returning 0 to the mask.
1703 */
1704 return 0;
1705 }
1706
icl_readout_refclk(struct intel_display * display,struct intel_cdclk_config * cdclk_config)1707 static void icl_readout_refclk(struct intel_display *display,
1708 struct intel_cdclk_config *cdclk_config)
1709 {
1710 u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
1711
1712 switch (dssm) {
1713 default:
1714 MISSING_CASE(dssm);
1715 fallthrough;
1716 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1717 cdclk_config->ref = 24000;
1718 break;
1719 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1720 cdclk_config->ref = 19200;
1721 break;
1722 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1723 cdclk_config->ref = 38400;
1724 break;
1725 }
1726 }
1727
bxt_de_pll_readout(struct intel_display * display,struct intel_cdclk_config * cdclk_config)1728 static void bxt_de_pll_readout(struct intel_display *display,
1729 struct intel_cdclk_config *cdclk_config)
1730 {
1731 u32 val, ratio;
1732
1733 if (display->platform.dg2)
1734 cdclk_config->ref = 38400;
1735 else if (DISPLAY_VER(display) >= 11)
1736 icl_readout_refclk(display, cdclk_config);
1737 else
1738 cdclk_config->ref = 19200;
1739
1740 val = intel_de_read(display, BXT_DE_PLL_ENABLE);
1741 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1742 (val & BXT_DE_PLL_LOCK) == 0) {
1743 /*
1744 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1745 * setting it to zero is a way to signal that.
1746 */
1747 cdclk_config->vco = 0;
1748 return;
1749 }
1750
1751 /*
1752 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register,
1753 * gen9lp had it in a separate PLL control register.
1754 */
1755 if (DISPLAY_VER(display) >= 11)
1756 ratio = val & ICL_CDCLK_PLL_RATIO_MASK;
1757 else
1758 ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
1759
1760 cdclk_config->vco = ratio * cdclk_config->ref;
1761 }
1762
bxt_get_cdclk(struct intel_display * display,struct intel_cdclk_config * cdclk_config)1763 static void bxt_get_cdclk(struct intel_display *display,
1764 struct intel_cdclk_config *cdclk_config)
1765 {
1766 u32 squash_ctl = 0;
1767 u32 divider;
1768 int div;
1769
1770 bxt_de_pll_readout(display, cdclk_config);
1771
1772 if (DISPLAY_VER(display) >= 12)
1773 cdclk_config->bypass = cdclk_config->ref / 2;
1774 else if (DISPLAY_VER(display) >= 11)
1775 cdclk_config->bypass = 50000;
1776 else
1777 cdclk_config->bypass = cdclk_config->ref;
1778
1779 if (cdclk_config->vco == 0) {
1780 cdclk_config->cdclk = cdclk_config->bypass;
1781 goto out;
1782 }
1783
1784 divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1785
1786 switch (divider) {
1787 case BXT_CDCLK_CD2X_DIV_SEL_1:
1788 div = 2;
1789 break;
1790 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1791 div = 3;
1792 break;
1793 case BXT_CDCLK_CD2X_DIV_SEL_2:
1794 div = 4;
1795 break;
1796 case BXT_CDCLK_CD2X_DIV_SEL_4:
1797 div = 8;
1798 break;
1799 default:
1800 MISSING_CASE(divider);
1801 return;
1802 }
1803
1804 if (HAS_CDCLK_SQUASH(display))
1805 squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL);
1806
1807 if (squash_ctl & CDCLK_SQUASH_ENABLE) {
1808 u16 waveform;
1809 int size;
1810
1811 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1;
1812 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size);
1813
1814 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) *
1815 cdclk_config->vco, size * div);
1816 } else {
1817 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
1818 }
1819
1820 out:
1821 if (DISPLAY_VER(display) >= 20)
1822 cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;
1823 /*
1824 * Can't read this out :( Let's assume it's
1825 * at least what the CDCLK frequency requires.
1826 */
1827 cdclk_config->voltage_level =
1828 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk);
1829 }
1830
bxt_de_pll_disable(struct intel_display * display)1831 static void bxt_de_pll_disable(struct intel_display *display)
1832 {
1833 intel_de_write(display, BXT_DE_PLL_ENABLE, 0);
1834
1835 /* Timeout 200us */
1836 if (intel_de_wait_for_clear_ms(display,
1837 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1838 drm_err(display->drm, "timeout waiting for DE PLL unlock\n");
1839
1840 display->cdclk.hw.vco = 0;
1841 }
1842
bxt_de_pll_enable(struct intel_display * display,int vco)1843 static void bxt_de_pll_enable(struct intel_display *display, int vco)
1844 {
1845 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1846
1847 intel_de_rmw(display, BXT_DE_PLL_CTL,
1848 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio));
1849
1850 intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1851
1852 /* Timeout 200us */
1853 if (intel_de_wait_for_set_ms(display,
1854 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1855 drm_err(display->drm, "timeout waiting for DE PLL lock\n");
1856
1857 display->cdclk.hw.vco = vco;
1858 }
1859
icl_cdclk_pll_disable(struct intel_display * display)1860 static void icl_cdclk_pll_disable(struct intel_display *display)
1861 {
1862 /*
1863 * Wa_13012396614:
1864 * Fixes: A sporadic race condition between MDCLK selection and PLL
1865 * enabling.
1866 * Workaround:
1867 * Change programming of MDCLK source selection in CDCLK_CTL:
1868 * - When disabling the CDCLK PLL, first set MDCLK source to be CD2XCLK.
1869 * - When enabling the CDCLK PLL, update MDCLK source selection only
1870 * after the PLL is enabled (which is already done as part of the
1871 * normal flow of _bxt_set_cdclk()).
1872 */
1873 if (intel_display_wa(display, 13012396614))
1874 intel_de_rmw(display, CDCLK_CTL, MDCLK_SOURCE_SEL_MASK, MDCLK_SOURCE_SEL_CD2XCLK);
1875
1876 intel_de_rmw(display, BXT_DE_PLL_ENABLE,
1877 BXT_DE_PLL_PLL_ENABLE, 0);
1878
1879 /* Timeout 200us */
1880 if (intel_de_wait_for_clear_ms(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1881 drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n");
1882
1883 display->cdclk.hw.vco = 0;
1884 }
1885
icl_cdclk_pll_enable(struct intel_display * display,int vco)1886 static void icl_cdclk_pll_enable(struct intel_display *display, int vco)
1887 {
1888 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1889 u32 val;
1890
1891 val = ICL_CDCLK_PLL_RATIO(ratio);
1892 intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1893
1894 val |= BXT_DE_PLL_PLL_ENABLE;
1895 intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1896
1897 /* Timeout 200us */
1898 if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1899 drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n");
1900
1901 display->cdclk.hw.vco = vco;
1902 }
1903
adlp_cdclk_pll_crawl(struct intel_display * display,int vco)1904 static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco)
1905 {
1906 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1907 u32 val;
1908
1909 /* Write PLL ratio without disabling */
1910 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
1911 intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1912
1913 /* Submit freq change request */
1914 val |= BXT_DE_PLL_FREQ_REQ;
1915 intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1916
1917 /* Timeout 200us */
1918 if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE,
1919 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
1920 drm_err(display->drm, "timeout waiting for FREQ change request ack\n");
1921
1922 val &= ~BXT_DE_PLL_FREQ_REQ;
1923 intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1924
1925 display->cdclk.hw.vco = vco;
1926 }
1927
bxt_cdclk_cd2x_pipe(struct intel_display * display,enum pipe pipe)1928 static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe)
1929 {
1930 if (DISPLAY_VER(display) >= 12) {
1931 if (pipe == INVALID_PIPE)
1932 return TGL_CDCLK_CD2X_PIPE_NONE;
1933 else
1934 return TGL_CDCLK_CD2X_PIPE(pipe);
1935 } else if (DISPLAY_VER(display) >= 11) {
1936 if (pipe == INVALID_PIPE)
1937 return ICL_CDCLK_CD2X_PIPE_NONE;
1938 else
1939 return ICL_CDCLK_CD2X_PIPE(pipe);
1940 } else {
1941 if (pipe == INVALID_PIPE)
1942 return BXT_CDCLK_CD2X_PIPE_NONE;
1943 else
1944 return BXT_CDCLK_CD2X_PIPE(pipe);
1945 }
1946 }
1947
bxt_cdclk_cd2x_div_sel(struct intel_display * display,int cdclk,int vco,u16 waveform)1948 static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display,
1949 int cdclk, int vco, u16 waveform)
1950 {
1951 u32 ret;
1952
1953 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1954 switch (cdclk_divider(cdclk, vco, waveform)) {
1955 default:
1956 drm_WARN_ON(display->drm,
1957 cdclk != display->cdclk.hw.bypass);
1958 drm_WARN_ON(display->drm, vco != 0);
1959 fallthrough;
1960 case 2:
1961 ret = BXT_CDCLK_CD2X_DIV_SEL_1;
1962 break;
1963 case 3:
1964 ret = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1965 break;
1966 case 4:
1967 ret = BXT_CDCLK_CD2X_DIV_SEL_2;
1968 break;
1969 case 8:
1970 ret = BXT_CDCLK_CD2X_DIV_SEL_4;
1971 break;
1972 }
1973
1974 /*
1975 * On Xe3_LPD onward, the expectation is to always have
1976 * BXT_CDCLK_CD2X_DIV_SEL_1 as the default.
1977 */
1978 if (DISPLAY_VER(display) >= 30)
1979 drm_WARN_ON(display->drm, ret != BXT_CDCLK_CD2X_DIV_SEL_1);
1980
1981 return ret;
1982 }
1983
cdclk_squash_waveform(struct intel_display * display,int cdclk)1984 static u16 cdclk_squash_waveform(struct intel_display *display,
1985 int cdclk)
1986 {
1987 const struct intel_cdclk_vals *table = display->cdclk.table;
1988 int i;
1989
1990 if (cdclk == display->cdclk.hw.bypass)
1991 return 0;
1992
1993 for (i = 0; table[i].refclk; i++)
1994 if (table[i].refclk == display->cdclk.hw.ref &&
1995 table[i].cdclk == cdclk)
1996 return table[i].waveform;
1997
1998 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",
1999 cdclk, display->cdclk.hw.ref);
2000
2001 return 0xffff;
2002 }
2003
icl_cdclk_pll_update(struct intel_display * display,int vco)2004 static void icl_cdclk_pll_update(struct intel_display *display, int vco)
2005 {
2006 if (display->cdclk.hw.vco != 0 &&
2007 display->cdclk.hw.vco != vco)
2008 icl_cdclk_pll_disable(display);
2009
2010 if (display->cdclk.hw.vco != vco)
2011 icl_cdclk_pll_enable(display, vco);
2012 }
2013
bxt_cdclk_pll_update(struct intel_display * display,int vco)2014 static void bxt_cdclk_pll_update(struct intel_display *display, int vco)
2015 {
2016 if (display->cdclk.hw.vco != 0 &&
2017 display->cdclk.hw.vco != vco)
2018 bxt_de_pll_disable(display);
2019
2020 if (display->cdclk.hw.vco != vco)
2021 bxt_de_pll_enable(display, vco);
2022 }
2023
dg2_cdclk_squash_program(struct intel_display * display,u16 waveform)2024 static void dg2_cdclk_squash_program(struct intel_display *display,
2025 u16 waveform)
2026 {
2027 u32 squash_ctl = 0;
2028
2029 if (waveform)
2030 squash_ctl = CDCLK_SQUASH_ENABLE |
2031 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
2032
2033 intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl);
2034 }
2035
cdclk_pll_is_unknown(unsigned int vco)2036 static bool cdclk_pll_is_unknown(unsigned int vco)
2037 {
2038 /*
2039 * Ensure driver does not take the crawl path for the
2040 * case when the vco is set to ~0 in the
2041 * sanitize path.
2042 */
2043 return vco == ~0;
2044 }
2045
mdclk_source_is_cdclk_pll(struct intel_display * display)2046 static bool mdclk_source_is_cdclk_pll(struct intel_display *display)
2047 {
2048 return DISPLAY_VER(display) >= 20;
2049 }
2050
xe2lpd_mdclk_source_sel(struct intel_display * display)2051 static u32 xe2lpd_mdclk_source_sel(struct intel_display *display)
2052 {
2053 if (mdclk_source_is_cdclk_pll(display))
2054 return MDCLK_SOURCE_SEL_CDCLK_PLL;
2055
2056 return MDCLK_SOURCE_SEL_CD2XCLK;
2057 }
2058
intel_mdclk_cdclk_ratio(struct intel_display * display,const struct intel_cdclk_config * cdclk_config)2059 int intel_mdclk_cdclk_ratio(struct intel_display *display,
2060 const struct intel_cdclk_config *cdclk_config)
2061 {
2062 if (mdclk_source_is_cdclk_pll(display))
2063 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);
2064
2065 /* Otherwise, source for MDCLK is CD2XCLK. */
2066 return 2;
2067 }
2068
xe2lpd_mdclk_cdclk_ratio_program(struct intel_display * display,const struct intel_cdclk_config * cdclk_config)2069 static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display,
2070 const struct intel_cdclk_config *cdclk_config)
2071 {
2072 intel_dbuf_mdclk_cdclk_ratio_update(display,
2073 intel_mdclk_cdclk_ratio(display, cdclk_config),
2074 cdclk_config->joined_mbus);
2075 }
2076
cdclk_compute_crawl_and_squash_midpoint(struct intel_display * display,const struct intel_cdclk_config * old_cdclk_config,const struct intel_cdclk_config * new_cdclk_config,struct intel_cdclk_config * mid_cdclk_config)2077 static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display,
2078 const struct intel_cdclk_config *old_cdclk_config,
2079 const struct intel_cdclk_config *new_cdclk_config,
2080 struct intel_cdclk_config *mid_cdclk_config)
2081 {
2082 u16 old_waveform, new_waveform, mid_waveform;
2083 int old_div, new_div, mid_div;
2084
2085 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */
2086 if (cdclk_pll_is_unknown(old_cdclk_config->vco))
2087 return false;
2088
2089 /* Return if both Squash and Crawl are not present */
2090 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))
2091 return false;
2092
2093 old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk);
2094 new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk);
2095
2096 /* Return if Squash only or Crawl only is the desired action */
2097 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 ||
2098 old_cdclk_config->vco == new_cdclk_config->vco ||
2099 old_waveform == new_waveform)
2100 return false;
2101
2102 old_div = cdclk_divider(old_cdclk_config->cdclk,
2103 old_cdclk_config->vco, old_waveform);
2104 new_div = cdclk_divider(new_cdclk_config->cdclk,
2105 new_cdclk_config->vco, new_waveform);
2106
2107 /*
2108 * Should not happen currently. We might need more midpoint
2109 * transitions if we need to also change the cd2x divider.
2110 */
2111 if (drm_WARN_ON(display->drm, old_div != new_div))
2112 return false;
2113
2114 *mid_cdclk_config = *new_cdclk_config;
2115
2116 /*
2117 * Populate the mid_cdclk_config accordingly.
2118 * - If moving to a higher cdclk, the desired action is squashing.
2119 * The mid cdclk config should have the new (squash) waveform.
2120 * - If moving to a lower cdclk, the desired action is crawling.
2121 * The mid cdclk config should have the new vco.
2122 */
2123
2124 if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) {
2125 mid_cdclk_config->vco = old_cdclk_config->vco;
2126 mid_div = old_div;
2127 mid_waveform = new_waveform;
2128 } else {
2129 mid_cdclk_config->vco = new_cdclk_config->vco;
2130 mid_div = new_div;
2131 mid_waveform = old_waveform;
2132 }
2133
2134 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
2135 mid_cdclk_config->vco,
2136 cdclk_squash_len * mid_div);
2137
2138 /* make sure the mid clock came out sane */
2139
2140 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk <
2141 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
2142 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk >
2143 display->cdclk.max_cdclk_freq);
2144 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) !=
2145 mid_waveform);
2146
2147 return true;
2148 }
2149
pll_enable_wa_needed(struct intel_display * display)2150 static bool pll_enable_wa_needed(struct intel_display *display)
2151 {
2152 return (DISPLAY_VERx100(display) == 2000 ||
2153 DISPLAY_VERx100(display) == 1400 ||
2154 display->platform.dg2) &&
2155 display->cdclk.hw.vco > 0;
2156 }
2157
bxt_cdclk_ctl(struct intel_display * display,const struct intel_cdclk_config * cdclk_config,enum pipe pipe)2158 static u32 bxt_cdclk_ctl(struct intel_display *display,
2159 const struct intel_cdclk_config *cdclk_config,
2160 enum pipe pipe)
2161 {
2162 int cdclk = cdclk_config->cdclk;
2163 int vco = cdclk_config->vco;
2164 u16 waveform;
2165 u32 val;
2166
2167 waveform = cdclk_squash_waveform(display, cdclk);
2168
2169 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform);
2170
2171 if (DISPLAY_VER(display) < 30)
2172 val |= bxt_cdclk_cd2x_pipe(display, pipe);
2173
2174 /*
2175 * Disable SSA Precharge when CD clock frequency < 500 MHz,
2176 * enable otherwise.
2177 */
2178 if ((display->platform.geminilake || display->platform.broxton) &&
2179 cdclk >= 500000)
2180 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
2181
2182 if (DISPLAY_VER(display) >= 20) {
2183 /*
2184 * Wa_13012396614 requires selecting CD2XCLK as MDCLK source
2185 * prior to disabling the PLL, which is already handled by
2186 * icl_cdclk_pll_disable(). Here we are just making sure
2187 * we keep the expected value.
2188 */
2189 if (intel_display_wa(display, 13012396614) && vco == 0)
2190 val |= MDCLK_SOURCE_SEL_CD2XCLK;
2191 else
2192 val |= xe2lpd_mdclk_source_sel(display);
2193 } else {
2194 val |= skl_cdclk_decimal(cdclk);
2195 }
2196
2197 return val;
2198 }
2199
_bxt_set_cdclk(struct intel_display * display,const struct intel_cdclk_config * cdclk_config,enum pipe pipe)2200 static void _bxt_set_cdclk(struct intel_display *display,
2201 const struct intel_cdclk_config *cdclk_config,
2202 enum pipe pipe)
2203 {
2204 int cdclk = cdclk_config->cdclk;
2205 int vco = cdclk_config->vco;
2206
2207 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 &&
2208 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) {
2209 if (display->cdclk.hw.vco != vco)
2210 adlp_cdclk_pll_crawl(display, vco);
2211 } else if (DISPLAY_VER(display) >= 11) {
2212 /* wa_15010685871: dg2, mtl */
2213 if (pll_enable_wa_needed(display))
2214 dg2_cdclk_squash_program(display, 0);
2215
2216 icl_cdclk_pll_update(display, vco);
2217 } else {
2218 bxt_cdclk_pll_update(display, vco);
2219 }
2220
2221 if (HAS_CDCLK_SQUASH(display)) {
2222 u16 waveform = cdclk_squash_waveform(display, cdclk);
2223
2224 dg2_cdclk_squash_program(display, waveform);
2225 }
2226
2227 intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe));
2228
2229 if (pipe != INVALID_PIPE)
2230 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));
2231 }
2232
bxt_set_cdclk(struct intel_display * display,const struct intel_cdclk_config * cdclk_config,enum pipe pipe)2233 static void bxt_set_cdclk(struct intel_display *display,
2234 const struct intel_cdclk_config *cdclk_config,
2235 enum pipe pipe)
2236 {
2237 struct intel_cdclk_config mid_cdclk_config;
2238 int cdclk = cdclk_config->cdclk;
2239 int ret = 0;
2240
2241 /*
2242 * Inform power controller of upcoming frequency change.
2243 * Display versions 14 and beyond do not follow the PUnit
2244 * mailbox communication, skip
2245 * this step.
2246 */
2247 if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
2248 ; /* NOOP */
2249 else if (DISPLAY_VER(display) >= 11)
2250 ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL,
2251 SKL_CDCLK_PREPARE_FOR_CHANGE,
2252 SKL_CDCLK_READY_FOR_CHANGE,
2253 SKL_CDCLK_READY_FOR_CHANGE, 3);
2254 else
2255 /*
2256 * BSpec requires us to wait up to 150usec, but that leads to
2257 * timeouts; the 2ms used here is based on experiment.
2258 */
2259 ret = intel_pcode_write_timeout(display->drm,
2260 HSW_PCODE_DE_WRITE_FREQ_REQ,
2261 0x80000000, 2);
2262
2263 if (ret) {
2264 drm_err(display->drm,
2265 "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
2266 ret, cdclk);
2267 return;
2268 }
2269
2270 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk)
2271 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
2272
2273 if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw,
2274 cdclk_config, &mid_cdclk_config)) {
2275 _bxt_set_cdclk(display, &mid_cdclk_config, pipe);
2276 _bxt_set_cdclk(display, cdclk_config, pipe);
2277 } else {
2278 _bxt_set_cdclk(display, cdclk_config, pipe);
2279 }
2280
2281 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)
2282 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
2283
2284 if (DISPLAY_VER(display) >= 14)
2285 /*
2286 * NOOP - No Pcode communication needed for
2287 * Display versions 14 and beyond
2288 */;
2289 else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2)
2290 ret = intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL,
2291 cdclk_config->voltage_level);
2292 if (DISPLAY_VER(display) < 11) {
2293 /*
2294 * The timeout isn't specified, the 2ms used here is based on
2295 * experiment.
2296 * FIXME: Waiting for the request completion could be delayed
2297 * until the next PCODE request based on BSpec.
2298 */
2299 ret = intel_pcode_write_timeout(display->drm,
2300 HSW_PCODE_DE_WRITE_FREQ_REQ,
2301 cdclk_config->voltage_level, 2);
2302 }
2303 if (ret) {
2304 drm_err(display->drm,
2305 "PCode CDCLK freq set failed, (err %d, freq %d)\n",
2306 ret, cdclk);
2307 return;
2308 }
2309
2310 intel_update_cdclk(display);
2311
2312 if (DISPLAY_VER(display) >= 11)
2313 /*
2314 * Can't read out the voltage level :(
2315 * Let's just assume everything is as expected.
2316 */
2317 display->cdclk.hw.voltage_level = cdclk_config->voltage_level;
2318 }
2319
bxt_sanitize_cdclk(struct intel_display * display)2320 static void bxt_sanitize_cdclk(struct intel_display *display)
2321 {
2322 u32 cdctl, expected;
2323 int cdclk, vco;
2324
2325 intel_update_cdclk(display);
2326 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
2327
2328 if (display->cdclk.hw.vco == 0 ||
2329 display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
2330 goto sanitize;
2331
2332 /* Make sure this is a legal cdclk value for the platform */
2333 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk);
2334 if (cdclk != display->cdclk.hw.cdclk)
2335 goto sanitize;
2336
2337 /* Make sure the VCO is correct for the cdclk */
2338 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
2339 if (vco != display->cdclk.hw.vco)
2340 goto sanitize;
2341
2342 /*
2343 * Some BIOS versions leave an incorrect decimal frequency value and
2344 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
2345 * so sanitize this register.
2346 */
2347 cdctl = intel_de_read(display, CDCLK_CTL);
2348 expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE);
2349
2350 /*
2351 * Let's ignore the pipe field, since BIOS could have configured the
2352 * dividers both syncing to an active pipe, or asynchronously
2353 * (PIPE_NONE).
2354 */
2355 cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
2356 expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
2357
2358 if (cdctl == expected)
2359 /* All well; nothing to sanitize */
2360 return;
2361
2362 sanitize:
2363 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
2364
2365 /* force cdclk programming */
2366 display->cdclk.hw.cdclk = 0;
2367
2368 /* force full PLL disable + enable */
2369 display->cdclk.hw.vco = ~0;
2370 }
2371
bxt_cdclk_init_hw(struct intel_display * display)2372 static void bxt_cdclk_init_hw(struct intel_display *display)
2373 {
2374 struct intel_cdclk_config cdclk_config;
2375
2376 bxt_sanitize_cdclk(display);
2377
2378 if (display->cdclk.hw.cdclk != 0 &&
2379 display->cdclk.hw.vco != 0)
2380 return;
2381
2382 cdclk_config = display->cdclk.hw;
2383
2384 /*
2385 * FIXME:
2386 * - The initial CDCLK needs to be read from VBT.
2387 * Need to make this change after VBT has changes for BXT.
2388 */
2389 cdclk_config.cdclk = bxt_calc_cdclk(display, 0);
2390 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk);
2391 cdclk_config.voltage_level =
2392 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);
2393
2394 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);
2395 }
2396
bxt_cdclk_uninit_hw(struct intel_display * display)2397 static void bxt_cdclk_uninit_hw(struct intel_display *display)
2398 {
2399 struct intel_cdclk_config cdclk_config = display->cdclk.hw;
2400
2401 cdclk_config.cdclk = cdclk_config.bypass;
2402 cdclk_config.vco = 0;
2403 cdclk_config.voltage_level =
2404 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);
2405
2406 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);
2407 }
2408
2409 /**
2410 * intel_cdclk_init_hw - Initialize CDCLK hardware
2411 * @display: display instance
2412 *
2413 * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and
2414 * sanitizing the state of the hardware if needed. This is generally done only
2415 * during the display core initialization sequence, after which the DMC will
2416 * take care of turning CDCLK off/on as needed.
2417 */
intel_cdclk_init_hw(struct intel_display * display)2418 void intel_cdclk_init_hw(struct intel_display *display)
2419 {
2420 if (DISPLAY_VER(display) >= 10 || display->platform.broxton)
2421 bxt_cdclk_init_hw(display);
2422 else if (DISPLAY_VER(display) == 9)
2423 skl_cdclk_init_hw(display);
2424 }
2425
2426 /**
2427 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
2428 * @display: display instance
2429 *
2430 * Uninitialize CDCLK. This is done only during the display core
2431 * uninitialization sequence.
2432 */
intel_cdclk_uninit_hw(struct intel_display * display)2433 void intel_cdclk_uninit_hw(struct intel_display *display)
2434 {
2435 if (DISPLAY_VER(display) >= 10 || display->platform.broxton)
2436 bxt_cdclk_uninit_hw(display);
2437 else if (DISPLAY_VER(display) == 9)
2438 skl_cdclk_uninit_hw(display);
2439 }
2440
intel_cdclk_can_crawl_and_squash(struct intel_display * display,const struct intel_cdclk_config * a,const struct intel_cdclk_config * b)2441 static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display,
2442 const struct intel_cdclk_config *a,
2443 const struct intel_cdclk_config *b)
2444 {
2445 u16 old_waveform;
2446 u16 new_waveform;
2447
2448 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco));
2449
2450 if (a->vco == 0 || b->vco == 0)
2451 return false;
2452
2453 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))
2454 return false;
2455
2456 old_waveform = cdclk_squash_waveform(display, a->cdclk);
2457 new_waveform = cdclk_squash_waveform(display, b->cdclk);
2458
2459 return a->vco != b->vco &&
2460 old_waveform != new_waveform;
2461 }
2462
intel_cdclk_can_crawl(struct intel_display * display,const struct intel_cdclk_config * a,const struct intel_cdclk_config * b)2463 static bool intel_cdclk_can_crawl(struct intel_display *display,
2464 const struct intel_cdclk_config *a,
2465 const struct intel_cdclk_config *b)
2466 {
2467 int a_div, b_div;
2468
2469 if (!HAS_CDCLK_CRAWL(display))
2470 return false;
2471
2472 /*
2473 * The vco and cd2x divider will change independently
2474 * from each, so we disallow cd2x change when crawling.
2475 */
2476 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
2477 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
2478
2479 return a->vco != 0 && b->vco != 0 &&
2480 a->vco != b->vco &&
2481 a_div == b_div &&
2482 a->ref == b->ref;
2483 }
2484
intel_cdclk_can_squash(struct intel_display * display,const struct intel_cdclk_config * a,const struct intel_cdclk_config * b)2485 static bool intel_cdclk_can_squash(struct intel_display *display,
2486 const struct intel_cdclk_config *a,
2487 const struct intel_cdclk_config *b)
2488 {
2489 /*
2490 * FIXME should store a bit more state in intel_cdclk_config
2491 * to differentiate squasher vs. cd2x divider properly. For
2492 * the moment all platforms with squasher use a fixed cd2x
2493 * divider.
2494 */
2495 if (!HAS_CDCLK_SQUASH(display))
2496 return false;
2497
2498 return a->cdclk != b->cdclk &&
2499 a->vco != 0 &&
2500 a->vco == b->vco &&
2501 a->ref == b->ref;
2502 }
2503
2504 /**
2505 * intel_cdclk_clock_changed - Check whether the clock changed
2506 * @a: first CDCLK configuration
2507 * @b: second CDCLK configuration
2508 *
2509 * Returns:
2510 * True if CDCLK changed in a way that requires re-programming and
2511 * False otherwise.
2512 */
intel_cdclk_clock_changed(const struct intel_cdclk_config * a,const struct intel_cdclk_config * b)2513 bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
2514 const struct intel_cdclk_config *b)
2515 {
2516 return a->cdclk != b->cdclk ||
2517 a->vco != b->vco ||
2518 a->ref != b->ref;
2519 }
2520
2521 /**
2522 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
2523 * configurations requires only a cd2x divider update
2524 * @display: display instance
2525 * @a: first CDCLK configuration
2526 * @b: second CDCLK configuration
2527 *
2528 * Returns:
2529 * True if changing between the two CDCLK configurations
2530 * can be done with just a cd2x divider update, false if not.
2531 */
intel_cdclk_can_cd2x_update(struct intel_display * display,const struct intel_cdclk_config * a,const struct intel_cdclk_config * b)2532 static bool intel_cdclk_can_cd2x_update(struct intel_display *display,
2533 const struct intel_cdclk_config *a,
2534 const struct intel_cdclk_config *b)
2535 {
2536 /* Older hw doesn't have the capability */
2537 if (DISPLAY_VER(display) < 10 && !display->platform.broxton)
2538 return false;
2539
2540 /*
2541 * FIXME should store a bit more state in intel_cdclk_config
2542 * to differentiate squasher vs. cd2x divider properly. For
2543 * the moment all platforms with squasher use a fixed cd2x
2544 * divider.
2545 */
2546 if (HAS_CDCLK_SQUASH(display))
2547 return false;
2548
2549 return a->cdclk != b->cdclk &&
2550 a->vco != 0 &&
2551 a->vco == b->vco &&
2552 a->ref == b->ref;
2553 }
2554
2555 /**
2556 * intel_cdclk_changed - Determine if two CDCLK configurations are different
2557 * @a: first CDCLK configuration
2558 * @b: second CDCLK configuration
2559 *
2560 * Returns:
2561 * True if the CDCLK configurations don't match, false if they do.
2562 */
intel_cdclk_changed(const struct intel_cdclk_config * a,const struct intel_cdclk_config * b)2563 static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
2564 const struct intel_cdclk_config *b)
2565 {
2566 return intel_cdclk_clock_changed(a, b) ||
2567 a->voltage_level != b->voltage_level;
2568 }
2569
intel_cdclk_dump_config(struct intel_display * display,const struct intel_cdclk_config * cdclk_config,const char * context)2570 void intel_cdclk_dump_config(struct intel_display *display,
2571 const struct intel_cdclk_config *cdclk_config,
2572 const char *context)
2573 {
2574 drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
2575 context, cdclk_config->cdclk, cdclk_config->vco,
2576 cdclk_config->ref, cdclk_config->bypass,
2577 cdclk_config->voltage_level);
2578 }
2579
intel_pcode_notify(struct intel_display * display,u8 voltage_level,u8 active_pipe_count,u16 cdclk,bool cdclk_update_valid,bool pipe_count_update_valid)2580 static void intel_pcode_notify(struct intel_display *display,
2581 u8 voltage_level,
2582 u8 active_pipe_count,
2583 u16 cdclk,
2584 bool cdclk_update_valid,
2585 bool pipe_count_update_valid)
2586 {
2587 int ret;
2588 u32 update_mask = 0;
2589
2590 if (!display->platform.dg2)
2591 return;
2592
2593 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level);
2594
2595 if (cdclk_update_valid)
2596 update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID;
2597
2598 if (pipe_count_update_valid)
2599 update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
2600
2601 ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL,
2602 SKL_CDCLK_PREPARE_FOR_CHANGE |
2603 update_mask,
2604 SKL_CDCLK_READY_FOR_CHANGE,
2605 SKL_CDCLK_READY_FOR_CHANGE, 3);
2606 if (ret)
2607 drm_err(display->drm,
2608 "Failed to inform PCU about display config (err %d)\n",
2609 ret);
2610 }
2611
intel_set_cdclk(struct intel_display * display,const struct intel_cdclk_config * cdclk_config,enum pipe pipe,const char * context)2612 static void intel_set_cdclk(struct intel_display *display,
2613 const struct intel_cdclk_config *cdclk_config,
2614 enum pipe pipe, const char *context)
2615 {
2616 struct intel_encoder *encoder;
2617
2618 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config))
2619 return;
2620
2621 if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk))
2622 return;
2623
2624 intel_cdclk_dump_config(display, cdclk_config, context);
2625
2626 for_each_intel_encoder_with_psr(display->drm, encoder) {
2627 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2628
2629 intel_psr_pause(intel_dp);
2630 }
2631
2632 intel_audio_cdclk_change_pre(display);
2633
2634 /*
2635 * Lock aux/gmbus while we change cdclk in case those
2636 * functions use cdclk. Not all platforms/ports do,
2637 * but we'll lock them all for simplicity.
2638 */
2639 mutex_lock(&display->gmbus.mutex);
2640 for_each_intel_dp(display->drm, encoder) {
2641 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2642
2643 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
2644 &display->gmbus.mutex);
2645 }
2646
2647 intel_cdclk_set_cdclk(display, cdclk_config, pipe);
2648
2649 for_each_intel_dp(display->drm, encoder) {
2650 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2651
2652 mutex_unlock(&intel_dp->aux.hw_mutex);
2653 }
2654 mutex_unlock(&display->gmbus.mutex);
2655
2656 for_each_intel_encoder_with_psr(display->drm, encoder) {
2657 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2658
2659 intel_psr_resume(intel_dp);
2660 }
2661
2662 intel_audio_cdclk_change_post(display);
2663
2664 if (drm_WARN(display->drm,
2665 intel_cdclk_changed(&display->cdclk.hw, cdclk_config),
2666 "cdclk state doesn't match!\n")) {
2667 intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]");
2668 intel_cdclk_dump_config(display, cdclk_config, "[sw state]");
2669 }
2670 }
2671
dg2_power_well_count(struct intel_display * display,const struct intel_cdclk_state * cdclk_state)2672 static bool dg2_power_well_count(struct intel_display *display,
2673 const struct intel_cdclk_state *cdclk_state)
2674 {
2675 return display->platform.dg2 ? hweight8(cdclk_state->active_pipes) : 0;
2676 }
2677
intel_cdclk_pcode_pre_notify(struct intel_atomic_state * state)2678 static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
2679 {
2680 struct intel_display *display = to_intel_display(state);
2681 const struct intel_cdclk_state *old_cdclk_state =
2682 intel_atomic_get_old_cdclk_state(state);
2683 const struct intel_cdclk_state *new_cdclk_state =
2684 intel_atomic_get_new_cdclk_state(state);
2685 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
2686 bool change_cdclk, update_pipe_count;
2687
2688 if (!intel_cdclk_changed(&old_cdclk_state->actual,
2689 &new_cdclk_state->actual) &&
2690 dg2_power_well_count(display, old_cdclk_state) ==
2691 dg2_power_well_count(display, new_cdclk_state))
2692 return;
2693
2694 /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */
2695 voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX;
2696
2697 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2698 update_pipe_count = dg2_power_well_count(display, new_cdclk_state) >
2699 dg2_power_well_count(display, old_cdclk_state);
2700
2701 /*
2702 * According to "Sequence Before Frequency Change",
2703 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK,
2704 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK,
2705 * which basically means we choose the maximum of old and new CDCLK, if we know both
2706 */
2707 if (change_cdclk)
2708 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);
2709
2710 /*
2711 * According to "Sequence For Pipe Count Change",
2712 * if pipe count is increasing, set bits 25:16 to upcoming pipe count
2713 * (power well is enabled)
2714 * no action if it is decreasing, before the change
2715 */
2716 if (update_pipe_count)
2717 num_active_pipes = dg2_power_well_count(display, new_cdclk_state);
2718
2719 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
2720 change_cdclk, update_pipe_count);
2721 }
2722
intel_cdclk_pcode_post_notify(struct intel_atomic_state * state)2723 static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
2724 {
2725 struct intel_display *display = to_intel_display(state);
2726 const struct intel_cdclk_state *new_cdclk_state =
2727 intel_atomic_get_new_cdclk_state(state);
2728 const struct intel_cdclk_state *old_cdclk_state =
2729 intel_atomic_get_old_cdclk_state(state);
2730 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
2731 bool update_cdclk, update_pipe_count;
2732
2733 /* According to "Sequence After Frequency Change", set voltage to used level */
2734 voltage_level = new_cdclk_state->actual.voltage_level;
2735
2736 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2737 update_pipe_count = dg2_power_well_count(display, new_cdclk_state) <
2738 dg2_power_well_count(display, old_cdclk_state);
2739
2740 /*
2741 * According to "Sequence After Frequency Change",
2742 * set bits 25:16 to current CDCLK
2743 */
2744 if (update_cdclk)
2745 cdclk = new_cdclk_state->actual.cdclk;
2746
2747 /*
2748 * According to "Sequence For Pipe Count Change",
2749 * if pipe count is decreasing, set bits 25:16 to current pipe count,
2750 * after the change(power well is disabled)
2751 * no action if it is increasing, after the change
2752 */
2753 if (update_pipe_count)
2754 num_active_pipes = dg2_power_well_count(display, new_cdclk_state);
2755
2756 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
2757 update_cdclk, update_pipe_count);
2758 }
2759
intel_cdclk_is_decreasing_later(struct intel_atomic_state * state)2760 bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)
2761 {
2762 const struct intel_cdclk_state *old_cdclk_state =
2763 intel_atomic_get_old_cdclk_state(state);
2764 const struct intel_cdclk_state *new_cdclk_state =
2765 intel_atomic_get_new_cdclk_state(state);
2766
2767 return new_cdclk_state && !new_cdclk_state->disable_pipes &&
2768 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk;
2769 }
2770
2771 /**
2772 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2773 * @state: intel atomic state
2774 *
2775 * Program the hardware before updating the HW plane state based on the
2776 * new CDCLK state, if necessary.
2777 */
2778 void
intel_set_cdclk_pre_plane_update(struct intel_atomic_state * state)2779 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
2780 {
2781 struct intel_display *display = to_intel_display(state);
2782 const struct intel_cdclk_state *old_cdclk_state =
2783 intel_atomic_get_old_cdclk_state(state);
2784 const struct intel_cdclk_state *new_cdclk_state =
2785 intel_atomic_get_new_cdclk_state(state);
2786 struct intel_cdclk_config cdclk_config;
2787 enum pipe pipe;
2788
2789 if (!new_cdclk_state)
2790 return;
2791
2792 if (!intel_cdclk_changed(&old_cdclk_state->actual,
2793 &new_cdclk_state->actual))
2794 return;
2795
2796 if (display->platform.dg2)
2797 intel_cdclk_pcode_pre_notify(state);
2798
2799 if (new_cdclk_state->disable_pipes) {
2800 cdclk_config = new_cdclk_state->actual;
2801 pipe = INVALID_PIPE;
2802 } else {
2803 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) {
2804 cdclk_config = new_cdclk_state->actual;
2805 pipe = new_cdclk_state->pipe;
2806 } else {
2807 cdclk_config = old_cdclk_state->actual;
2808 pipe = INVALID_PIPE;
2809 }
2810
2811 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level,
2812 old_cdclk_state->actual.voltage_level);
2813 }
2814
2815 /*
2816 * mbus joining will be changed later by
2817 * intel_dbuf_mbus_{pre,post}_ddb_update()
2818 */
2819 cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus;
2820
2821 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
2822
2823 intel_set_cdclk(display, &cdclk_config, pipe,
2824 "Pre changing CDCLK to");
2825 }
2826
2827 /**
2828 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2829 * @state: intel atomic state
2830 *
2831 * Program the hardware after updating the HW plane state based on the
2832 * new CDCLK state, if necessary.
2833 */
2834 void
intel_set_cdclk_post_plane_update(struct intel_atomic_state * state)2835 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
2836 {
2837 struct intel_display *display = to_intel_display(state);
2838 const struct intel_cdclk_state *old_cdclk_state =
2839 intel_atomic_get_old_cdclk_state(state);
2840 const struct intel_cdclk_state *new_cdclk_state =
2841 intel_atomic_get_new_cdclk_state(state);
2842 enum pipe pipe;
2843
2844 if (!new_cdclk_state)
2845 return;
2846
2847 if (!intel_cdclk_changed(&old_cdclk_state->actual,
2848 &new_cdclk_state->actual))
2849 return;
2850
2851 if (display->platform.dg2)
2852 intel_cdclk_pcode_post_notify(state);
2853
2854 if (!new_cdclk_state->disable_pipes &&
2855 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk)
2856 pipe = new_cdclk_state->pipe;
2857 else
2858 pipe = INVALID_PIPE;
2859
2860 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
2861
2862 intel_set_cdclk(display, &new_cdclk_state->actual, pipe,
2863 "Post changing CDCLK to");
2864 }
2865
2866 /* pixels per CDCLK */
intel_cdclk_ppc(struct intel_display * display,bool double_wide)2867 static int intel_cdclk_ppc(struct intel_display *display, bool double_wide)
2868 {
2869 return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1;
2870 }
2871
2872 /* max pixel rate as % of CDCLK (not accounting for PPC) */
intel_cdclk_guardband(struct intel_display * display)2873 static int intel_cdclk_guardband(struct intel_display *display)
2874 {
2875 if (DISPLAY_VER(display) >= 9 ||
2876 display->platform.broadwell || display->platform.haswell)
2877 return 100;
2878 else if (display->platform.cherryview)
2879 return 95;
2880 else
2881 return 90;
2882 }
2883
_intel_pixel_rate_to_cdclk(const struct intel_crtc_state * crtc_state,int pixel_rate)2884 static int _intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state, int pixel_rate)
2885 {
2886 struct intel_display *display = to_intel_display(crtc_state);
2887 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);
2888 int guardband = intel_cdclk_guardband(display);
2889
2890 return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc);
2891 }
2892
intel_pixel_rate_to_cdclk(const struct intel_crtc_state * crtc_state)2893 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
2894 {
2895 return _intel_pixel_rate_to_cdclk(crtc_state, crtc_state->pixel_rate);
2896 }
2897
intel_planes_min_cdclk(const struct intel_crtc_state * crtc_state)2898 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
2899 {
2900 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2901 struct intel_display *display = to_intel_display(crtc);
2902 struct intel_plane *plane;
2903 int min_cdclk = 0;
2904
2905 for_each_intel_plane_on_crtc(display->drm, crtc, plane)
2906 min_cdclk = max(min_cdclk, crtc_state->plane_min_cdclk[plane->id]);
2907
2908 return min_cdclk;
2909 }
2910
intel_crtc_min_cdclk(const struct intel_crtc_state * crtc_state)2911 int intel_crtc_min_cdclk(const struct intel_crtc_state *crtc_state)
2912 {
2913 int min_cdclk;
2914
2915 if (!crtc_state->hw.enable)
2916 return 0;
2917
2918 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
2919 min_cdclk = max(min_cdclk, intel_crtc_bw_min_cdclk(crtc_state));
2920 min_cdclk = max(min_cdclk, intel_fbc_min_cdclk(crtc_state));
2921 min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state));
2922 min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state));
2923 min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state));
2924 min_cdclk = max(min_cdclk, intel_planes_min_cdclk(crtc_state));
2925 min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
2926
2927 return min_cdclk;
2928 }
2929
intel_cdclk_update_crtc_min_cdclk(struct intel_atomic_state * state,struct intel_crtc * crtc,int old_min_cdclk,int new_min_cdclk,bool * need_cdclk_calc)2930 static int intel_cdclk_update_crtc_min_cdclk(struct intel_atomic_state *state,
2931 struct intel_crtc *crtc,
2932 int old_min_cdclk, int new_min_cdclk,
2933 bool *need_cdclk_calc)
2934 {
2935 struct intel_display *display = to_intel_display(state);
2936 struct intel_cdclk_state *cdclk_state;
2937 bool allow_cdclk_decrease = intel_any_crtc_needs_modeset(state);
2938 int ret;
2939
2940 if (new_min_cdclk == old_min_cdclk)
2941 return 0;
2942
2943 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk)
2944 return 0;
2945
2946 cdclk_state = intel_atomic_get_cdclk_state(state);
2947 if (IS_ERR(cdclk_state))
2948 return PTR_ERR(cdclk_state);
2949
2950 old_min_cdclk = cdclk_state->min_cdclk[crtc->pipe];
2951
2952 if (new_min_cdclk == old_min_cdclk)
2953 return 0;
2954
2955 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk)
2956 return 0;
2957
2958 cdclk_state->min_cdclk[crtc->pipe] = new_min_cdclk;
2959
2960 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2961 if (ret)
2962 return ret;
2963
2964 *need_cdclk_calc = true;
2965
2966 drm_dbg_kms(display->drm,
2967 "[CRTC:%d:%s] min cdclk: %d kHz -> %d kHz\n",
2968 crtc->base.base.id, crtc->base.name,
2969 old_min_cdclk, new_min_cdclk);
2970
2971 return 0;
2972 }
2973
intel_cdclk_update_dbuf_bw_min_cdclk(struct intel_atomic_state * state,int old_min_cdclk,int new_min_cdclk,bool * need_cdclk_calc)2974 int intel_cdclk_update_dbuf_bw_min_cdclk(struct intel_atomic_state *state,
2975 int old_min_cdclk, int new_min_cdclk,
2976 bool *need_cdclk_calc)
2977 {
2978 struct intel_display *display = to_intel_display(state);
2979 struct intel_cdclk_state *cdclk_state;
2980 bool allow_cdclk_decrease = intel_any_crtc_needs_modeset(state);
2981 int ret;
2982
2983 if (new_min_cdclk == old_min_cdclk)
2984 return 0;
2985
2986 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk)
2987 return 0;
2988
2989 cdclk_state = intel_atomic_get_cdclk_state(state);
2990 if (IS_ERR(cdclk_state))
2991 return PTR_ERR(cdclk_state);
2992
2993 old_min_cdclk = cdclk_state->dbuf_bw_min_cdclk;
2994
2995 if (new_min_cdclk == old_min_cdclk)
2996 return 0;
2997
2998 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk)
2999 return 0;
3000
3001 cdclk_state->dbuf_bw_min_cdclk = new_min_cdclk;
3002
3003 ret = intel_atomic_lock_global_state(&cdclk_state->base);
3004 if (ret)
3005 return ret;
3006
3007 *need_cdclk_calc = true;
3008
3009 drm_dbg_kms(display->drm,
3010 "dbuf bandwidth min cdclk: %d kHz -> %d kHz\n",
3011 old_min_cdclk, new_min_cdclk);
3012
3013 return 0;
3014 }
3015
glk_cdclk_audio_wa_needed(struct intel_display * display,const struct intel_cdclk_state * cdclk_state)3016 static bool glk_cdclk_audio_wa_needed(struct intel_display *display,
3017 const struct intel_cdclk_state *cdclk_state)
3018 {
3019 return display->platform.geminilake &&
3020 cdclk_state->enabled_pipes &&
3021 !is_power_of_2(cdclk_state->enabled_pipes);
3022 }
3023
intel_compute_min_cdclk(struct intel_atomic_state * state)3024 static int intel_compute_min_cdclk(struct intel_atomic_state *state)
3025 {
3026 struct intel_display *display = to_intel_display(state);
3027 struct intel_cdclk_state *cdclk_state =
3028 intel_atomic_get_new_cdclk_state(state);
3029 enum pipe pipe;
3030 int min_cdclk;
3031
3032 min_cdclk = cdclk_state->force_min_cdclk;
3033 min_cdclk = max(min_cdclk, cdclk_state->dbuf_bw_min_cdclk);
3034 for_each_pipe(display, pipe)
3035 min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]);
3036
3037 /*
3038 * Avoid glk_force_audio_cdclk() causing excessive screen
3039 * blinking when multiple pipes are active by making sure
3040 * CDCLK frequency is always high enough for audio. With a
3041 * single active pipe we can always change CDCLK frequency
3042 * by changing the cd2x divider (see glk_cdclk_table[]) and
3043 * thus a full modeset won't be needed then.
3044 */
3045 if (glk_cdclk_audio_wa_needed(display, cdclk_state))
3046 min_cdclk = max(min_cdclk, 2 * 96000);
3047
3048 if (min_cdclk > display->cdclk.max_cdclk_freq) {
3049 drm_dbg_kms(display->drm,
3050 "required cdclk (%d kHz) exceeds max (%d kHz)\n",
3051 min_cdclk, display->cdclk.max_cdclk_freq);
3052 return -EINVAL;
3053 }
3054
3055 return min_cdclk;
3056 }
3057
3058 /*
3059 * Account for port clock min voltage level requirements.
3060 * This only really does something on DISPLA_VER >= 11 but can be
3061 * called on earlier platforms as well.
3062 *
3063 * Note that this functions assumes that 0 is
3064 * the lowest voltage value, and higher values
3065 * correspond to increasingly higher voltages.
3066 *
3067 * Should that relationship no longer hold on
3068 * future platforms this code will need to be
3069 * adjusted.
3070 */
bxt_compute_min_voltage_level(struct intel_atomic_state * state)3071 static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
3072 {
3073 struct intel_display *display = to_intel_display(state);
3074 struct intel_cdclk_state *cdclk_state =
3075 intel_atomic_get_new_cdclk_state(state);
3076 struct intel_crtc *crtc;
3077 struct intel_crtc_state *crtc_state;
3078 u8 min_voltage_level;
3079 int i;
3080 enum pipe pipe;
3081
3082 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
3083 int ret;
3084
3085 if (crtc_state->hw.enable)
3086 min_voltage_level = crtc_state->min_voltage_level;
3087 else
3088 min_voltage_level = 0;
3089
3090 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level)
3091 continue;
3092
3093 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level;
3094
3095 ret = intel_atomic_lock_global_state(&cdclk_state->base);
3096 if (ret)
3097 return ret;
3098 }
3099
3100 min_voltage_level = 0;
3101 for_each_pipe(display, pipe)
3102 min_voltage_level = max(min_voltage_level,
3103 cdclk_state->min_voltage_level[pipe]);
3104
3105 return min_voltage_level;
3106 }
3107
vlv_modeset_calc_cdclk(struct intel_atomic_state * state)3108 static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
3109 {
3110 struct intel_display *display = to_intel_display(state);
3111 struct intel_cdclk_state *cdclk_state =
3112 intel_atomic_get_new_cdclk_state(state);
3113 int min_cdclk, cdclk;
3114
3115 min_cdclk = intel_compute_min_cdclk(state);
3116 if (min_cdclk < 0)
3117 return min_cdclk;
3118
3119 cdclk = vlv_calc_cdclk(display, min_cdclk);
3120
3121 cdclk_state->logical.cdclk = cdclk;
3122 cdclk_state->logical.voltage_level =
3123 vlv_calc_voltage_level(display, cdclk);
3124
3125 if (!cdclk_state->active_pipes) {
3126 cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk);
3127
3128 cdclk_state->actual.cdclk = cdclk;
3129 cdclk_state->actual.voltage_level =
3130 vlv_calc_voltage_level(display, cdclk);
3131 } else {
3132 cdclk_state->actual = cdclk_state->logical;
3133 }
3134
3135 return 0;
3136 }
3137
bdw_modeset_calc_cdclk(struct intel_atomic_state * state)3138 static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
3139 {
3140 struct intel_cdclk_state *cdclk_state =
3141 intel_atomic_get_new_cdclk_state(state);
3142 int min_cdclk, cdclk;
3143
3144 min_cdclk = intel_compute_min_cdclk(state);
3145 if (min_cdclk < 0)
3146 return min_cdclk;
3147
3148 cdclk = bdw_calc_cdclk(min_cdclk);
3149
3150 cdclk_state->logical.cdclk = cdclk;
3151 cdclk_state->logical.voltage_level =
3152 bdw_calc_voltage_level(cdclk);
3153
3154 if (!cdclk_state->active_pipes) {
3155 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk);
3156
3157 cdclk_state->actual.cdclk = cdclk;
3158 cdclk_state->actual.voltage_level =
3159 bdw_calc_voltage_level(cdclk);
3160 } else {
3161 cdclk_state->actual = cdclk_state->logical;
3162 }
3163
3164 return 0;
3165 }
3166
skl_dpll0_vco(struct intel_atomic_state * state)3167 static int skl_dpll0_vco(struct intel_atomic_state *state)
3168 {
3169 struct intel_display *display = to_intel_display(state);
3170 struct intel_cdclk_state *cdclk_state =
3171 intel_atomic_get_new_cdclk_state(state);
3172 struct intel_crtc *crtc;
3173 struct intel_crtc_state *crtc_state;
3174 int vco, i;
3175
3176 vco = cdclk_state->logical.vco;
3177 if (!vco)
3178 vco = display->cdclk.skl_preferred_vco_freq;
3179
3180 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
3181 if (!crtc_state->hw.enable)
3182 continue;
3183
3184 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
3185 continue;
3186
3187 /*
3188 * DPLL0 VCO may need to be adjusted to get the correct
3189 * clock for eDP. This will affect cdclk as well.
3190 */
3191 switch (crtc_state->port_clock / 2) {
3192 case 108000:
3193 case 216000:
3194 vco = 8640000;
3195 break;
3196 default:
3197 vco = 8100000;
3198 break;
3199 }
3200 }
3201
3202 return vco;
3203 }
3204
skl_modeset_calc_cdclk(struct intel_atomic_state * state)3205 static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
3206 {
3207 struct intel_cdclk_state *cdclk_state =
3208 intel_atomic_get_new_cdclk_state(state);
3209 int min_cdclk, cdclk, vco;
3210
3211 min_cdclk = intel_compute_min_cdclk(state);
3212 if (min_cdclk < 0)
3213 return min_cdclk;
3214
3215 vco = skl_dpll0_vco(state);
3216
3217 cdclk = skl_calc_cdclk(min_cdclk, vco);
3218
3219 cdclk_state->logical.vco = vco;
3220 cdclk_state->logical.cdclk = cdclk;
3221 cdclk_state->logical.voltage_level =
3222 skl_calc_voltage_level(cdclk);
3223
3224 if (!cdclk_state->active_pipes) {
3225 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);
3226
3227 cdclk_state->actual.vco = vco;
3228 cdclk_state->actual.cdclk = cdclk;
3229 cdclk_state->actual.voltage_level =
3230 skl_calc_voltage_level(cdclk);
3231 } else {
3232 cdclk_state->actual = cdclk_state->logical;
3233 }
3234
3235 return 0;
3236 }
3237
bxt_modeset_calc_cdclk(struct intel_atomic_state * state)3238 static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
3239 {
3240 struct intel_display *display = to_intel_display(state);
3241 struct intel_cdclk_state *cdclk_state =
3242 intel_atomic_get_new_cdclk_state(state);
3243 int min_cdclk, min_voltage_level, cdclk, vco;
3244
3245 min_cdclk = intel_compute_min_cdclk(state);
3246 if (min_cdclk < 0)
3247 return min_cdclk;
3248
3249 min_voltage_level = bxt_compute_min_voltage_level(state);
3250 if (min_voltage_level < 0)
3251 return min_voltage_level;
3252
3253 cdclk = bxt_calc_cdclk(display, min_cdclk);
3254 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
3255
3256 cdclk_state->logical.vco = vco;
3257 cdclk_state->logical.cdclk = cdclk;
3258 cdclk_state->logical.voltage_level =
3259 max_t(int, min_voltage_level,
3260 intel_cdclk_calc_voltage_level(display, cdclk));
3261
3262 if (!cdclk_state->active_pipes) {
3263 cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk);
3264 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
3265
3266 cdclk_state->actual.vco = vco;
3267 cdclk_state->actual.cdclk = cdclk;
3268 cdclk_state->actual.voltage_level =
3269 intel_cdclk_calc_voltage_level(display, cdclk);
3270 } else {
3271 cdclk_state->actual = cdclk_state->logical;
3272 }
3273
3274 return 0;
3275 }
3276
fixed_modeset_calc_cdclk(struct intel_atomic_state * state)3277 static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state)
3278 {
3279 int min_cdclk;
3280
3281 /*
3282 * We can't change the cdclk frequency, but we still want to
3283 * check that the required minimum frequency doesn't exceed
3284 * the actual cdclk frequency.
3285 */
3286 min_cdclk = intel_compute_min_cdclk(state);
3287 if (min_cdclk < 0)
3288 return min_cdclk;
3289
3290 return 0;
3291 }
3292
intel_cdclk_duplicate_state(struct intel_global_obj * obj)3293 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
3294 {
3295 struct intel_cdclk_state *cdclk_state;
3296
3297 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
3298 if (!cdclk_state)
3299 return NULL;
3300
3301 cdclk_state->pipe = INVALID_PIPE;
3302 cdclk_state->disable_pipes = false;
3303
3304 return &cdclk_state->base;
3305 }
3306
intel_cdclk_destroy_state(struct intel_global_obj * obj,struct intel_global_state * state)3307 static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
3308 struct intel_global_state *state)
3309 {
3310 kfree(state);
3311 }
3312
3313 static const struct intel_global_state_funcs intel_cdclk_funcs = {
3314 .atomic_duplicate_state = intel_cdclk_duplicate_state,
3315 .atomic_destroy_state = intel_cdclk_destroy_state,
3316 };
3317
3318 struct intel_cdclk_state *
intel_atomic_get_cdclk_state(struct intel_atomic_state * state)3319 intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
3320 {
3321 struct intel_display *display = to_intel_display(state);
3322 struct intel_global_state *cdclk_state;
3323
3324 cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj);
3325 if (IS_ERR(cdclk_state))
3326 return ERR_CAST(cdclk_state);
3327
3328 return to_intel_cdclk_state(cdclk_state);
3329 }
3330
intel_cdclk_modeset_checks(struct intel_atomic_state * state,bool * need_cdclk_calc)3331 static int intel_cdclk_modeset_checks(struct intel_atomic_state *state,
3332 bool *need_cdclk_calc)
3333 {
3334 struct intel_display *display = to_intel_display(state);
3335 const struct intel_cdclk_state *old_cdclk_state;
3336 struct intel_cdclk_state *new_cdclk_state;
3337 int ret;
3338
3339 if (!intel_any_crtc_enable_changed(state) &&
3340 !intel_any_crtc_active_changed(state))
3341 return 0;
3342
3343 new_cdclk_state = intel_atomic_get_cdclk_state(state);
3344 if (IS_ERR(new_cdclk_state))
3345 return PTR_ERR(new_cdclk_state);
3346
3347 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
3348
3349 new_cdclk_state->enabled_pipes =
3350 intel_calc_enabled_pipes(state, old_cdclk_state->enabled_pipes);
3351
3352 new_cdclk_state->active_pipes =
3353 intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
3354
3355 ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
3356 if (ret)
3357 return ret;
3358
3359 if (!old_cdclk_state->active_pipes != !new_cdclk_state->active_pipes)
3360 *need_cdclk_calc = true;
3361
3362 if (glk_cdclk_audio_wa_needed(display, old_cdclk_state) !=
3363 glk_cdclk_audio_wa_needed(display, new_cdclk_state))
3364 *need_cdclk_calc = true;
3365
3366 if (dg2_power_well_count(display, old_cdclk_state) !=
3367 dg2_power_well_count(display, new_cdclk_state))
3368 *need_cdclk_calc = true;
3369
3370 return 0;
3371 }
3372
intel_crtcs_calc_min_cdclk(struct intel_atomic_state * state,bool * need_cdclk_calc)3373 static int intel_crtcs_calc_min_cdclk(struct intel_atomic_state *state,
3374 bool *need_cdclk_calc)
3375 {
3376 const struct intel_crtc_state *old_crtc_state;
3377 const struct intel_crtc_state *new_crtc_state;
3378 struct intel_crtc *crtc;
3379 int i, ret;
3380
3381 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
3382 new_crtc_state, i) {
3383 ret = intel_cdclk_update_crtc_min_cdclk(state, crtc,
3384 old_crtc_state->min_cdclk,
3385 new_crtc_state->min_cdclk,
3386 need_cdclk_calc);
3387 if (ret)
3388 return ret;
3389 }
3390
3391 return 0;
3392 }
3393
intel_cdclk_state_set_joined_mbus(struct intel_atomic_state * state,bool joined_mbus)3394 int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus)
3395 {
3396 struct intel_cdclk_state *cdclk_state;
3397
3398 cdclk_state = intel_atomic_get_cdclk_state(state);
3399 if (IS_ERR(cdclk_state))
3400 return PTR_ERR(cdclk_state);
3401
3402 cdclk_state->actual.joined_mbus = joined_mbus;
3403 cdclk_state->logical.joined_mbus = joined_mbus;
3404
3405 return intel_atomic_lock_global_state(&cdclk_state->base);
3406 }
3407
intel_cdclk_init(struct intel_display * display)3408 int intel_cdclk_init(struct intel_display *display)
3409 {
3410 struct intel_cdclk_state *cdclk_state;
3411
3412 cdclk_state = kzalloc_obj(*cdclk_state);
3413 if (!cdclk_state)
3414 return -ENOMEM;
3415
3416 intel_atomic_global_obj_init(display, &display->cdclk.obj,
3417 &cdclk_state->base, &intel_cdclk_funcs);
3418
3419 return 0;
3420 }
3421
intel_cdclk_need_serialize(struct intel_display * display,const struct intel_cdclk_state * old_cdclk_state,const struct intel_cdclk_state * new_cdclk_state)3422 static bool intel_cdclk_need_serialize(struct intel_display *display,
3423 const struct intel_cdclk_state *old_cdclk_state,
3424 const struct intel_cdclk_state *new_cdclk_state)
3425 {
3426 /*
3427 * We need to poke hw for DG2, because we notify PCode if
3428 * pipe power well count changes.
3429 */
3430 return intel_cdclk_changed(&old_cdclk_state->actual,
3431 &new_cdclk_state->actual) ||
3432 dg2_power_well_count(display, old_cdclk_state) !=
3433 dg2_power_well_count(display, new_cdclk_state);
3434 }
3435
intel_modeset_calc_cdclk(struct intel_atomic_state * state)3436 static int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
3437 {
3438 struct intel_display *display = to_intel_display(state);
3439 const struct intel_cdclk_state *old_cdclk_state;
3440 struct intel_cdclk_state *new_cdclk_state;
3441 enum pipe pipe = INVALID_PIPE;
3442 int ret;
3443
3444 new_cdclk_state = intel_atomic_get_cdclk_state(state);
3445 if (IS_ERR(new_cdclk_state))
3446 return PTR_ERR(new_cdclk_state);
3447
3448 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
3449
3450 ret = intel_cdclk_modeset_calc_cdclk(state);
3451 if (ret)
3452 return ret;
3453
3454 if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) {
3455 /*
3456 * Also serialize commits across all crtcs
3457 * if the actual hw needs to be poked.
3458 */
3459 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
3460 if (ret)
3461 return ret;
3462 } else if (intel_cdclk_changed(&old_cdclk_state->logical,
3463 &new_cdclk_state->logical)) {
3464 ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
3465 if (ret)
3466 return ret;
3467 } else {
3468 return 0;
3469 }
3470
3471 if (is_power_of_2(new_cdclk_state->active_pipes) &&
3472 intel_cdclk_can_cd2x_update(display,
3473 &old_cdclk_state->actual,
3474 &new_cdclk_state->actual)) {
3475 struct intel_crtc *crtc;
3476 struct intel_crtc_state *crtc_state;
3477
3478 pipe = ilog2(new_cdclk_state->active_pipes);
3479 crtc = intel_crtc_for_pipe(display, pipe);
3480
3481 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
3482 if (IS_ERR(crtc_state))
3483 return PTR_ERR(crtc_state);
3484
3485 if (intel_crtc_needs_modeset(crtc_state))
3486 pipe = INVALID_PIPE;
3487 }
3488
3489 if (intel_cdclk_can_crawl_and_squash(display,
3490 &old_cdclk_state->actual,
3491 &new_cdclk_state->actual)) {
3492 drm_dbg_kms(display->drm,
3493 "Can change cdclk via crawling and squashing\n");
3494 } else if (intel_cdclk_can_squash(display,
3495 &old_cdclk_state->actual,
3496 &new_cdclk_state->actual)) {
3497 drm_dbg_kms(display->drm,
3498 "Can change cdclk via squashing\n");
3499 } else if (intel_cdclk_can_crawl(display,
3500 &old_cdclk_state->actual,
3501 &new_cdclk_state->actual)) {
3502 drm_dbg_kms(display->drm,
3503 "Can change cdclk via crawling\n");
3504 } else if (pipe != INVALID_PIPE) {
3505 new_cdclk_state->pipe = pipe;
3506
3507 drm_dbg_kms(display->drm,
3508 "Can change cdclk cd2x divider with pipe %c active\n",
3509 pipe_name(pipe));
3510 } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual,
3511 &new_cdclk_state->actual)) {
3512 /* All pipes must be switched off while we change the cdclk. */
3513 ret = intel_modeset_all_pipes_late(state, "CDCLK change");
3514 if (ret)
3515 return ret;
3516
3517 new_cdclk_state->disable_pipes = true;
3518
3519 drm_dbg_kms(display->drm,
3520 "Modeset required for cdclk change\n");
3521 }
3522
3523 if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) !=
3524 intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) {
3525 int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual);
3526
3527 ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio);
3528 if (ret)
3529 return ret;
3530 }
3531
3532 drm_dbg_kms(display->drm,
3533 "New cdclk calculated to be logical %u kHz, actual %u kHz\n",
3534 new_cdclk_state->logical.cdclk,
3535 new_cdclk_state->actual.cdclk);
3536 drm_dbg_kms(display->drm,
3537 "New voltage level calculated to be logical %u, actual %u\n",
3538 new_cdclk_state->logical.voltage_level,
3539 new_cdclk_state->actual.voltage_level);
3540
3541 return 0;
3542 }
3543
intel_cdclk_atomic_check(struct intel_atomic_state * state)3544 int intel_cdclk_atomic_check(struct intel_atomic_state *state)
3545 {
3546 const struct intel_cdclk_state *old_cdclk_state;
3547 struct intel_cdclk_state *new_cdclk_state;
3548 bool need_cdclk_calc = false;
3549 int ret;
3550
3551 ret = intel_cdclk_modeset_checks(state, &need_cdclk_calc);
3552 if (ret)
3553 return ret;
3554
3555 ret = intel_crtcs_calc_min_cdclk(state, &need_cdclk_calc);
3556 if (ret)
3557 return ret;
3558
3559 ret = intel_dbuf_bw_calc_min_cdclk(state, &need_cdclk_calc);
3560 if (ret)
3561 return ret;
3562
3563 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
3564 new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
3565
3566 if (new_cdclk_state &&
3567 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) {
3568 ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
3569 if (ret)
3570 return ret;
3571
3572 need_cdclk_calc = true;
3573 }
3574
3575 if (need_cdclk_calc) {
3576 ret = intel_modeset_calc_cdclk(state);
3577 if (ret)
3578 return ret;
3579 }
3580
3581 return 0;
3582 }
3583
intel_cdclk_update_hw_state(struct intel_display * display)3584 void intel_cdclk_update_hw_state(struct intel_display *display)
3585 {
3586 const struct intel_dbuf_bw_state *dbuf_bw_state =
3587 to_intel_dbuf_bw_state(display->dbuf_bw.obj.state);
3588 struct intel_cdclk_state *cdclk_state =
3589 to_intel_cdclk_state(display->cdclk.obj.state);
3590 struct intel_crtc *crtc;
3591
3592 cdclk_state->enabled_pipes = 0;
3593 cdclk_state->active_pipes = 0;
3594
3595 for_each_intel_crtc(display->drm, crtc) {
3596 const struct intel_crtc_state *crtc_state =
3597 to_intel_crtc_state(crtc->base.state);
3598 enum pipe pipe = crtc->pipe;
3599
3600 if (crtc_state->hw.enable)
3601 cdclk_state->enabled_pipes |= BIT(pipe);
3602 if (crtc_state->hw.active)
3603 cdclk_state->active_pipes |= BIT(pipe);
3604
3605 cdclk_state->min_cdclk[pipe] = crtc_state->min_cdclk;
3606 cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level;
3607 }
3608
3609 cdclk_state->dbuf_bw_min_cdclk = intel_dbuf_bw_min_cdclk(display, dbuf_bw_state);
3610 }
3611
intel_cdclk_crtc_disable_noatomic(struct intel_crtc * crtc)3612 void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc)
3613 {
3614 struct intel_display *display = to_intel_display(crtc);
3615
3616 intel_cdclk_update_hw_state(display);
3617 }
3618
intel_compute_max_dotclk(struct intel_display * display)3619 static int intel_compute_max_dotclk(struct intel_display *display)
3620 {
3621 int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display));
3622 int guardband = intel_cdclk_guardband(display);
3623 int max_cdclk_freq = display->cdclk.max_cdclk_freq;
3624
3625 return ppc * max_cdclk_freq * guardband / 100;
3626 }
3627
3628 /**
3629 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
3630 * @display: display instance
3631 *
3632 * Determine the maximum CDCLK frequency the platform supports, and also
3633 * derive the maximum dot clock frequency the maximum CDCLK frequency
3634 * allows.
3635 */
intel_update_max_cdclk(struct intel_display * display)3636 void intel_update_max_cdclk(struct intel_display *display)
3637 {
3638 if (DISPLAY_VER(display) >= 35) {
3639 display->cdclk.max_cdclk_freq = 787200;
3640 } else if (DISPLAY_VERx100(display) >= 3002) {
3641 display->cdclk.max_cdclk_freq = 480000;
3642 } else if (DISPLAY_VER(display) >= 30) {
3643 display->cdclk.max_cdclk_freq = 691200;
3644 } else if (display->platform.jasperlake || display->platform.elkhartlake) {
3645 if (display->cdclk.hw.ref == 24000)
3646 display->cdclk.max_cdclk_freq = 552000;
3647 else
3648 display->cdclk.max_cdclk_freq = 556800;
3649 } else if (DISPLAY_VER(display) >= 11) {
3650 if (display->cdclk.hw.ref == 24000)
3651 display->cdclk.max_cdclk_freq = 648000;
3652 else
3653 display->cdclk.max_cdclk_freq = 652800;
3654 } else if (display->platform.geminilake) {
3655 display->cdclk.max_cdclk_freq = 316800;
3656 } else if (display->platform.broxton) {
3657 display->cdclk.max_cdclk_freq = 624000;
3658 } else if (DISPLAY_VER(display) == 9) {
3659 u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
3660 int max_cdclk, vco;
3661
3662 vco = display->cdclk.skl_preferred_vco_freq;
3663 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
3664
3665 /*
3666 * Use the lower (vco 8640) cdclk values as a
3667 * first guess. skl_calc_cdclk() will correct it
3668 * if the preferred vco is 8100 instead.
3669 */
3670 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
3671 max_cdclk = 617143;
3672 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
3673 max_cdclk = 540000;
3674 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
3675 max_cdclk = 432000;
3676 else
3677 max_cdclk = 308571;
3678
3679 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
3680 } else if (display->platform.broadwell) {
3681 /*
3682 * FIXME with extra cooling we can allow
3683 * 540 MHz for ULX and 675 Mhz for ULT.
3684 * How can we know if extra cooling is
3685 * available? PCI ID, VTB, something else?
3686 */
3687 if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
3688 display->cdclk.max_cdclk_freq = 450000;
3689 else if (display->platform.broadwell_ulx)
3690 display->cdclk.max_cdclk_freq = 450000;
3691 else if (display->platform.broadwell_ult)
3692 display->cdclk.max_cdclk_freq = 540000;
3693 else
3694 display->cdclk.max_cdclk_freq = 675000;
3695 } else if (display->platform.cherryview) {
3696 display->cdclk.max_cdclk_freq = 320000;
3697 } else if (display->platform.valleyview) {
3698 display->cdclk.max_cdclk_freq = 400000;
3699 } else {
3700 /* otherwise assume cdclk is fixed */
3701 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk;
3702 }
3703
3704 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display);
3705
3706 drm_dbg(display->drm, "Max CD clock rate: %d kHz\n",
3707 display->cdclk.max_cdclk_freq);
3708
3709 drm_dbg(display->drm, "Max dotclock rate: %d kHz\n",
3710 display->cdclk.max_dotclk_freq);
3711 }
3712
3713 /**
3714 * intel_update_cdclk - Determine the current CDCLK frequency
3715 * @display: display instance
3716 *
3717 * Determine the current CDCLK frequency.
3718 */
intel_update_cdclk(struct intel_display * display)3719 void intel_update_cdclk(struct intel_display *display)
3720 {
3721 intel_cdclk_get_cdclk(display, &display->cdclk.hw);
3722
3723 /*
3724 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
3725 * Programmng [sic] note: bit[9:2] should be programmed to the number
3726 * of cdclk that generates 4MHz reference clock freq which is used to
3727 * generate GMBus clock. This will vary with the cdclk freq.
3728 */
3729 if (display->platform.valleyview || display->platform.cherryview)
3730 intel_de_write(display, GMBUSFREQ_VLV,
3731 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000));
3732 }
3733
dg1_rawclk(struct intel_display * display)3734 static int dg1_rawclk(struct intel_display *display)
3735 {
3736 /*
3737 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us
3738 * "Program Numerator=2, Denominator=4, Divider=37 decimal."
3739 */
3740 intel_de_write(display, PCH_RAWCLK_FREQ,
3741 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
3742
3743 return 38400;
3744 }
3745
cnp_rawclk(struct intel_display * display)3746 static int cnp_rawclk(struct intel_display *display)
3747 {
3748 int divider, fraction;
3749 u32 rawclk;
3750
3751 if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
3752 /* 24 MHz */
3753 divider = 24000;
3754 fraction = 0;
3755 } else {
3756 /* 19.2 MHz */
3757 divider = 19000;
3758 fraction = 200;
3759 }
3760
3761 rawclk = CNP_RAWCLK_DIV(divider / 1000);
3762 if (fraction) {
3763 int numerator = 1;
3764
3765 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
3766 fraction) - 1);
3767 if (INTEL_PCH_TYPE(display) >= PCH_ICP)
3768 rawclk |= ICP_RAWCLK_NUM(numerator);
3769 }
3770
3771 intel_de_write(display, PCH_RAWCLK_FREQ, rawclk);
3772 return divider + fraction;
3773 }
3774
pch_rawclk(struct intel_display * display)3775 static int pch_rawclk(struct intel_display *display)
3776 {
3777 return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
3778 }
3779
i9xx_hrawclk(struct intel_display * display)3780 static int i9xx_hrawclk(struct intel_display *display)
3781 {
3782 /* hrawclock is 1/4 the FSB frequency */
3783 return DIV_ROUND_CLOSEST(intel_fsb_freq(display), 4);
3784 }
3785
3786 /**
3787 * intel_read_rawclk - Determine the current RAWCLK frequency
3788 * @display: display instance
3789 *
3790 * Determine the current RAWCLK frequency. RAWCLK is a fixed
3791 * frequency clock so this needs to done only once.
3792 */
intel_read_rawclk(struct intel_display * display)3793 u32 intel_read_rawclk(struct intel_display *display)
3794 {
3795 u32 freq;
3796
3797 if (INTEL_PCH_TYPE(display) >= PCH_MTL)
3798 /*
3799 * MTL always uses a 38.4 MHz rawclk. The bspec tells us
3800 * "RAWCLK_FREQ defaults to the values for 38.4 and does
3801 * not need to be programmed."
3802 */
3803 freq = 38400;
3804 else if (INTEL_PCH_TYPE(display) >= PCH_DG1)
3805 freq = dg1_rawclk(display);
3806 else if (INTEL_PCH_TYPE(display) >= PCH_CNP)
3807 freq = cnp_rawclk(display);
3808 else if (HAS_PCH_SPLIT(display))
3809 freq = pch_rawclk(display);
3810 else if (display->platform.valleyview || display->platform.cherryview)
3811 freq = vlv_clock_get_hrawclk(display->drm);
3812 else if (DISPLAY_VER(display) >= 3)
3813 freq = i9xx_hrawclk(display);
3814 else
3815 /* no rawclk on other platforms, or no need to know it */
3816 return 0;
3817
3818 return freq;
3819 }
3820
i915_cdclk_info_show(struct seq_file * m,void * unused)3821 static int i915_cdclk_info_show(struct seq_file *m, void *unused)
3822 {
3823 struct intel_display *display = m->private;
3824
3825 seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk);
3826 seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq);
3827 seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq);
3828
3829 return 0;
3830 }
3831
3832 DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info);
3833
intel_cdclk_debugfs_register(struct intel_display * display)3834 void intel_cdclk_debugfs_register(struct intel_display *display)
3835 {
3836 debugfs_create_file("i915_cdclk_info", 0444, display->drm->debugfs_root,
3837 display, &i915_cdclk_info_fops);
3838 }
3839
3840 static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = {
3841 .get_cdclk = bxt_get_cdclk,
3842 .set_cdclk = bxt_set_cdclk,
3843 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3844 .calc_voltage_level = xe3lpd_calc_voltage_level,
3845 };
3846
3847 static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
3848 .get_cdclk = bxt_get_cdclk,
3849 .set_cdclk = bxt_set_cdclk,
3850 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3851 .calc_voltage_level = rplu_calc_voltage_level,
3852 };
3853
3854 static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
3855 .get_cdclk = bxt_get_cdclk,
3856 .set_cdclk = bxt_set_cdclk,
3857 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3858 .calc_voltage_level = tgl_calc_voltage_level,
3859 };
3860
3861 static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
3862 .get_cdclk = bxt_get_cdclk,
3863 .set_cdclk = bxt_set_cdclk,
3864 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3865 .calc_voltage_level = ehl_calc_voltage_level,
3866 };
3867
3868 static const struct intel_cdclk_funcs icl_cdclk_funcs = {
3869 .get_cdclk = bxt_get_cdclk,
3870 .set_cdclk = bxt_set_cdclk,
3871 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3872 .calc_voltage_level = icl_calc_voltage_level,
3873 };
3874
3875 static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
3876 .get_cdclk = bxt_get_cdclk,
3877 .set_cdclk = bxt_set_cdclk,
3878 .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3879 .calc_voltage_level = bxt_calc_voltage_level,
3880 };
3881
3882 static const struct intel_cdclk_funcs skl_cdclk_funcs = {
3883 .get_cdclk = skl_get_cdclk,
3884 .set_cdclk = skl_set_cdclk,
3885 .modeset_calc_cdclk = skl_modeset_calc_cdclk,
3886 };
3887
3888 static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
3889 .get_cdclk = bdw_get_cdclk,
3890 .set_cdclk = bdw_set_cdclk,
3891 .modeset_calc_cdclk = bdw_modeset_calc_cdclk,
3892 };
3893
3894 static const struct intel_cdclk_funcs chv_cdclk_funcs = {
3895 .get_cdclk = vlv_get_cdclk,
3896 .set_cdclk = chv_set_cdclk,
3897 .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
3898 };
3899
3900 static const struct intel_cdclk_funcs vlv_cdclk_funcs = {
3901 .get_cdclk = vlv_get_cdclk,
3902 .set_cdclk = vlv_set_cdclk,
3903 .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
3904 };
3905
3906 static const struct intel_cdclk_funcs hsw_cdclk_funcs = {
3907 .get_cdclk = hsw_get_cdclk,
3908 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3909 };
3910
3911 /* SNB, IVB, 965G, 945G */
3912 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
3913 .get_cdclk = fixed_400mhz_get_cdclk,
3914 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3915 };
3916
3917 static const struct intel_cdclk_funcs ilk_cdclk_funcs = {
3918 .get_cdclk = fixed_450mhz_get_cdclk,
3919 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3920 };
3921
3922 static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
3923 .get_cdclk = gm45_get_cdclk,
3924 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3925 };
3926
3927 /* G45 uses G33 */
3928
3929 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
3930 .get_cdclk = i965gm_get_cdclk,
3931 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3932 };
3933
3934 /* i965G uses fixed 400 */
3935
3936 static const struct intel_cdclk_funcs pnv_cdclk_funcs = {
3937 .get_cdclk = pnv_get_cdclk,
3938 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3939 };
3940
3941 static const struct intel_cdclk_funcs g33_cdclk_funcs = {
3942 .get_cdclk = g33_get_cdclk,
3943 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3944 };
3945
3946 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
3947 .get_cdclk = i945gm_get_cdclk,
3948 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3949 };
3950
3951 /* i945G uses fixed 400 */
3952
3953 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = {
3954 .get_cdclk = i915gm_get_cdclk,
3955 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3956 };
3957
3958 static const struct intel_cdclk_funcs i915g_cdclk_funcs = {
3959 .get_cdclk = fixed_333mhz_get_cdclk,
3960 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3961 };
3962
3963 static const struct intel_cdclk_funcs i865g_cdclk_funcs = {
3964 .get_cdclk = fixed_266mhz_get_cdclk,
3965 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3966 };
3967
3968 static const struct intel_cdclk_funcs i85x_cdclk_funcs = {
3969 .get_cdclk = i85x_get_cdclk,
3970 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3971 };
3972
3973 static const struct intel_cdclk_funcs i845g_cdclk_funcs = {
3974 .get_cdclk = fixed_200mhz_get_cdclk,
3975 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3976 };
3977
3978 static const struct intel_cdclk_funcs i830_cdclk_funcs = {
3979 .get_cdclk = fixed_133mhz_get_cdclk,
3980 .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3981 };
3982
3983 /**
3984 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
3985 * @display: display instance
3986 */
intel_init_cdclk_hooks(struct intel_display * display)3987 void intel_init_cdclk_hooks(struct intel_display *display)
3988 {
3989 if (DISPLAY_VER(display) >= 35) {
3990 display->funcs.cdclk = &xe3lpd_cdclk_funcs;
3991 display->cdclk.table = xe3p_lpd_cdclk_table;
3992 } else if (DISPLAY_VER(display) >= 30) {
3993 display->funcs.cdclk = &xe3lpd_cdclk_funcs;
3994 display->cdclk.table = xe3lpd_cdclk_table;
3995 } else if (DISPLAY_VER(display) >= 20) {
3996 display->funcs.cdclk = &rplu_cdclk_funcs;
3997 display->cdclk.table = xe2lpd_cdclk_table;
3998 } else if (DISPLAY_VERx100(display) >= 1401) {
3999 display->funcs.cdclk = &rplu_cdclk_funcs;
4000 display->cdclk.table = xe2hpd_cdclk_table;
4001 } else if (DISPLAY_VER(display) >= 14) {
4002 display->funcs.cdclk = &rplu_cdclk_funcs;
4003 display->cdclk.table = mtl_cdclk_table;
4004 } else if (display->platform.dg2) {
4005 display->funcs.cdclk = &tgl_cdclk_funcs;
4006 display->cdclk.table = dg2_cdclk_table;
4007 } else if (display->platform.alderlake_p) {
4008 /* Wa_22011320316:adl-p[a0] */
4009 if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {
4010 display->cdclk.table = adlp_a_step_cdclk_table;
4011 display->funcs.cdclk = &tgl_cdclk_funcs;
4012 } else if (display->platform.alderlake_p_raptorlake_u) {
4013 display->cdclk.table = rplu_cdclk_table;
4014 display->funcs.cdclk = &rplu_cdclk_funcs;
4015 } else {
4016 display->cdclk.table = adlp_cdclk_table;
4017 display->funcs.cdclk = &tgl_cdclk_funcs;
4018 }
4019 } else if (display->platform.rocketlake) {
4020 display->funcs.cdclk = &tgl_cdclk_funcs;
4021 display->cdclk.table = rkl_cdclk_table;
4022 } else if (DISPLAY_VER(display) >= 12) {
4023 display->funcs.cdclk = &tgl_cdclk_funcs;
4024 display->cdclk.table = icl_cdclk_table;
4025 } else if (display->platform.jasperlake || display->platform.elkhartlake) {
4026 display->funcs.cdclk = &ehl_cdclk_funcs;
4027 display->cdclk.table = icl_cdclk_table;
4028 } else if (DISPLAY_VER(display) >= 11) {
4029 display->funcs.cdclk = &icl_cdclk_funcs;
4030 display->cdclk.table = icl_cdclk_table;
4031 } else if (display->platform.geminilake || display->platform.broxton) {
4032 display->funcs.cdclk = &bxt_cdclk_funcs;
4033 if (display->platform.geminilake)
4034 display->cdclk.table = glk_cdclk_table;
4035 else
4036 display->cdclk.table = bxt_cdclk_table;
4037 } else if (DISPLAY_VER(display) == 9) {
4038 display->funcs.cdclk = &skl_cdclk_funcs;
4039 } else if (display->platform.broadwell) {
4040 display->funcs.cdclk = &bdw_cdclk_funcs;
4041 } else if (display->platform.haswell) {
4042 display->funcs.cdclk = &hsw_cdclk_funcs;
4043 } else if (display->platform.cherryview) {
4044 display->funcs.cdclk = &chv_cdclk_funcs;
4045 } else if (display->platform.valleyview) {
4046 display->funcs.cdclk = &vlv_cdclk_funcs;
4047 } else if (display->platform.sandybridge || display->platform.ivybridge) {
4048 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
4049 } else if (display->platform.ironlake) {
4050 display->funcs.cdclk = &ilk_cdclk_funcs;
4051 } else if (display->platform.gm45) {
4052 display->funcs.cdclk = &gm45_cdclk_funcs;
4053 } else if (display->platform.g45) {
4054 display->funcs.cdclk = &g33_cdclk_funcs;
4055 } else if (display->platform.i965gm) {
4056 display->funcs.cdclk = &i965gm_cdclk_funcs;
4057 } else if (display->platform.i965g) {
4058 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
4059 } else if (display->platform.pineview) {
4060 display->funcs.cdclk = &pnv_cdclk_funcs;
4061 } else if (display->platform.g33) {
4062 display->funcs.cdclk = &g33_cdclk_funcs;
4063 } else if (display->platform.i945gm) {
4064 display->funcs.cdclk = &i945gm_cdclk_funcs;
4065 } else if (display->platform.i945g) {
4066 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
4067 } else if (display->platform.i915gm) {
4068 display->funcs.cdclk = &i915gm_cdclk_funcs;
4069 } else if (display->platform.i915g) {
4070 display->funcs.cdclk = &i915g_cdclk_funcs;
4071 } else if (display->platform.i865g) {
4072 display->funcs.cdclk = &i865g_cdclk_funcs;
4073 } else if (display->platform.i85x) {
4074 display->funcs.cdclk = &i85x_cdclk_funcs;
4075 } else if (display->platform.i845g) {
4076 display->funcs.cdclk = &i845g_cdclk_funcs;
4077 } else if (display->platform.i830) {
4078 display->funcs.cdclk = &i830_cdclk_funcs;
4079 }
4080
4081 if (drm_WARN(display->drm, !display->funcs.cdclk,
4082 "Unknown platform. Assuming i830\n"))
4083 display->funcs.cdclk = &i830_cdclk_funcs;
4084 }
4085
intel_cdclk_logical(const struct intel_cdclk_state * cdclk_state)4086 int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state)
4087 {
4088 return cdclk_state->logical.cdclk;
4089 }
4090
intel_cdclk_actual(const struct intel_cdclk_state * cdclk_state)4091 int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state)
4092 {
4093 return cdclk_state->actual.cdclk;
4094 }
4095
intel_cdclk_actual_voltage_level(const struct intel_cdclk_state * cdclk_state)4096 int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state)
4097 {
4098 return cdclk_state->actual.voltage_level;
4099 }
4100
intel_cdclk_min_cdclk(const struct intel_cdclk_state * cdclk_state,enum pipe pipe)4101 int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe)
4102 {
4103 return cdclk_state->min_cdclk[pipe];
4104 }
4105
intel_cdclk_pmdemand_needs_update(struct intel_atomic_state * state)4106 bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state)
4107 {
4108 const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state;
4109
4110 new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
4111 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
4112
4113 if (new_cdclk_state &&
4114 (new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk ||
4115 new_cdclk_state->actual.voltage_level != old_cdclk_state->actual.voltage_level))
4116 return true;
4117
4118 return false;
4119 }
4120
intel_cdclk_force_min_cdclk(struct intel_cdclk_state * cdclk_state,int force_min_cdclk)4121 void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk)
4122 {
4123 cdclk_state->force_min_cdclk = force_min_cdclk;
4124 }
4125
intel_cdclk_read_hw(struct intel_display * display)4126 void intel_cdclk_read_hw(struct intel_display *display)
4127 {
4128 struct intel_cdclk_state *cdclk_state;
4129
4130 cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state);
4131
4132 intel_update_cdclk(display);
4133 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
4134 cdclk_state->actual = display->cdclk.hw;
4135 cdclk_state->logical = display->cdclk.hw;
4136 }
4137
calc_cdclk(const struct intel_crtc_state * crtc_state,int min_cdclk)4138 static int calc_cdclk(const struct intel_crtc_state *crtc_state, int min_cdclk)
4139 {
4140 struct intel_display *display = to_intel_display(crtc_state);
4141
4142 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) {
4143 return bxt_calc_cdclk(display, min_cdclk);
4144 } else if (DISPLAY_VER(display) == 9) {
4145 int vco;
4146
4147 vco = display->cdclk.skl_preferred_vco_freq;
4148 if (vco == 0)
4149 vco = 8100000;
4150
4151 return skl_calc_cdclk(min_cdclk, vco);
4152 } else if (display->platform.broadwell) {
4153 return bdw_calc_cdclk(min_cdclk);
4154 } else if (display->platform.cherryview || display->platform.valleyview) {
4155 return vlv_calc_cdclk(display, min_cdclk);
4156 } else {
4157 return display->cdclk.max_cdclk_freq;
4158 }
4159 }
4160
_intel_cdclk_prefill_adj(const struct intel_crtc_state * crtc_state,int clock,int min_cdclk)4161 static unsigned int _intel_cdclk_prefill_adj(const struct intel_crtc_state *crtc_state,
4162 int clock, int min_cdclk)
4163 {
4164 struct intel_display *display = to_intel_display(crtc_state);
4165 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);
4166 int cdclk = calc_cdclk(crtc_state, min_cdclk);
4167
4168 return min(0x10000, DIV_ROUND_UP_ULL((u64)clock << 16, ppc * cdclk));
4169 }
4170
intel_cdclk_prefill_adjustment(const struct intel_crtc_state * crtc_state)4171 unsigned int intel_cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
4172 {
4173 /* FIXME use the actual min_cdclk for the pipe here */
4174 return intel_cdclk_prefill_adjustment_worst(crtc_state);
4175 }
4176
intel_cdclk_prefill_adjustment_worst(const struct intel_crtc_state * crtc_state)4177 unsigned int intel_cdclk_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state)
4178 {
4179 int clock = crtc_state->hw.pipe_mode.crtc_clock;
4180 int min_cdclk;
4181
4182 /*
4183 * FIXME could perhaps consider a few more of the factors
4184 * that go the per-crtc min_cdclk. Namely anything that
4185 * only changes during full modesets.
4186 *
4187 * FIXME this assumes 1:1 scaling, but the other _worst() stuff
4188 * assumes max downscaling, so the final result will be
4189 * unrealistically bad. Figure out where the actual maximum value
4190 * lies and use that to compute a more realistic worst case
4191 * estimate...
4192 */
4193 min_cdclk = _intel_pixel_rate_to_cdclk(crtc_state, clock);
4194
4195 return _intel_cdclk_prefill_adj(crtc_state, clock, min_cdclk);
4196 }
4197
intel_cdclk_min_cdclk_for_prefill(const struct intel_crtc_state * crtc_state,unsigned int prefill_lines_unadjusted,unsigned int prefill_lines_available)4198 int intel_cdclk_min_cdclk_for_prefill(const struct intel_crtc_state *crtc_state,
4199 unsigned int prefill_lines_unadjusted,
4200 unsigned int prefill_lines_available)
4201 {
4202 struct intel_display *display = to_intel_display(crtc_state);
4203 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
4204 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);
4205
4206 return DIV_ROUND_UP_ULL(mul_u32_u32(pipe_mode->crtc_clock, prefill_lines_unadjusted),
4207 ppc * prefill_lines_available);
4208 }
4209