1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright(c) 2021 Intel Corporation. All rights reserved. */
3 #include <linux/platform_device.h>
4 #include <linux/module.h>
5 #include <linux/device.h>
6 #include <linux/kernel.h>
7 #include <linux/acpi.h>
8 #include <linux/pci.h>
9 #include <linux/node.h>
10 #include <asm/div64.h>
11 #include "cxlpci.h"
12 #include "cxl.h"
13
14 static const guid_t acpi_cxl_qtg_id_guid =
15 GUID_INIT(0xF365F9A6, 0xA7DE, 0x4071,
16 0xA6, 0x6A, 0xB4, 0x0C, 0x0B, 0x4F, 0x8E, 0x52);
17
18 #define HBIW_TO_NR_MAPS_SIZE (CXL_DECODER_MAX_INTERLEAVE + 1)
19 static const int hbiw_to_nr_maps[HBIW_TO_NR_MAPS_SIZE] = {
20 [1] = 0, [2] = 1, [3] = 0, [4] = 2, [6] = 1, [8] = 3, [12] = 2, [16] = 4
21 };
22
23 static const int valid_hbiw[] = { 1, 2, 3, 4, 6, 8, 12, 16 };
24
cxl_do_xormap_calc(struct cxl_cxims_data * cximsd,u64 addr,int hbiw)25 u64 cxl_do_xormap_calc(struct cxl_cxims_data *cximsd, u64 addr, int hbiw)
26 {
27 int nr_maps_to_apply = -1;
28 u64 val;
29 int pos;
30
31 /*
32 * Strictly validate hbiw since this function is used for testing and
33 * that nullifies any expectation of trusted parameters from the CXL
34 * Region Driver.
35 */
36 for (int i = 0; i < ARRAY_SIZE(valid_hbiw); i++) {
37 if (valid_hbiw[i] == hbiw) {
38 nr_maps_to_apply = hbiw_to_nr_maps[hbiw];
39 break;
40 }
41 }
42 if (nr_maps_to_apply == -1 || nr_maps_to_apply > cximsd->nr_maps)
43 return ULLONG_MAX;
44
45 /*
46 * In regions using XOR interleave arithmetic the CXL HPA may not
47 * be the same as the SPA. This helper performs the SPA->CXL HPA
48 * or the CXL HPA->SPA translation. Since XOR is self-inverting,
49 * so is this function.
50 *
51 * For root decoders using xormaps (hbiw: 2,4,6,8,12,16) applying the
52 * xormaps will toggle a position bit.
53 *
54 * pos is the lowest set bit in an XORMAP
55 * val is the XORALLBITS(addr & XORMAP)
56 *
57 * XORALLBITS: The CXL spec (3.1 Table 9-22) defines XORALLBITS
58 * as an operation that outputs a single bit by XORing all the
59 * bits in the input (addr & xormap). Implement XORALLBITS using
60 * hweight64(). If the hamming weight is even the XOR of those
61 * bits results in val==0, if odd the XOR result is val==1.
62 */
63
64 for (int i = 0; i < cximsd->nr_maps; i++) {
65 if (!cximsd->xormaps[i])
66 continue;
67 pos = __ffs(cximsd->xormaps[i]);
68 val = (hweight64(addr & cximsd->xormaps[i]) & 1);
69 addr = (addr & ~(1ULL << pos)) | (val << pos);
70 }
71
72 return addr;
73 }
74 EXPORT_SYMBOL_FOR_MODULES(cxl_do_xormap_calc, "cxl_translate");
75
cxl_apply_xor_maps(struct cxl_root_decoder * cxlrd,u64 addr)76 static u64 cxl_apply_xor_maps(struct cxl_root_decoder *cxlrd, u64 addr)
77 {
78 int hbiw = cxlrd->cxlsd.nr_targets;
79 struct cxl_cxims_data *cximsd;
80
81 /* No xormaps for host bridge interleave ways of 1 or 3 */
82 if (hbiw == 1 || hbiw == 3)
83 return addr;
84
85 cximsd = cxlrd->platform_data;
86
87 return cxl_do_xormap_calc(cximsd, addr, hbiw);
88 }
89
90 struct cxl_cxims_context {
91 struct device *dev;
92 struct cxl_root_decoder *cxlrd;
93 };
94
cxl_parse_cxims(union acpi_subtable_headers * header,void * arg,const unsigned long end)95 static int cxl_parse_cxims(union acpi_subtable_headers *header, void *arg,
96 const unsigned long end)
97 {
98 struct acpi_cedt_cxims *cxims = (struct acpi_cedt_cxims *)header;
99 struct cxl_cxims_context *ctx = arg;
100 struct cxl_root_decoder *cxlrd = ctx->cxlrd;
101 struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
102 struct device *dev = ctx->dev;
103 struct cxl_cxims_data *cximsd;
104 unsigned int hbig, nr_maps;
105 int rc;
106
107 rc = eig_to_granularity(cxims->hbig, &hbig);
108 if (rc)
109 return rc;
110
111 /* Does this CXIMS entry apply to the given CXL Window? */
112 if (hbig != cxld->interleave_granularity)
113 return 0;
114
115 /* IW 1,3 do not use xormaps and skip this parsing entirely */
116 if (is_power_of_2(cxld->interleave_ways))
117 /* 2, 4, 8, 16 way */
118 nr_maps = ilog2(cxld->interleave_ways);
119 else
120 /* 6, 12 way */
121 nr_maps = ilog2(cxld->interleave_ways / 3);
122
123 if (cxims->nr_xormaps < nr_maps) {
124 dev_dbg(dev, "CXIMS nr_xormaps[%d] expected[%d]\n",
125 cxims->nr_xormaps, nr_maps);
126 return -ENXIO;
127 }
128
129 cximsd = devm_kzalloc(dev, struct_size(cximsd, xormaps, nr_maps),
130 GFP_KERNEL);
131 if (!cximsd)
132 return -ENOMEM;
133 cximsd->nr_maps = nr_maps;
134 memcpy(cximsd->xormaps, cxims->xormap_list,
135 nr_maps * sizeof(*cximsd->xormaps));
136 cxlrd->platform_data = cximsd;
137
138 return 0;
139 }
140
cfmws_to_decoder_flags(int restrictions)141 static unsigned long cfmws_to_decoder_flags(int restrictions)
142 {
143 unsigned long flags = CXL_DECODER_F_ENABLE;
144
145 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_DEVMEM)
146 flags |= CXL_DECODER_F_TYPE2;
147 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_HOSTONLYMEM)
148 flags |= CXL_DECODER_F_TYPE3;
149 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE)
150 flags |= CXL_DECODER_F_RAM;
151 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM)
152 flags |= CXL_DECODER_F_PMEM;
153 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED)
154 flags |= CXL_DECODER_F_LOCK;
155
156 return flags;
157 }
158
cxl_acpi_cfmws_verify(struct device * dev,struct acpi_cedt_cfmws * cfmws)159 static int cxl_acpi_cfmws_verify(struct device *dev,
160 struct acpi_cedt_cfmws *cfmws)
161 {
162 int rc, expected_len;
163 unsigned int ways;
164
165 if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO &&
166 cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
167 dev_err(dev, "CFMWS Unknown Interleave Arithmetic: %d\n",
168 cfmws->interleave_arithmetic);
169 return -EINVAL;
170 }
171
172 if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) {
173 dev_err(dev, "CFMWS Base HPA not 256MB aligned\n");
174 return -EINVAL;
175 }
176
177 if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) {
178 dev_err(dev, "CFMWS Window Size not 256MB aligned\n");
179 return -EINVAL;
180 }
181
182 rc = eiw_to_ways(cfmws->interleave_ways, &ways);
183 if (rc) {
184 dev_err(dev, "CFMWS Interleave Ways (%d) invalid\n",
185 cfmws->interleave_ways);
186 return -EINVAL;
187 }
188
189 expected_len = struct_size(cfmws, interleave_targets, ways);
190
191 if (cfmws->header.length < expected_len) {
192 dev_err(dev, "CFMWS length %d less than expected %d\n",
193 cfmws->header.length, expected_len);
194 return -EINVAL;
195 }
196
197 if (cfmws->header.length > expected_len)
198 dev_dbg(dev, "CFMWS length %d greater than expected %d\n",
199 cfmws->header.length, expected_len);
200
201 return 0;
202 }
203
204 /*
205 * Note, @dev must be the first member, see 'struct cxl_chbs_context'
206 * and mock_acpi_table_parse_cedt()
207 */
208 struct cxl_cfmws_context {
209 struct device *dev;
210 struct cxl_port *root_port;
211 struct resource *cxl_res;
212 int id;
213 };
214
215 /**
216 * cxl_acpi_evaluate_qtg_dsm - Retrieve QTG ids via ACPI _DSM
217 * @handle: ACPI handle
218 * @coord: performance access coordinates
219 * @entries: number of QTG IDs to return
220 * @qos_class: int array provided by caller to return QTG IDs
221 *
222 * Return: number of QTG IDs returned, or -errno for errors
223 *
224 * Issue QTG _DSM with accompanied bandwidth and latency data in order to get
225 * the QTG IDs that are suitable for the performance point in order of most
226 * suitable to least suitable. Write back array of QTG IDs and return the
227 * actual number of QTG IDs written back.
228 */
229 static int
cxl_acpi_evaluate_qtg_dsm(acpi_handle handle,struct access_coordinate * coord,int entries,int * qos_class)230 cxl_acpi_evaluate_qtg_dsm(acpi_handle handle, struct access_coordinate *coord,
231 int entries, int *qos_class)
232 {
233 union acpi_object *out_obj, *out_buf, *obj;
234 union acpi_object in_array[4] = {
235 [0].integer = { ACPI_TYPE_INTEGER, coord->read_latency },
236 [1].integer = { ACPI_TYPE_INTEGER, coord->write_latency },
237 [2].integer = { ACPI_TYPE_INTEGER, coord->read_bandwidth },
238 [3].integer = { ACPI_TYPE_INTEGER, coord->write_bandwidth },
239 };
240 union acpi_object in_obj = {
241 .package = {
242 .type = ACPI_TYPE_PACKAGE,
243 .count = 4,
244 .elements = in_array,
245 },
246 };
247 int count, pkg_entries, i;
248 u16 max_qtg;
249 int rc;
250
251 if (!entries)
252 return -EINVAL;
253
254 out_obj = acpi_evaluate_dsm(handle, &acpi_cxl_qtg_id_guid, 1, 1, &in_obj);
255 if (!out_obj)
256 return -ENXIO;
257
258 if (out_obj->type != ACPI_TYPE_PACKAGE) {
259 rc = -ENXIO;
260 goto out;
261 }
262
263 /* Check Max QTG ID */
264 obj = &out_obj->package.elements[0];
265 if (obj->type != ACPI_TYPE_INTEGER) {
266 rc = -ENXIO;
267 goto out;
268 }
269
270 max_qtg = obj->integer.value;
271
272 /* It's legal to have 0 QTG entries */
273 pkg_entries = out_obj->package.count;
274 if (pkg_entries <= 1) {
275 rc = 0;
276 goto out;
277 }
278
279 /* Retrieve QTG IDs package */
280 obj = &out_obj->package.elements[1];
281 if (obj->type != ACPI_TYPE_PACKAGE) {
282 rc = -ENXIO;
283 goto out;
284 }
285
286 pkg_entries = obj->package.count;
287 count = min(entries, pkg_entries);
288 for (i = 0; i < count; i++) {
289 u16 qtg_id;
290
291 out_buf = &obj->package.elements[i];
292 if (out_buf->type != ACPI_TYPE_INTEGER) {
293 rc = -ENXIO;
294 goto out;
295 }
296
297 qtg_id = out_buf->integer.value;
298 if (qtg_id > max_qtg)
299 pr_warn("QTG ID %u greater than MAX %u\n",
300 qtg_id, max_qtg);
301
302 qos_class[i] = qtg_id;
303 }
304 rc = count;
305
306 out:
307 ACPI_FREE(out_obj);
308 return rc;
309 }
310
cxl_acpi_qos_class(struct cxl_root * cxl_root,struct access_coordinate * coord,int entries,int * qos_class)311 static int cxl_acpi_qos_class(struct cxl_root *cxl_root,
312 struct access_coordinate *coord, int entries,
313 int *qos_class)
314 {
315 struct device *dev = cxl_root->port.uport_dev;
316 acpi_handle handle;
317
318 if (!dev_is_platform(dev))
319 return -ENODEV;
320
321 handle = ACPI_HANDLE(dev);
322 if (!handle)
323 return -ENODEV;
324
325 return cxl_acpi_evaluate_qtg_dsm(handle, coord, entries, qos_class);
326 }
327
del_cxl_resource(struct resource * res)328 static void del_cxl_resource(struct resource *res)
329 {
330 if (!res)
331 return;
332 kfree(res->name);
333 kfree(res);
334 }
335
alloc_cxl_resource(resource_size_t base,resource_size_t n,int id)336 static struct resource *alloc_cxl_resource(resource_size_t base,
337 resource_size_t n, int id)
338 {
339 struct resource *res __free(kfree) = kzalloc_obj(*res);
340
341 if (!res)
342 return NULL;
343
344 res->start = base;
345 res->end = base + n - 1;
346 res->flags = IORESOURCE_MEM;
347 res->name = kasprintf(GFP_KERNEL, "CXL Window %d", id);
348 if (!res->name)
349 return NULL;
350
351 return no_free_ptr(res);
352 }
353
add_or_reset_cxl_resource(struct resource * parent,struct resource * res)354 static int add_or_reset_cxl_resource(struct resource *parent, struct resource *res)
355 {
356 int rc = insert_resource(parent, res);
357
358 if (rc)
359 del_cxl_resource(res);
360 return rc;
361 }
362
cxl_setup_extended_linear_cache(struct cxl_root_decoder * cxlrd)363 static void cxl_setup_extended_linear_cache(struct cxl_root_decoder *cxlrd)
364 {
365 struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
366 struct range *hpa = &cxld->hpa_range;
367 resource_size_t size = range_len(hpa);
368 resource_size_t start = hpa->start;
369 resource_size_t cache_size;
370 struct resource res;
371 int nid, rc;
372
373 /* Explicitly initialize cache size to 0 at the beginning */
374 cxlrd->cache_size = 0;
375 res = DEFINE_RES_MEM(start, size);
376 nid = phys_to_target_node(start);
377
378 rc = hmat_get_extended_linear_cache_size(&res, nid, &cache_size);
379 if (rc)
380 return;
381
382 /*
383 * The cache range is expected to be within the CFMWS.
384 * Currently there is only support cache_size == cxl_size. CXL
385 * size is then half of the total CFMWS window size.
386 */
387 size = size >> 1;
388 if (cache_size && size != cache_size) {
389 dev_warn(&cxld->dev,
390 "Extended Linear Cache size %pa != CXL size %pa. No Support!",
391 &cache_size, &size);
392 return;
393 }
394
395 cxlrd->cache_size = cache_size;
396 }
397
398 DEFINE_FREE(put_cxlrd, struct cxl_root_decoder *,
399 if (!IS_ERR_OR_NULL(_T)) put_device(&_T->cxlsd.cxld.dev))
DEFINE_FREE(del_cxl_resource,struct resource *,if (_T)del_cxl_resource (_T))400 DEFINE_FREE(del_cxl_resource, struct resource *, if (_T) del_cxl_resource(_T))
401 static int __cxl_parse_cfmws(struct acpi_cedt_cfmws *cfmws,
402 struct cxl_cfmws_context *ctx)
403 {
404 struct cxl_port *root_port = ctx->root_port;
405 struct cxl_cxims_context cxims_ctx;
406 struct device *dev = ctx->dev;
407 struct cxl_decoder *cxld;
408 unsigned int ways, i, ig;
409 int rc;
410
411 rc = cxl_acpi_cfmws_verify(dev, cfmws);
412 if (rc)
413 return rc;
414
415 rc = eiw_to_ways(cfmws->interleave_ways, &ways);
416 if (rc)
417 return rc;
418 rc = eig_to_granularity(cfmws->granularity, &ig);
419 if (rc)
420 return rc;
421
422 struct resource *res __free(del_cxl_resource) = alloc_cxl_resource(
423 cfmws->base_hpa, cfmws->window_size, ctx->id++);
424 if (!res)
425 return -ENOMEM;
426
427 /* add to the local resource tracking to establish a sort order */
428 rc = add_or_reset_cxl_resource(ctx->cxl_res, no_free_ptr(res));
429 if (rc)
430 return rc;
431
432 struct cxl_root_decoder *cxlrd __free(put_cxlrd) =
433 cxl_root_decoder_alloc(root_port, ways);
434
435 if (IS_ERR(cxlrd))
436 return PTR_ERR(cxlrd);
437
438 cxld = &cxlrd->cxlsd.cxld;
439 cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
440 cxld->target_type = CXL_DECODER_HOSTONLYMEM;
441 cxld->hpa_range = (struct range) {
442 .start = cfmws->base_hpa,
443 .end = cfmws->base_hpa + cfmws->window_size - 1,
444 };
445 cxld->interleave_ways = ways;
446 for (i = 0; i < ways; i++)
447 cxld->target_map[i] = cfmws->interleave_targets[i];
448 /*
449 * Minimize the x1 granularity to advertise support for any
450 * valid region granularity
451 */
452 if (ways == 1)
453 ig = CXL_DECODER_MIN_GRANULARITY;
454 cxld->interleave_granularity = ig;
455
456 if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
457 if (ways != 1 && ways != 3) {
458 cxims_ctx = (struct cxl_cxims_context) {
459 .dev = dev,
460 .cxlrd = cxlrd,
461 };
462 rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CXIMS,
463 cxl_parse_cxims, &cxims_ctx);
464 if (rc < 0)
465 return rc;
466 if (!cxlrd->platform_data) {
467 dev_err(dev, "No CXIMS for HBIG %u\n", ig);
468 return -EINVAL;
469 }
470 }
471 cxlrd->ops.hpa_to_spa = cxl_apply_xor_maps;
472 cxlrd->ops.spa_to_hpa = cxl_apply_xor_maps;
473 }
474
475 cxl_setup_extended_linear_cache(cxlrd);
476
477 cxlrd->qos_class = cfmws->qtg_id;
478
479 rc = cxl_decoder_add(cxld);
480 if (rc)
481 return rc;
482
483 rc = cxl_root_decoder_autoremove(dev, no_free_ptr(cxlrd));
484 if (rc)
485 return rc;
486
487 dev_dbg(root_port->dev.parent, "%s added to %s\n",
488 dev_name(&cxld->dev), dev_name(&root_port->dev));
489
490 return 0;
491 }
492
cxl_parse_cfmws(union acpi_subtable_headers * header,void * arg,const unsigned long end)493 static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
494 const unsigned long end)
495 {
496 struct acpi_cedt_cfmws *cfmws = (struct acpi_cedt_cfmws *)header;
497 struct cxl_cfmws_context *ctx = arg;
498 struct device *dev = ctx->dev;
499 int rc;
500
501 rc = __cxl_parse_cfmws(cfmws, ctx);
502 if (rc)
503 dev_err(dev,
504 "Failed to add decode range: [%#llx - %#llx] (%d)\n",
505 cfmws->base_hpa,
506 cfmws->base_hpa + cfmws->window_size - 1, rc);
507 else
508 dev_dbg(dev, "decode range: node: %d range [%#llx - %#llx]\n",
509 phys_to_target_node(cfmws->base_hpa), cfmws->base_hpa,
510 cfmws->base_hpa + cfmws->window_size - 1);
511
512 /* never fail cxl_acpi load for a single window failure */
513 return 0;
514 }
515
to_cxl_host_bridge(struct device * host,struct device * dev)516 __mock struct acpi_device *to_cxl_host_bridge(struct device *host,
517 struct device *dev)
518 {
519 struct acpi_device *adev = to_acpi_device(dev);
520
521 if (!acpi_pci_find_root(adev->handle))
522 return NULL;
523
524 if (strcmp(acpi_device_hid(adev), "ACPI0016") == 0)
525 return adev;
526 return NULL;
527 }
528
529 /* Note, @dev is used by mock_acpi_table_parse_cedt() */
530 struct cxl_chbs_context {
531 struct device *dev;
532 unsigned long long uid;
533 resource_size_t base;
534 u32 cxl_version;
535 int nr_versions;
536 u32 saved_version;
537 };
538
cxl_get_chbs_iter(union acpi_subtable_headers * header,void * arg,const unsigned long end)539 static int cxl_get_chbs_iter(union acpi_subtable_headers *header, void *arg,
540 const unsigned long end)
541 {
542 struct cxl_chbs_context *ctx = arg;
543 struct acpi_cedt_chbs *chbs;
544
545 chbs = (struct acpi_cedt_chbs *) header;
546
547 if (chbs->cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11 &&
548 chbs->length != ACPI_CEDT_CHBS_LENGTH_CXL11)
549 return 0;
550
551 if (chbs->cxl_version == ACPI_CEDT_CHBS_VERSION_CXL20 &&
552 chbs->length != ACPI_CEDT_CHBS_LENGTH_CXL20)
553 return 0;
554
555 if (!chbs->base)
556 return 0;
557
558 if (ctx->saved_version != chbs->cxl_version) {
559 /*
560 * cxl_version cannot be overwritten before the next two
561 * checks, then use saved_version
562 */
563 ctx->saved_version = chbs->cxl_version;
564 ctx->nr_versions++;
565 }
566
567 if (ctx->base != CXL_RESOURCE_NONE)
568 return 0;
569
570 if (ctx->uid != chbs->uid)
571 return 0;
572
573 ctx->cxl_version = chbs->cxl_version;
574 ctx->base = chbs->base;
575
576 return 0;
577 }
578
cxl_get_chbs(struct device * dev,struct acpi_device * hb,struct cxl_chbs_context * ctx)579 static int cxl_get_chbs(struct device *dev, struct acpi_device *hb,
580 struct cxl_chbs_context *ctx)
581 {
582 unsigned long long uid;
583 int rc;
584
585 rc = acpi_evaluate_integer(hb->handle, METHOD_NAME__UID, NULL, &uid);
586 if (rc != AE_OK) {
587 dev_err(dev, "unable to retrieve _UID\n");
588 return -ENOENT;
589 }
590
591 dev_dbg(dev, "UID found: %lld\n", uid);
592 *ctx = (struct cxl_chbs_context) {
593 .dev = dev,
594 .uid = uid,
595 .base = CXL_RESOURCE_NONE,
596 .cxl_version = UINT_MAX,
597 .saved_version = UINT_MAX,
598 };
599
600 acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbs_iter, ctx);
601
602 if (ctx->nr_versions > 1) {
603 /*
604 * Disclaim eRCD support given some component register may
605 * only be found via CHBCR
606 */
607 dev_info(dev, "Unsupported platform config, mixed Virtual Host and Restricted CXL Host hierarchy.");
608 }
609
610 return 0;
611 }
612
get_genport_coordinates(struct device * dev,struct cxl_dport * dport)613 static int get_genport_coordinates(struct device *dev, struct cxl_dport *dport)
614 {
615 struct acpi_device *hb = to_cxl_host_bridge(NULL, dev);
616 u32 uid;
617
618 if (kstrtou32(acpi_device_uid(hb), 0, &uid))
619 return -EINVAL;
620
621 return acpi_get_genport_coordinates(uid, dport->coord);
622 }
623
add_host_bridge_dport(struct device * match,void * arg)624 static int add_host_bridge_dport(struct device *match, void *arg)
625 {
626 int ret;
627 acpi_status rc;
628 struct device *bridge;
629 struct cxl_dport *dport;
630 struct cxl_chbs_context ctx;
631 struct acpi_pci_root *pci_root;
632 struct cxl_port *root_port = arg;
633 struct device *host = root_port->dev.parent;
634 struct acpi_device *hb = to_cxl_host_bridge(host, match);
635
636 if (!hb)
637 return 0;
638
639 rc = cxl_get_chbs(match, hb, &ctx);
640 if (rc)
641 return rc;
642
643 if (ctx.cxl_version == UINT_MAX) {
644 dev_warn(match, "No CHBS found for Host Bridge (UID %lld)\n",
645 ctx.uid);
646 return 0;
647 }
648
649 if (ctx.base == CXL_RESOURCE_NONE) {
650 dev_warn(match, "CHBS invalid for Host Bridge (UID %lld)\n",
651 ctx.uid);
652 return 0;
653 }
654
655 pci_root = acpi_pci_find_root(hb->handle);
656 bridge = pci_root->bus->bridge;
657
658 /*
659 * In RCH mode, bind the component regs base to the dport. In
660 * VH mode it will be bound to the CXL host bridge's port
661 * object later in add_host_bridge_uport().
662 */
663 if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {
664 dev_dbg(match, "RCRB found for UID %lld: %pa\n", ctx.uid,
665 &ctx.base);
666 dport = devm_cxl_add_rch_dport(root_port, bridge, ctx.uid,
667 ctx.base);
668 } else {
669 dport = devm_cxl_add_dport(root_port, bridge, ctx.uid,
670 CXL_RESOURCE_NONE);
671 }
672
673 if (IS_ERR(dport))
674 return PTR_ERR(dport);
675
676 ret = get_genport_coordinates(match, dport);
677 if (ret)
678 dev_dbg(match, "Failed to get generic port perf coordinates.\n");
679
680 return 0;
681 }
682
683 /*
684 * A host bridge is a dport to a CFMWS decode and it is a uport to the
685 * dport (PCIe Root Ports) in the host bridge.
686 */
add_host_bridge_uport(struct device * match,void * arg)687 static int add_host_bridge_uport(struct device *match, void *arg)
688 {
689 struct cxl_port *root_port = arg;
690 struct device *host = root_port->dev.parent;
691 struct acpi_device *hb = to_cxl_host_bridge(host, match);
692 struct acpi_pci_root *pci_root;
693 struct cxl_dport *dport;
694 struct cxl_port *port;
695 struct device *bridge;
696 struct cxl_chbs_context ctx;
697 resource_size_t component_reg_phys;
698 int rc;
699
700 if (!hb)
701 return 0;
702
703 pci_root = acpi_pci_find_root(hb->handle);
704 bridge = pci_root->bus->bridge;
705 dport = cxl_find_dport_by_dev(root_port, bridge);
706 if (!dport) {
707 dev_dbg(host, "host bridge expected and not found\n");
708 return 0;
709 }
710
711 if (dport->rch) {
712 dev_info(bridge, "host supports CXL (restricted)\n");
713 return 0;
714 }
715
716 rc = cxl_get_chbs(match, hb, &ctx);
717 if (rc)
718 return rc;
719
720 if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {
721 dev_warn(bridge,
722 "CXL CHBS version mismatch, skip port registration\n");
723 return 0;
724 }
725
726 component_reg_phys = ctx.base;
727 if (component_reg_phys != CXL_RESOURCE_NONE)
728 dev_dbg(match, "CHBCR found for UID %lld: %pa\n",
729 ctx.uid, &component_reg_phys);
730
731 rc = devm_cxl_register_pci_bus(host, bridge, pci_root->bus);
732 if (rc)
733 return rc;
734
735 port = devm_cxl_add_port(host, bridge, component_reg_phys, dport);
736 if (IS_ERR(port))
737 return PTR_ERR(port);
738
739 dev_info(bridge, "host supports CXL\n");
740
741 return 0;
742 }
743
add_root_nvdimm_bridge(struct device * match,void * data)744 static int add_root_nvdimm_bridge(struct device *match, void *data)
745 {
746 struct cxl_decoder *cxld;
747 struct cxl_port *root_port = data;
748 struct cxl_nvdimm_bridge *cxl_nvb;
749 struct device *host = root_port->dev.parent;
750
751 if (!is_root_decoder(match))
752 return 0;
753
754 cxld = to_cxl_decoder(match);
755 if (!(cxld->flags & CXL_DECODER_F_PMEM))
756 return 0;
757
758 cxl_nvb = devm_cxl_add_nvdimm_bridge(host, root_port);
759 if (IS_ERR(cxl_nvb)) {
760 dev_dbg(host, "failed to register pmem\n");
761 return PTR_ERR(cxl_nvb);
762 }
763 dev_dbg(host, "%s: add: %s\n", dev_name(&root_port->dev),
764 dev_name(&cxl_nvb->dev));
765 return 1;
766 }
767
768 static struct lock_class_key cxl_root_key;
769
cxl_acpi_lock_reset_class(void * dev)770 static void cxl_acpi_lock_reset_class(void *dev)
771 {
772 device_lock_reset_class(dev);
773 }
774
cxl_set_public_resource(struct resource * priv,struct resource * pub)775 static void cxl_set_public_resource(struct resource *priv, struct resource *pub)
776 {
777 priv->desc = (unsigned long) pub;
778 }
779
cxl_get_public_resource(struct resource * priv)780 static struct resource *cxl_get_public_resource(struct resource *priv)
781 {
782 return (struct resource *) priv->desc;
783 }
784
remove_cxl_resources(void * data)785 static void remove_cxl_resources(void *data)
786 {
787 struct resource *res, *next, *cxl = data;
788
789 for (res = cxl->child; res; res = next) {
790 struct resource *victim = cxl_get_public_resource(res);
791
792 next = res->sibling;
793 remove_resource(res);
794
795 if (victim) {
796 remove_resource(victim);
797 kfree(victim);
798 }
799
800 del_cxl_resource(res);
801 }
802 }
803
804 /**
805 * add_cxl_resources() - reflect CXL fixed memory windows in iomem_resource
806 * @cxl_res: A standalone resource tree where each CXL window is a sibling
807 *
808 * Walk each CXL window in @cxl_res and add it to iomem_resource potentially
809 * expanding its boundaries to ensure that any conflicting resources become
810 * children. If a window is expanded it may then conflict with a another window
811 * entry and require the window to be truncated or trimmed. Consider this
812 * situation::
813 *
814 * |-- "CXL Window 0" --||----- "CXL Window 1" -----|
815 * |--------------- "System RAM" -------------|
816 *
817 * ...where platform firmware has established as System RAM resource across 2
818 * windows, but has left some portion of window 1 for dynamic CXL region
819 * provisioning. In this case "Window 0" will span the entirety of the "System
820 * RAM" span, and "CXL Window 1" is truncated to the remaining tail past the end
821 * of that "System RAM" resource.
822 */
add_cxl_resources(struct resource * cxl_res)823 static int add_cxl_resources(struct resource *cxl_res)
824 {
825 struct resource *res, *new, *next;
826
827 for (res = cxl_res->child; res; res = next) {
828 new = kzalloc_obj(*new);
829 if (!new)
830 return -ENOMEM;
831 new->name = res->name;
832 new->start = res->start;
833 new->end = res->end;
834 new->flags = IORESOURCE_MEM;
835 new->desc = IORES_DESC_CXL;
836
837 /*
838 * Record the public resource in the private cxl_res tree for
839 * later removal.
840 */
841 cxl_set_public_resource(res, new);
842
843 insert_resource_expand_to_fit(&iomem_resource, new);
844
845 next = res->sibling;
846 while (next && resource_overlaps(new, next)) {
847 if (resource_contains(new, next)) {
848 struct resource *_next = next->sibling;
849
850 remove_resource(next);
851 del_cxl_resource(next);
852 next = _next;
853 } else
854 next->start = new->end + 1;
855 }
856 }
857 return 0;
858 }
859
pair_cxl_resource(struct device * dev,void * data)860 static int pair_cxl_resource(struct device *dev, void *data)
861 {
862 struct resource *cxl_res = data;
863 struct resource *p;
864
865 if (!is_root_decoder(dev))
866 return 0;
867
868 for (p = cxl_res->child; p; p = p->sibling) {
869 struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev);
870 struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
871 struct resource res = {
872 .start = cxld->hpa_range.start,
873 .end = cxld->hpa_range.end,
874 .flags = IORESOURCE_MEM,
875 };
876
877 if (resource_contains(p, &res)) {
878 cxlrd->res = cxl_get_public_resource(p);
879 break;
880 }
881 }
882
883 return 0;
884 }
885
cxl_acpi_probe(struct platform_device * pdev)886 static int cxl_acpi_probe(struct platform_device *pdev)
887 {
888 int rc;
889 struct resource *cxl_res;
890 struct cxl_root *cxl_root;
891 struct cxl_port *root_port;
892 struct device *host = &pdev->dev;
893 struct acpi_device *adev = ACPI_COMPANION(host);
894 struct cxl_cfmws_context ctx;
895
896 device_lock_set_class(&pdev->dev, &cxl_root_key);
897 rc = devm_add_action_or_reset(&pdev->dev, cxl_acpi_lock_reset_class,
898 &pdev->dev);
899 if (rc)
900 return rc;
901
902 cxl_res = devm_kzalloc(host, sizeof(*cxl_res), GFP_KERNEL);
903 if (!cxl_res)
904 return -ENOMEM;
905 cxl_res->name = "CXL mem";
906 cxl_res->start = 0;
907 cxl_res->end = -1;
908 cxl_res->flags = IORESOURCE_MEM;
909
910 cxl_root = devm_cxl_add_root(host);
911 if (IS_ERR(cxl_root))
912 return PTR_ERR(cxl_root);
913 cxl_root->ops.qos_class = cxl_acpi_qos_class;
914 root_port = &cxl_root->port;
915
916 cxl_setup_prm_address_translation(cxl_root);
917
918 rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
919 add_host_bridge_dport);
920 if (rc < 0)
921 return rc;
922
923 rc = devm_add_action_or_reset(host, remove_cxl_resources, cxl_res);
924 if (rc)
925 return rc;
926
927 ctx = (struct cxl_cfmws_context) {
928 .dev = host,
929 .root_port = root_port,
930 .cxl_res = cxl_res,
931 };
932 rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, cxl_parse_cfmws, &ctx);
933 if (rc < 0)
934 return -ENXIO;
935
936 rc = add_cxl_resources(cxl_res);
937 if (rc)
938 return rc;
939
940 /*
941 * Populate the root decoders with their related iomem resource,
942 * if present
943 */
944 device_for_each_child(&root_port->dev, cxl_res, pair_cxl_resource);
945
946 /*
947 * Root level scanned with host-bridge as dports, now scan host-bridges
948 * for their role as CXL uports to their CXL-capable PCIe Root Ports.
949 */
950 rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
951 add_host_bridge_uport);
952 if (rc < 0)
953 return rc;
954
955 if (IS_ENABLED(CONFIG_CXL_PMEM))
956 rc = device_for_each_child(&root_port->dev, root_port,
957 add_root_nvdimm_bridge);
958 if (rc < 0)
959 return rc;
960
961 /* In case PCI is scanned before ACPI re-trigger memdev attach */
962 cxl_bus_rescan();
963 return 0;
964 }
965
966 static const struct acpi_device_id cxl_acpi_ids[] = {
967 { "ACPI0017" },
968 { },
969 };
970 MODULE_DEVICE_TABLE(acpi, cxl_acpi_ids);
971
972 static const struct platform_device_id cxl_test_ids[] = {
973 { "cxl_acpi" },
974 { },
975 };
976 MODULE_DEVICE_TABLE(platform, cxl_test_ids);
977
978 static struct platform_driver cxl_acpi_driver = {
979 .probe = cxl_acpi_probe,
980 .driver = {
981 .name = KBUILD_MODNAME,
982 .acpi_match_table = cxl_acpi_ids,
983 },
984 .id_table = cxl_test_ids,
985 };
986
cxl_acpi_init(void)987 static int __init cxl_acpi_init(void)
988 {
989 return platform_driver_register(&cxl_acpi_driver);
990 }
991
cxl_acpi_exit(void)992 static void __exit cxl_acpi_exit(void)
993 {
994 platform_driver_unregister(&cxl_acpi_driver);
995 cxl_bus_drain();
996 }
997
998 /*
999 * Load before dax_hmem sees 'Soft Reserved' CXL ranges. Use
1000 * subsys_initcall_sync() since there is an order dependency with
1001 * subsys_initcall(efisubsys_init), which must run first.
1002 */
1003 subsys_initcall_sync(cxl_acpi_init);
1004
1005 /*
1006 * Arrange for host-bridge ports to be active synchronous with
1007 * cxl_acpi_probe() exit.
1008 */
1009 MODULE_SOFTDEP("pre: cxl_port");
1010
1011 module_exit(cxl_acpi_exit);
1012 MODULE_DESCRIPTION("CXL ACPI: Platform Support");
1013 MODULE_LICENSE("GPL v2");
1014 MODULE_IMPORT_NS("CXL");
1015 MODULE_IMPORT_NS("ACPI");
1016