1 /* 2 * linux/drivers/video/arkfb.c -- Frame buffer device driver for ARK 2000PV 3 * with ICS 5342 dac (it is easy to add support for different dacs). 4 * 5 * Copyright (c) 2007 Ondrej Zajicek <santiago@crfreenet.org> 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file COPYING in the main directory of this archive for 9 * more details. 10 * 11 * Code is based on s3fb 12 */ 13 14 #include <linux/aperture.h> 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/errno.h> 18 #include <linux/string.h> 19 #include <linux/mm.h> 20 #include <linux/tty.h> 21 #include <linux/slab.h> 22 #include <linux/delay.h> 23 #include <linux/fb.h> 24 #include <linux/svga.h> 25 #include <linux/init.h> 26 #include <linux/pci.h> 27 #include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */ 28 #include <video/vga.h> 29 30 struct arkfb_info { 31 int mclk_freq; 32 int wc_cookie; 33 34 struct dac_info *dac; 35 struct vgastate state; 36 struct mutex open_lock; 37 unsigned int ref_count; 38 u32 pseudo_palette[16]; 39 }; 40 41 42 /* ------------------------------------------------------------------------- */ 43 44 45 static const struct svga_fb_format arkfb_formats[] = { 46 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, 47 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 8}, 48 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, 49 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16}, 50 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1, 51 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16}, 52 { 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, 53 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 8}, 54 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0, 55 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4}, 56 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0, 57 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4}, 58 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, 59 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 8, 8}, 60 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, 61 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 2}, 62 SVGA_FORMAT_END 63 }; 64 65 66 /* CRT timing register sets */ 67 68 static const struct vga_regset ark_h_total_regs[] = {{0x00, 0, 7}, {0x41, 7, 7}, VGA_REGSET_END}; 69 static const struct vga_regset ark_h_display_regs[] = {{0x01, 0, 7}, {0x41, 6, 6}, VGA_REGSET_END}; 70 static const struct vga_regset ark_h_blank_start_regs[] = {{0x02, 0, 7}, {0x41, 5, 5}, VGA_REGSET_END}; 71 static const struct vga_regset ark_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7 }, VGA_REGSET_END}; 72 static const struct vga_regset ark_h_sync_start_regs[] = {{0x04, 0, 7}, {0x41, 4, 4}, VGA_REGSET_END}; 73 static const struct vga_regset ark_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END}; 74 75 static const struct vga_regset ark_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x40, 7, 7}, VGA_REGSET_END}; 76 static const struct vga_regset ark_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x40, 6, 6}, VGA_REGSET_END}; 77 static const struct vga_regset ark_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x40, 5, 5}, VGA_REGSET_END}; 78 // const struct vga_regset ark_v_blank_end_regs[] = {{0x16, 0, 6}, VGA_REGSET_END}; 79 static const struct vga_regset ark_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END}; 80 static const struct vga_regset ark_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x40, 4, 4}, VGA_REGSET_END}; 81 static const struct vga_regset ark_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END}; 82 83 static const struct vga_regset ark_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, VGA_REGSET_END}; 84 static const struct vga_regset ark_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x40, 0, 2}, VGA_REGSET_END}; 85 static const struct vga_regset ark_offset_regs[] = {{0x13, 0, 7}, {0x41, 3, 3}, VGA_REGSET_END}; 86 87 static const struct svga_timing_regs ark_timing_regs = { 88 ark_h_total_regs, ark_h_display_regs, ark_h_blank_start_regs, 89 ark_h_blank_end_regs, ark_h_sync_start_regs, ark_h_sync_end_regs, 90 ark_v_total_regs, ark_v_display_regs, ark_v_blank_start_regs, 91 ark_v_blank_end_regs, ark_v_sync_start_regs, ark_v_sync_end_regs, 92 }; 93 94 95 /* ------------------------------------------------------------------------- */ 96 97 98 /* Module parameters */ 99 100 static char *mode_option = "640x480-8@60"; 101 102 MODULE_AUTHOR("(c) 2007 Ondrej Zajicek <santiago@crfreenet.org>"); 103 MODULE_LICENSE("GPL"); 104 MODULE_DESCRIPTION("fbdev driver for ARK 2000PV"); 105 106 module_param(mode_option, charp, 0444); 107 MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)"); 108 module_param_named(mode, mode_option, charp, 0444); 109 MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)"); 110 111 static int threshold = 4; 112 113 module_param(threshold, int, 0644); 114 MODULE_PARM_DESC(threshold, "FIFO threshold"); 115 116 117 /* ------------------------------------------------------------------------- */ 118 119 120 static void arkfb_settile(struct fb_info *info, struct fb_tilemap *map) 121 { 122 const u8 *font = map->data; 123 u8 __iomem *fb = (u8 __iomem *)info->screen_base; 124 int i, c; 125 126 if ((map->width != 8) || (map->height != 16) || 127 (map->depth != 1) || (map->length != 256)) { 128 fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n", 129 map->width, map->height, map->depth, map->length); 130 return; 131 } 132 133 fb += 2; 134 for (c = 0; c < map->length; c++) { 135 for (i = 0; i < map->height; i++) { 136 fb_writeb(font[i], &fb[i * 4]); 137 fb_writeb(font[i], &fb[i * 4 + (128 * 8)]); 138 } 139 fb += 128; 140 141 if ((c % 8) == 7) 142 fb += 128*8; 143 144 font += map->height; 145 } 146 } 147 148 static void arkfb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor) 149 { 150 struct arkfb_info *par = info->par; 151 152 svga_tilecursor(par->state.vgabase, info, cursor); 153 } 154 155 static struct fb_tile_ops arkfb_tile_ops = { 156 .fb_settile = arkfb_settile, 157 .fb_tilecopy = svga_tilecopy, 158 .fb_tilefill = svga_tilefill, 159 .fb_tileblit = svga_tileblit, 160 .fb_tilecursor = arkfb_tilecursor, 161 .fb_get_tilemax = svga_get_tilemax, 162 }; 163 164 165 /* ------------------------------------------------------------------------- */ 166 167 168 /* image data is MSB-first, fb structure is MSB-first too */ 169 static inline u32 expand_color(u32 c) 170 { 171 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF; 172 } 173 174 /* arkfb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */ 175 static void arkfb_iplan_imageblit(struct fb_info *info, const struct fb_image *image) 176 { 177 u32 fg = expand_color(image->fg_color); 178 u32 bg = expand_color(image->bg_color); 179 const u8 *src1, *src; 180 u8 __iomem *dst1; 181 u32 __iomem *dst; 182 u32 val; 183 int x, y; 184 185 src1 = image->data; 186 dst1 = info->screen_base + (image->dy * info->fix.line_length) 187 + ((image->dx / 8) * 4); 188 189 for (y = 0; y < image->height; y++) { 190 src = src1; 191 dst = (u32 __iomem *) dst1; 192 for (x = 0; x < image->width; x += 8) { 193 val = *(src++) * 0x01010101; 194 val = (val & fg) | (~val & bg); 195 fb_writel(val, dst++); 196 } 197 src1 += image->width / 8; 198 dst1 += info->fix.line_length; 199 } 200 201 } 202 203 /* arkfb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */ 204 static void arkfb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 205 { 206 u32 fg = expand_color(rect->color); 207 u8 __iomem *dst1; 208 u32 __iomem *dst; 209 int x, y; 210 211 dst1 = info->screen_base + (rect->dy * info->fix.line_length) 212 + ((rect->dx / 8) * 4); 213 214 for (y = 0; y < rect->height; y++) { 215 dst = (u32 __iomem *) dst1; 216 for (x = 0; x < rect->width; x += 8) { 217 fb_writel(fg, dst++); 218 } 219 dst1 += info->fix.line_length; 220 } 221 222 } 223 224 225 /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */ 226 static inline u32 expand_pixel(u32 c) 227 { 228 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) | 229 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF; 230 } 231 232 /* arkfb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */ 233 static void arkfb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image) 234 { 235 u32 fg = image->fg_color * 0x11111111; 236 u32 bg = image->bg_color * 0x11111111; 237 const u8 *src1, *src; 238 u8 __iomem *dst1; 239 u32 __iomem *dst; 240 u32 val; 241 int x, y; 242 243 src1 = image->data; 244 dst1 = info->screen_base + (image->dy * info->fix.line_length) 245 + ((image->dx / 8) * 4); 246 247 for (y = 0; y < image->height; y++) { 248 src = src1; 249 dst = (u32 __iomem *) dst1; 250 for (x = 0; x < image->width; x += 8) { 251 val = expand_pixel(*(src++)); 252 val = (val & fg) | (~val & bg); 253 fb_writel(val, dst++); 254 } 255 src1 += image->width / 8; 256 dst1 += info->fix.line_length; 257 } 258 259 } 260 261 static void arkfb_imageblit(struct fb_info *info, const struct fb_image *image) 262 { 263 if ((info->var.bits_per_pixel == 4) && (image->depth == 1) 264 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) { 265 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES) 266 arkfb_iplan_imageblit(info, image); 267 else 268 arkfb_cfb4_imageblit(info, image); 269 } else 270 cfb_imageblit(info, image); 271 } 272 273 static void arkfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 274 { 275 if ((info->var.bits_per_pixel == 4) 276 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0) 277 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)) 278 arkfb_iplan_fillrect(info, rect); 279 else 280 cfb_fillrect(info, rect); 281 } 282 283 284 /* ------------------------------------------------------------------------- */ 285 286 287 enum 288 { 289 DAC_PSEUDO8_8, 290 DAC_RGB1555_8, 291 DAC_RGB0565_8, 292 DAC_RGB0888_8, 293 DAC_RGB8888_8, 294 DAC_PSEUDO8_16, 295 DAC_RGB1555_16, 296 DAC_RGB0565_16, 297 DAC_RGB0888_16, 298 DAC_RGB8888_16, 299 DAC_MAX 300 }; 301 302 struct dac_ops { 303 int (*dac_get_mode)(struct dac_info *info); 304 int (*dac_set_mode)(struct dac_info *info, int mode); 305 int (*dac_get_freq)(struct dac_info *info, int channel); 306 int (*dac_set_freq)(struct dac_info *info, int channel, u32 freq); 307 void (*dac_release)(struct dac_info *info); 308 }; 309 310 typedef void (*dac_read_regs_t)(void *data, u8 *code, int count); 311 typedef void (*dac_write_regs_t)(void *data, u8 *code, int count); 312 313 struct dac_info 314 { 315 struct dac_ops *dacops; 316 dac_read_regs_t dac_read_regs; 317 dac_write_regs_t dac_write_regs; 318 void *data; 319 }; 320 321 static inline void dac_read_regs(struct dac_info *info, u8 *code, int count) 322 { 323 info->dac_read_regs(info->data, code, count); 324 } 325 326 static inline void dac_write_reg(struct dac_info *info, u8 reg, u8 val) 327 { 328 u8 code[2] = {reg, val}; 329 info->dac_write_regs(info->data, code, 1); 330 } 331 332 static inline void dac_write_regs(struct dac_info *info, u8 *code, int count) 333 { 334 info->dac_write_regs(info->data, code, count); 335 } 336 337 static inline int dac_set_mode(struct dac_info *info, int mode) 338 { 339 return info->dacops->dac_set_mode(info, mode); 340 } 341 342 static inline int dac_set_freq(struct dac_info *info, int channel, u32 freq) 343 { 344 return info->dacops->dac_set_freq(info, channel, freq); 345 } 346 347 static inline void dac_release(struct dac_info *info) 348 { 349 info->dacops->dac_release(info); 350 } 351 352 353 /* ------------------------------------------------------------------------- */ 354 355 356 /* ICS5342 DAC */ 357 358 struct ics5342_info 359 { 360 struct dac_info dac; 361 u8 mode; 362 }; 363 364 #define DAC_PAR(info) ((struct ics5342_info *) info) 365 366 /* LSB is set to distinguish unused slots */ 367 static const u8 ics5342_mode_table[DAC_MAX] = { 368 [DAC_PSEUDO8_8] = 0x01, [DAC_RGB1555_8] = 0x21, [DAC_RGB0565_8] = 0x61, 369 [DAC_RGB0888_8] = 0x41, [DAC_PSEUDO8_16] = 0x11, [DAC_RGB1555_16] = 0x31, 370 [DAC_RGB0565_16] = 0x51, [DAC_RGB0888_16] = 0x91, [DAC_RGB8888_16] = 0x71 371 }; 372 373 static int ics5342_set_mode(struct dac_info *info, int mode) 374 { 375 u8 code; 376 377 if (mode >= DAC_MAX) 378 return -EINVAL; 379 380 code = ics5342_mode_table[mode]; 381 382 if (! code) 383 return -EINVAL; 384 385 dac_write_reg(info, 6, code & 0xF0); 386 DAC_PAR(info)->mode = mode; 387 388 return 0; 389 } 390 391 static const struct svga_pll ics5342_pll = {3, 129, 3, 33, 0, 3, 392 60000, 250000, 14318}; 393 394 /* pd4 - allow only posdivider 4 (r=2) */ 395 static const struct svga_pll ics5342_pll_pd4 = {3, 129, 3, 33, 2, 2, 396 60000, 335000, 14318}; 397 398 /* 270 MHz should be upper bound for VCO clock according to specs, 399 but that is too restrictive in pd4 case */ 400 401 static int ics5342_set_freq(struct dac_info *info, int channel, u32 freq) 402 { 403 u16 m, n, r; 404 405 /* only postdivider 4 (r=2) is valid in mode DAC_PSEUDO8_16 */ 406 int rv = svga_compute_pll((DAC_PAR(info)->mode == DAC_PSEUDO8_16) 407 ? &ics5342_pll_pd4 : &ics5342_pll, 408 freq, &m, &n, &r, 0); 409 410 if (rv < 0) { 411 return -EINVAL; 412 } else { 413 u8 code[6] = {4, 3, 5, m-2, 5, (n-2) | (r << 5)}; 414 dac_write_regs(info, code, 3); 415 return 0; 416 } 417 } 418 419 static void ics5342_release(struct dac_info *info) 420 { 421 ics5342_set_mode(info, DAC_PSEUDO8_8); 422 kfree(info); 423 } 424 425 static struct dac_ops ics5342_ops = { 426 .dac_set_mode = ics5342_set_mode, 427 .dac_set_freq = ics5342_set_freq, 428 .dac_release = ics5342_release 429 }; 430 431 432 static struct dac_info * ics5342_init(dac_read_regs_t drr, dac_write_regs_t dwr, void *data) 433 { 434 struct ics5342_info *ics_info = kzalloc_obj(struct ics5342_info, 435 GFP_KERNEL); 436 struct dac_info *info = &ics_info->dac; 437 438 if (!ics_info) 439 return NULL; 440 441 info->dacops = &ics5342_ops; 442 info->dac_read_regs = drr; 443 info->dac_write_regs = dwr; 444 info->data = data; 445 DAC_PAR(info)->mode = DAC_PSEUDO8_8; /* estimation */ 446 return info; 447 } 448 449 450 /* ------------------------------------------------------------------------- */ 451 452 453 static unsigned short dac_regs[4] = {0x3c8, 0x3c9, 0x3c6, 0x3c7}; 454 455 static void ark_dac_read_regs(void *data, u8 *code, int count) 456 { 457 struct fb_info *info = data; 458 struct arkfb_info *par; 459 u8 regval; 460 461 par = info->par; 462 regval = vga_rseq(par->state.vgabase, 0x1C); 463 while (count != 0) 464 { 465 vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0)); 466 code[1] = vga_r(par->state.vgabase, dac_regs[code[0] & 3]); 467 count--; 468 code += 2; 469 } 470 471 vga_wseq(par->state.vgabase, 0x1C, regval); 472 } 473 474 static void ark_dac_write_regs(void *data, u8 *code, int count) 475 { 476 struct fb_info *info = data; 477 struct arkfb_info *par; 478 u8 regval; 479 480 par = info->par; 481 regval = vga_rseq(par->state.vgabase, 0x1C); 482 while (count != 0) 483 { 484 vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0)); 485 vga_w(par->state.vgabase, dac_regs[code[0] & 3], code[1]); 486 count--; 487 code += 2; 488 } 489 490 vga_wseq(par->state.vgabase, 0x1C, regval); 491 } 492 493 494 static void ark_set_pixclock(struct fb_info *info, u32 pixclock) 495 { 496 struct arkfb_info *par = info->par; 497 u8 regval; 498 499 int rv = dac_set_freq(par->dac, 0, 1000000000 / pixclock); 500 if (rv < 0) { 501 fb_err(info, "cannot set requested pixclock, keeping old value\n"); 502 return; 503 } 504 505 /* Set VGA misc register */ 506 regval = vga_r(par->state.vgabase, VGA_MIS_R); 507 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); 508 } 509 510 511 /* Open framebuffer */ 512 513 static int arkfb_open(struct fb_info *info, int user) 514 { 515 struct arkfb_info *par = info->par; 516 517 mutex_lock(&(par->open_lock)); 518 if (par->ref_count == 0) { 519 void __iomem *vgabase = par->state.vgabase; 520 521 memset(&(par->state), 0, sizeof(struct vgastate)); 522 par->state.vgabase = vgabase; 523 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; 524 par->state.num_crtc = 0x60; 525 par->state.num_seq = 0x30; 526 save_vga(&(par->state)); 527 } 528 529 par->ref_count++; 530 mutex_unlock(&(par->open_lock)); 531 532 return 0; 533 } 534 535 /* Close framebuffer */ 536 537 static int arkfb_release(struct fb_info *info, int user) 538 { 539 struct arkfb_info *par = info->par; 540 541 mutex_lock(&(par->open_lock)); 542 if (par->ref_count == 0) { 543 mutex_unlock(&(par->open_lock)); 544 return -EINVAL; 545 } 546 547 if (par->ref_count == 1) { 548 restore_vga(&(par->state)); 549 dac_set_mode(par->dac, DAC_PSEUDO8_8); 550 } 551 552 par->ref_count--; 553 mutex_unlock(&(par->open_lock)); 554 555 return 0; 556 } 557 558 /* Validate passed in var */ 559 560 static int arkfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 561 { 562 int rv, mem, step; 563 564 if (!var->pixclock) 565 return -EINVAL; 566 567 /* Find appropriate format */ 568 rv = svga_match_format (arkfb_formats, var, NULL); 569 if (rv < 0) 570 { 571 fb_err(info, "unsupported mode requested\n"); 572 return rv; 573 } 574 575 /* Do not allow to have real resoulution larger than virtual */ 576 if (var->xres > var->xres_virtual) 577 var->xres_virtual = var->xres; 578 579 if (var->yres > var->yres_virtual) 580 var->yres_virtual = var->yres; 581 582 /* Round up xres_virtual to have proper alignment of lines */ 583 step = arkfb_formats[rv].xresstep - 1; 584 var->xres_virtual = (var->xres_virtual+step) & ~step; 585 586 587 /* Check whether have enough memory */ 588 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; 589 if (mem > info->screen_size) 590 { 591 fb_err(info, "not enough framebuffer memory (%d kB requested, %d kB available)\n", 592 mem >> 10, (unsigned int) (info->screen_size >> 10)); 593 return -EINVAL; 594 } 595 596 rv = svga_check_timings (&ark_timing_regs, var, info->node); 597 if (rv < 0) 598 { 599 fb_err(info, "invalid timings requested\n"); 600 return rv; 601 } 602 603 /* Interlaced mode is broken */ 604 if (var->vmode & FB_VMODE_INTERLACED) 605 return -EINVAL; 606 607 return 0; 608 } 609 610 /* Set video mode from par */ 611 612 static int arkfb_set_par(struct fb_info *info) 613 { 614 struct arkfb_info *par = info->par; 615 u32 value, mode, hmul, hdiv, offset_value, screen_size; 616 u32 bpp = info->var.bits_per_pixel; 617 u8 regval; 618 619 if (bpp != 0) { 620 info->fix.ypanstep = 1; 621 info->fix.line_length = (info->var.xres_virtual * bpp) / 8; 622 623 info->flags &= ~FBINFO_MISC_TILEBLITTING; 624 info->tileops = NULL; 625 626 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */ 627 if (bpp == 4) { 628 bitmap_zero(info->pixmap.blit_x, FB_MAX_BLIT_WIDTH); 629 set_bit(8 - 1, info->pixmap.blit_x); 630 } else { 631 bitmap_fill(info->pixmap.blit_x, FB_MAX_BLIT_WIDTH); 632 } 633 bitmap_fill(info->pixmap.blit_y, FB_MAX_BLIT_HEIGHT); 634 635 offset_value = (info->var.xres_virtual * bpp) / 64; 636 screen_size = info->var.yres_virtual * info->fix.line_length; 637 } else { 638 info->fix.ypanstep = 16; 639 info->fix.line_length = 0; 640 641 info->flags |= FBINFO_MISC_TILEBLITTING; 642 info->tileops = &arkfb_tile_ops; 643 644 /* supports 8x16 tiles only */ 645 bitmap_zero(info->pixmap.blit_x, FB_MAX_BLIT_WIDTH); 646 set_bit(8 - 1, info->pixmap.blit_x); 647 bitmap_zero(info->pixmap.blit_y, FB_MAX_BLIT_HEIGHT); 648 set_bit(16 - 1, info->pixmap.blit_y); 649 650 offset_value = info->var.xres_virtual / 16; 651 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64; 652 } 653 654 info->var.xoffset = 0; 655 info->var.yoffset = 0; 656 info->var.activate = FB_ACTIVATE_NOW; 657 658 /* Unlock registers */ 659 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); 660 661 /* Blank screen and turn off sync */ 662 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); 663 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); 664 665 /* Set default values */ 666 svga_set_default_gfx_regs(par->state.vgabase); 667 svga_set_default_atc_regs(par->state.vgabase); 668 svga_set_default_seq_regs(par->state.vgabase); 669 svga_set_default_crt_regs(par->state.vgabase); 670 svga_wcrt_multi(par->state.vgabase, ark_line_compare_regs, 0xFFFFFFFF); 671 svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, 0); 672 673 /* ARK specific initialization */ 674 svga_wseq_mask(par->state.vgabase, 0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */ 675 svga_wseq_mask(par->state.vgabase, 0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */ 676 677 vga_wseq(par->state.vgabase, 0x13, info->fix.smem_start >> 16); 678 vga_wseq(par->state.vgabase, 0x14, info->fix.smem_start >> 24); 679 vga_wseq(par->state.vgabase, 0x15, 0); 680 vga_wseq(par->state.vgabase, 0x16, 0); 681 682 /* Set the FIFO threshold register */ 683 /* It is fascinating way to store 5-bit value in 8-bit register */ 684 regval = 0x10 | ((threshold & 0x0E) >> 1) | (threshold & 0x01) << 7 | (threshold & 0x10) << 1; 685 vga_wseq(par->state.vgabase, 0x18, regval); 686 687 /* Set the offset register */ 688 fb_dbg(info, "offset register : %d\n", offset_value); 689 svga_wcrt_multi(par->state.vgabase, ark_offset_regs, offset_value); 690 691 /* fix for hi-res textmode */ 692 svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); 693 694 if (info->var.vmode & FB_VMODE_DOUBLE) 695 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80); 696 else 697 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80); 698 699 if (info->var.vmode & FB_VMODE_INTERLACED) 700 svga_wcrt_mask(par->state.vgabase, 0x44, 0x04, 0x04); 701 else 702 svga_wcrt_mask(par->state.vgabase, 0x44, 0x00, 0x04); 703 704 hmul = 1; 705 hdiv = 1; 706 mode = svga_match_format(arkfb_formats, &(info->var), &(info->fix)); 707 708 /* Set mode-specific register values */ 709 switch (mode) { 710 case 0: 711 fb_dbg(info, "text mode\n"); 712 svga_set_textmode_vga_regs(par->state.vgabase); 713 714 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */ 715 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ 716 dac_set_mode(par->dac, DAC_PSEUDO8_8); 717 718 break; 719 case 1: 720 fb_dbg(info, "4 bit pseudocolor\n"); 721 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); 722 723 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */ 724 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ 725 dac_set_mode(par->dac, DAC_PSEUDO8_8); 726 break; 727 case 2: 728 fb_dbg(info, "4 bit pseudocolor, planar\n"); 729 730 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */ 731 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ 732 dac_set_mode(par->dac, DAC_PSEUDO8_8); 733 break; 734 case 3: 735 fb_dbg(info, "8 bit pseudocolor\n"); 736 737 vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode */ 738 739 if (info->var.pixclock > 20000) { 740 fb_dbg(info, "not using multiplex\n"); 741 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ 742 dac_set_mode(par->dac, DAC_PSEUDO8_8); 743 } else { 744 fb_dbg(info, "using multiplex\n"); 745 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ 746 dac_set_mode(par->dac, DAC_PSEUDO8_16); 747 hdiv = 2; 748 } 749 break; 750 case 4: 751 fb_dbg(info, "5/5/5 truecolor\n"); 752 753 vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */ 754 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ 755 dac_set_mode(par->dac, DAC_RGB1555_16); 756 break; 757 case 5: 758 fb_dbg(info, "5/6/5 truecolor\n"); 759 760 vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */ 761 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ 762 dac_set_mode(par->dac, DAC_RGB0565_16); 763 break; 764 case 6: 765 fb_dbg(info, "8/8/8 truecolor\n"); 766 767 vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode ??? */ 768 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ 769 dac_set_mode(par->dac, DAC_RGB0888_16); 770 hmul = 3; 771 hdiv = 2; 772 break; 773 case 7: 774 fb_dbg(info, "8/8/8/8 truecolor\n"); 775 776 vga_wseq(par->state.vgabase, 0x11, 0x1E); /* 32bpp accel mode */ 777 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ 778 dac_set_mode(par->dac, DAC_RGB8888_16); 779 hmul = 2; 780 break; 781 default: 782 fb_err(info, "unsupported mode - bug\n"); 783 return -EINVAL; 784 } 785 786 value = (hdiv * info->var.pixclock) / hmul; 787 if (!value) { 788 fb_dbg(info, "invalid pixclock\n"); 789 value = 1; 790 } 791 ark_set_pixclock(info, value); 792 svga_set_timings(par->state.vgabase, &ark_timing_regs, &(info->var), hmul, hdiv, 793 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, 794 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1, 795 hmul, info->node); 796 797 /* Set interlaced mode start/end register */ 798 value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len; 799 value = ((value * hmul / hdiv) / 8) - 5; 800 vga_wcrt(par->state.vgabase, 0x42, (value + 1) / 2); 801 802 if (screen_size > info->screen_size) 803 screen_size = info->screen_size; 804 memset_io(info->screen_base, 0x00, screen_size); 805 /* Device and screen back on */ 806 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); 807 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); 808 809 return 0; 810 } 811 812 /* Set a colour register */ 813 814 static int arkfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 815 u_int transp, struct fb_info *fb) 816 { 817 switch (fb->var.bits_per_pixel) { 818 case 0: 819 case 4: 820 if (regno >= 16) 821 return -EINVAL; 822 823 if ((fb->var.bits_per_pixel == 4) && 824 (fb->var.nonstd == 0)) { 825 outb(0xF0, VGA_PEL_MSK); 826 outb(regno*16, VGA_PEL_IW); 827 } else { 828 outb(0x0F, VGA_PEL_MSK); 829 outb(regno, VGA_PEL_IW); 830 } 831 outb(red >> 10, VGA_PEL_D); 832 outb(green >> 10, VGA_PEL_D); 833 outb(blue >> 10, VGA_PEL_D); 834 break; 835 case 8: 836 if (regno >= 256) 837 return -EINVAL; 838 839 outb(0xFF, VGA_PEL_MSK); 840 outb(regno, VGA_PEL_IW); 841 outb(red >> 10, VGA_PEL_D); 842 outb(green >> 10, VGA_PEL_D); 843 outb(blue >> 10, VGA_PEL_D); 844 break; 845 case 16: 846 if (regno >= 16) 847 return 0; 848 849 if (fb->var.green.length == 5) 850 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) | 851 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11); 852 else if (fb->var.green.length == 6) 853 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) | 854 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11); 855 else 856 return -EINVAL; 857 break; 858 case 24: 859 case 32: 860 if (regno >= 16) 861 return 0; 862 863 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) | 864 (green & 0xFF00) | ((blue & 0xFF00) >> 8); 865 break; 866 default: 867 return -EINVAL; 868 } 869 870 return 0; 871 } 872 873 /* Set the display blanking state */ 874 875 static int arkfb_blank(int blank_mode, struct fb_info *info) 876 { 877 struct arkfb_info *par = info->par; 878 879 switch (blank_mode) { 880 case FB_BLANK_UNBLANK: 881 fb_dbg(info, "unblank\n"); 882 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); 883 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); 884 break; 885 case FB_BLANK_NORMAL: 886 fb_dbg(info, "blank\n"); 887 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); 888 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); 889 break; 890 case FB_BLANK_POWERDOWN: 891 case FB_BLANK_HSYNC_SUSPEND: 892 case FB_BLANK_VSYNC_SUSPEND: 893 fb_dbg(info, "sync down\n"); 894 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); 895 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); 896 break; 897 } 898 return 0; 899 } 900 901 902 /* Pan the display */ 903 904 static int arkfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) 905 { 906 struct arkfb_info *par = info->par; 907 unsigned int offset; 908 909 /* Calculate the offset */ 910 if (info->var.bits_per_pixel == 0) { 911 offset = (var->yoffset / 16) * (info->var.xres_virtual / 2) 912 + (var->xoffset / 2); 913 offset = offset >> 2; 914 } else { 915 offset = (var->yoffset * info->fix.line_length) + 916 (var->xoffset * info->var.bits_per_pixel / 8); 917 offset = offset >> ((info->var.bits_per_pixel == 4) ? 2 : 3); 918 } 919 920 /* Set the offset */ 921 svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, offset); 922 923 return 0; 924 } 925 926 927 /* ------------------------------------------------------------------------- */ 928 929 930 /* Frame buffer operations */ 931 932 static const struct fb_ops arkfb_ops = { 933 .owner = THIS_MODULE, 934 .fb_open = arkfb_open, 935 .fb_release = arkfb_release, 936 __FB_DEFAULT_IOMEM_OPS_RDWR, 937 .fb_check_var = arkfb_check_var, 938 .fb_set_par = arkfb_set_par, 939 .fb_setcolreg = arkfb_setcolreg, 940 .fb_blank = arkfb_blank, 941 .fb_pan_display = arkfb_pan_display, 942 .fb_fillrect = arkfb_fillrect, 943 .fb_copyarea = cfb_copyarea, 944 .fb_imageblit = arkfb_imageblit, 945 __FB_DEFAULT_IOMEM_OPS_MMAP, 946 .fb_get_caps = svga_get_caps, 947 }; 948 949 950 /* ------------------------------------------------------------------------- */ 951 952 953 /* PCI probe */ 954 static int ark_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 955 { 956 struct pci_bus_region bus_reg; 957 struct resource vga_res; 958 struct fb_info *info; 959 struct arkfb_info *par; 960 int rc; 961 u8 regval; 962 963 rc = aperture_remove_conflicting_pci_devices(dev, "arkfb"); 964 if (rc < 0) 965 return rc; 966 967 /* Ignore secondary VGA device because there is no VGA arbitration */ 968 if (! svga_primary_device(dev)) { 969 dev_info(&(dev->dev), "ignoring secondary device\n"); 970 return -ENODEV; 971 } 972 973 /* Allocate and fill driver data structure */ 974 info = framebuffer_alloc(sizeof(struct arkfb_info), &(dev->dev)); 975 if (!info) 976 return -ENOMEM; 977 978 par = info->par; 979 mutex_init(&par->open_lock); 980 981 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN; 982 info->fbops = &arkfb_ops; 983 984 /* Prepare PCI device */ 985 rc = pci_enable_device(dev); 986 if (rc < 0) { 987 dev_err(info->device, "cannot enable PCI device\n"); 988 goto err_enable_device; 989 } 990 991 rc = pci_request_regions(dev, "arkfb"); 992 if (rc < 0) { 993 dev_err(info->device, "cannot reserve framebuffer region\n"); 994 goto err_request_regions; 995 } 996 997 par->dac = ics5342_init(ark_dac_read_regs, ark_dac_write_regs, info); 998 if (! par->dac) { 999 rc = -ENOMEM; 1000 dev_err(info->device, "RAMDAC initialization failed\n"); 1001 goto err_dac; 1002 } 1003 1004 info->fix.smem_start = pci_resource_start(dev, 0); 1005 info->fix.smem_len = pci_resource_len(dev, 0); 1006 1007 /* Map physical IO memory address into kernel space */ 1008 info->screen_base = pci_iomap_wc(dev, 0, 0); 1009 if (! info->screen_base) { 1010 rc = -ENOMEM; 1011 dev_err(info->device, "iomap for framebuffer failed\n"); 1012 goto err_iomap; 1013 } 1014 1015 bus_reg.start = 0; 1016 bus_reg.end = 64 * 1024; 1017 1018 vga_res.flags = IORESOURCE_IO; 1019 1020 pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg); 1021 1022 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start; 1023 1024 /* FIXME get memsize */ 1025 regval = vga_rseq(par->state.vgabase, 0x10); 1026 info->screen_size = (1 << (regval >> 6)) << 20; 1027 info->fix.smem_len = info->screen_size; 1028 1029 strcpy(info->fix.id, "ARK 2000PV"); 1030 info->fix.mmio_start = 0; 1031 info->fix.mmio_len = 0; 1032 info->fix.type = FB_TYPE_PACKED_PIXELS; 1033 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; 1034 info->fix.ypanstep = 0; 1035 info->fix.accel = FB_ACCEL_NONE; 1036 info->pseudo_palette = (void*) (par->pseudo_palette); 1037 1038 /* Prepare startup mode */ 1039 rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8); 1040 if (! ((rc == 1) || (rc == 2))) { 1041 rc = -EINVAL; 1042 dev_err(info->device, "mode %s not found\n", mode_option); 1043 goto err_find_mode; 1044 } 1045 1046 rc = fb_alloc_cmap(&info->cmap, 256, 0); 1047 if (rc < 0) { 1048 dev_err(info->device, "cannot allocate colormap\n"); 1049 goto err_alloc_cmap; 1050 } 1051 1052 rc = register_framebuffer(info); 1053 if (rc < 0) { 1054 dev_err(info->device, "cannot register framebuffer\n"); 1055 goto err_reg_fb; 1056 } 1057 1058 fb_info(info, "%s on %s, %d MB RAM\n", 1059 info->fix.id, pci_name(dev), info->fix.smem_len >> 20); 1060 1061 /* Record a reference to the driver data */ 1062 pci_set_drvdata(dev, info); 1063 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start, 1064 info->fix.smem_len); 1065 return 0; 1066 1067 /* Error handling */ 1068 err_reg_fb: 1069 fb_dealloc_cmap(&info->cmap); 1070 err_alloc_cmap: 1071 err_find_mode: 1072 pci_iounmap(dev, info->screen_base); 1073 err_iomap: 1074 dac_release(par->dac); 1075 err_dac: 1076 pci_release_regions(dev); 1077 err_request_regions: 1078 /* pci_disable_device(dev); */ 1079 err_enable_device: 1080 framebuffer_release(info); 1081 return rc; 1082 } 1083 1084 /* PCI remove */ 1085 1086 static void ark_pci_remove(struct pci_dev *dev) 1087 { 1088 struct fb_info *info = pci_get_drvdata(dev); 1089 1090 if (info) { 1091 struct arkfb_info *par = info->par; 1092 arch_phys_wc_del(par->wc_cookie); 1093 dac_release(par->dac); 1094 unregister_framebuffer(info); 1095 fb_dealloc_cmap(&info->cmap); 1096 1097 pci_iounmap(dev, info->screen_base); 1098 pci_release_regions(dev); 1099 /* pci_disable_device(dev); */ 1100 1101 framebuffer_release(info); 1102 } 1103 } 1104 1105 1106 /* PCI suspend */ 1107 1108 static int __maybe_unused ark_pci_suspend(struct device *dev) 1109 { 1110 struct fb_info *info = dev_get_drvdata(dev); 1111 struct arkfb_info *par = info->par; 1112 1113 dev_info(info->device, "suspend\n"); 1114 1115 console_lock(); 1116 mutex_lock(&(par->open_lock)); 1117 1118 if (par->ref_count == 0) { 1119 mutex_unlock(&(par->open_lock)); 1120 console_unlock(); 1121 return 0; 1122 } 1123 1124 fb_set_suspend(info, 1); 1125 1126 mutex_unlock(&(par->open_lock)); 1127 console_unlock(); 1128 1129 return 0; 1130 } 1131 1132 1133 /* PCI resume */ 1134 1135 static int __maybe_unused ark_pci_resume(struct device *dev) 1136 { 1137 struct fb_info *info = dev_get_drvdata(dev); 1138 struct arkfb_info *par = info->par; 1139 1140 dev_info(info->device, "resume\n"); 1141 1142 console_lock(); 1143 mutex_lock(&(par->open_lock)); 1144 1145 if (par->ref_count == 0) 1146 goto fail; 1147 1148 arkfb_set_par(info); 1149 fb_set_suspend(info, 0); 1150 1151 fail: 1152 mutex_unlock(&(par->open_lock)); 1153 console_unlock(); 1154 return 0; 1155 } 1156 1157 static const struct dev_pm_ops ark_pci_pm_ops = { 1158 #ifdef CONFIG_PM_SLEEP 1159 .suspend = ark_pci_suspend, 1160 .resume = ark_pci_resume, 1161 .freeze = NULL, 1162 .thaw = ark_pci_resume, 1163 .poweroff = ark_pci_suspend, 1164 .restore = ark_pci_resume, 1165 #endif 1166 }; 1167 1168 /* List of boards that we are trying to support */ 1169 1170 static const struct pci_device_id ark_devices[] = { 1171 {PCI_DEVICE(0xEDD8, 0xA099)}, 1172 {0, 0, 0, 0, 0, 0, 0} 1173 }; 1174 1175 1176 MODULE_DEVICE_TABLE(pci, ark_devices); 1177 1178 static struct pci_driver arkfb_pci_driver = { 1179 .name = "arkfb", 1180 .id_table = ark_devices, 1181 .probe = ark_pci_probe, 1182 .remove = ark_pci_remove, 1183 .driver.pm = &ark_pci_pm_ops, 1184 }; 1185 1186 /* Cleanup */ 1187 1188 static void __exit arkfb_cleanup(void) 1189 { 1190 pr_debug("arkfb: cleaning up\n"); 1191 pci_unregister_driver(&arkfb_pci_driver); 1192 } 1193 1194 /* Driver Initialisation */ 1195 1196 static int __init arkfb_init(void) 1197 { 1198 1199 #ifndef MODULE 1200 char *option = NULL; 1201 #endif 1202 1203 if (fb_modesetting_disabled("arkfb")) 1204 return -ENODEV; 1205 1206 #ifndef MODULE 1207 if (fb_get_options("arkfb", &option)) 1208 return -ENODEV; 1209 1210 if (option && *option) 1211 mode_option = option; 1212 #endif 1213 1214 pr_debug("arkfb: initializing\n"); 1215 return pci_register_driver(&arkfb_pci_driver); 1216 } 1217 1218 module_init(arkfb_init); 1219 module_exit(arkfb_cleanup); 1220