Work around a bug in QEMU when loading data with a load pair instruction
where the source register is also the first destination register.

If this is the case, and we raise an exception in the middl

Work around a bug in QEMU when loading data with a load pair instruction
where the source register is also the first destination register.

If this is the case, and we raise an exception in the middle of the
instruction, for example the load is across two pages and the second page
isn't mapped, QEMU will have overwritten the address with invalid data.

This is a valid behaviour in most cases, with the exception of when a
destination register is also use in address generation. As such switch
the order of the registers to ensure the address register is second so it
will be written to second, after any exceptions have happened.

This has been acknowledged in upstream QEMU, however as the workaround is
simple also handle it here.

Sponsored by: DARPA, AFRL

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