1 /* 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $ 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include "opt_inet.h" 41 #include "opt_bwi.h" 42 #include "opt_wlan.h" 43 44 #include <sys/param.h> 45 #include <sys/endian.h> 46 #include <sys/kernel.h> 47 #include <sys/bus.h> 48 #include <sys/malloc.h> 49 #include <sys/proc.h> 50 #include <sys/rman.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/systm.h> 55 #include <sys/taskqueue.h> 56 57 #include <net/if.h> 58 #include <net/if_var.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 #include <net/if_arp.h> 63 #include <net/ethernet.h> 64 #include <net/if_llc.h> 65 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 #include <net80211/ieee80211_regdomain.h> 69 #include <net80211/ieee80211_phy.h> 70 #include <net80211/ieee80211_ratectl.h> 71 72 #include <net/bpf.h> 73 74 #ifdef INET 75 #include <netinet/in.h> 76 #include <netinet/if_ether.h> 77 #endif 78 79 #include <machine/bus.h> 80 81 #include <dev/pci/pcivar.h> 82 #include <dev/pci/pcireg.h> 83 84 #include <dev/bwi/bitops.h> 85 #include <dev/bwi/if_bwireg.h> 86 #include <dev/bwi/if_bwivar.h> 87 #include <dev/bwi/bwimac.h> 88 #include <dev/bwi/bwirf.h> 89 90 struct bwi_clock_freq { 91 u_int clkfreq_min; 92 u_int clkfreq_max; 93 }; 94 95 struct bwi_myaddr_bssid { 96 uint8_t myaddr[IEEE80211_ADDR_LEN]; 97 uint8_t bssid[IEEE80211_ADDR_LEN]; 98 } __packed; 99 100 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *, 101 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 102 const uint8_t [IEEE80211_ADDR_LEN], 103 const uint8_t [IEEE80211_ADDR_LEN]); 104 static void bwi_vap_delete(struct ieee80211vap *); 105 static void bwi_init(struct bwi_softc *); 106 static void bwi_parent(struct ieee80211com *); 107 static int bwi_transmit(struct ieee80211com *, struct mbuf *); 108 static void bwi_start_locked(struct bwi_softc *); 109 static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *, 110 const struct ieee80211_bpf_params *); 111 static void bwi_watchdog(void *); 112 static void bwi_scan_start(struct ieee80211com *); 113 static void bwi_getradiocaps(struct ieee80211com *, int, int *, 114 struct ieee80211_channel[]); 115 static void bwi_set_channel(struct ieee80211com *); 116 static void bwi_scan_end(struct ieee80211com *); 117 static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int); 118 static void bwi_updateslot(struct ieee80211com *); 119 static int bwi_media_change(struct ifnet *); 120 121 static void bwi_calibrate(void *); 122 123 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *); 124 static int bwi_calc_noise(struct bwi_softc *); 125 static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phytype); 126 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *, 127 struct bwi_rxbuf_hdr *, const void *, int, int, int); 128 129 static void bwi_restart(void *, int); 130 static void bwi_init_statechg(struct bwi_softc *, int); 131 static void bwi_stop(struct bwi_softc *, int); 132 static void bwi_stop_locked(struct bwi_softc *, int); 133 static int bwi_newbuf(struct bwi_softc *, int, int); 134 static int bwi_encap(struct bwi_softc *, int, struct mbuf *, 135 struct ieee80211_node *); 136 static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *, 137 struct ieee80211_node *, 138 const struct ieee80211_bpf_params *); 139 140 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t, 141 bus_addr_t, int, int); 142 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t); 143 144 static int bwi_init_tx_ring32(struct bwi_softc *, int); 145 static int bwi_init_rx_ring32(struct bwi_softc *); 146 static int bwi_init_txstats32(struct bwi_softc *); 147 static void bwi_free_tx_ring32(struct bwi_softc *, int); 148 static void bwi_free_rx_ring32(struct bwi_softc *); 149 static void bwi_free_txstats32(struct bwi_softc *); 150 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int); 151 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *, 152 int, bus_addr_t, int); 153 static int bwi_rxeof32(struct bwi_softc *); 154 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int); 155 static void bwi_txeof_status32(struct bwi_softc *); 156 157 static int bwi_init_tx_ring64(struct bwi_softc *, int); 158 static int bwi_init_rx_ring64(struct bwi_softc *); 159 static int bwi_init_txstats64(struct bwi_softc *); 160 static void bwi_free_tx_ring64(struct bwi_softc *, int); 161 static void bwi_free_rx_ring64(struct bwi_softc *); 162 static void bwi_free_txstats64(struct bwi_softc *); 163 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int); 164 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *, 165 int, bus_addr_t, int); 166 static int bwi_rxeof64(struct bwi_softc *); 167 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int); 168 static void bwi_txeof_status64(struct bwi_softc *); 169 170 static int bwi_rxeof(struct bwi_softc *, int); 171 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int); 172 static void bwi_txeof(struct bwi_softc *); 173 static void bwi_txeof_status(struct bwi_softc *, int); 174 static void bwi_enable_intrs(struct bwi_softc *, uint32_t); 175 static void bwi_disable_intrs(struct bwi_softc *, uint32_t); 176 177 static int bwi_dma_alloc(struct bwi_softc *); 178 static void bwi_dma_free(struct bwi_softc *); 179 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t, 180 struct bwi_ring_data *, bus_size_t, 181 uint32_t); 182 static int bwi_dma_mbuf_create(struct bwi_softc *); 183 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int); 184 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t); 185 static void bwi_dma_txstats_free(struct bwi_softc *); 186 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 187 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int, 188 bus_size_t, int); 189 190 static void bwi_power_on(struct bwi_softc *, int); 191 static int bwi_power_off(struct bwi_softc *, int); 192 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode); 193 static int bwi_set_clock_delay(struct bwi_softc *); 194 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *); 195 static int bwi_get_pwron_delay(struct bwi_softc *sc); 196 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t, 197 const uint8_t *); 198 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *); 199 200 static void bwi_get_card_flags(struct bwi_softc *); 201 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *); 202 203 static int bwi_bus_attach(struct bwi_softc *); 204 static int bwi_bbp_attach(struct bwi_softc *); 205 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode); 206 static void bwi_bbp_power_off(struct bwi_softc *); 207 208 static const char *bwi_regwin_name(const struct bwi_regwin *); 209 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *); 210 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *); 211 static int bwi_regwin_select(struct bwi_softc *, int); 212 213 static void bwi_led_attach(struct bwi_softc *); 214 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state); 215 static void bwi_led_event(struct bwi_softc *, int); 216 static void bwi_led_blink_start(struct bwi_softc *, int, int); 217 static void bwi_led_blink_next(void *); 218 static void bwi_led_blink_end(void *); 219 220 static const struct { 221 uint16_t did_min; 222 uint16_t did_max; 223 uint16_t bbp_id; 224 } bwi_bbpid_map[] = { 225 { 0x4301, 0x4301, 0x4301 }, 226 { 0x4305, 0x4307, 0x4307 }, 227 { 0x4402, 0x4403, 0x4402 }, 228 { 0x4610, 0x4615, 0x4610 }, 229 { 0x4710, 0x4715, 0x4710 }, 230 { 0x4720, 0x4725, 0x4309 } 231 }; 232 233 static const struct { 234 uint16_t bbp_id; 235 int nregwin; 236 } bwi_regwin_count[] = { 237 { 0x4301, 5 }, 238 { 0x4306, 6 }, 239 { 0x4307, 5 }, 240 { 0x4310, 8 }, 241 { 0x4401, 3 }, 242 { 0x4402, 3 }, 243 { 0x4610, 9 }, 244 { 0x4704, 9 }, 245 { 0x4710, 9 }, 246 { 0x5365, 7 } 247 }; 248 249 #define CLKSRC(src) \ 250 [BWI_CLKSRC_ ## src] = { \ 251 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \ 252 .freq_max = BWI_CLKSRC_ ##src## _FMAX \ 253 } 254 255 static const struct { 256 u_int freq_min; 257 u_int freq_max; 258 } bwi_clkfreq[BWI_CLKSRC_MAX] = { 259 CLKSRC(LP_OSC), 260 CLKSRC(CS_OSC), 261 CLKSRC(PCI) 262 }; 263 264 #undef CLKSRC 265 266 #define VENDOR_LED_ACT(vendor) \ 267 { \ 268 .vid = PCI_VENDOR_##vendor, \ 269 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \ 270 } 271 272 static const struct { 273 #define PCI_VENDOR_COMPAQ 0x0e11 274 #define PCI_VENDOR_LINKSYS 0x1737 275 uint16_t vid; 276 uint8_t led_act[BWI_LED_MAX]; 277 } bwi_vendor_led_act[] = { 278 VENDOR_LED_ACT(COMPAQ), 279 VENDOR_LED_ACT(LINKSYS) 280 #undef PCI_VENDOR_LINKSYS 281 #undef PCI_VENDOR_COMPAQ 282 }; 283 284 static const uint8_t bwi_default_led_act[BWI_LED_MAX] = 285 { BWI_VENDOR_LED_ACT_DEFAULT }; 286 287 #undef VENDOR_LED_ACT 288 289 static const struct { 290 int on_dur; 291 int off_dur; 292 } bwi_led_duration[109] = { 293 [0] = { 400, 100 }, 294 [2] = { 150, 75 }, 295 [4] = { 90, 45 }, 296 [11] = { 66, 34 }, 297 [12] = { 53, 26 }, 298 [18] = { 42, 21 }, 299 [22] = { 35, 17 }, 300 [24] = { 32, 16 }, 301 [36] = { 21, 10 }, 302 [48] = { 16, 8 }, 303 [72] = { 11, 5 }, 304 [96] = { 9, 4 }, 305 [108] = { 7, 3 } 306 }; 307 308 static const uint8_t bwi_chan_2ghz[] = 309 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 }; 310 311 #ifdef BWI_DEBUG 312 #ifdef BWI_DEBUG_VERBOSE 313 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER; 314 #else 315 static uint32_t bwi_debug; 316 #endif 317 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug); 318 #endif /* BWI_DEBUG */ 319 320 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN]; 321 322 uint16_t 323 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs) 324 { 325 return CSR_READ_2(sc, ofs + BWI_SPROM_START); 326 } 327 328 static __inline void 329 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array, 330 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len, 331 int tx) 332 { 333 struct bwi_desc32 *desc = &desc_array[desc_idx]; 334 uint32_t ctrl, addr, addr_hi, addr_lo; 335 336 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK); 337 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK); 338 339 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) | 340 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK); 341 342 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) | 343 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK); 344 if (desc_idx == ndesc - 1) 345 ctrl |= BWI_DESC32_C_EOR; 346 if (tx) { 347 /* XXX */ 348 ctrl |= BWI_DESC32_C_FRAME_START | 349 BWI_DESC32_C_FRAME_END | 350 BWI_DESC32_C_INTR; 351 } 352 353 desc->addr = htole32(addr); 354 desc->ctrl = htole32(ctrl); 355 } 356 357 int 358 bwi_attach(struct bwi_softc *sc) 359 { 360 struct ieee80211com *ic = &sc->sc_ic; 361 device_t dev = sc->sc_dev; 362 struct bwi_mac *mac; 363 struct bwi_phy *phy; 364 int i, error; 365 366 BWI_LOCK_INIT(sc); 367 368 /* 369 * Initialize taskq and various tasks 370 */ 371 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO, 372 taskqueue_thread_enqueue, &sc->sc_tq); 373 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 374 device_get_nameunit(dev)); 375 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc); 376 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0); 377 mbufq_init(&sc->sc_snd, ifqmaxlen); 378 379 /* 380 * Initialize sysctl variables 381 */ 382 sc->sc_fw_version = BWI_FW_VERSION3; 383 sc->sc_led_idle = (2350 * hz) / 1000; 384 sc->sc_led_ticks = ticks - sc->sc_led_idle; 385 sc->sc_led_blink = 1; 386 sc->sc_txpwr_calib = 1; 387 #ifdef BWI_DEBUG 388 sc->sc_debug = bwi_debug; 389 #endif 390 bwi_power_on(sc, 1); 391 392 error = bwi_bbp_attach(sc); 393 if (error) 394 goto fail; 395 396 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 397 if (error) 398 goto fail; 399 400 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) { 401 error = bwi_set_clock_delay(sc); 402 if (error) 403 goto fail; 404 405 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST); 406 if (error) 407 goto fail; 408 409 error = bwi_get_pwron_delay(sc); 410 if (error) 411 goto fail; 412 } 413 414 error = bwi_bus_attach(sc); 415 if (error) 416 goto fail; 417 418 bwi_get_card_flags(sc); 419 420 bwi_led_attach(sc); 421 422 for (i = 0; i < sc->sc_nmac; ++i) { 423 struct bwi_regwin *old; 424 425 mac = &sc->sc_mac[i]; 426 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old); 427 if (error) 428 goto fail; 429 430 error = bwi_mac_lateattach(mac); 431 if (error) 432 goto fail; 433 434 error = bwi_regwin_switch(sc, old, NULL); 435 if (error) 436 goto fail; 437 } 438 439 /* 440 * XXX First MAC is known to exist 441 * TODO2 442 */ 443 mac = &sc->sc_mac[0]; 444 phy = &mac->mac_phy; 445 446 bwi_bbp_power_off(sc); 447 448 error = bwi_dma_alloc(sc); 449 if (error) 450 goto fail; 451 452 error = bwi_mac_fw_alloc(mac); 453 if (error) 454 goto fail; 455 456 callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0); 457 458 /* 459 * Setup ratesets, phytype, channels and get MAC address 460 */ 461 if (phy->phy_mode == IEEE80211_MODE_11B || 462 phy->phy_mode == IEEE80211_MODE_11G) { 463 if (phy->phy_mode == IEEE80211_MODE_11B) { 464 ic->ic_phytype = IEEE80211_T_DS; 465 } else { 466 ic->ic_phytype = IEEE80211_T_OFDM; 467 } 468 469 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_macaddr); 470 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) { 471 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_macaddr); 472 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) { 473 device_printf(dev, 474 "invalid MAC address: %6D\n", 475 ic->ic_macaddr, ":"); 476 } 477 } 478 } else if (phy->phy_mode == IEEE80211_MODE_11A) { 479 /* TODO:11A */ 480 error = ENXIO; 481 goto fail; 482 } else { 483 panic("unknown phymode %d\n", phy->phy_mode); 484 } 485 486 /* Get locale */ 487 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO), 488 BWI_SPROM_CARD_INFO_LOCALE); 489 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale); 490 /* XXX use locale */ 491 bwi_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 492 ic->ic_channels); 493 494 ic->ic_softc = sc; 495 ic->ic_name = device_get_nameunit(dev); 496 ic->ic_caps = IEEE80211_C_STA | 497 IEEE80211_C_SHSLOT | 498 IEEE80211_C_SHPREAMBLE | 499 IEEE80211_C_WPA | 500 IEEE80211_C_BGSCAN | 501 IEEE80211_C_MONITOR; 502 ic->ic_opmode = IEEE80211_M_STA; 503 ieee80211_ifattach(ic); 504 505 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr); 506 507 /* override default methods */ 508 ic->ic_vap_create = bwi_vap_create; 509 ic->ic_vap_delete = bwi_vap_delete; 510 ic->ic_raw_xmit = bwi_raw_xmit; 511 ic->ic_updateslot = bwi_updateslot; 512 ic->ic_scan_start = bwi_scan_start; 513 ic->ic_scan_end = bwi_scan_end; 514 ic->ic_getradiocaps = bwi_getradiocaps; 515 ic->ic_set_channel = bwi_set_channel; 516 ic->ic_transmit = bwi_transmit; 517 ic->ic_parent = bwi_parent; 518 519 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 520 521 ieee80211_radiotap_attach(ic, 522 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 523 BWI_TX_RADIOTAP_PRESENT, 524 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 525 BWI_RX_RADIOTAP_PRESENT); 526 527 /* 528 * Add sysctl nodes 529 */ 530 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 531 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 532 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0, 533 "Firmware version"); 534 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 535 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 536 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0, 537 "# ticks before LED enters idle state"); 538 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 539 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 540 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0, 541 "Allow LED to blink"); 542 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 543 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 544 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0, 545 "Enable software TX power calibration"); 546 #ifdef BWI_DEBUG 547 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 548 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 549 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 550 #endif 551 if (bootverbose) 552 ieee80211_announce(ic); 553 554 return (0); 555 fail: 556 BWI_LOCK_DESTROY(sc); 557 return (error); 558 } 559 560 int 561 bwi_detach(struct bwi_softc *sc) 562 { 563 struct ieee80211com *ic = &sc->sc_ic; 564 int i; 565 566 bwi_stop(sc, 1); 567 callout_drain(&sc->sc_led_blink_ch); 568 callout_drain(&sc->sc_calib_ch); 569 callout_drain(&sc->sc_watchdog_timer); 570 ieee80211_ifdetach(ic); 571 572 for (i = 0; i < sc->sc_nmac; ++i) 573 bwi_mac_detach(&sc->sc_mac[i]); 574 bwi_dma_free(sc); 575 taskqueue_free(sc->sc_tq); 576 mbufq_drain(&sc->sc_snd); 577 578 BWI_LOCK_DESTROY(sc); 579 580 return (0); 581 } 582 583 static struct ieee80211vap * 584 bwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 585 enum ieee80211_opmode opmode, int flags, 586 const uint8_t bssid[IEEE80211_ADDR_LEN], 587 const uint8_t mac[IEEE80211_ADDR_LEN]) 588 { 589 struct bwi_vap *bvp; 590 struct ieee80211vap *vap; 591 592 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 593 return NULL; 594 bvp = malloc(sizeof(struct bwi_vap), M_80211_VAP, M_WAITOK | M_ZERO); 595 vap = &bvp->bv_vap; 596 /* enable s/w bmiss handling for sta mode */ 597 ieee80211_vap_setup(ic, vap, name, unit, opmode, 598 flags | IEEE80211_CLONE_NOBEACONS, bssid); 599 600 /* override default methods */ 601 bvp->bv_newstate = vap->iv_newstate; 602 vap->iv_newstate = bwi_newstate; 603 #if 0 604 vap->iv_update_beacon = bwi_beacon_update; 605 #endif 606 ieee80211_ratectl_init(vap); 607 608 /* complete setup */ 609 ieee80211_vap_attach(vap, bwi_media_change, ieee80211_media_status, 610 mac); 611 ic->ic_opmode = opmode; 612 return vap; 613 } 614 615 static void 616 bwi_vap_delete(struct ieee80211vap *vap) 617 { 618 struct bwi_vap *bvp = BWI_VAP(vap); 619 620 ieee80211_ratectl_deinit(vap); 621 ieee80211_vap_detach(vap); 622 free(bvp, M_80211_VAP); 623 } 624 625 void 626 bwi_suspend(struct bwi_softc *sc) 627 { 628 bwi_stop(sc, 1); 629 } 630 631 void 632 bwi_resume(struct bwi_softc *sc) 633 { 634 635 if (sc->sc_ic.ic_nrunning > 0) 636 bwi_init(sc); 637 } 638 639 int 640 bwi_shutdown(struct bwi_softc *sc) 641 { 642 bwi_stop(sc, 1); 643 return 0; 644 } 645 646 static void 647 bwi_power_on(struct bwi_softc *sc, int with_pll) 648 { 649 uint32_t gpio_in, gpio_out, gpio_en; 650 uint16_t status; 651 652 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); 653 if (gpio_in & BWI_PCIM_GPIO_PWR_ON) 654 goto back; 655 656 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 657 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 658 659 gpio_out |= BWI_PCIM_GPIO_PWR_ON; 660 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 661 if (with_pll) { 662 /* Turn off PLL first */ 663 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 664 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 665 } 666 667 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 668 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 669 DELAY(1000); 670 671 if (with_pll) { 672 /* Turn on PLL */ 673 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF; 674 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 675 DELAY(5000); 676 } 677 678 back: 679 /* Clear "Signaled Target Abort" */ 680 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 681 status &= ~PCIM_STATUS_STABORT; 682 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 683 } 684 685 static int 686 bwi_power_off(struct bwi_softc *sc, int with_pll) 687 { 688 uint32_t gpio_out, gpio_en; 689 690 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */ 691 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 692 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 693 694 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON; 695 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 696 if (with_pll) { 697 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 698 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 699 } 700 701 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 702 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 703 return 0; 704 } 705 706 int 707 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw, 708 struct bwi_regwin **old_rw) 709 { 710 int error; 711 712 if (old_rw != NULL) 713 *old_rw = NULL; 714 715 if (!BWI_REGWIN_EXIST(rw)) 716 return EINVAL; 717 718 if (sc->sc_cur_regwin != rw) { 719 error = bwi_regwin_select(sc, rw->rw_id); 720 if (error) { 721 device_printf(sc->sc_dev, "can't select regwin %d\n", 722 rw->rw_id); 723 return error; 724 } 725 } 726 727 if (old_rw != NULL) 728 *old_rw = sc->sc_cur_regwin; 729 sc->sc_cur_regwin = rw; 730 return 0; 731 } 732 733 static int 734 bwi_regwin_select(struct bwi_softc *sc, int id) 735 { 736 uint32_t win = BWI_PCIM_REGWIN(id); 737 int i; 738 739 #define RETRY_MAX 50 740 for (i = 0; i < RETRY_MAX; ++i) { 741 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4); 742 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win) 743 return 0; 744 DELAY(10); 745 } 746 #undef RETRY_MAX 747 748 return ENXIO; 749 } 750 751 static void 752 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev) 753 { 754 uint32_t val; 755 756 val = CSR_READ_4(sc, BWI_ID_HI); 757 *type = BWI_ID_HI_REGWIN_TYPE(val); 758 *rev = BWI_ID_HI_REGWIN_REV(val); 759 760 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, " 761 "vendor 0x%04x\n", *type, *rev, 762 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK)); 763 } 764 765 static int 766 bwi_bbp_attach(struct bwi_softc *sc) 767 { 768 uint16_t bbp_id, rw_type; 769 uint8_t rw_rev; 770 uint32_t info; 771 int error, nregwin, i; 772 773 /* 774 * Get 0th regwin information 775 * NOTE: 0th regwin should exist 776 */ 777 error = bwi_regwin_select(sc, 0); 778 if (error) { 779 device_printf(sc->sc_dev, "can't select regwin 0\n"); 780 return error; 781 } 782 bwi_regwin_info(sc, &rw_type, &rw_rev); 783 784 /* 785 * Find out BBP id 786 */ 787 bbp_id = 0; 788 info = 0; 789 if (rw_type == BWI_REGWIN_T_COM) { 790 info = CSR_READ_4(sc, BWI_INFO); 791 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK); 792 793 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev); 794 795 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY); 796 } else { 797 for (i = 0; i < nitems(bwi_bbpid_map); ++i) { 798 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min && 799 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) { 800 bbp_id = bwi_bbpid_map[i].bbp_id; 801 break; 802 } 803 } 804 if (bbp_id == 0) { 805 device_printf(sc->sc_dev, "no BBP id for device id " 806 "0x%04x\n", sc->sc_pci_did); 807 return ENXIO; 808 } 809 810 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) | 811 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK); 812 } 813 814 /* 815 * Find out number of regwins 816 */ 817 nregwin = 0; 818 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) { 819 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK); 820 } else { 821 for (i = 0; i < nitems(bwi_regwin_count); ++i) { 822 if (bwi_regwin_count[i].bbp_id == bbp_id) { 823 nregwin = bwi_regwin_count[i].nregwin; 824 break; 825 } 826 } 827 if (nregwin == 0) { 828 device_printf(sc->sc_dev, "no number of win for " 829 "BBP id 0x%04x\n", bbp_id); 830 return ENXIO; 831 } 832 } 833 834 /* Record BBP id/rev for later using */ 835 sc->sc_bbp_id = bbp_id; 836 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK); 837 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK); 838 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n", 839 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg); 840 841 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n", 842 nregwin, sc->sc_cap); 843 844 /* 845 * Create rest of the regwins 846 */ 847 848 /* Don't re-create common regwin, if it is already created */ 849 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0; 850 851 for (; i < nregwin; ++i) { 852 /* 853 * Get regwin information 854 */ 855 error = bwi_regwin_select(sc, i); 856 if (error) { 857 device_printf(sc->sc_dev, 858 "can't select regwin %d\n", i); 859 return error; 860 } 861 bwi_regwin_info(sc, &rw_type, &rw_rev); 862 863 /* 864 * Try attach: 865 * 1) Bus (PCI/PCIE) regwin 866 * 2) MAC regwin 867 * Ignore rest types of regwin 868 */ 869 if (rw_type == BWI_REGWIN_T_BUSPCI || 870 rw_type == BWI_REGWIN_T_BUSPCIE) { 871 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 872 device_printf(sc->sc_dev, 873 "bus regwin already exists\n"); 874 } else { 875 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i, 876 rw_type, rw_rev); 877 } 878 } else if (rw_type == BWI_REGWIN_T_MAC) { 879 /* XXX ignore return value */ 880 bwi_mac_attach(sc, i, rw_rev); 881 } 882 } 883 884 /* At least one MAC shold exist */ 885 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) { 886 device_printf(sc->sc_dev, "no MAC was found\n"); 887 return ENXIO; 888 } 889 KASSERT(sc->sc_nmac > 0, ("no mac's")); 890 891 /* Bus regwin must exist */ 892 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 893 device_printf(sc->sc_dev, "no bus regwin was found\n"); 894 return ENXIO; 895 } 896 897 /* Start with first MAC */ 898 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL); 899 if (error) 900 return error; 901 902 return 0; 903 } 904 905 int 906 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac) 907 { 908 struct bwi_regwin *old, *bus; 909 uint32_t val; 910 int error; 911 912 bus = &sc->sc_bus_regwin; 913 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin")); 914 915 /* 916 * Tell bus to generate requested interrupts 917 */ 918 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) { 919 /* 920 * NOTE: Read BWI_FLAGS from MAC regwin 921 */ 922 val = CSR_READ_4(sc, BWI_FLAGS); 923 924 error = bwi_regwin_switch(sc, bus, &old); 925 if (error) 926 return error; 927 928 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK)); 929 } else { 930 uint32_t mac_mask; 931 932 mac_mask = 1 << mac->mac_id; 933 934 error = bwi_regwin_switch(sc, bus, &old); 935 if (error) 936 return error; 937 938 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4); 939 val |= mac_mask << 8; 940 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4); 941 } 942 943 if (sc->sc_flags & BWI_F_BUS_INITED) 944 goto back; 945 946 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) { 947 /* 948 * Enable prefetch and burst 949 */ 950 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, 951 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST); 952 953 if (bus->rw_rev < 5) { 954 struct bwi_regwin *com = &sc->sc_com_regwin; 955 956 /* 957 * Configure timeouts for bus operation 958 */ 959 960 /* 961 * Set service timeout and request timeout 962 */ 963 CSR_SETBITS_4(sc, BWI_CONF_LO, 964 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) | 965 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK)); 966 967 /* 968 * If there is common regwin, we switch to that regwin 969 * and switch back to bus regwin once we have done. 970 */ 971 if (BWI_REGWIN_EXIST(com)) { 972 error = bwi_regwin_switch(sc, com, NULL); 973 if (error) 974 return error; 975 } 976 977 /* Let bus know what we have changed */ 978 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC); 979 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */ 980 CSR_WRITE_4(sc, BWI_BUS_DATA, 0); 981 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */ 982 983 if (BWI_REGWIN_EXIST(com)) { 984 error = bwi_regwin_switch(sc, bus, NULL); 985 if (error) 986 return error; 987 } 988 } else if (bus->rw_rev >= 11) { 989 /* 990 * Enable memory read multiple 991 */ 992 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM); 993 } 994 } else { 995 /* TODO:PCIE */ 996 } 997 998 sc->sc_flags |= BWI_F_BUS_INITED; 999 back: 1000 return bwi_regwin_switch(sc, old, NULL); 1001 } 1002 1003 static void 1004 bwi_get_card_flags(struct bwi_softc *sc) 1005 { 1006 #define PCI_VENDOR_APPLE 0x106b 1007 #define PCI_VENDOR_DELL 0x1028 1008 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS); 1009 if (sc->sc_card_flags == 0xffff) 1010 sc->sc_card_flags = 0; 1011 1012 if (sc->sc_pci_subvid == PCI_VENDOR_DELL && 1013 sc->sc_bbp_id == BWI_BBPID_BCM4301 && 1014 sc->sc_pci_revid == 0x74) 1015 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST; 1016 1017 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE && 1018 sc->sc_pci_subdid == 0x4e && /* XXX */ 1019 sc->sc_pci_revid > 0x40) 1020 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9; 1021 1022 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags); 1023 #undef PCI_VENDOR_DELL 1024 #undef PCI_VENDOR_APPLE 1025 } 1026 1027 static void 1028 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr) 1029 { 1030 int i; 1031 1032 for (i = 0; i < 3; ++i) { 1033 *((uint16_t *)eaddr + i) = 1034 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i)); 1035 } 1036 } 1037 1038 static void 1039 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq) 1040 { 1041 struct bwi_regwin *com; 1042 uint32_t val; 1043 u_int div; 1044 int src; 1045 1046 bzero(freq, sizeof(*freq)); 1047 com = &sc->sc_com_regwin; 1048 1049 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist")); 1050 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin")); 1051 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode")); 1052 1053 /* 1054 * Calculate clock frequency 1055 */ 1056 src = -1; 1057 div = 0; 1058 if (com->rw_rev < 6) { 1059 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 1060 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) { 1061 src = BWI_CLKSRC_PCI; 1062 div = 64; 1063 } else { 1064 src = BWI_CLKSRC_CS_OSC; 1065 div = 32; 1066 } 1067 } else if (com->rw_rev < 10) { 1068 val = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1069 1070 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC); 1071 if (src == BWI_CLKSRC_LP_OSC) { 1072 div = 1; 1073 } else { 1074 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2; 1075 1076 /* Unknown source */ 1077 if (src >= BWI_CLKSRC_MAX) 1078 src = BWI_CLKSRC_CS_OSC; 1079 } 1080 } else { 1081 val = CSR_READ_4(sc, BWI_CLOCK_INFO); 1082 1083 src = BWI_CLKSRC_CS_OSC; 1084 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2; 1085 } 1086 1087 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src)); 1088 KASSERT(div != 0, ("div zero")); 1089 1090 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n", 1091 src == BWI_CLKSRC_PCI ? "PCI" : 1092 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC")); 1093 1094 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div; 1095 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div; 1096 1097 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n", 1098 freq->clkfreq_min, freq->clkfreq_max); 1099 } 1100 1101 static int 1102 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 1103 { 1104 struct bwi_regwin *old, *com; 1105 uint32_t clk_ctrl, clk_src; 1106 int error, pwr_off = 0; 1107 1108 com = &sc->sc_com_regwin; 1109 if (!BWI_REGWIN_EXIST(com)) 1110 return 0; 1111 1112 if (com->rw_rev >= 10 || com->rw_rev < 6) 1113 return 0; 1114 1115 /* 1116 * For common regwin whose rev is [6, 10), the chip 1117 * must be capable to change clock mode. 1118 */ 1119 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 1120 return 0; 1121 1122 error = bwi_regwin_switch(sc, com, &old); 1123 if (error) 1124 return error; 1125 1126 if (clk_mode == BWI_CLOCK_MODE_FAST) 1127 bwi_power_on(sc, 0); /* Don't turn on PLL */ 1128 1129 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1130 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC); 1131 1132 switch (clk_mode) { 1133 case BWI_CLOCK_MODE_FAST: 1134 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW; 1135 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL; 1136 break; 1137 case BWI_CLOCK_MODE_SLOW: 1138 clk_ctrl |= BWI_CLOCK_CTRL_SLOW; 1139 break; 1140 case BWI_CLOCK_MODE_DYN: 1141 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW | 1142 BWI_CLOCK_CTRL_IGNPLL | 1143 BWI_CLOCK_CTRL_NODYN); 1144 if (clk_src != BWI_CLKSRC_CS_OSC) { 1145 clk_ctrl |= BWI_CLOCK_CTRL_NODYN; 1146 pwr_off = 1; 1147 } 1148 break; 1149 } 1150 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl); 1151 1152 if (pwr_off) 1153 bwi_power_off(sc, 0); /* Leave PLL as it is */ 1154 1155 return bwi_regwin_switch(sc, old, NULL); 1156 } 1157 1158 static int 1159 bwi_set_clock_delay(struct bwi_softc *sc) 1160 { 1161 struct bwi_regwin *old, *com; 1162 int error; 1163 1164 com = &sc->sc_com_regwin; 1165 if (!BWI_REGWIN_EXIST(com)) 1166 return 0; 1167 1168 error = bwi_regwin_switch(sc, com, &old); 1169 if (error) 1170 return error; 1171 1172 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) { 1173 if (sc->sc_bbp_rev == 0) 1174 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0); 1175 else if (sc->sc_bbp_rev == 1) 1176 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1); 1177 } 1178 1179 if (sc->sc_cap & BWI_CAP_CLKMODE) { 1180 if (com->rw_rev >= 10) { 1181 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000); 1182 } else { 1183 struct bwi_clock_freq freq; 1184 1185 bwi_get_clock_freq(sc, &freq); 1186 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY, 1187 howmany(freq.clkfreq_max * 150, 1000000)); 1188 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY, 1189 howmany(freq.clkfreq_max * 15, 1000000)); 1190 } 1191 } 1192 1193 return bwi_regwin_switch(sc, old, NULL); 1194 } 1195 1196 static void 1197 bwi_init(struct bwi_softc *sc) 1198 { 1199 struct ieee80211com *ic = &sc->sc_ic; 1200 1201 BWI_LOCK(sc); 1202 bwi_init_statechg(sc, 1); 1203 BWI_UNLOCK(sc); 1204 1205 if (sc->sc_flags & BWI_F_RUNNING) 1206 ieee80211_start_all(ic); /* start all vap's */ 1207 } 1208 1209 static void 1210 bwi_init_statechg(struct bwi_softc *sc, int statechg) 1211 { 1212 struct bwi_mac *mac; 1213 int error; 1214 1215 BWI_ASSERT_LOCKED(sc); 1216 1217 bwi_stop_locked(sc, statechg); 1218 1219 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 1220 1221 /* TODO: 2 MAC */ 1222 1223 mac = &sc->sc_mac[0]; 1224 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL); 1225 if (error) { 1226 device_printf(sc->sc_dev, "%s: error %d on regwin switch\n", 1227 __func__, error); 1228 goto bad; 1229 } 1230 error = bwi_mac_init(mac); 1231 if (error) { 1232 device_printf(sc->sc_dev, "%s: error %d on MAC init\n", 1233 __func__, error); 1234 goto bad; 1235 } 1236 1237 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN); 1238 1239 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */ 1240 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, sc->sc_ic.ic_macaddr); 1241 1242 bwi_mac_reset_hwkeys(mac); 1243 1244 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) { 1245 int i; 1246 1247 #define NRETRY 1000 1248 /* 1249 * Drain any possible pending TX status 1250 */ 1251 for (i = 0; i < NRETRY; ++i) { 1252 if ((CSR_READ_4(sc, BWI_TXSTATUS0) & 1253 BWI_TXSTATUS0_VALID) == 0) 1254 break; 1255 CSR_READ_4(sc, BWI_TXSTATUS1); 1256 } 1257 if (i == NRETRY) 1258 device_printf(sc->sc_dev, 1259 "%s: can't drain TX status\n", __func__); 1260 #undef NRETRY 1261 } 1262 1263 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G) 1264 bwi_mac_updateslot(mac, 1); 1265 1266 /* Start MAC */ 1267 error = bwi_mac_start(mac); 1268 if (error) { 1269 device_printf(sc->sc_dev, "%s: error %d starting MAC\n", 1270 __func__, error); 1271 goto bad; 1272 } 1273 1274 /* Clear stop flag before enabling interrupt */ 1275 sc->sc_flags &= ~BWI_F_STOP; 1276 sc->sc_flags |= BWI_F_RUNNING; 1277 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1278 1279 /* Enable intrs */ 1280 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1281 return; 1282 bad: 1283 bwi_stop_locked(sc, 1); 1284 } 1285 1286 static void 1287 bwi_parent(struct ieee80211com *ic) 1288 { 1289 struct bwi_softc *sc = ic->ic_softc; 1290 int startall = 0; 1291 1292 BWI_LOCK(sc); 1293 if (ic->ic_nrunning > 0) { 1294 struct bwi_mac *mac; 1295 int promisc = -1; 1296 1297 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1298 ("current regwin type %d", 1299 sc->sc_cur_regwin->rw_type)); 1300 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1301 1302 if (ic->ic_promisc > 0 && (sc->sc_flags & BWI_F_PROMISC) == 0) { 1303 promisc = 1; 1304 sc->sc_flags |= BWI_F_PROMISC; 1305 } else if (ic->ic_promisc == 0 && 1306 (sc->sc_flags & BWI_F_PROMISC) != 0) { 1307 promisc = 0; 1308 sc->sc_flags &= ~BWI_F_PROMISC; 1309 } 1310 1311 if (promisc >= 0) 1312 bwi_mac_set_promisc(mac, promisc); 1313 } 1314 if (ic->ic_nrunning > 0) { 1315 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1316 bwi_init_statechg(sc, 1); 1317 startall = 1; 1318 } 1319 } else if (sc->sc_flags & BWI_F_RUNNING) 1320 bwi_stop_locked(sc, 1); 1321 BWI_UNLOCK(sc); 1322 if (startall) 1323 ieee80211_start_all(ic); 1324 } 1325 1326 static int 1327 bwi_transmit(struct ieee80211com *ic, struct mbuf *m) 1328 { 1329 struct bwi_softc *sc = ic->ic_softc; 1330 int error; 1331 1332 BWI_LOCK(sc); 1333 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1334 BWI_UNLOCK(sc); 1335 return (ENXIO); 1336 } 1337 error = mbufq_enqueue(&sc->sc_snd, m); 1338 if (error) { 1339 BWI_UNLOCK(sc); 1340 return (error); 1341 } 1342 bwi_start_locked(sc); 1343 BWI_UNLOCK(sc); 1344 return (0); 1345 } 1346 1347 static void 1348 bwi_start_locked(struct bwi_softc *sc) 1349 { 1350 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1351 struct ieee80211_frame *wh; 1352 struct ieee80211_node *ni; 1353 struct mbuf *m; 1354 int trans, idx; 1355 1356 BWI_ASSERT_LOCKED(sc); 1357 1358 trans = 0; 1359 idx = tbd->tbd_idx; 1360 1361 while (tbd->tbd_buf[idx].tb_mbuf == NULL && 1362 tbd->tbd_used + BWI_TX_NSPRDESC < BWI_TX_NDESC && 1363 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1364 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1365 wh = mtod(m, struct ieee80211_frame *); 1366 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) != 0 && 1367 ieee80211_crypto_encap(ni, m) == NULL) { 1368 if_inc_counter(ni->ni_vap->iv_ifp, 1369 IFCOUNTER_OERRORS, 1); 1370 ieee80211_free_node(ni); 1371 m_freem(m); 1372 continue; 1373 } 1374 if (bwi_encap(sc, idx, m, ni) != 0) { 1375 /* 'm' is freed in bwi_encap() if we reach here */ 1376 if (ni != NULL) { 1377 if_inc_counter(ni->ni_vap->iv_ifp, 1378 IFCOUNTER_OERRORS, 1); 1379 ieee80211_free_node(ni); 1380 } else 1381 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1382 continue; 1383 } 1384 trans = 1; 1385 tbd->tbd_used++; 1386 idx = (idx + 1) % BWI_TX_NDESC; 1387 } 1388 1389 tbd->tbd_idx = idx; 1390 if (trans) 1391 sc->sc_tx_timer = 5; 1392 } 1393 1394 static int 1395 bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1396 const struct ieee80211_bpf_params *params) 1397 { 1398 struct ieee80211com *ic = ni->ni_ic; 1399 struct bwi_softc *sc = ic->ic_softc; 1400 /* XXX wme? */ 1401 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1402 int idx, error; 1403 1404 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1405 m_freem(m); 1406 return ENETDOWN; 1407 } 1408 1409 BWI_LOCK(sc); 1410 idx = tbd->tbd_idx; 1411 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx)); 1412 if (params == NULL) { 1413 /* 1414 * Legacy path; interpret frame contents to decide 1415 * precisely how to send the frame. 1416 */ 1417 error = bwi_encap(sc, idx, m, ni); 1418 } else { 1419 /* 1420 * Caller supplied explicit parameters to use in 1421 * sending the frame. 1422 */ 1423 error = bwi_encap_raw(sc, idx, m, ni, params); 1424 } 1425 if (error == 0) { 1426 tbd->tbd_used++; 1427 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC; 1428 sc->sc_tx_timer = 5; 1429 } 1430 BWI_UNLOCK(sc); 1431 return error; 1432 } 1433 1434 static void 1435 bwi_watchdog(void *arg) 1436 { 1437 struct bwi_softc *sc; 1438 1439 sc = arg; 1440 BWI_ASSERT_LOCKED(sc); 1441 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) { 1442 device_printf(sc->sc_dev, "watchdog timeout\n"); 1443 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1444 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1445 } 1446 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1447 } 1448 1449 static void 1450 bwi_stop(struct bwi_softc *sc, int statechg) 1451 { 1452 BWI_LOCK(sc); 1453 bwi_stop_locked(sc, statechg); 1454 BWI_UNLOCK(sc); 1455 } 1456 1457 static void 1458 bwi_stop_locked(struct bwi_softc *sc, int statechg) 1459 { 1460 struct bwi_mac *mac; 1461 int i, error, pwr_off = 0; 1462 1463 BWI_ASSERT_LOCKED(sc); 1464 1465 callout_stop(&sc->sc_calib_ch); 1466 callout_stop(&sc->sc_led_blink_ch); 1467 sc->sc_led_blinking = 0; 1468 sc->sc_flags |= BWI_F_STOP; 1469 1470 if (sc->sc_flags & BWI_F_RUNNING) { 1471 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1472 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1473 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1474 1475 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1476 CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1477 bwi_mac_stop(mac); 1478 } 1479 1480 for (i = 0; i < sc->sc_nmac; ++i) { 1481 struct bwi_regwin *old_rw; 1482 1483 mac = &sc->sc_mac[i]; 1484 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0) 1485 continue; 1486 1487 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw); 1488 if (error) 1489 continue; 1490 1491 bwi_mac_shutdown(mac); 1492 pwr_off = 1; 1493 1494 bwi_regwin_switch(sc, old_rw, NULL); 1495 } 1496 1497 if (pwr_off) 1498 bwi_bbp_power_off(sc); 1499 1500 sc->sc_tx_timer = 0; 1501 callout_stop(&sc->sc_watchdog_timer); 1502 sc->sc_flags &= ~BWI_F_RUNNING; 1503 } 1504 1505 void 1506 bwi_intr(void *xsc) 1507 { 1508 struct bwi_softc *sc = xsc; 1509 struct bwi_mac *mac; 1510 uint32_t intr_status; 1511 uint32_t txrx_intr_status[BWI_TXRX_NRING]; 1512 int i, txrx_error, tx = 0, rx_data = -1; 1513 1514 BWI_LOCK(sc); 1515 1516 if ((sc->sc_flags & BWI_F_RUNNING) == 0 || 1517 (sc->sc_flags & BWI_F_STOP)) { 1518 BWI_UNLOCK(sc); 1519 return; 1520 } 1521 /* 1522 * Get interrupt status 1523 */ 1524 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); 1525 if (intr_status == 0xffffffff) { /* Not for us */ 1526 BWI_UNLOCK(sc); 1527 return; 1528 } 1529 1530 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status); 1531 1532 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1533 if (intr_status == 0) { /* Nothing is interesting */ 1534 BWI_UNLOCK(sc); 1535 return; 1536 } 1537 1538 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1539 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1540 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1541 1542 txrx_error = 0; 1543 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr"); 1544 for (i = 0; i < BWI_TXRX_NRING; ++i) { 1545 uint32_t mask; 1546 1547 if (BWI_TXRX_IS_RX(i)) 1548 mask = BWI_TXRX_RX_INTRS; 1549 else 1550 mask = BWI_TXRX_TX_INTRS; 1551 1552 txrx_intr_status[i] = 1553 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask; 1554 1555 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x", 1556 i, txrx_intr_status[i]); 1557 1558 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) { 1559 device_printf(sc->sc_dev, 1560 "%s: intr fatal TX/RX (%d) error 0x%08x\n", 1561 __func__, i, txrx_intr_status[i]); 1562 txrx_error = 1; 1563 } 1564 } 1565 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", ""); 1566 1567 /* 1568 * Acknowledge interrupt 1569 */ 1570 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status); 1571 1572 for (i = 0; i < BWI_TXRX_NRING; ++i) 1573 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]); 1574 1575 /* Disable all interrupts */ 1576 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1577 1578 /* 1579 * http://bcm-specs.sipsolutions.net/Interrupts 1580 * Says for this bit (0x800): 1581 * "Fatal Error 1582 * 1583 * We got this one while testing things when by accident the 1584 * template ram wasn't set to big endian when it should have 1585 * been after writing the initial values. It keeps on being 1586 * triggered, the only way to stop it seems to shut down the 1587 * chip." 1588 * 1589 * Suggesting that we should never get it and if we do we're not 1590 * feeding TX packets into the MAC correctly if we do... Apparently, 1591 * it is valid only on mac version 5 and higher, but I couldn't 1592 * find a reference for that... Since I see them from time to time 1593 * on my card, this suggests an error in the tx path still... 1594 */ 1595 if (intr_status & BWI_INTR_PHY_TXERR) { 1596 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) { 1597 device_printf(sc->sc_dev, "%s: intr PHY TX error\n", 1598 __func__); 1599 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1600 BWI_UNLOCK(sc); 1601 return; 1602 } 1603 } 1604 1605 if (txrx_error) { 1606 /* TODO: reset device */ 1607 } 1608 1609 if (intr_status & BWI_INTR_TBTT) 1610 bwi_mac_config_ps(mac); 1611 1612 if (intr_status & BWI_INTR_EO_ATIM) 1613 device_printf(sc->sc_dev, "EO_ATIM\n"); 1614 1615 if (intr_status & BWI_INTR_PMQ) { 1616 for (;;) { 1617 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0) 1618 break; 1619 } 1620 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2); 1621 } 1622 1623 if (intr_status & BWI_INTR_NOISE) 1624 device_printf(sc->sc_dev, "intr noise\n"); 1625 1626 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) { 1627 rx_data = sc->sc_rxeof(sc); 1628 if (sc->sc_flags & BWI_F_STOP) { 1629 BWI_UNLOCK(sc); 1630 return; 1631 } 1632 } 1633 1634 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) { 1635 sc->sc_txeof_status(sc); 1636 tx = 1; 1637 } 1638 1639 if (intr_status & BWI_INTR_TX_DONE) { 1640 bwi_txeof(sc); 1641 tx = 1; 1642 } 1643 1644 /* Re-enable interrupts */ 1645 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1646 1647 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 1648 int evt = BWI_LED_EVENT_NONE; 1649 1650 if (tx && rx_data > 0) { 1651 if (sc->sc_rx_rate > sc->sc_tx_rate) 1652 evt = BWI_LED_EVENT_RX; 1653 else 1654 evt = BWI_LED_EVENT_TX; 1655 } else if (tx) { 1656 evt = BWI_LED_EVENT_TX; 1657 } else if (rx_data > 0) { 1658 evt = BWI_LED_EVENT_RX; 1659 } else if (rx_data == 0) { 1660 evt = BWI_LED_EVENT_POLL; 1661 } 1662 1663 if (evt != BWI_LED_EVENT_NONE) 1664 bwi_led_event(sc, evt); 1665 } 1666 1667 BWI_UNLOCK(sc); 1668 } 1669 1670 static void 1671 bwi_scan_start(struct ieee80211com *ic) 1672 { 1673 struct bwi_softc *sc = ic->ic_softc; 1674 1675 BWI_LOCK(sc); 1676 /* Enable MAC beacon promiscuity */ 1677 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1678 BWI_UNLOCK(sc); 1679 } 1680 1681 static void 1682 bwi_getradiocaps(struct ieee80211com *ic, 1683 int maxchans, int *nchans, struct ieee80211_channel chans[]) 1684 { 1685 struct bwi_softc *sc = ic->ic_softc; 1686 struct bwi_mac *mac; 1687 struct bwi_phy *phy; 1688 uint8_t bands[IEEE80211_MODE_BYTES]; 1689 1690 /* 1691 * XXX First MAC is known to exist 1692 * TODO2 1693 */ 1694 mac = &sc->sc_mac[0]; 1695 phy = &mac->mac_phy; 1696 1697 memset(bands, 0, sizeof(bands)); 1698 switch (phy->phy_mode) { 1699 case IEEE80211_MODE_11G: 1700 setbit(bands, IEEE80211_MODE_11G); 1701 /* FALLTHROUGH */ 1702 case IEEE80211_MODE_11B: 1703 setbit(bands, IEEE80211_MODE_11B); 1704 break; 1705 case IEEE80211_MODE_11A: 1706 /* TODO:11A */ 1707 setbit(bands, IEEE80211_MODE_11A); 1708 device_printf(sc->sc_dev, "no 11a support\n"); 1709 return; 1710 default: 1711 panic("unknown phymode %d\n", phy->phy_mode); 1712 } 1713 1714 ieee80211_add_channel_list_2ghz(chans, maxchans, nchans, 1715 bwi_chan_2ghz, nitems(bwi_chan_2ghz), bands, 0); 1716 } 1717 1718 static void 1719 bwi_set_channel(struct ieee80211com *ic) 1720 { 1721 struct bwi_softc *sc = ic->ic_softc; 1722 struct ieee80211_channel *c = ic->ic_curchan; 1723 struct bwi_mac *mac; 1724 1725 BWI_LOCK(sc); 1726 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1727 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1728 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1729 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0); 1730 1731 sc->sc_rates = ieee80211_get_ratetable(c); 1732 1733 /* 1734 * Setup radio tap channel freq and flags 1735 */ 1736 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 1737 htole16(c->ic_freq); 1738 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 1739 htole16(c->ic_flags & 0xffff); 1740 1741 BWI_UNLOCK(sc); 1742 } 1743 1744 static void 1745 bwi_scan_end(struct ieee80211com *ic) 1746 { 1747 struct bwi_softc *sc = ic->ic_softc; 1748 1749 BWI_LOCK(sc); 1750 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1751 BWI_UNLOCK(sc); 1752 } 1753 1754 static int 1755 bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1756 { 1757 struct bwi_vap *bvp = BWI_VAP(vap); 1758 struct ieee80211com *ic= vap->iv_ic; 1759 struct bwi_softc *sc = ic->ic_softc; 1760 enum ieee80211_state ostate = vap->iv_state; 1761 struct bwi_mac *mac; 1762 int error; 1763 1764 BWI_LOCK(sc); 1765 1766 callout_stop(&sc->sc_calib_ch); 1767 1768 if (nstate == IEEE80211_S_INIT) 1769 sc->sc_txpwrcb_type = BWI_TXPWR_INIT; 1770 1771 bwi_led_newstate(sc, nstate); 1772 1773 error = bvp->bv_newstate(vap, nstate, arg); 1774 if (error != 0) 1775 goto back; 1776 1777 /* 1778 * Clear the BSSID when we stop a STA 1779 */ 1780 if (vap->iv_opmode == IEEE80211_M_STA) { 1781 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { 1782 /* 1783 * Clear out the BSSID. If we reassociate to 1784 * the same AP, this will reinialize things 1785 * correctly... 1786 */ 1787 if (ic->ic_opmode == IEEE80211_M_STA && 1788 !(sc->sc_flags & BWI_F_STOP)) 1789 bwi_set_bssid(sc, bwi_zero_addr); 1790 } 1791 } 1792 1793 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1794 /* Nothing to do */ 1795 } else if (nstate == IEEE80211_S_RUN) { 1796 bwi_set_bssid(sc, vap->iv_bss->ni_bssid); 1797 1798 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1799 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1800 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1801 1802 /* Initial TX power calibration */ 1803 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT); 1804 #ifdef notyet 1805 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE; 1806 #else 1807 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 1808 #endif 1809 1810 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc); 1811 } 1812 back: 1813 BWI_UNLOCK(sc); 1814 1815 return error; 1816 } 1817 1818 static int 1819 bwi_media_change(struct ifnet *ifp) 1820 { 1821 int error = ieee80211_media_change(ifp); 1822 /* NB: only the fixed rate can change and that doesn't need a reset */ 1823 return (error == ENETRESET ? 0 : error); 1824 } 1825 1826 static int 1827 bwi_dma_alloc(struct bwi_softc *sc) 1828 { 1829 int error, i, has_txstats; 1830 bus_addr_t lowaddr = 0; 1831 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0; 1832 uint32_t txrx_ctrl_step = 0; 1833 1834 has_txstats = 0; 1835 for (i = 0; i < sc->sc_nmac; ++i) { 1836 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) { 1837 has_txstats = 1; 1838 break; 1839 } 1840 } 1841 1842 switch (sc->sc_bus_space) { 1843 case BWI_BUS_SPACE_30BIT: 1844 case BWI_BUS_SPACE_32BIT: 1845 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT) 1846 lowaddr = BWI_BUS_SPACE_MAXADDR; 1847 else 1848 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1849 desc_sz = sizeof(struct bwi_desc32); 1850 txrx_ctrl_step = 0x20; 1851 1852 sc->sc_init_tx_ring = bwi_init_tx_ring32; 1853 sc->sc_free_tx_ring = bwi_free_tx_ring32; 1854 sc->sc_init_rx_ring = bwi_init_rx_ring32; 1855 sc->sc_free_rx_ring = bwi_free_rx_ring32; 1856 sc->sc_setup_rxdesc = bwi_setup_rx_desc32; 1857 sc->sc_setup_txdesc = bwi_setup_tx_desc32; 1858 sc->sc_rxeof = bwi_rxeof32; 1859 sc->sc_start_tx = bwi_start_tx32; 1860 if (has_txstats) { 1861 sc->sc_init_txstats = bwi_init_txstats32; 1862 sc->sc_free_txstats = bwi_free_txstats32; 1863 sc->sc_txeof_status = bwi_txeof_status32; 1864 } 1865 break; 1866 1867 case BWI_BUS_SPACE_64BIT: 1868 lowaddr = BUS_SPACE_MAXADDR; /* XXX */ 1869 desc_sz = sizeof(struct bwi_desc64); 1870 txrx_ctrl_step = 0x40; 1871 1872 sc->sc_init_tx_ring = bwi_init_tx_ring64; 1873 sc->sc_free_tx_ring = bwi_free_tx_ring64; 1874 sc->sc_init_rx_ring = bwi_init_rx_ring64; 1875 sc->sc_free_rx_ring = bwi_free_rx_ring64; 1876 sc->sc_setup_rxdesc = bwi_setup_rx_desc64; 1877 sc->sc_setup_txdesc = bwi_setup_tx_desc64; 1878 sc->sc_rxeof = bwi_rxeof64; 1879 sc->sc_start_tx = bwi_start_tx64; 1880 if (has_txstats) { 1881 sc->sc_init_txstats = bwi_init_txstats64; 1882 sc->sc_free_txstats = bwi_free_txstats64; 1883 sc->sc_txeof_status = bwi_txeof_status64; 1884 } 1885 break; 1886 } 1887 1888 KASSERT(lowaddr != 0, ("lowaddr zero")); 1889 KASSERT(desc_sz != 0, ("desc_sz zero")); 1890 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero")); 1891 1892 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN); 1893 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN); 1894 1895 /* 1896 * Create top level DMA tag 1897 */ 1898 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1899 BWI_ALIGN, 0, /* alignment, bounds */ 1900 lowaddr, /* lowaddr */ 1901 BUS_SPACE_MAXADDR, /* highaddr */ 1902 NULL, NULL, /* filter, filterarg */ 1903 BUS_SPACE_MAXSIZE, /* maxsize */ 1904 BUS_SPACE_UNRESTRICTED, /* nsegments */ 1905 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1906 0, /* flags */ 1907 NULL, NULL, /* lockfunc, lockarg */ 1908 &sc->sc_parent_dtag); 1909 if (error) { 1910 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 1911 return error; 1912 } 1913 1914 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step) 1915 1916 /* 1917 * Create TX ring DMA stuffs 1918 */ 1919 error = bus_dma_tag_create(sc->sc_parent_dtag, 1920 BWI_RING_ALIGN, 0, 1921 BUS_SPACE_MAXADDR, 1922 BUS_SPACE_MAXADDR, 1923 NULL, NULL, 1924 tx_ring_sz, 1925 1, 1926 tx_ring_sz, 1927 0, 1928 NULL, NULL, 1929 &sc->sc_txring_dtag); 1930 if (error) { 1931 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n"); 1932 return error; 1933 } 1934 1935 for (i = 0; i < BWI_TX_NRING; ++i) { 1936 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag, 1937 &sc->sc_tx_rdata[i], tx_ring_sz, 1938 TXRX_CTRL(i)); 1939 if (error) { 1940 device_printf(sc->sc_dev, "%dth TX ring " 1941 "DMA alloc failed\n", i); 1942 return error; 1943 } 1944 } 1945 1946 /* 1947 * Create RX ring DMA stuffs 1948 */ 1949 error = bus_dma_tag_create(sc->sc_parent_dtag, 1950 BWI_RING_ALIGN, 0, 1951 BUS_SPACE_MAXADDR, 1952 BUS_SPACE_MAXADDR, 1953 NULL, NULL, 1954 rx_ring_sz, 1955 1, 1956 rx_ring_sz, 1957 0, 1958 NULL, NULL, 1959 &sc->sc_rxring_dtag); 1960 if (error) { 1961 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n"); 1962 return error; 1963 } 1964 1965 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata, 1966 rx_ring_sz, TXRX_CTRL(0)); 1967 if (error) { 1968 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n"); 1969 return error; 1970 } 1971 1972 if (has_txstats) { 1973 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz); 1974 if (error) { 1975 device_printf(sc->sc_dev, 1976 "TX stats DMA alloc failed\n"); 1977 return error; 1978 } 1979 } 1980 1981 #undef TXRX_CTRL 1982 1983 return bwi_dma_mbuf_create(sc); 1984 } 1985 1986 static void 1987 bwi_dma_free(struct bwi_softc *sc) 1988 { 1989 if (sc->sc_txring_dtag != NULL) { 1990 int i; 1991 1992 for (i = 0; i < BWI_TX_NRING; ++i) { 1993 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i]; 1994 1995 if (rd->rdata_desc != NULL) { 1996 bus_dmamap_unload(sc->sc_txring_dtag, 1997 rd->rdata_dmap); 1998 bus_dmamem_free(sc->sc_txring_dtag, 1999 rd->rdata_desc, 2000 rd->rdata_dmap); 2001 } 2002 } 2003 bus_dma_tag_destroy(sc->sc_txring_dtag); 2004 } 2005 2006 if (sc->sc_rxring_dtag != NULL) { 2007 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2008 2009 if (rd->rdata_desc != NULL) { 2010 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap); 2011 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc, 2012 rd->rdata_dmap); 2013 } 2014 bus_dma_tag_destroy(sc->sc_rxring_dtag); 2015 } 2016 2017 bwi_dma_txstats_free(sc); 2018 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1); 2019 2020 if (sc->sc_parent_dtag != NULL) 2021 bus_dma_tag_destroy(sc->sc_parent_dtag); 2022 } 2023 2024 static int 2025 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag, 2026 struct bwi_ring_data *rd, bus_size_t size, 2027 uint32_t txrx_ctrl) 2028 { 2029 int error; 2030 2031 error = bus_dmamem_alloc(dtag, &rd->rdata_desc, 2032 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2033 &rd->rdata_dmap); 2034 if (error) { 2035 device_printf(sc->sc_dev, "can't allocate DMA mem\n"); 2036 return error; 2037 } 2038 2039 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size, 2040 bwi_dma_ring_addr, &rd->rdata_paddr, 2041 BUS_DMA_NOWAIT); 2042 if (error) { 2043 device_printf(sc->sc_dev, "can't load DMA mem\n"); 2044 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap); 2045 rd->rdata_desc = NULL; 2046 return error; 2047 } 2048 2049 rd->rdata_txrx_ctrl = txrx_ctrl; 2050 return 0; 2051 } 2052 2053 static int 2054 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base, 2055 bus_size_t desc_sz) 2056 { 2057 struct bwi_txstats_data *st; 2058 bus_size_t dma_size; 2059 int error; 2060 2061 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO); 2062 if (st == NULL) { 2063 device_printf(sc->sc_dev, "can't allocate txstats data\n"); 2064 return ENOMEM; 2065 } 2066 sc->sc_txstats = st; 2067 2068 /* 2069 * Create TX stats descriptor DMA stuffs 2070 */ 2071 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN); 2072 2073 error = bus_dma_tag_create(sc->sc_parent_dtag, 2074 BWI_RING_ALIGN, 2075 0, 2076 BUS_SPACE_MAXADDR, 2077 BUS_SPACE_MAXADDR, 2078 NULL, NULL, 2079 dma_size, 2080 1, 2081 dma_size, 2082 0, 2083 NULL, NULL, 2084 &st->stats_ring_dtag); 2085 if (error) { 2086 device_printf(sc->sc_dev, "can't create txstats ring " 2087 "DMA tag\n"); 2088 return error; 2089 } 2090 2091 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring, 2092 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2093 &st->stats_ring_dmap); 2094 if (error) { 2095 device_printf(sc->sc_dev, "can't allocate txstats ring " 2096 "DMA mem\n"); 2097 bus_dma_tag_destroy(st->stats_ring_dtag); 2098 st->stats_ring_dtag = NULL; 2099 return error; 2100 } 2101 2102 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap, 2103 st->stats_ring, dma_size, 2104 bwi_dma_ring_addr, &st->stats_ring_paddr, 2105 BUS_DMA_NOWAIT); 2106 if (error) { 2107 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n"); 2108 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2109 st->stats_ring_dmap); 2110 bus_dma_tag_destroy(st->stats_ring_dtag); 2111 st->stats_ring_dtag = NULL; 2112 return error; 2113 } 2114 2115 /* 2116 * Create TX stats DMA stuffs 2117 */ 2118 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC, 2119 BWI_ALIGN); 2120 2121 error = bus_dma_tag_create(sc->sc_parent_dtag, 2122 BWI_ALIGN, 2123 0, 2124 BUS_SPACE_MAXADDR, 2125 BUS_SPACE_MAXADDR, 2126 NULL, NULL, 2127 dma_size, 2128 1, 2129 dma_size, 2130 0, 2131 NULL, NULL, 2132 &st->stats_dtag); 2133 if (error) { 2134 device_printf(sc->sc_dev, "can't create txstats DMA tag\n"); 2135 return error; 2136 } 2137 2138 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats, 2139 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2140 &st->stats_dmap); 2141 if (error) { 2142 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n"); 2143 bus_dma_tag_destroy(st->stats_dtag); 2144 st->stats_dtag = NULL; 2145 return error; 2146 } 2147 2148 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats, 2149 dma_size, bwi_dma_ring_addr, &st->stats_paddr, 2150 BUS_DMA_NOWAIT); 2151 if (error) { 2152 device_printf(sc->sc_dev, "can't load txstats DMA mem\n"); 2153 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2154 bus_dma_tag_destroy(st->stats_dtag); 2155 st->stats_dtag = NULL; 2156 return error; 2157 } 2158 2159 st->stats_ctrl_base = ctrl_base; 2160 return 0; 2161 } 2162 2163 static void 2164 bwi_dma_txstats_free(struct bwi_softc *sc) 2165 { 2166 struct bwi_txstats_data *st; 2167 2168 if (sc->sc_txstats == NULL) 2169 return; 2170 st = sc->sc_txstats; 2171 2172 if (st->stats_ring_dtag != NULL) { 2173 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap); 2174 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2175 st->stats_ring_dmap); 2176 bus_dma_tag_destroy(st->stats_ring_dtag); 2177 } 2178 2179 if (st->stats_dtag != NULL) { 2180 bus_dmamap_unload(st->stats_dtag, st->stats_dmap); 2181 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2182 bus_dma_tag_destroy(st->stats_dtag); 2183 } 2184 2185 free(st, M_DEVBUF); 2186 } 2187 2188 static void 2189 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 2190 { 2191 KASSERT(nseg == 1, ("too many segments\n")); 2192 *((bus_addr_t *)arg) = seg->ds_addr; 2193 } 2194 2195 static int 2196 bwi_dma_mbuf_create(struct bwi_softc *sc) 2197 { 2198 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2199 int i, j, k, ntx, error; 2200 2201 /* 2202 * Create TX/RX mbuf DMA tag 2203 */ 2204 error = bus_dma_tag_create(sc->sc_parent_dtag, 2205 1, 2206 0, 2207 BUS_SPACE_MAXADDR, 2208 BUS_SPACE_MAXADDR, 2209 NULL, NULL, 2210 MCLBYTES, 2211 1, 2212 MCLBYTES, 2213 BUS_DMA_ALLOCNOW, 2214 NULL, NULL, 2215 &sc->sc_buf_dtag); 2216 if (error) { 2217 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 2218 return error; 2219 } 2220 2221 ntx = 0; 2222 2223 /* 2224 * Create TX mbuf DMA map 2225 */ 2226 for (i = 0; i < BWI_TX_NRING; ++i) { 2227 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2228 2229 for (j = 0; j < BWI_TX_NDESC; ++j) { 2230 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2231 &tbd->tbd_buf[j].tb_dmap); 2232 if (error) { 2233 device_printf(sc->sc_dev, "can't create " 2234 "%dth tbd, %dth DMA map\n", i, j); 2235 2236 ntx = i; 2237 for (k = 0; k < j; ++k) { 2238 bus_dmamap_destroy(sc->sc_buf_dtag, 2239 tbd->tbd_buf[k].tb_dmap); 2240 } 2241 goto fail; 2242 } 2243 } 2244 } 2245 ntx = BWI_TX_NRING; 2246 2247 /* 2248 * Create RX mbuf DMA map and a spare DMA map 2249 */ 2250 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2251 &rbd->rbd_tmp_dmap); 2252 if (error) { 2253 device_printf(sc->sc_dev, 2254 "can't create spare RX buf DMA map\n"); 2255 goto fail; 2256 } 2257 2258 for (j = 0; j < BWI_RX_NDESC; ++j) { 2259 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2260 &rbd->rbd_buf[j].rb_dmap); 2261 if (error) { 2262 device_printf(sc->sc_dev, "can't create %dth " 2263 "RX buf DMA map\n", j); 2264 2265 for (k = 0; k < j; ++k) { 2266 bus_dmamap_destroy(sc->sc_buf_dtag, 2267 rbd->rbd_buf[j].rb_dmap); 2268 } 2269 bus_dmamap_destroy(sc->sc_buf_dtag, 2270 rbd->rbd_tmp_dmap); 2271 goto fail; 2272 } 2273 } 2274 2275 return 0; 2276 fail: 2277 bwi_dma_mbuf_destroy(sc, ntx, 0); 2278 return error; 2279 } 2280 2281 static void 2282 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx) 2283 { 2284 int i, j; 2285 2286 if (sc->sc_buf_dtag == NULL) 2287 return; 2288 2289 for (i = 0; i < ntx; ++i) { 2290 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2291 2292 for (j = 0; j < BWI_TX_NDESC; ++j) { 2293 struct bwi_txbuf *tb = &tbd->tbd_buf[j]; 2294 2295 if (tb->tb_mbuf != NULL) { 2296 bus_dmamap_unload(sc->sc_buf_dtag, 2297 tb->tb_dmap); 2298 m_freem(tb->tb_mbuf); 2299 } 2300 if (tb->tb_ni != NULL) 2301 ieee80211_free_node(tb->tb_ni); 2302 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap); 2303 } 2304 } 2305 2306 if (nrx) { 2307 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2308 2309 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap); 2310 for (j = 0; j < BWI_RX_NDESC; ++j) { 2311 struct bwi_rxbuf *rb = &rbd->rbd_buf[j]; 2312 2313 if (rb->rb_mbuf != NULL) { 2314 bus_dmamap_unload(sc->sc_buf_dtag, 2315 rb->rb_dmap); 2316 m_freem(rb->rb_mbuf); 2317 } 2318 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap); 2319 } 2320 } 2321 2322 bus_dma_tag_destroy(sc->sc_buf_dtag); 2323 sc->sc_buf_dtag = NULL; 2324 } 2325 2326 static void 2327 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs) 2328 { 2329 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs); 2330 } 2331 2332 static void 2333 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs) 2334 { 2335 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs); 2336 } 2337 2338 static int 2339 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx) 2340 { 2341 struct bwi_ring_data *rd; 2342 struct bwi_txbuf_data *tbd; 2343 uint32_t val, addr_hi, addr_lo; 2344 2345 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2346 rd = &sc->sc_tx_rdata[ring_idx]; 2347 tbd = &sc->sc_tx_bdata[ring_idx]; 2348 2349 tbd->tbd_idx = 0; 2350 tbd->tbd_used = 0; 2351 2352 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC); 2353 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 2354 BUS_DMASYNC_PREWRITE); 2355 2356 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2357 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2358 2359 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2360 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2361 BWI_TXRX32_RINGINFO_FUNC_MASK); 2362 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val); 2363 2364 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2365 BWI_TXRX32_CTRL_ENABLE; 2366 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val); 2367 2368 return 0; 2369 } 2370 2371 static void 2372 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base, 2373 bus_addr_t paddr, int hdr_size, int ndesc) 2374 { 2375 uint32_t val, addr_hi, addr_lo; 2376 2377 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2378 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2379 2380 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2381 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2382 BWI_TXRX32_RINGINFO_FUNC_MASK); 2383 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val); 2384 2385 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) | 2386 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2387 BWI_TXRX32_CTRL_ENABLE; 2388 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val); 2389 2390 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 2391 (ndesc - 1) * sizeof(struct bwi_desc32)); 2392 } 2393 2394 static int 2395 bwi_init_rx_ring32(struct bwi_softc *sc) 2396 { 2397 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2398 int i, error; 2399 2400 sc->sc_rx_bdata.rbd_idx = 0; 2401 2402 for (i = 0; i < BWI_RX_NDESC; ++i) { 2403 error = bwi_newbuf(sc, i, 1); 2404 if (error) { 2405 device_printf(sc->sc_dev, 2406 "can't allocate %dth RX buffer\n", i); 2407 return error; 2408 } 2409 } 2410 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2411 BUS_DMASYNC_PREWRITE); 2412 2413 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr, 2414 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC); 2415 return 0; 2416 } 2417 2418 static int 2419 bwi_init_txstats32(struct bwi_softc *sc) 2420 { 2421 struct bwi_txstats_data *st = sc->sc_txstats; 2422 bus_addr_t stats_paddr; 2423 int i; 2424 2425 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats)); 2426 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE); 2427 2428 st->stats_idx = 0; 2429 2430 stats_paddr = st->stats_paddr; 2431 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) { 2432 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i, 2433 stats_paddr, sizeof(struct bwi_txstats), 0); 2434 stats_paddr += sizeof(struct bwi_txstats); 2435 } 2436 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap, 2437 BUS_DMASYNC_PREWRITE); 2438 2439 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base, 2440 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC); 2441 return 0; 2442 } 2443 2444 static void 2445 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2446 int buf_len) 2447 { 2448 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2449 2450 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2451 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx, 2452 paddr, buf_len, 0); 2453 } 2454 2455 static void 2456 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd, 2457 int buf_idx, bus_addr_t paddr, int buf_len) 2458 { 2459 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 2460 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx, 2461 paddr, buf_len, 1); 2462 } 2463 2464 static int 2465 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx) 2466 { 2467 /* TODO:64 */ 2468 return EOPNOTSUPP; 2469 } 2470 2471 static int 2472 bwi_init_rx_ring64(struct bwi_softc *sc) 2473 { 2474 /* TODO:64 */ 2475 return EOPNOTSUPP; 2476 } 2477 2478 static int 2479 bwi_init_txstats64(struct bwi_softc *sc) 2480 { 2481 /* TODO:64 */ 2482 return EOPNOTSUPP; 2483 } 2484 2485 static void 2486 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2487 int buf_len) 2488 { 2489 /* TODO:64 */ 2490 } 2491 2492 static void 2493 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd, 2494 int buf_idx, bus_addr_t paddr, int buf_len) 2495 { 2496 /* TODO:64 */ 2497 } 2498 2499 static void 2500 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 2501 bus_size_t mapsz __unused, int error) 2502 { 2503 if (!error) { 2504 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 2505 *((bus_addr_t *)arg) = seg->ds_addr; 2506 } 2507 } 2508 2509 static int 2510 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init) 2511 { 2512 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2513 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx]; 2514 struct bwi_rxbuf_hdr *hdr; 2515 bus_dmamap_t map; 2516 bus_addr_t paddr; 2517 struct mbuf *m; 2518 int error; 2519 2520 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2521 2522 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2523 if (m == NULL) { 2524 error = ENOBUFS; 2525 2526 /* 2527 * If the NIC is up and running, we need to: 2528 * - Clear RX buffer's header. 2529 * - Restore RX descriptor settings. 2530 */ 2531 if (init) 2532 return error; 2533 else 2534 goto back; 2535 } 2536 m->m_len = m->m_pkthdr.len = MCLBYTES; 2537 2538 /* 2539 * Try to load RX buf into temporary DMA map 2540 */ 2541 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m, 2542 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 2543 if (error) { 2544 m_freem(m); 2545 2546 /* 2547 * See the comment above 2548 */ 2549 if (init) 2550 return error; 2551 else 2552 goto back; 2553 } 2554 2555 if (!init) 2556 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap); 2557 rxbuf->rb_mbuf = m; 2558 rxbuf->rb_paddr = paddr; 2559 2560 /* 2561 * Swap RX buf's DMA map with the loaded temporary one 2562 */ 2563 map = rxbuf->rb_dmap; 2564 rxbuf->rb_dmap = rbd->rbd_tmp_dmap; 2565 rbd->rbd_tmp_dmap = map; 2566 2567 back: 2568 /* 2569 * Clear RX buf header 2570 */ 2571 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *); 2572 bzero(hdr, sizeof(*hdr)); 2573 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE); 2574 2575 /* 2576 * Setup RX buf descriptor 2577 */ 2578 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr, 2579 rxbuf->rb_mbuf->m_len - sizeof(*hdr)); 2580 return error; 2581 } 2582 2583 static void 2584 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs, 2585 const uint8_t *addr) 2586 { 2587 int i; 2588 2589 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL, 2590 BWI_ADDR_FILTER_CTRL_SET | addr_ofs); 2591 2592 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) { 2593 uint16_t addr_val; 2594 2595 addr_val = (uint16_t)addr[i * 2] | 2596 (((uint16_t)addr[(i * 2) + 1]) << 8); 2597 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val); 2598 } 2599 } 2600 2601 static int 2602 bwi_rxeof(struct bwi_softc *sc, int end_idx) 2603 { 2604 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2605 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2606 struct ieee80211com *ic = &sc->sc_ic; 2607 int idx, rx_data = 0; 2608 2609 idx = rbd->rbd_idx; 2610 while (idx != end_idx) { 2611 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx]; 2612 struct bwi_rxbuf_hdr *hdr; 2613 struct ieee80211_frame_min *wh; 2614 struct ieee80211_node *ni; 2615 struct mbuf *m; 2616 uint32_t plcp; 2617 uint16_t flags2; 2618 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate; 2619 2620 m = rb->rb_mbuf; 2621 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap, 2622 BUS_DMASYNC_POSTREAD); 2623 2624 if (bwi_newbuf(sc, idx, 0)) { 2625 counter_u64_add(ic->ic_ierrors, 1); 2626 goto next; 2627 } 2628 2629 hdr = mtod(m, struct bwi_rxbuf_hdr *); 2630 flags2 = le16toh(hdr->rxh_flags2); 2631 2632 hdr_extra = 0; 2633 if (flags2 & BWI_RXH_F2_TYPE2FRAME) 2634 hdr_extra = 2; 2635 wh_ofs = hdr_extra + 6; /* XXX magic number */ 2636 2637 buflen = le16toh(hdr->rxh_buflen); 2638 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) { 2639 device_printf(sc->sc_dev, 2640 "%s: zero length data, hdr_extra %d\n", 2641 __func__, hdr_extra); 2642 counter_u64_add(ic->ic_ierrors, 1); 2643 m_freem(m); 2644 goto next; 2645 } 2646 2647 bcopy((uint8_t *)(hdr + 1) + hdr_extra, &plcp, sizeof(plcp)); 2648 rssi = bwi_calc_rssi(sc, hdr); 2649 noise = bwi_calc_noise(sc); 2650 2651 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr); 2652 m_adj(m, sizeof(*hdr) + wh_ofs); 2653 2654 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM) 2655 rate = bwi_plcp2rate(plcp, IEEE80211_T_OFDM); 2656 else 2657 rate = bwi_plcp2rate(plcp, IEEE80211_T_CCK); 2658 2659 /* RX radio tap */ 2660 if (ieee80211_radiotap_active(ic)) 2661 bwi_rx_radiotap(sc, m, hdr, &plcp, rate, rssi, noise); 2662 2663 m_adj(m, -IEEE80211_CRC_LEN); 2664 2665 BWI_UNLOCK(sc); 2666 2667 wh = mtod(m, struct ieee80211_frame_min *); 2668 ni = ieee80211_find_rxnode(ic, wh); 2669 if (ni != NULL) { 2670 type = ieee80211_input(ni, m, rssi - noise, noise); 2671 ieee80211_free_node(ni); 2672 } else 2673 type = ieee80211_input_all(ic, m, rssi - noise, noise); 2674 if (type == IEEE80211_FC0_TYPE_DATA) { 2675 rx_data = 1; 2676 sc->sc_rx_rate = rate; 2677 } 2678 2679 BWI_LOCK(sc); 2680 next: 2681 idx = (idx + 1) % BWI_RX_NDESC; 2682 2683 if (sc->sc_flags & BWI_F_STOP) { 2684 /* 2685 * Take the fast lane, don't do 2686 * any damage to softc 2687 */ 2688 return -1; 2689 } 2690 } 2691 2692 rbd->rbd_idx = idx; 2693 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2694 BUS_DMASYNC_PREWRITE); 2695 2696 return rx_data; 2697 } 2698 2699 static int 2700 bwi_rxeof32(struct bwi_softc *sc) 2701 { 2702 uint32_t val, rx_ctrl; 2703 int end_idx, rx_data; 2704 2705 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl; 2706 2707 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2708 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 2709 sizeof(struct bwi_desc32); 2710 2711 rx_data = bwi_rxeof(sc, end_idx); 2712 if (rx_data >= 0) { 2713 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX, 2714 end_idx * sizeof(struct bwi_desc32)); 2715 } 2716 return rx_data; 2717 } 2718 2719 static int 2720 bwi_rxeof64(struct bwi_softc *sc) 2721 { 2722 /* TODO:64 */ 2723 return 0; 2724 } 2725 2726 static void 2727 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl) 2728 { 2729 int i; 2730 2731 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0); 2732 2733 #define NRETRY 10 2734 2735 for (i = 0; i < NRETRY; ++i) { 2736 uint32_t status; 2737 2738 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2739 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) == 2740 BWI_RX32_STATUS_STATE_DISABLED) 2741 break; 2742 2743 DELAY(1000); 2744 } 2745 if (i == NRETRY) 2746 device_printf(sc->sc_dev, "reset rx ring timedout\n"); 2747 2748 #undef NRETRY 2749 2750 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0); 2751 } 2752 2753 static void 2754 bwi_free_txstats32(struct bwi_softc *sc) 2755 { 2756 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base); 2757 } 2758 2759 static void 2760 bwi_free_rx_ring32(struct bwi_softc *sc) 2761 { 2762 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2763 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2764 int i; 2765 2766 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl); 2767 2768 for (i = 0; i < BWI_RX_NDESC; ++i) { 2769 struct bwi_rxbuf *rb = &rbd->rbd_buf[i]; 2770 2771 if (rb->rb_mbuf != NULL) { 2772 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap); 2773 m_freem(rb->rb_mbuf); 2774 rb->rb_mbuf = NULL; 2775 } 2776 } 2777 } 2778 2779 static void 2780 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx) 2781 { 2782 struct bwi_ring_data *rd; 2783 struct bwi_txbuf_data *tbd; 2784 uint32_t state, val; 2785 int i; 2786 2787 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2788 rd = &sc->sc_tx_rdata[ring_idx]; 2789 tbd = &sc->sc_tx_bdata[ring_idx]; 2790 2791 #define NRETRY 10 2792 2793 for (i = 0; i < NRETRY; ++i) { 2794 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2795 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2796 if (state == BWI_TX32_STATUS_STATE_DISABLED || 2797 state == BWI_TX32_STATUS_STATE_IDLE || 2798 state == BWI_TX32_STATUS_STATE_STOPPED) 2799 break; 2800 2801 DELAY(1000); 2802 } 2803 if (i == NRETRY) { 2804 device_printf(sc->sc_dev, 2805 "%s: wait for TX ring(%d) stable timed out\n", 2806 __func__, ring_idx); 2807 } 2808 2809 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0); 2810 for (i = 0; i < NRETRY; ++i) { 2811 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2812 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2813 if (state == BWI_TX32_STATUS_STATE_DISABLED) 2814 break; 2815 2816 DELAY(1000); 2817 } 2818 if (i == NRETRY) 2819 device_printf(sc->sc_dev, "%s: reset TX ring (%d) timed out\n", 2820 __func__, ring_idx); 2821 2822 #undef NRETRY 2823 2824 DELAY(1000); 2825 2826 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0); 2827 2828 for (i = 0; i < BWI_TX_NDESC; ++i) { 2829 struct bwi_txbuf *tb = &tbd->tbd_buf[i]; 2830 2831 if (tb->tb_mbuf != NULL) { 2832 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 2833 m_freem(tb->tb_mbuf); 2834 tb->tb_mbuf = NULL; 2835 } 2836 if (tb->tb_ni != NULL) { 2837 ieee80211_free_node(tb->tb_ni); 2838 tb->tb_ni = NULL; 2839 } 2840 } 2841 } 2842 2843 static void 2844 bwi_free_txstats64(struct bwi_softc *sc) 2845 { 2846 /* TODO:64 */ 2847 } 2848 2849 static void 2850 bwi_free_rx_ring64(struct bwi_softc *sc) 2851 { 2852 /* TODO:64 */ 2853 } 2854 2855 static void 2856 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx) 2857 { 2858 /* TODO:64 */ 2859 } 2860 2861 /* XXX does not belong here */ 2862 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0) 2863 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5) 2864 2865 static __inline void 2866 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate) 2867 { 2868 uint32_t plcp; 2869 2870 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM), 2871 IEEE80211_OFDM_PLCP_RATE_MASK) | 2872 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK); 2873 *plcp0 = htole32(plcp); 2874 } 2875 2876 static __inline void 2877 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len, 2878 uint8_t rate) 2879 { 2880 int len, service, pkt_bitlen; 2881 2882 pkt_bitlen = pkt_len * NBBY; 2883 len = howmany(pkt_bitlen * 2, rate); 2884 2885 service = IEEE80211_PLCP_SERVICE_LOCKED; 2886 if (rate == (11 * 2)) { 2887 int pkt_bitlen1; 2888 2889 /* 2890 * PLCP service field needs to be adjusted, 2891 * if TX rate is 11Mbytes/s 2892 */ 2893 pkt_bitlen1 = len * 11; 2894 if (pkt_bitlen1 - pkt_bitlen >= NBBY) 2895 service |= IEEE80211_PLCP_SERVICE_LENEXT7; 2896 } 2897 2898 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK); 2899 plcp->i_service = service; 2900 plcp->i_length = htole16(len); 2901 /* NOTE: do NOT touch i_crc */ 2902 } 2903 2904 static __inline void 2905 bwi_plcp_header(const struct ieee80211_rate_table *rt, 2906 void *plcp, int pkt_len, uint8_t rate) 2907 { 2908 enum ieee80211_phytype modtype; 2909 2910 /* 2911 * Assume caller has zeroed 'plcp' 2912 */ 2913 modtype = ieee80211_rate2phytype(rt, rate); 2914 if (modtype == IEEE80211_T_OFDM) 2915 bwi_ofdm_plcp_header(plcp, pkt_len, rate); 2916 else if (modtype == IEEE80211_T_DS) 2917 bwi_ds_plcp_header(plcp, pkt_len, rate); 2918 else 2919 panic("unsupport modulation type %u\n", modtype); 2920 } 2921 2922 static int 2923 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m, 2924 struct ieee80211_node *ni) 2925 { 2926 struct ieee80211vap *vap = ni->ni_vap; 2927 struct ieee80211com *ic = &sc->sc_ic; 2928 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 2929 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 2930 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 2931 struct bwi_mac *mac; 2932 struct bwi_txbuf_hdr *hdr; 2933 struct ieee80211_frame *wh; 2934 const struct ieee80211_txparam *tp = ni->ni_txparms; 2935 uint8_t rate, rate_fb; 2936 uint32_t mac_ctrl; 2937 uint16_t phy_ctrl; 2938 bus_addr_t paddr; 2939 int type, ismcast, pkt_len, error, rix; 2940 #if 0 2941 const uint8_t *p; 2942 int i; 2943 #endif 2944 2945 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 2946 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 2947 mac = (struct bwi_mac *)sc->sc_cur_regwin; 2948 2949 wh = mtod(m, struct ieee80211_frame *); 2950 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2951 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2952 2953 /* Get 802.11 frame len before prepending TX header */ 2954 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 2955 2956 /* 2957 * Find TX rate 2958 */ 2959 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) { 2960 rate = rate_fb = tp->mgmtrate; 2961 } else if (ismcast) { 2962 rate = rate_fb = tp->mcastrate; 2963 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 2964 rate = rate_fb = tp->ucastrate; 2965 } else { 2966 rix = ieee80211_ratectl_rate(ni, NULL, pkt_len); 2967 rate = ni->ni_txrate; 2968 2969 if (rix > 0) { 2970 rate_fb = ni->ni_rates.rs_rates[rix-1] & 2971 IEEE80211_RATE_VAL; 2972 } else { 2973 rate_fb = rate; 2974 } 2975 } 2976 tb->tb_rate[0] = rate; 2977 tb->tb_rate[1] = rate_fb; 2978 sc->sc_tx_rate = rate; 2979 2980 /* 2981 * TX radio tap 2982 */ 2983 if (ieee80211_radiotap_active_vap(vap)) { 2984 sc->sc_tx_th.wt_flags = 0; 2985 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 2986 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2987 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS && 2988 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2989 rate != (1 * 2)) { 2990 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2991 } 2992 sc->sc_tx_th.wt_rate = rate; 2993 2994 ieee80211_radiotap_tx(vap, m); 2995 } 2996 2997 /* 2998 * Setup the embedded TX header 2999 */ 3000 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 3001 if (m == NULL) { 3002 device_printf(sc->sc_dev, "%s: prepend TX header failed\n", 3003 __func__); 3004 return ENOBUFS; 3005 } 3006 hdr = mtod(m, struct bwi_txbuf_hdr *); 3007 3008 bzero(hdr, sizeof(*hdr)); 3009 3010 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3011 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3012 3013 if (!ismcast) { 3014 uint16_t dur; 3015 3016 dur = ieee80211_ack_duration(sc->sc_rates, rate, 3017 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE); 3018 3019 hdr->txh_fb_duration = htole16(dur); 3020 } 3021 3022 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3023 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3024 3025 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3026 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3027 3028 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3029 BWI_TXH_PHY_C_ANTMODE_MASK); 3030 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 3031 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3032 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1)) 3033 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3034 3035 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3036 if (!ismcast) 3037 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3038 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM) 3039 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3040 3041 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3042 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3043 3044 /* Catch any further usage */ 3045 hdr = NULL; 3046 wh = NULL; 3047 3048 /* DMA load */ 3049 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3050 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3051 if (error && error != EFBIG) { 3052 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n", 3053 __func__, error); 3054 goto back; 3055 } 3056 3057 if (error) { /* error == EFBIG */ 3058 struct mbuf *m_new; 3059 3060 m_new = m_defrag(m, M_NOWAIT); 3061 if (m_new == NULL) { 3062 device_printf(sc->sc_dev, 3063 "%s: can't defrag TX buffer\n", __func__); 3064 error = ENOBUFS; 3065 goto back; 3066 } else { 3067 m = m_new; 3068 } 3069 3070 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3071 bwi_dma_buf_addr, &paddr, 3072 BUS_DMA_NOWAIT); 3073 if (error) { 3074 device_printf(sc->sc_dev, 3075 "%s: can't load TX buffer (2) %d\n", 3076 __func__, error); 3077 goto back; 3078 } 3079 } 3080 error = 0; 3081 3082 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3083 3084 tb->tb_mbuf = m; 3085 tb->tb_ni = ni; 3086 3087 #if 0 3088 p = mtod(m, const uint8_t *); 3089 for (i = 0; i < m->m_pkthdr.len; ++i) { 3090 if (i != 0 && i % 8 == 0) 3091 printf("\n"); 3092 printf("%02x ", p[i]); 3093 } 3094 printf("\n"); 3095 #endif 3096 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3097 idx, pkt_len, m->m_pkthdr.len); 3098 3099 /* Setup TX descriptor */ 3100 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3101 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3102 BUS_DMASYNC_PREWRITE); 3103 3104 /* Kick start */ 3105 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3106 3107 back: 3108 if (error) 3109 m_freem(m); 3110 return error; 3111 } 3112 3113 static int 3114 bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m, 3115 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3116 { 3117 struct ieee80211vap *vap = ni->ni_vap; 3118 struct ieee80211com *ic = ni->ni_ic; 3119 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 3120 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 3121 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 3122 struct bwi_mac *mac; 3123 struct bwi_txbuf_hdr *hdr; 3124 struct ieee80211_frame *wh; 3125 uint8_t rate, rate_fb; 3126 uint32_t mac_ctrl; 3127 uint16_t phy_ctrl; 3128 bus_addr_t paddr; 3129 int ismcast, pkt_len, error; 3130 3131 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3132 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3133 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3134 3135 wh = mtod(m, struct ieee80211_frame *); 3136 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3137 3138 /* Get 802.11 frame len before prepending TX header */ 3139 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 3140 3141 /* 3142 * Find TX rate 3143 */ 3144 rate = params->ibp_rate0; 3145 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3146 /* XXX fall back to mcast/mgmt rate? */ 3147 m_freem(m); 3148 return EINVAL; 3149 } 3150 if (params->ibp_try1 != 0) { 3151 rate_fb = params->ibp_rate1; 3152 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) { 3153 /* XXX fall back to rate0? */ 3154 m_freem(m); 3155 return EINVAL; 3156 } 3157 } else 3158 rate_fb = rate; 3159 tb->tb_rate[0] = rate; 3160 tb->tb_rate[1] = rate_fb; 3161 sc->sc_tx_rate = rate; 3162 3163 /* 3164 * TX radio tap 3165 */ 3166 if (ieee80211_radiotap_active_vap(vap)) { 3167 sc->sc_tx_th.wt_flags = 0; 3168 /* XXX IEEE80211_BPF_CRYPTO */ 3169 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3170 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3171 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3172 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3173 sc->sc_tx_th.wt_rate = rate; 3174 3175 ieee80211_radiotap_tx(vap, m); 3176 } 3177 3178 /* 3179 * Setup the embedded TX header 3180 */ 3181 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 3182 if (m == NULL) { 3183 device_printf(sc->sc_dev, "%s: prepend TX header failed\n", 3184 __func__); 3185 return ENOBUFS; 3186 } 3187 hdr = mtod(m, struct bwi_txbuf_hdr *); 3188 3189 bzero(hdr, sizeof(*hdr)); 3190 3191 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3192 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3193 3194 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3195 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 3196 uint16_t dur; 3197 3198 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0); 3199 3200 hdr->txh_fb_duration = htole16(dur); 3201 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3202 } 3203 3204 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3205 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3206 3207 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3208 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3209 3210 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3211 BWI_TXH_PHY_C_ANTMODE_MASK); 3212 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 3213 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3214 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3215 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3216 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3217 3218 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3219 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3220 3221 /* Catch any further usage */ 3222 hdr = NULL; 3223 wh = NULL; 3224 3225 /* DMA load */ 3226 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3227 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3228 if (error != 0) { 3229 struct mbuf *m_new; 3230 3231 if (error != EFBIG) { 3232 device_printf(sc->sc_dev, 3233 "%s: can't load TX buffer (1) %d\n", 3234 __func__, error); 3235 goto back; 3236 } 3237 m_new = m_defrag(m, M_NOWAIT); 3238 if (m_new == NULL) { 3239 device_printf(sc->sc_dev, 3240 "%s: can't defrag TX buffer\n", __func__); 3241 error = ENOBUFS; 3242 goto back; 3243 } 3244 m = m_new; 3245 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3246 bwi_dma_buf_addr, &paddr, 3247 BUS_DMA_NOWAIT); 3248 if (error) { 3249 device_printf(sc->sc_dev, 3250 "%s: can't load TX buffer (2) %d\n", 3251 __func__, error); 3252 goto back; 3253 } 3254 } 3255 3256 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3257 3258 tb->tb_mbuf = m; 3259 tb->tb_ni = ni; 3260 3261 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3262 idx, pkt_len, m->m_pkthdr.len); 3263 3264 /* Setup TX descriptor */ 3265 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3266 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3267 BUS_DMASYNC_PREWRITE); 3268 3269 /* Kick start */ 3270 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3271 back: 3272 if (error) 3273 m_freem(m); 3274 return error; 3275 } 3276 3277 static void 3278 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3279 { 3280 idx = (idx + 1) % BWI_TX_NDESC; 3281 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX, 3282 idx * sizeof(struct bwi_desc32)); 3283 } 3284 3285 static void 3286 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3287 { 3288 /* TODO:64 */ 3289 } 3290 3291 static void 3292 bwi_txeof_status32(struct bwi_softc *sc) 3293 { 3294 uint32_t val, ctrl_base; 3295 int end_idx; 3296 3297 ctrl_base = sc->sc_txstats->stats_ctrl_base; 3298 3299 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS); 3300 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 3301 sizeof(struct bwi_desc32); 3302 3303 bwi_txeof_status(sc, end_idx); 3304 3305 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 3306 end_idx * sizeof(struct bwi_desc32)); 3307 3308 bwi_start_locked(sc); 3309 } 3310 3311 static void 3312 bwi_txeof_status64(struct bwi_softc *sc) 3313 { 3314 /* TODO:64 */ 3315 } 3316 3317 static void 3318 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt) 3319 { 3320 struct bwi_txbuf_data *tbd; 3321 struct bwi_txbuf *tb; 3322 int ring_idx, buf_idx; 3323 struct ieee80211_node *ni; 3324 3325 if (tx_id == 0) { 3326 device_printf(sc->sc_dev, "%s: zero tx id\n", __func__); 3327 return; 3328 } 3329 3330 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK); 3331 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK); 3332 3333 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx)); 3334 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 3335 3336 tbd = &sc->sc_tx_bdata[ring_idx]; 3337 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used)); 3338 tbd->tbd_used--; 3339 3340 tb = &tbd->tbd_buf[buf_idx]; 3341 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, " 3342 "acked %d, data_txcnt %d, ni %p\n", 3343 buf_idx, acked, data_txcnt, tb->tb_ni); 3344 3345 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 3346 3347 if ((ni = tb->tb_ni) != NULL) { 3348 const struct bwi_txbuf_hdr *hdr = 3349 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *); 3350 struct ieee80211_ratectl_tx_status txs; 3351 3352 /* NB: update rate control only for unicast frames */ 3353 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) { 3354 /* 3355 * Feed back 'acked and data_txcnt'. Note that the 3356 * generic AMRR code only understands one tx rate 3357 * and the estimator doesn't handle real retry counts 3358 * well so to avoid over-aggressive downshifting we 3359 * treat any number of retries as "1". 3360 */ 3361 txs.flags = IEEE80211_RATECTL_STATUS_LONG_RETRY; 3362 txs.long_retries = acked; 3363 if (data_txcnt > 1) 3364 txs.status = IEEE80211_RATECTL_TX_SUCCESS; 3365 else { 3366 txs.status = 3367 IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 3368 } 3369 ieee80211_ratectl_tx_complete(ni, &txs); 3370 } 3371 ieee80211_tx_complete(ni, tb->tb_mbuf, !acked); 3372 tb->tb_ni = NULL; 3373 } else 3374 m_freem(tb->tb_mbuf); 3375 tb->tb_mbuf = NULL; 3376 3377 if (tbd->tbd_used == 0) 3378 sc->sc_tx_timer = 0; 3379 } 3380 3381 static void 3382 bwi_txeof_status(struct bwi_softc *sc, int end_idx) 3383 { 3384 struct bwi_txstats_data *st = sc->sc_txstats; 3385 int idx; 3386 3387 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD); 3388 3389 idx = st->stats_idx; 3390 while (idx != end_idx) { 3391 const struct bwi_txstats *stats = &st->stats[idx]; 3392 3393 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) { 3394 int data_txcnt; 3395 3396 data_txcnt = __SHIFTOUT(stats->txs_txcnt, 3397 BWI_TXS_TXCNT_DATA); 3398 _bwi_txeof(sc, le16toh(stats->txs_id), 3399 stats->txs_flags & BWI_TXS_F_ACKED, 3400 data_txcnt); 3401 } 3402 idx = (idx + 1) % BWI_TXSTATS_NDESC; 3403 } 3404 st->stats_idx = idx; 3405 } 3406 3407 static void 3408 bwi_txeof(struct bwi_softc *sc) 3409 { 3410 3411 for (;;) { 3412 uint32_t tx_status0, tx_status1; 3413 uint16_t tx_id; 3414 int data_txcnt; 3415 3416 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0); 3417 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0) 3418 break; 3419 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1); 3420 3421 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK); 3422 data_txcnt = __SHIFTOUT(tx_status0, 3423 BWI_TXSTATUS0_DATA_TXCNT_MASK); 3424 3425 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING)) 3426 continue; 3427 3428 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED, 3429 data_txcnt); 3430 } 3431 3432 bwi_start_locked(sc); 3433 } 3434 3435 static int 3436 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 3437 { 3438 bwi_power_on(sc, 1); 3439 return bwi_set_clock_mode(sc, clk_mode); 3440 } 3441 3442 static void 3443 bwi_bbp_power_off(struct bwi_softc *sc) 3444 { 3445 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW); 3446 bwi_power_off(sc, 1); 3447 } 3448 3449 static int 3450 bwi_get_pwron_delay(struct bwi_softc *sc) 3451 { 3452 struct bwi_regwin *com, *old; 3453 struct bwi_clock_freq freq; 3454 uint32_t val; 3455 int error; 3456 3457 com = &sc->sc_com_regwin; 3458 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin")); 3459 3460 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 3461 return 0; 3462 3463 error = bwi_regwin_switch(sc, com, &old); 3464 if (error) 3465 return error; 3466 3467 bwi_get_clock_freq(sc, &freq); 3468 3469 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY); 3470 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min); 3471 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay); 3472 3473 return bwi_regwin_switch(sc, old, NULL); 3474 } 3475 3476 static int 3477 bwi_bus_attach(struct bwi_softc *sc) 3478 { 3479 struct bwi_regwin *bus, *old; 3480 int error; 3481 3482 bus = &sc->sc_bus_regwin; 3483 3484 error = bwi_regwin_switch(sc, bus, &old); 3485 if (error) 3486 return error; 3487 3488 if (!bwi_regwin_is_enabled(sc, bus)) 3489 bwi_regwin_enable(sc, bus, 0); 3490 3491 /* Disable interripts */ 3492 CSR_WRITE_4(sc, BWI_INTRVEC, 0); 3493 3494 return bwi_regwin_switch(sc, old, NULL); 3495 } 3496 3497 static const char * 3498 bwi_regwin_name(const struct bwi_regwin *rw) 3499 { 3500 switch (rw->rw_type) { 3501 case BWI_REGWIN_T_COM: 3502 return "COM"; 3503 case BWI_REGWIN_T_BUSPCI: 3504 return "PCI"; 3505 case BWI_REGWIN_T_MAC: 3506 return "MAC"; 3507 case BWI_REGWIN_T_BUSPCIE: 3508 return "PCIE"; 3509 } 3510 panic("unknown regwin type 0x%04x\n", rw->rw_type); 3511 return NULL; 3512 } 3513 3514 static uint32_t 3515 bwi_regwin_disable_bits(struct bwi_softc *sc) 3516 { 3517 uint32_t busrev; 3518 3519 /* XXX cache this */ 3520 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK); 3521 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC, 3522 "bus rev %u\n", busrev); 3523 3524 if (busrev == BWI_BUSREV_0) 3525 return BWI_STATE_LO_DISABLE1; 3526 else if (busrev == BWI_BUSREV_1) 3527 return BWI_STATE_LO_DISABLE2; 3528 else 3529 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2); 3530 } 3531 3532 int 3533 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw) 3534 { 3535 uint32_t val, disable_bits; 3536 3537 disable_bits = bwi_regwin_disable_bits(sc); 3538 val = CSR_READ_4(sc, BWI_STATE_LO); 3539 3540 if ((val & (BWI_STATE_LO_CLOCK | 3541 BWI_STATE_LO_RESET | 3542 disable_bits)) == BWI_STATE_LO_CLOCK) { 3543 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n", 3544 bwi_regwin_name(rw)); 3545 return 1; 3546 } else { 3547 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n", 3548 bwi_regwin_name(rw)); 3549 return 0; 3550 } 3551 } 3552 3553 void 3554 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3555 { 3556 uint32_t state_lo, disable_bits; 3557 int i; 3558 3559 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3560 3561 /* 3562 * If current regwin is in 'reset' state, it was already disabled. 3563 */ 3564 if (state_lo & BWI_STATE_LO_RESET) { 3565 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, 3566 "%s was already disabled\n", bwi_regwin_name(rw)); 3567 return; 3568 } 3569 3570 disable_bits = bwi_regwin_disable_bits(sc); 3571 3572 /* 3573 * Disable normal clock 3574 */ 3575 state_lo = BWI_STATE_LO_CLOCK | disable_bits; 3576 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3577 3578 /* 3579 * Wait until normal clock is disabled 3580 */ 3581 #define NRETRY 1000 3582 for (i = 0; i < NRETRY; ++i) { 3583 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3584 if (state_lo & disable_bits) 3585 break; 3586 DELAY(10); 3587 } 3588 if (i == NRETRY) { 3589 device_printf(sc->sc_dev, "%s disable clock timeout\n", 3590 bwi_regwin_name(rw)); 3591 } 3592 3593 for (i = 0; i < NRETRY; ++i) { 3594 uint32_t state_hi; 3595 3596 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3597 if ((state_hi & BWI_STATE_HI_BUSY) == 0) 3598 break; 3599 DELAY(10); 3600 } 3601 if (i == NRETRY) { 3602 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n", 3603 bwi_regwin_name(rw)); 3604 } 3605 #undef NRETRY 3606 3607 /* 3608 * Reset and disable regwin with gated clock 3609 */ 3610 state_lo = BWI_STATE_LO_RESET | disable_bits | 3611 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK | 3612 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3613 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3614 3615 /* Flush pending bus write */ 3616 CSR_READ_4(sc, BWI_STATE_LO); 3617 DELAY(1); 3618 3619 /* Reset and disable regwin */ 3620 state_lo = BWI_STATE_LO_RESET | disable_bits | 3621 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3622 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3623 3624 /* Flush pending bus write */ 3625 CSR_READ_4(sc, BWI_STATE_LO); 3626 DELAY(1); 3627 } 3628 3629 void 3630 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3631 { 3632 uint32_t state_lo, state_hi, imstate; 3633 3634 bwi_regwin_disable(sc, rw, flags); 3635 3636 /* Reset regwin with gated clock */ 3637 state_lo = BWI_STATE_LO_RESET | 3638 BWI_STATE_LO_CLOCK | 3639 BWI_STATE_LO_GATED_CLOCK | 3640 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3641 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3642 3643 /* Flush pending bus write */ 3644 CSR_READ_4(sc, BWI_STATE_LO); 3645 DELAY(1); 3646 3647 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3648 if (state_hi & BWI_STATE_HI_SERROR) 3649 CSR_WRITE_4(sc, BWI_STATE_HI, 0); 3650 3651 imstate = CSR_READ_4(sc, BWI_IMSTATE); 3652 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) { 3653 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT); 3654 CSR_WRITE_4(sc, BWI_IMSTATE, imstate); 3655 } 3656 3657 /* Enable regwin with gated clock */ 3658 state_lo = BWI_STATE_LO_CLOCK | 3659 BWI_STATE_LO_GATED_CLOCK | 3660 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3661 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3662 3663 /* Flush pending bus write */ 3664 CSR_READ_4(sc, BWI_STATE_LO); 3665 DELAY(1); 3666 3667 /* Enable regwin with normal clock */ 3668 state_lo = BWI_STATE_LO_CLOCK | 3669 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3670 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3671 3672 /* Flush pending bus write */ 3673 CSR_READ_4(sc, BWI_STATE_LO); 3674 DELAY(1); 3675 } 3676 3677 static void 3678 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid) 3679 { 3680 struct bwi_mac *mac; 3681 struct bwi_myaddr_bssid buf; 3682 const uint8_t *p; 3683 uint32_t val; 3684 int n, i; 3685 3686 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3687 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3688 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3689 3690 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid); 3691 3692 bcopy(sc->sc_ic.ic_macaddr, buf.myaddr, sizeof(buf.myaddr)); 3693 bcopy(bssid, buf.bssid, sizeof(buf.bssid)); 3694 3695 n = sizeof(buf) / sizeof(val); 3696 p = (const uint8_t *)&buf; 3697 for (i = 0; i < n; ++i) { 3698 int j; 3699 3700 val = 0; 3701 for (j = 0; j < sizeof(val); ++j) 3702 val |= ((uint32_t)(*p++)) << (j * 8); 3703 3704 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val); 3705 } 3706 } 3707 3708 static void 3709 bwi_updateslot(struct ieee80211com *ic) 3710 { 3711 struct bwi_softc *sc = ic->ic_softc; 3712 struct bwi_mac *mac; 3713 3714 BWI_LOCK(sc); 3715 if (sc->sc_flags & BWI_F_RUNNING) { 3716 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__); 3717 3718 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3719 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3720 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3721 3722 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT)); 3723 } 3724 BWI_UNLOCK(sc); 3725 } 3726 3727 static void 3728 bwi_calibrate(void *xsc) 3729 { 3730 struct bwi_softc *sc = xsc; 3731 struct bwi_mac *mac; 3732 3733 BWI_ASSERT_LOCKED(sc); 3734 3735 KASSERT(sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR, 3736 ("opmode %d", sc->sc_ic.ic_opmode)); 3737 3738 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3739 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3740 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3741 3742 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type); 3743 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 3744 3745 /* XXX 15 seconds */ 3746 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc); 3747 } 3748 3749 static int 3750 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr) 3751 { 3752 struct bwi_mac *mac; 3753 3754 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3755 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3756 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3757 3758 return bwi_rf_calc_rssi(mac, hdr); 3759 } 3760 3761 static int 3762 bwi_calc_noise(struct bwi_softc *sc) 3763 { 3764 struct bwi_mac *mac; 3765 3766 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3767 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3768 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3769 3770 return bwi_rf_calc_noise(mac); 3771 } 3772 3773 static __inline uint8_t 3774 bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phytype type) 3775 { 3776 uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK; 3777 return (ieee80211_plcp2rate(plcp, type)); 3778 } 3779 3780 static void 3781 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m, 3782 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise) 3783 { 3784 const struct ieee80211_frame_min *wh; 3785 3786 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS; 3787 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE) 3788 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3789 3790 wh = mtod(m, const struct ieee80211_frame_min *); 3791 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3792 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 3793 3794 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian conversion */ 3795 sc->sc_rx_th.wr_rate = rate; 3796 sc->sc_rx_th.wr_antsignal = rssi; 3797 sc->sc_rx_th.wr_antnoise = noise; 3798 } 3799 3800 static void 3801 bwi_led_attach(struct bwi_softc *sc) 3802 { 3803 const uint8_t *led_act = NULL; 3804 uint16_t gpio, val[BWI_LED_MAX]; 3805 int i; 3806 3807 for (i = 0; i < nitems(bwi_vendor_led_act); ++i) { 3808 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) { 3809 led_act = bwi_vendor_led_act[i].led_act; 3810 break; 3811 } 3812 } 3813 if (led_act == NULL) 3814 led_act = bwi_default_led_act; 3815 3816 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01); 3817 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0); 3818 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1); 3819 3820 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23); 3821 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2); 3822 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3); 3823 3824 for (i = 0; i < BWI_LED_MAX; ++i) { 3825 struct bwi_led *led = &sc->sc_leds[i]; 3826 3827 if (val[i] == 0xff) { 3828 led->l_act = led_act[i]; 3829 } else { 3830 if (val[i] & BWI_LED_ACT_LOW) 3831 led->l_flags |= BWI_LED_F_ACTLOW; 3832 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK); 3833 } 3834 led->l_mask = (1 << i); 3835 3836 if (led->l_act == BWI_LED_ACT_BLINK_SLOW || 3837 led->l_act == BWI_LED_ACT_BLINK_POLL || 3838 led->l_act == BWI_LED_ACT_BLINK) { 3839 led->l_flags |= BWI_LED_F_BLINK; 3840 if (led->l_act == BWI_LED_ACT_BLINK_POLL) 3841 led->l_flags |= BWI_LED_F_POLLABLE; 3842 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW) 3843 led->l_flags |= BWI_LED_F_SLOW; 3844 3845 if (sc->sc_blink_led == NULL) { 3846 sc->sc_blink_led = led; 3847 if (led->l_flags & BWI_LED_F_SLOW) 3848 BWI_LED_SLOWDOWN(sc->sc_led_idle); 3849 } 3850 } 3851 3852 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH, 3853 "%dth led, act %d, lowact %d\n", i, 3854 led->l_act, led->l_flags & BWI_LED_F_ACTLOW); 3855 } 3856 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0); 3857 } 3858 3859 static __inline uint16_t 3860 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on) 3861 { 3862 if (led->l_flags & BWI_LED_F_ACTLOW) 3863 on = !on; 3864 if (on) 3865 val |= led->l_mask; 3866 else 3867 val &= ~led->l_mask; 3868 return val; 3869 } 3870 3871 static void 3872 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate) 3873 { 3874 struct ieee80211com *ic = &sc->sc_ic; 3875 uint16_t val; 3876 int i; 3877 3878 if (nstate == IEEE80211_S_INIT) { 3879 callout_stop(&sc->sc_led_blink_ch); 3880 sc->sc_led_blinking = 0; 3881 } 3882 3883 if ((sc->sc_flags & BWI_F_RUNNING) == 0) 3884 return; 3885 3886 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3887 for (i = 0; i < BWI_LED_MAX; ++i) { 3888 struct bwi_led *led = &sc->sc_leds[i]; 3889 int on; 3890 3891 if (led->l_act == BWI_LED_ACT_UNKN || 3892 led->l_act == BWI_LED_ACT_NULL) 3893 continue; 3894 3895 if ((led->l_flags & BWI_LED_F_BLINK) && 3896 nstate != IEEE80211_S_INIT) 3897 continue; 3898 3899 switch (led->l_act) { 3900 case BWI_LED_ACT_ON: /* Always on */ 3901 on = 1; 3902 break; 3903 case BWI_LED_ACT_OFF: /* Always off */ 3904 case BWI_LED_ACT_5GHZ: /* TODO: 11A */ 3905 on = 0; 3906 break; 3907 default: 3908 on = 1; 3909 switch (nstate) { 3910 case IEEE80211_S_INIT: 3911 on = 0; 3912 break; 3913 case IEEE80211_S_RUN: 3914 if (led->l_act == BWI_LED_ACT_11G && 3915 ic->ic_curmode != IEEE80211_MODE_11G) 3916 on = 0; 3917 break; 3918 default: 3919 if (led->l_act == BWI_LED_ACT_ASSOC) 3920 on = 0; 3921 break; 3922 } 3923 break; 3924 } 3925 3926 val = bwi_led_onoff(led, val, on); 3927 } 3928 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3929 } 3930 static void 3931 bwi_led_event(struct bwi_softc *sc, int event) 3932 { 3933 struct bwi_led *led = sc->sc_blink_led; 3934 int rate; 3935 3936 if (event == BWI_LED_EVENT_POLL) { 3937 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0) 3938 return; 3939 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 3940 return; 3941 } 3942 3943 sc->sc_led_ticks = ticks; 3944 if (sc->sc_led_blinking) 3945 return; 3946 3947 switch (event) { 3948 case BWI_LED_EVENT_RX: 3949 rate = sc->sc_rx_rate; 3950 break; 3951 case BWI_LED_EVENT_TX: 3952 rate = sc->sc_tx_rate; 3953 break; 3954 case BWI_LED_EVENT_POLL: 3955 rate = 0; 3956 break; 3957 default: 3958 panic("unknown LED event %d\n", event); 3959 break; 3960 } 3961 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur, 3962 bwi_led_duration[rate].off_dur); 3963 } 3964 3965 static void 3966 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur) 3967 { 3968 struct bwi_led *led = sc->sc_blink_led; 3969 uint16_t val; 3970 3971 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3972 val = bwi_led_onoff(led, val, 1); 3973 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3974 3975 if (led->l_flags & BWI_LED_F_SLOW) { 3976 BWI_LED_SLOWDOWN(on_dur); 3977 BWI_LED_SLOWDOWN(off_dur); 3978 } 3979 3980 sc->sc_led_blinking = 1; 3981 sc->sc_led_blink_offdur = off_dur; 3982 3983 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc); 3984 } 3985 3986 static void 3987 bwi_led_blink_next(void *xsc) 3988 { 3989 struct bwi_softc *sc = xsc; 3990 uint16_t val; 3991 3992 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3993 val = bwi_led_onoff(sc->sc_blink_led, val, 0); 3994 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3995 3996 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 3997 bwi_led_blink_end, sc); 3998 } 3999 4000 static void 4001 bwi_led_blink_end(void *xsc) 4002 { 4003 struct bwi_softc *sc = xsc; 4004 sc->sc_led_blinking = 0; 4005 } 4006 4007 static void 4008 bwi_restart(void *xsc, int pending) 4009 { 4010 struct bwi_softc *sc = xsc; 4011 4012 device_printf(sc->sc_dev, "%s begin, help!\n", __func__); 4013 BWI_LOCK(sc); 4014 bwi_init_statechg(sc, 0); 4015 #if 0 4016 bwi_start_locked(sc); 4017 #endif 4018 BWI_UNLOCK(sc); 4019 } 4020