1 /*- 2 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _FENV_H_ 30 #define _FENV_H_ 31 32 #include <sys/_types.h> 33 34 #ifndef __fenv_static 35 #define __fenv_static static 36 #endif 37 38 typedef __uint32_t fenv_t; 39 typedef __uint32_t fexcept_t; 40 41 /* Exception flags */ 42 #define FE_INEXACT 0x02000000 43 #define FE_DIVBYZERO 0x04000000 44 #define FE_UNDERFLOW 0x08000000 45 #define FE_OVERFLOW 0x10000000 46 #define FE_INVALID 0x20000000 /* all types of invalid FP ops */ 47 48 /* 49 * The PowerPC architecture has extra invalid flags that indicate the 50 * specific type of invalid operation occurred. These flags may be 51 * tested, set, and cleared---but not masked---separately. All of 52 * these bits are cleared when FE_INVALID is cleared, but only 53 * FE_VXSOFT is set when FE_INVALID is explicitly set in software. 54 */ 55 #define FE_VXCVI 0x00000100 /* invalid integer convert */ 56 #define FE_VXSQRT 0x00000200 /* square root of a negative */ 57 #define FE_VXSOFT 0x00000400 /* software-requested exception */ 58 #define FE_VXVC 0x00080000 /* ordered comparison involving NaN */ 59 #define FE_VXIMZ 0x00100000 /* inf * 0 */ 60 #define FE_VXZDZ 0x00200000 /* 0 / 0 */ 61 #define FE_VXIDI 0x00400000 /* inf / inf */ 62 #define FE_VXISI 0x00800000 /* inf - inf */ 63 #define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */ 64 #define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \ 65 FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \ 66 FE_VXSNAN | FE_INVALID) 67 #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ 68 FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW) 69 70 /* Rounding modes */ 71 #define FE_TONEAREST 0x0000 72 #define FE_TOWARDZERO 0x0001 73 #define FE_UPWARD 0x0002 74 #define FE_DOWNWARD 0x0003 75 #define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ 76 FE_UPWARD | FE_TOWARDZERO) 77 78 __BEGIN_DECLS 79 80 /* Default floating-point environment */ 81 extern const fenv_t __fe_dfl_env; 82 #define FE_DFL_ENV (&__fe_dfl_env) 83 84 /* We need to be able to map status flag positions to mask flag positions */ 85 #define _FPUSW_SHIFT 22 86 #define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ 87 FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT) 88 89 #ifndef _SOFT_FLOAT 90 #ifdef __SPE__ 91 #define __mffs(__env) __asm __volatile("mfspr %0, 512" : "=r" (*(__env))) 92 #define __mtfsf(__env) __asm __volatile("mtspr 512,%0" : : "r" (__env)) 93 #else 94 #define __mffs(__env) __asm __volatile("mffs %0" : "=f" (*(__env))) 95 #define __mtfsf(__env) __asm __volatile("mtfsf 255,%0" : : "f" (__env)) 96 #endif 97 #else 98 #define __mffs(__env) 99 #define __mtfsf(__env) 100 #endif 101 102 union __fpscr { 103 double __d; 104 struct { 105 #if _BYTE_ORDER == _LITTLE_ENDIAN 106 fenv_t __reg; 107 __uint32_t __junk; 108 #else 109 __uint32_t __junk; 110 fenv_t __reg; 111 #endif 112 } __bits; 113 }; 114 115 __fenv_static inline int 116 feclearexcept(int __excepts) 117 { 118 union __fpscr __r; 119 120 if (__excepts & FE_INVALID) 121 __excepts |= FE_ALL_INVALID; 122 __mffs(&__r.__d); 123 __r.__bits.__reg &= ~__excepts; 124 __mtfsf(__r.__d); 125 return (0); 126 } 127 128 __fenv_static inline int 129 fegetexceptflag(fexcept_t *__flagp, int __excepts) 130 { 131 union __fpscr __r; 132 133 __mffs(&__r.__d); 134 *__flagp = __r.__bits.__reg & __excepts; 135 return (0); 136 } 137 138 __fenv_static inline int 139 fesetexceptflag(const fexcept_t *__flagp, int __excepts) 140 { 141 union __fpscr __r; 142 143 if (__excepts & FE_INVALID) 144 __excepts |= FE_ALL_EXCEPT; 145 __mffs(&__r.__d); 146 __r.__bits.__reg &= ~__excepts; 147 __r.__bits.__reg |= *__flagp & __excepts; 148 __mtfsf(__r.__d); 149 return (0); 150 } 151 152 __fenv_static inline int 153 feraiseexcept(int __excepts) 154 { 155 union __fpscr __r; 156 157 if (__excepts & FE_INVALID) 158 __excepts |= FE_VXSOFT; 159 __mffs(&__r.__d); 160 __r.__bits.__reg |= __excepts; 161 __mtfsf(__r.__d); 162 return (0); 163 } 164 165 __fenv_static inline int 166 fetestexcept(int __excepts) 167 { 168 union __fpscr __r; 169 170 __mffs(&__r.__d); 171 return (__r.__bits.__reg & __excepts); 172 } 173 174 __fenv_static inline int 175 fegetround(void) 176 { 177 union __fpscr __r; 178 179 __mffs(&__r.__d); 180 return (__r.__bits.__reg & _ROUND_MASK); 181 } 182 183 __fenv_static inline int 184 fesetround(int __round) 185 { 186 union __fpscr __r; 187 188 if (__round & ~_ROUND_MASK) 189 return (-1); 190 __mffs(&__r.__d); 191 __r.__bits.__reg &= ~_ROUND_MASK; 192 __r.__bits.__reg |= __round; 193 __mtfsf(__r.__d); 194 return (0); 195 } 196 197 __fenv_static inline int 198 fegetenv(fenv_t *__envp) 199 { 200 union __fpscr __r; 201 202 __mffs(&__r.__d); 203 *__envp = __r.__bits.__reg; 204 return (0); 205 } 206 207 __fenv_static inline int 208 feholdexcept(fenv_t *__envp) 209 { 210 union __fpscr __r; 211 212 __mffs(&__r.__d); 213 *__envp = __r.__d; 214 __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK); 215 __mtfsf(__r.__d); 216 return (0); 217 } 218 219 __fenv_static inline int 220 fesetenv(const fenv_t *__envp) 221 { 222 union __fpscr __r; 223 224 __r.__bits.__reg = *__envp; 225 __mtfsf(__r.__d); 226 return (0); 227 } 228 229 __fenv_static inline int 230 feupdateenv(const fenv_t *__envp) 231 { 232 union __fpscr __r; 233 234 __mffs(&__r.__d); 235 __r.__bits.__reg &= FE_ALL_EXCEPT; 236 __r.__bits.__reg |= *__envp; 237 __mtfsf(__r.__d); 238 return (0); 239 } 240 241 #if __BSD_VISIBLE 242 243 /* We currently provide no external definitions of the functions below. */ 244 245 static inline int 246 feenableexcept(int __mask) 247 { 248 union __fpscr __r; 249 fenv_t __oldmask; 250 251 __mffs(&__r.__d); 252 __oldmask = __r.__bits.__reg; 253 __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT; 254 __mtfsf(__r.__d); 255 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 256 } 257 258 static inline int 259 fedisableexcept(int __mask) 260 { 261 union __fpscr __r; 262 fenv_t __oldmask; 263 264 __mffs(&__r.__d); 265 __oldmask = __r.__bits.__reg; 266 __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT); 267 __mtfsf(__r.__d); 268 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 269 } 270 271 static inline int 272 fegetexcept(void) 273 { 274 union __fpscr __r; 275 276 __mffs(&__r.__d); 277 return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT); 278 } 279 280 #endif /* __BSD_VISIBLE */ 281 282 __END_DECLS 283 284 #endif /* !_FENV_H_ */ 285