Remove $FreeBSD$: two-line .h pattern

Remove /^\s*\*\n \*\s+\$FreeBSD\$$\n/

spdx: The BSD-2-Clause-FreeBSD identifier is obsolete, drop -FreeBSD

The SPDX folks have obsoleted the BSD-2-Clause-FreeBSD identifier. Catch
up to that fact and revert to their recommended match of

spdx: The BSD-2-Clause-FreeBSD identifier is obsolete, drop -FreeBSD

The SPDX folks have obsoleted the BSD-2-Clause-FreeBSD identifier. Catch
up to that fact and revert to their recommended match of BSD-2-Clause.

Discussed with: pfg
MFC After: 3 days
Sponsored by: Netflix

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libm: Add feenableexcept and fedisableexcept to library on powerpc

Summary:
These functions are missing from the library itself, and exist solely in
the header. This breaks a few ports that expect

libm: Add feenableexcept and fedisableexcept to library on powerpc

Summary:
These functions are missing from the library itself, and exist solely in
the header. This breaks a few ports that expect libm to have the
symbols in the library itself.

Questions on MFC-ability: Can this be MFC'd to 13.2, and how?

Reviewers: imp, emaste, kib

Reviewed By: kib

Differential Revision: https://reviews.freebsd.org/D35204

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msun fixes for SPE

Summary:
Fix FPU exception management for powerpcspe. Bits are in a different place from
the standard FPSCR, so we need to handle the shifting differences. Also,
there's no conc

msun fixes for SPE

Summary:
Fix FPU exception management for powerpcspe. Bits are in a different place from
the standard FPSCR, so we need to handle the shifting differences. Also,
there's no concept of a "software exception" raise, so we need to do exceptional
math to trigger the exception from software.

Reviewed By: alfredo
Differential Revision: https://reviews.freebsd.org/D22824

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[POWERPC] msun: fix incorrect flag in fesetexceptflag

Fix incorrect mask being used when FE_INVALID bit is wanted by user.
The problem was noticed thanks to msun fenv tests.

Reviewed by: jhibbits,

[POWERPC] msun: fix incorrect flag in fesetexceptflag

Fix incorrect mask being used when FE_INVALID bit is wanted by user.
The problem was noticed thanks to msun fenv tests.

Reviewed by: jhibbits, luporl
Sponsored by: Eldorado Research Institute (eldorado.org.br)
Differential Revision: https://reviews.freebsd.org/D27201

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Merge ^/head r357408 through r357661.

[PowerPC] Fix feholdexcept() on powerpc referencing the wrong struct member

In r355656, endianness handling of the floating point environment was fixed
in the PowerPC code to work as intended.

Howe

[PowerPC] Fix feholdexcept() on powerpc referencing the wrong struct member

In r355656, endianness handling of the floating point environment was fixed
in the PowerPC code to work as intended.

However, one bit got missed, causing feholdexcept() to mis-save the fenv.

Submitted by: Renato Riolino <renato.riolino@eldorado.org.br>
Differential Revision: https://reviews.freebsd.org/D23382

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[PowerPC] Fix SPE floating point environment manipulation

Fix multiple problems in the powerpcspe floating point code.

* Endianness handling of the SPEFSCR in fenv.h was completely broken.
* Ensure

[PowerPC] Fix SPE floating point environment manipulation

Fix multiple problems in the powerpcspe floating point code.

* Endianness handling of the SPEFSCR in fenv.h was completely broken.
* Ensure SPEFSCR synchronization requirements are being met.

The __r.__d -> __r transformations were written by jhibbits.

Reviewed by: jhibbits
Differential Revision: https://reviews.freebsd.org/D22526

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lib: further adoption of SPDX licensing ID tags.

Mainly focus on files that use BSD 2-Clause license, however the tool I
was using mis-identified many licenses so this was mostly a manual - error
pr

lib: further adoption of SPDX licensing ID tags.

Mainly focus on files that use BSD 2-Clause license, however the tool I
was using mis-identified many licenses so this was mostly a manual - error
prone - task.

The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.

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Merge ^/head r307736 through r308146.

Create a new MACHINE_ARCH for Freescale PowerPC e500v2

Summary:
The Freescale e500v2 PowerPC core does not use a standard FPU.
Instead, it uses a Signal Processing Engine (SPE)--a DSP-style vector p

Create a new MACHINE_ARCH for Freescale PowerPC e500v2

Summary:
The Freescale e500v2 PowerPC core does not use a standard FPU.
Instead, it uses a Signal Processing Engine (SPE)--a DSP-style vector processor
unit, which doubles as a FPU. The PowerPC SPE ABI is incompatible with the
stock powerpc ABI, so a new MACHINE_ARCH was created to deal with this.
Additionaly, the SPE opcodes overlap with Altivec, so these are mutually
exclusive. Taking advantage of this fact, a new file, powerpc/booke/spe.c, was
created with the same function set as in powerpc/powerpc/altivec.c, so it
becomes effectively a drop-in replacement. setjmp/longjmp were modified to save
the upper 32-bits of the now-64-bit GPRs (upper 32-bits are only accessible by
the SPE).

Note: This does _not_ support the SPE in the e500v1, as the e500v1 SPE does not
support double-precision floating point.

Also, without a new MACHINE_ARCH it would be impossible to provide binary
packages which utilize the SPE.

Additionally, no work has been done to support ports, work is needed for this.
This also means no newer gcc can yet be used. However, gcc's powerpc support
has been refactored which would make adding a powerpcspe-freebsd target very
easy.

Test Plan:
This was lightly tested on a RouterBoard RB800 and an AmigaOne A1222
(P1022-based) board, compiled against the new ABI. Base system utilities
(/bin/sh, /bin/ls, etc) still function appropriately, the system is able to boot
multiuser.

Reviewed By: bdrewery, imp
Relnotes: yes
Differential Revision: https://reviews.freebsd.org/D5683

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Merge ^/head r296007 through r296368.

MFH

Sponsored by: The FreeBSD Foundation

Make FPSCR definition endian clean.

PR: 207526
Submitted by: Simon Byrne
Obtained from: Julia
MFC after: 1 month

IFC @230489 (pending review).

IFC @ r226824

Provide external definitions of all of the standardized functions in
fenv.h that are currently inlined.

The definitions are provided in fenv.c via 'extern inline'
declaractions. This assumes the co

Provide external definitions of all of the standardized functions in
fenv.h that are currently inlined.

The definitions are provided in fenv.c via 'extern inline'
declaractions. This assumes the compiler handles 'extern inline' as
specified in C99, which has been true under FreeBSD since 8.0.

The goal is to eventually remove the 'static' keyword from the inline
definitions in fenv.h, so that non-inlined references all wind up
pointing to the same external definition like they're supposed to.
I am deferring the second step to provide a window where
newly-compiled apps will still link against old math libraries.
(This isn't supported, but there's no need to cause undue breakage.)

Reviewed by: stefanf, bde

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Let PowerPC world optionally build with -msoft-float. For FPU-less PowerPC
variations (e500 currently), this provides a gcc-level FPU emulation and is an
alternative approach to the recently introduc

Let PowerPC world optionally build with -msoft-float. For FPU-less PowerPC
variations (e500 currently), this provides a gcc-level FPU emulation and is an
alternative approach to the recently introduced kernel-level emulation
(FPU_EMU).

Approved by: cognet (mentor)
MFp4: e500

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Replace fegetmask() and fesetmask() with feenableexcept(),
fedisableexcept(), and fegetexcept(). These two sets of routines
provide the same functionality. I implemented the former as an
undocument

Replace fegetmask() and fesetmask() with feenableexcept(),
fedisableexcept(), and fegetexcept(). These two sets of routines
provide the same functionality. I implemented the former as an
undocumented internal interface to make the regression test easier to
write. However, fe(enable|disable|get)except() is already part of
glibc, and I would like to avoid gratuitous differences. The only
major flaw in the glibc API is that there's no good way to report
errors on processors that don't support all the unmasked exceptions.

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Mark all inline asms that read the floating-point control or status
registers as volatile. Instructions that *wrote* to FP state were
already marked volatile, but apparently gcc has license to move

Mark all inline asms that read the floating-point control or status
registers as volatile. Instructions that *wrote* to FP state were
already marked volatile, but apparently gcc has license to move
non-volatile asms past volatile asms. This broke amd64's feupdateenv
at -O2 due to a WAR conflict between fnstsw and fldenv there.

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Add an fenv.h implementation for the powerpc port.

Reviewed by: standards@

Let PowerPC world optionally build with -msoft-float. For FPU-less PowerPC
variations (e500 currently), this provides a gcc-level FPU emulation and is an
alternative approach to the recently introduc

Let PowerPC world optionally build with -msoft-float. For FPU-less PowerPC
variations (e500 currently), this provides a gcc-level FPU emulation and is an
alternative approach to the recently introduced kernel-level emulation
(FPU_EMU).

Approved by: cognet (mentor)
MFp4: e500

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Replace fegetmask() and fesetmask() with feenableexcept(),
fedisableexcept(), and fegetexcept(). These two sets of routines
provide the same functionality. I implemented the former as an
undocument

Replace fegetmask() and fesetmask() with feenableexcept(),
fedisableexcept(), and fegetexcept(). These two sets of routines
provide the same functionality. I implemented the former as an
undocumented internal interface to make the regression test easier to
write. However, fe(enable|disable|get)except() is already part of
glibc, and I would like to avoid gratuitous differences. The only
major flaw in the glibc API is that there's no good way to report
errors on processors that don't support all the unmasked exceptions.

show more ...

Mark all inline asms that read the floating-point control or status
registers as volatile. Instructions that *wrote* to FP state were
already marked volatile, but apparently gcc has license to move

Mark all inline asms that read the floating-point control or status
registers as volatile. Instructions that *wrote* to FP state were
already marked volatile, but apparently gcc has license to move
non-volatile asms past volatile asms. This broke amd64's feupdateenv
at -O2 due to a WAR conflict between fnstsw and fldenv there.

show more ...

Add an fenv.h implementation for the powerpc port.

Reviewed by: standards@