1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/rwlock.h> 41 #include <sys/sx.h> 42 #include <vm/uma.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <machine/bus.h> 47 #include <sys/socket.h> 48 #include <sys/sysctl.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_media.h> 53 #include <netinet/in.h> 54 #include <netinet/tcp_lro.h> 55 56 #include "offload.h" 57 #include "t4_ioctl.h" 58 #include "common/t4_msg.h" 59 #include "firmware/t4fw_interface.h" 60 61 #define KTR_CXGBE KTR_SPARE3 62 MALLOC_DECLARE(M_CXGBE); 63 #define CXGBE_UNIMPLEMENTED(s) \ 64 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 65 66 #if defined(__i386__) || defined(__amd64__) 67 static __inline void 68 prefetch(void *x) 69 { 70 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 71 } 72 #else 73 #define prefetch(x) 74 #endif 75 76 #ifndef SYSCTL_ADD_UQUAD 77 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 78 #define sysctl_handle_64 sysctl_handle_quad 79 #define CTLTYPE_U64 CTLTYPE_QUAD 80 #endif 81 82 #if (__FreeBSD_version >= 900030) || \ 83 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 84 #define SBUF_DRAIN 1 85 #endif 86 87 struct adapter; 88 typedef struct adapter adapter_t; 89 90 enum { 91 /* 92 * All ingress queues use this entry size. Note that the firmware event 93 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 94 * be at least 64. 95 */ 96 IQ_ESIZE = 64, 97 98 /* Default queue sizes for all kinds of ingress queues */ 99 FW_IQ_QSIZE = 256, 100 RX_IQ_QSIZE = 1024, 101 102 /* All egress queues use this entry size */ 103 EQ_ESIZE = 64, 104 105 /* Default queue sizes for all kinds of egress queues */ 106 CTRL_EQ_QSIZE = 128, 107 TX_EQ_QSIZE = 1024, 108 109 #if MJUMPAGESIZE != MCLBYTES 110 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 111 #else 112 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 113 #endif 114 CL_METADATA_SIZE = CACHE_LINE_SIZE, 115 116 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 117 TX_SGL_SEGS = 39, 118 TX_SGL_SEGS_TSO = 38, 119 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 120 }; 121 122 enum { 123 /* adapter intr_type */ 124 INTR_INTX = (1 << 0), 125 INTR_MSI = (1 << 1), 126 INTR_MSIX = (1 << 2) 127 }; 128 129 enum { 130 XGMAC_MTU = (1 << 0), 131 XGMAC_PROMISC = (1 << 1), 132 XGMAC_ALLMULTI = (1 << 2), 133 XGMAC_VLANEX = (1 << 3), 134 XGMAC_UCADDR = (1 << 4), 135 XGMAC_MCADDRS = (1 << 5), 136 137 XGMAC_ALL = 0xffff 138 }; 139 140 enum { 141 /* flags understood by begin_synchronized_op */ 142 HOLD_LOCK = (1 << 0), 143 SLEEP_OK = (1 << 1), 144 INTR_OK = (1 << 2), 145 146 /* flags understood by end_synchronized_op */ 147 LOCK_HELD = HOLD_LOCK, 148 }; 149 150 enum { 151 /* adapter flags */ 152 FULL_INIT_DONE = (1 << 0), 153 FW_OK = (1 << 1), 154 /* INTR_DIRECT = (1 << 2), No longer used. */ 155 MASTER_PF = (1 << 3), 156 ADAP_SYSCTL_CTX = (1 << 4), 157 /* TOM_INIT_DONE= (1 << 5), No longer used */ 158 BUF_PACKING_OK = (1 << 6), 159 IS_VF = (1 << 7), 160 161 CXGBE_BUSY = (1 << 9), 162 163 /* port flags */ 164 HAS_TRACEQ = (1 << 3), 165 166 /* VI flags */ 167 DOOMED = (1 << 0), 168 VI_INIT_DONE = (1 << 1), 169 VI_SYSCTL_CTX = (1 << 2), 170 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */ 171 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */ 172 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ), 173 174 /* adapter debug_flags */ 175 DF_DUMP_MBOX = (1 << 0), 176 }; 177 178 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 179 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 180 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 181 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 182 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 183 184 struct vi_info { 185 device_t dev; 186 struct port_info *pi; 187 188 struct ifnet *ifp; 189 struct ifmedia media; 190 191 unsigned long flags; 192 int if_flags; 193 194 uint16_t *rss, *nm_rss; 195 int smt_idx; /* for convenience */ 196 uint16_t viid; 197 int16_t xact_addr_filt;/* index of exact MAC address filter */ 198 uint16_t rss_size; /* size of VI's RSS table slice */ 199 uint16_t rss_base; /* start of VI's RSS table slice */ 200 201 eventhandler_tag vlan_c; 202 203 int nintr; 204 int first_intr; 205 206 /* These need to be int as they are used in sysctl */ 207 int ntxq; /* # of tx queues */ 208 int first_txq; /* index of first tx queue */ 209 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 210 int nrxq; /* # of rx queues */ 211 int first_rxq; /* index of first rx queue */ 212 int nofldtxq; /* # of offload tx queues */ 213 int first_ofld_txq; /* index of first offload tx queue */ 214 int nofldrxq; /* # of offload rx queues */ 215 int first_ofld_rxq; /* index of first offload rx queue */ 216 int nnmtxq; 217 int first_nm_txq; 218 int nnmrxq; 219 int first_nm_rxq; 220 int tmr_idx; 221 int pktc_idx; 222 int qsize_rxq; 223 int qsize_txq; 224 225 struct timeval last_refreshed; 226 struct fw_vi_stats_vf stats; 227 228 struct callout tick; 229 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 230 231 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 232 }; 233 234 struct tx_ch_rl_params { 235 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 236 uint32_t maxrate; 237 }; 238 239 enum { 240 TX_CLRL_REFRESH = (1 << 0), /* Need to update hardware state. */ 241 TX_CLRL_ERROR = (1 << 1), /* Error, hardware state unknown. */ 242 }; 243 244 struct tx_cl_rl_params { 245 int refcount; 246 u_int flags; 247 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 248 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 249 enum fw_sched_params_mode mode; /* aggr or per-flow */ 250 uint32_t maxrate; 251 uint16_t pktsize; 252 }; 253 254 /* Tx scheduler parameters for a channel/port */ 255 struct tx_sched_params { 256 /* Channel Rate Limiter */ 257 struct tx_ch_rl_params ch_rl; 258 259 /* Class WRR */ 260 /* XXX */ 261 262 /* Class Rate Limiter */ 263 struct tx_cl_rl_params cl_rl[]; 264 }; 265 266 struct port_info { 267 device_t dev; 268 struct adapter *adapter; 269 270 struct vi_info *vi; 271 int nvi; 272 int up_vis; 273 int uld_vis; 274 275 struct tx_sched_params *sched_params; 276 277 struct mtx pi_lock; 278 char lockname[16]; 279 unsigned long flags; 280 281 uint8_t lport; /* associated offload logical port */ 282 int8_t mdio_addr; 283 uint8_t port_type; 284 uint8_t mod_type; 285 uint8_t port_id; 286 uint8_t tx_chan; 287 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 288 289 struct link_config link_cfg; 290 struct link_config old_link_cfg; 291 292 struct timeval last_refreshed; 293 struct port_stats stats; 294 u_int tnl_cong_drops; 295 u_int tx_parse_error; 296 297 struct callout tick; 298 }; 299 300 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 301 302 /* Where the cluster came from, how it has been carved up. */ 303 struct cluster_layout { 304 int8_t zidx; 305 int8_t hwidx; 306 uint16_t region1; /* mbufs laid out within this region */ 307 /* region2 is the DMA region */ 308 uint16_t region3; /* cluster_metadata within this region */ 309 }; 310 311 struct cluster_metadata { 312 u_int refcount; 313 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 314 }; 315 316 struct fl_sdesc { 317 caddr_t cl; 318 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 319 struct cluster_layout cll; 320 }; 321 322 struct tx_desc { 323 __be64 flit[8]; 324 }; 325 326 struct tx_sdesc { 327 struct mbuf *m; /* m_nextpkt linked chain of frames */ 328 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 329 }; 330 331 332 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 333 struct iq_desc { 334 struct rss_header rss; 335 uint8_t cpl[IQ_PAD]; 336 struct rsp_ctrl rsp; 337 }; 338 #undef IQ_PAD 339 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 340 341 enum { 342 /* iq flags */ 343 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 344 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 345 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 346 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 347 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 348 349 /* iq state */ 350 IQS_DISABLED = 0, 351 IQS_BUSY = 1, 352 IQS_IDLE = 2, 353 354 /* netmap related flags */ 355 NM_OFF = 0, 356 NM_ON = 1, 357 NM_BUSY = 2, 358 }; 359 360 struct sge_iq; 361 struct rss_header; 362 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 363 struct mbuf *); 364 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 365 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 366 367 /* 368 * Ingress Queue: T4 is producer, driver is consumer. 369 */ 370 struct sge_iq { 371 uint32_t flags; 372 volatile int state; 373 struct adapter *adapter; 374 cpl_handler_t set_tcb_rpl; 375 cpl_handler_t l2t_write_rpl; 376 struct iq_desc *desc; /* KVA of descriptor ring */ 377 int8_t intr_pktc_idx; /* packet count threshold index */ 378 uint8_t gen; /* generation bit */ 379 uint8_t intr_params; /* interrupt holdoff parameters */ 380 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 381 uint16_t qsize; /* size (# of entries) of the queue */ 382 uint16_t sidx; /* index of the entry with the status page */ 383 uint16_t cidx; /* consumer index */ 384 uint16_t cntxt_id; /* SGE context id for the iq */ 385 uint16_t abs_id; /* absolute SGE id for the iq */ 386 387 STAILQ_ENTRY(sge_iq) link; 388 389 bus_dma_tag_t desc_tag; 390 bus_dmamap_t desc_map; 391 bus_addr_t ba; /* bus address of descriptor ring */ 392 }; 393 394 enum { 395 EQ_CTRL = 1, 396 EQ_ETH = 2, 397 EQ_OFLD = 3, 398 399 /* eq flags */ 400 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 401 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 402 EQ_ENABLED = (1 << 3), /* open for business */ 403 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 404 }; 405 406 /* Listed in order of preference. Update t4_sysctls too if you change these */ 407 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 408 409 /* 410 * Egress Queue: driver is producer, T4 is consumer. 411 * 412 * Note: A free list is an egress queue (driver produces the buffers and T4 413 * consumes them) but it's special enough to have its own struct (see sge_fl). 414 */ 415 struct sge_eq { 416 unsigned int flags; /* MUST be first */ 417 unsigned int cntxt_id; /* SGE context id for the eq */ 418 unsigned int abs_id; /* absolute SGE id for the eq */ 419 struct mtx eq_lock; 420 421 struct tx_desc *desc; /* KVA of descriptor ring */ 422 uint16_t doorbells; 423 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 424 u_int udb_qid; /* relative qid within the doorbell page */ 425 uint16_t sidx; /* index of the entry with the status page */ 426 uint16_t cidx; /* consumer idx (desc idx) */ 427 uint16_t pidx; /* producer idx (desc idx) */ 428 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 429 uint16_t dbidx; /* pidx of the most recent doorbell */ 430 uint16_t iqid; /* iq that gets egr_update for the eq */ 431 uint8_t tx_chan; /* tx channel used by the eq */ 432 volatile u_int equiq; /* EQUIQ outstanding */ 433 434 bus_dma_tag_t desc_tag; 435 bus_dmamap_t desc_map; 436 bus_addr_t ba; /* bus address of descriptor ring */ 437 char lockname[16]; 438 }; 439 440 struct sw_zone_info { 441 uma_zone_t zone; /* zone that this cluster comes from */ 442 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 443 int type; /* EXT_xxx type of the cluster */ 444 int8_t head_hwidx; 445 int8_t tail_hwidx; 446 }; 447 448 struct hw_buf_info { 449 int8_t zidx; /* backpointer to zone; -ve means unused */ 450 int8_t next; /* next hwidx for this zone; -1 means no more */ 451 int size; 452 }; 453 454 enum { 455 NUM_MEMWIN = 3, 456 457 MEMWIN0_APERTURE = 2048, 458 MEMWIN0_BASE = 0x1b800, 459 460 MEMWIN1_APERTURE = 32768, 461 MEMWIN1_BASE = 0x28000, 462 463 MEMWIN2_APERTURE_T4 = 65536, 464 MEMWIN2_BASE_T4 = 0x30000, 465 466 MEMWIN2_APERTURE_T5 = 128 * 1024, 467 MEMWIN2_BASE_T5 = 0x60000, 468 }; 469 470 struct memwin { 471 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 472 uint32_t mw_base; /* constant after setup_memwin */ 473 uint32_t mw_aperture; /* ditto */ 474 uint32_t mw_curpos; /* protected by mw_lock */ 475 }; 476 477 enum { 478 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 479 FL_DOOMED = (1 << 1), /* about to be destroyed */ 480 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 481 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 482 }; 483 484 #define FL_RUNNING_LOW(fl) \ 485 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 486 #define FL_NOT_RUNNING_LOW(fl) \ 487 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 488 489 struct sge_fl { 490 struct mtx fl_lock; 491 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 492 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 493 struct cluster_layout cll_def; /* default refill zone, layout */ 494 uint16_t lowat; /* # of buffers <= this means fl needs help */ 495 int flags; 496 uint16_t buf_boundary; 497 498 /* The 16b idx all deal with hw descriptors */ 499 uint16_t dbidx; /* hw pidx after last doorbell */ 500 uint16_t sidx; /* index of status page */ 501 volatile uint16_t hw_cidx; 502 503 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 504 uint32_t cidx; /* consumer index */ 505 uint32_t pidx; /* producer index */ 506 507 uint32_t dbval; 508 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 509 volatile uint32_t *udb; 510 511 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 512 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 513 uint64_t cl_allocated; /* # of clusters allocated */ 514 uint64_t cl_recycled; /* # of clusters recycled */ 515 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 516 517 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 518 struct mbuf *m0; 519 struct mbuf **pnext; 520 u_int remaining; 521 522 uint16_t qsize; /* # of hw descriptors (status page included) */ 523 uint16_t cntxt_id; /* SGE context id for the freelist */ 524 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 525 bus_dma_tag_t desc_tag; 526 bus_dmamap_t desc_map; 527 char lockname[16]; 528 bus_addr_t ba; /* bus address of descriptor ring */ 529 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 530 }; 531 532 struct mp_ring; 533 534 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 535 struct sge_txq { 536 struct sge_eq eq; /* MUST be first */ 537 538 struct ifnet *ifp; /* the interface this txq belongs to */ 539 struct mp_ring *r; /* tx software ring */ 540 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 541 struct sglist *gl; 542 __be32 cpl_ctrl0; /* for convenience */ 543 int tc_idx; /* traffic class */ 544 545 struct task tx_reclaim_task; 546 /* stats for common events first */ 547 548 uint64_t txcsum; /* # of times hardware assisted with checksum */ 549 uint64_t tso_wrs; /* # of TSO work requests */ 550 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 551 uint64_t imm_wrs; /* # of work requests with immediate data */ 552 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 553 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 554 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 555 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 556 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 557 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 558 559 /* stats for not-that-common events */ 560 } __aligned(CACHE_LINE_SIZE); 561 562 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 563 struct sge_rxq { 564 struct sge_iq iq; /* MUST be first */ 565 struct sge_fl fl; /* MUST follow iq */ 566 567 struct ifnet *ifp; /* the interface this rxq belongs to */ 568 #if defined(INET) || defined(INET6) 569 struct lro_ctrl lro; /* LRO state */ 570 #endif 571 572 /* stats for common events first */ 573 574 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 575 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 576 577 /* stats for not-that-common events */ 578 579 } __aligned(CACHE_LINE_SIZE); 580 581 static inline struct sge_rxq * 582 iq_to_rxq(struct sge_iq *iq) 583 { 584 585 return (__containerof(iq, struct sge_rxq, iq)); 586 } 587 588 589 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 590 struct sge_ofld_rxq { 591 struct sge_iq iq; /* MUST be first */ 592 struct sge_fl fl; /* MUST follow iq */ 593 } __aligned(CACHE_LINE_SIZE); 594 595 static inline struct sge_ofld_rxq * 596 iq_to_ofld_rxq(struct sge_iq *iq) 597 { 598 599 return (__containerof(iq, struct sge_ofld_rxq, iq)); 600 } 601 602 struct wrqe { 603 STAILQ_ENTRY(wrqe) link; 604 struct sge_wrq *wrq; 605 int wr_len; 606 char wr[] __aligned(16); 607 }; 608 609 struct wrq_cookie { 610 TAILQ_ENTRY(wrq_cookie) link; 611 int ndesc; 612 int pidx; 613 }; 614 615 /* 616 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 617 * and offload tx queues are of this type. 618 */ 619 struct sge_wrq { 620 struct sge_eq eq; /* MUST be first */ 621 622 struct adapter *adapter; 623 struct task wrq_tx_task; 624 625 /* Tx desc reserved but WR not "committed" yet. */ 626 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 627 628 /* List of WRs ready to go out as soon as descriptors are available. */ 629 STAILQ_HEAD(, wrqe) wr_list; 630 u_int nwr_pending; 631 u_int ndesc_needed; 632 633 /* stats for common events first */ 634 635 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 636 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 637 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 638 639 /* stats for not-that-common events */ 640 641 /* 642 * Scratch space for work requests that wrap around after reaching the 643 * status page, and some information about the last WR that used it. 644 */ 645 uint16_t ss_pidx; 646 uint16_t ss_len; 647 uint8_t ss[SGE_MAX_WR_LEN]; 648 649 } __aligned(CACHE_LINE_SIZE); 650 651 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 652 struct sge_nm_rxq { 653 struct vi_info *vi; 654 655 struct iq_desc *iq_desc; 656 uint16_t iq_abs_id; 657 uint16_t iq_cntxt_id; 658 uint16_t iq_cidx; 659 uint16_t iq_sidx; 660 uint8_t iq_gen; 661 662 __be64 *fl_desc; 663 uint16_t fl_cntxt_id; 664 uint32_t fl_cidx; 665 uint32_t fl_pidx; 666 uint32_t fl_sidx; 667 uint32_t fl_db_val; 668 u_int fl_hwidx:4; 669 670 u_int nid; /* netmap ring # for this queue */ 671 672 /* infrequently used items after this */ 673 674 bus_dma_tag_t iq_desc_tag; 675 bus_dmamap_t iq_desc_map; 676 bus_addr_t iq_ba; 677 int intr_idx; 678 679 bus_dma_tag_t fl_desc_tag; 680 bus_dmamap_t fl_desc_map; 681 bus_addr_t fl_ba; 682 } __aligned(CACHE_LINE_SIZE); 683 684 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 685 struct sge_nm_txq { 686 struct tx_desc *desc; 687 uint16_t cidx; 688 uint16_t pidx; 689 uint16_t sidx; 690 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 691 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 692 uint16_t dbidx; /* pidx of the most recent doorbell */ 693 uint16_t doorbells; 694 volatile uint32_t *udb; 695 u_int udb_qid; 696 u_int cntxt_id; 697 __be32 cpl_ctrl0; /* for convenience */ 698 u_int nid; /* netmap ring # for this queue */ 699 700 /* infrequently used items after this */ 701 702 bus_dma_tag_t desc_tag; 703 bus_dmamap_t desc_map; 704 bus_addr_t ba; 705 int iqidx; 706 } __aligned(CACHE_LINE_SIZE); 707 708 struct sge { 709 int nrxq; /* total # of Ethernet rx queues */ 710 int ntxq; /* total # of Ethernet tx queues */ 711 int nofldrxq; /* total # of TOE rx queues */ 712 int nofldtxq; /* total # of TOE tx queues */ 713 int nnmrxq; /* total # of netmap rx queues */ 714 int nnmtxq; /* total # of netmap tx queues */ 715 int niq; /* total # of ingress queues */ 716 int neq; /* total # of egress queues */ 717 718 struct sge_iq fwq; /* Firmware event queue */ 719 struct sge_wrq mgmtq; /* Management queue (control queue) */ 720 struct sge_wrq *ctrlq; /* Control queues */ 721 struct sge_txq *txq; /* NIC tx queues */ 722 struct sge_rxq *rxq; /* NIC rx queues */ 723 struct sge_wrq *ofld_txq; /* TOE tx queues */ 724 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 725 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 726 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 727 728 uint16_t iq_start; /* first cntxt_id */ 729 uint16_t iq_base; /* first abs_id */ 730 int eq_start; /* first cntxt_id */ 731 int eq_base; /* first abs_id */ 732 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 733 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 734 735 int8_t safe_hwidx1; /* may not have room for metadata */ 736 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 737 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 738 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 739 }; 740 741 struct devnames { 742 const char *nexus_name; 743 const char *ifnet_name; 744 const char *vi_ifnet_name; 745 const char *pf03_drv_name; 746 const char *vf_nexus_name; 747 const char *vf_ifnet_name; 748 }; 749 750 struct adapter { 751 SLIST_ENTRY(adapter) link; 752 device_t dev; 753 struct cdev *cdev; 754 const struct devnames *names; 755 756 /* PCIe register resources */ 757 int regs_rid; 758 struct resource *regs_res; 759 int msix_rid; 760 struct resource *msix_res; 761 bus_space_handle_t bh; 762 bus_space_tag_t bt; 763 bus_size_t mmio_len; 764 int udbs_rid; 765 struct resource *udbs_res; 766 volatile uint8_t *udbs_base; 767 768 unsigned int pf; 769 unsigned int mbox; 770 unsigned int vpd_busy; 771 unsigned int vpd_flag; 772 773 /* Interrupt information */ 774 int intr_type; 775 int intr_count; 776 struct irq { 777 struct resource *res; 778 int rid; 779 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 780 void *tag; 781 struct sge_rxq *rxq; 782 struct sge_nm_rxq *nm_rxq; 783 } __aligned(CACHE_LINE_SIZE) *irq; 784 int sge_gts_reg; 785 int sge_kdoorbell_reg; 786 787 bus_dma_tag_t dmat; /* Parent DMA tag */ 788 789 struct sge sge; 790 int lro_timeout; 791 int sc_do_rxcopy; 792 793 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 794 struct port_info *port[MAX_NPORTS]; 795 uint8_t chan_map[MAX_NCHAN]; 796 797 void *tom_softc; /* (struct tom_data *) */ 798 struct tom_tunables tt; 799 void *iwarp_softc; /* (struct c4iw_dev *) */ 800 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 801 void *ccr_softc; /* (struct ccr_softc *) */ 802 struct l2t_data *l2t; /* L2 table */ 803 struct tid_info tids; 804 805 uint16_t doorbells; 806 int offload_map; /* ports with IFCAP_TOE enabled */ 807 int active_ulds; /* ULDs activated on this adapter */ 808 int flags; 809 int debug_flags; 810 811 char ifp_lockname[16]; 812 struct mtx ifp_lock; 813 struct ifnet *ifp; /* tracer ifp */ 814 struct ifmedia media; 815 int traceq; /* iq used by all tracers, -1 if none */ 816 int tracer_valid; /* bitmap of valid tracers */ 817 int tracer_enabled; /* bitmap of enabled tracers */ 818 819 char fw_version[16]; 820 char tp_version[16]; 821 char er_version[16]; 822 char bs_version[16]; 823 char cfg_file[32]; 824 u_int cfcsum; 825 struct adapter_params params; 826 const struct chip_params *chip_params; 827 struct t4_virt_res vres; 828 829 uint16_t nbmcaps; 830 uint16_t linkcaps; 831 uint16_t switchcaps; 832 uint16_t niccaps; 833 uint16_t toecaps; 834 uint16_t rdmacaps; 835 uint16_t cryptocaps; 836 uint16_t iscsicaps; 837 uint16_t fcoecaps; 838 839 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 840 841 struct mtx sc_lock; 842 char lockname[16]; 843 844 /* Starving free lists */ 845 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 846 TAILQ_HEAD(, sge_fl) sfl; 847 struct callout sfl_callout; 848 849 struct mtx reg_lock; /* for indirect register access */ 850 851 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 852 853 struct mtx tc_lock; 854 struct task tc_task; 855 856 const char *last_op; 857 const void *last_op_thr; 858 int last_op_flags; 859 }; 860 861 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 862 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 863 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 864 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 865 866 #define ASSERT_SYNCHRONIZED_OP(sc) \ 867 KASSERT(IS_BUSY(sc) && \ 868 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 869 ("%s: operation not synchronized.", __func__)) 870 871 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 872 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 873 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 874 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 875 876 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 877 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 878 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 879 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 880 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 881 882 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 883 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 884 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 885 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 886 887 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 888 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 889 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 890 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 891 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 892 893 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 894 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 895 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 896 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 897 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 898 899 #define CH_DUMP_MBOX(sc, mbox, data_reg) \ 900 do { \ 901 if (sc->debug_flags & DF_DUMP_MBOX) { \ 902 log(LOG_NOTICE, \ 903 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 904 "%016llx %016llx %016llx %016llx\n", \ 905 device_get_nameunit(sc->dev), mbox, \ 906 (unsigned long long)t4_read_reg64(sc, data_reg), \ 907 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 908 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 909 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 910 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 911 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 912 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 913 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 914 } \ 915 } while (0) 916 917 #define for_each_txq(vi, iter, q) \ 918 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 919 iter < vi->ntxq; ++iter, ++q) 920 #define for_each_rxq(vi, iter, q) \ 921 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 922 iter < vi->nrxq; ++iter, ++q) 923 #define for_each_ofld_txq(vi, iter, q) \ 924 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 925 iter < vi->nofldtxq; ++iter, ++q) 926 #define for_each_ofld_rxq(vi, iter, q) \ 927 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 928 iter < vi->nofldrxq; ++iter, ++q) 929 #define for_each_nm_txq(vi, iter, q) \ 930 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 931 iter < vi->nnmtxq; ++iter, ++q) 932 #define for_each_nm_rxq(vi, iter, q) \ 933 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 934 iter < vi->nnmrxq; ++iter, ++q) 935 #define for_each_vi(_pi, _iter, _vi) \ 936 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 937 ++(_iter), ++(_vi)) 938 939 #define IDXINCR(idx, incr, wrap) do { \ 940 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 941 } while (0) 942 #define IDXDIFF(head, tail, wrap) \ 943 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 944 945 /* One for errors, one for firmware events */ 946 #define T4_EXTRA_INTR 2 947 948 /* One for firmware events */ 949 #define T4VF_EXTRA_INTR 1 950 951 static inline uint32_t 952 t4_read_reg(struct adapter *sc, uint32_t reg) 953 { 954 955 return bus_space_read_4(sc->bt, sc->bh, reg); 956 } 957 958 static inline void 959 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 960 { 961 962 bus_space_write_4(sc->bt, sc->bh, reg, val); 963 } 964 965 static inline uint64_t 966 t4_read_reg64(struct adapter *sc, uint32_t reg) 967 { 968 969 #ifdef __LP64__ 970 return bus_space_read_8(sc->bt, sc->bh, reg); 971 #else 972 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 973 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 974 975 #endif 976 } 977 978 static inline void 979 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 980 { 981 982 #ifdef __LP64__ 983 bus_space_write_8(sc->bt, sc->bh, reg, val); 984 #else 985 bus_space_write_4(sc->bt, sc->bh, reg, val); 986 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 987 #endif 988 } 989 990 static inline void 991 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 992 { 993 994 *val = pci_read_config(sc->dev, reg, 1); 995 } 996 997 static inline void 998 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 999 { 1000 1001 pci_write_config(sc->dev, reg, val, 1); 1002 } 1003 1004 static inline void 1005 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1006 { 1007 1008 *val = pci_read_config(sc->dev, reg, 2); 1009 } 1010 1011 static inline void 1012 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1013 { 1014 1015 pci_write_config(sc->dev, reg, val, 2); 1016 } 1017 1018 static inline void 1019 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1020 { 1021 1022 *val = pci_read_config(sc->dev, reg, 4); 1023 } 1024 1025 static inline void 1026 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1027 { 1028 1029 pci_write_config(sc->dev, reg, val, 4); 1030 } 1031 1032 static inline struct port_info * 1033 adap2pinfo(struct adapter *sc, int idx) 1034 { 1035 1036 return (sc->port[idx]); 1037 } 1038 1039 static inline void 1040 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1041 { 1042 1043 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1044 } 1045 1046 static inline bool 1047 is_10G_port(const struct port_info *pi) 1048 { 1049 1050 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 1051 } 1052 1053 static inline bool 1054 is_25G_port(const struct port_info *pi) 1055 { 1056 1057 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0); 1058 } 1059 1060 static inline bool 1061 is_40G_port(const struct port_info *pi) 1062 { 1063 1064 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 1065 } 1066 1067 static inline bool 1068 is_100G_port(const struct port_info *pi) 1069 { 1070 1071 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0); 1072 } 1073 1074 static inline int 1075 port_top_speed(const struct port_info *pi) 1076 { 1077 1078 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) 1079 return (100); 1080 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 1081 return (40); 1082 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) 1083 return (25); 1084 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 1085 return (10); 1086 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 1087 return (1); 1088 1089 return (0); 1090 } 1091 1092 static inline int 1093 tx_resume_threshold(struct sge_eq *eq) 1094 { 1095 1096 /* not quite the same as qsize / 4, but this will do. */ 1097 return (eq->sidx / 4); 1098 } 1099 1100 static inline int 1101 t4_use_ldst(struct adapter *sc) 1102 { 1103 1104 #ifdef notyet 1105 return (sc->flags & FW_OK || !sc->use_bd); 1106 #else 1107 return (0); 1108 #endif 1109 } 1110 1111 /* t4_main.c */ 1112 extern int t4_ntxq10g; 1113 extern int t4_nrxq10g; 1114 extern int t4_ntxq1g; 1115 extern int t4_nrxq1g; 1116 extern int t4_intr_types; 1117 extern int t4_tmr_idx_10g; 1118 extern int t4_pktc_idx_10g; 1119 extern int t4_tmr_idx_1g; 1120 extern int t4_pktc_idx_1g; 1121 extern unsigned int t4_qsize_rxq; 1122 extern unsigned int t4_qsize_txq; 1123 extern device_method_t cxgbe_methods[]; 1124 1125 int t4_os_find_pci_capability(struct adapter *, int); 1126 int t4_os_pci_save_state(struct adapter *); 1127 int t4_os_pci_restore_state(struct adapter *); 1128 void t4_os_portmod_changed(struct port_info *); 1129 void t4_os_link_changed(struct port_info *); 1130 void t4_iterate(void (*)(struct adapter *, void *), void *); 1131 void t4_init_devnames(struct adapter *); 1132 void t4_add_adapter(struct adapter *); 1133 int t4_detach_common(device_t); 1134 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1135 int t4_map_bars_0_and_4(struct adapter *); 1136 int t4_map_bar_2(struct adapter *); 1137 int t4_setup_intr_handlers(struct adapter *); 1138 void t4_sysctls(struct adapter *); 1139 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1140 void doom_vi(struct adapter *, struct vi_info *); 1141 void end_synchronized_op(struct adapter *, int); 1142 int update_mac_settings(struct ifnet *, int); 1143 int adapter_full_init(struct adapter *); 1144 int adapter_full_uninit(struct adapter *); 1145 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1146 int vi_full_init(struct vi_info *); 1147 int vi_full_uninit(struct vi_info *); 1148 void vi_sysctls(struct vi_info *); 1149 void vi_tick(void *); 1150 1151 #ifdef DEV_NETMAP 1152 /* t4_netmap.c */ 1153 void cxgbe_nm_attach(struct vi_info *); 1154 void cxgbe_nm_detach(struct vi_info *); 1155 void t4_nm_intr(void *); 1156 #endif 1157 1158 /* t4_sge.c */ 1159 void t4_sge_modload(void); 1160 void t4_sge_modunload(void); 1161 uint64_t t4_sge_extfree_refs(void); 1162 void t4_tweak_chip_settings(struct adapter *); 1163 int t4_read_chip_settings(struct adapter *); 1164 int t4_create_dma_tag(struct adapter *); 1165 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1166 struct sysctl_oid_list *); 1167 int t4_destroy_dma_tag(struct adapter *); 1168 int t4_setup_adapter_queues(struct adapter *); 1169 int t4_teardown_adapter_queues(struct adapter *); 1170 int t4_setup_vi_queues(struct vi_info *); 1171 int t4_teardown_vi_queues(struct vi_info *); 1172 void t4_intr_all(void *); 1173 void t4_intr(void *); 1174 void t4_vi_intr(void *); 1175 void t4_intr_err(void *); 1176 void t4_intr_evt(void *); 1177 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1178 void t4_update_fl_bufsize(struct ifnet *); 1179 int parse_pkt(struct adapter *, struct mbuf **); 1180 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1181 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1182 int tnl_cong(struct port_info *, int); 1183 int t4_register_an_handler(an_handler_t); 1184 int t4_register_fw_msg_handler(int, fw_msg_handler_t); 1185 int t4_register_cpl_handler(int, cpl_handler_t); 1186 1187 /* t4_tracer.c */ 1188 struct t4_tracer; 1189 void t4_tracer_modload(void); 1190 void t4_tracer_modunload(void); 1191 void t4_tracer_port_detach(struct adapter *); 1192 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1193 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1194 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1195 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1196 1197 /* t4_sched.c */ 1198 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1199 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1200 int t4_init_tx_sched(struct adapter *); 1201 int t4_free_tx_sched(struct adapter *); 1202 void t4_update_tx_sched(struct adapter *); 1203 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1204 void t4_release_cl_rl_kbps(struct adapter *, int, int); 1205 1206 static inline struct wrqe * 1207 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1208 { 1209 int len = offsetof(struct wrqe, wr) + wr_len; 1210 struct wrqe *wr; 1211 1212 wr = malloc(len, M_CXGBE, M_NOWAIT); 1213 if (__predict_false(wr == NULL)) 1214 return (NULL); 1215 wr->wr_len = wr_len; 1216 wr->wrq = wrq; 1217 return (wr); 1218 } 1219 1220 static inline void * 1221 wrtod(struct wrqe *wr) 1222 { 1223 return (&wr->wr[0]); 1224 } 1225 1226 static inline void 1227 free_wrqe(struct wrqe *wr) 1228 { 1229 free(wr, M_CXGBE); 1230 } 1231 1232 static inline void 1233 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1234 { 1235 struct sge_wrq *wrq = wr->wrq; 1236 1237 TXQ_LOCK(wrq); 1238 t4_wrq_tx_locked(sc, wrq, wr); 1239 TXQ_UNLOCK(wrq); 1240 } 1241 1242 #endif 1243