1 /* 2 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include "opt_inet.h" 36 37 #ifdef TCP_OFFLOAD 38 #include <sys/types.h> 39 #include <sys/malloc.h> 40 #include <sys/socket.h> 41 #include <sys/socketvar.h> 42 #include <sys/sockio.h> 43 #include <sys/taskqueue.h> 44 #include <netinet/in.h> 45 #include <net/route.h> 46 47 #include <netinet/in_systm.h> 48 #include <netinet/in_pcb.h> 49 #include <netinet/ip.h> 50 #include <netinet/ip_var.h> 51 #include <netinet/tcp_var.h> 52 #include <netinet/tcp.h> 53 #include <netinet/tcpip.h> 54 55 #include <netinet/toecore.h> 56 57 struct sge_iq; 58 struct rss_header; 59 struct cpl_set_tcb_rpl; 60 #include <linux/types.h> 61 #include "offload.h" 62 #include "tom/t4_tom.h" 63 64 #include "iw_cxgbe.h" 65 #include "user.h" 66 67 static int creds(struct toepcb *toep, struct inpcb *inp, size_t wrsize); 68 69 70 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state) 71 { 72 unsigned long flag; 73 spin_lock_irqsave(&qhp->lock, flag); 74 qhp->attr.state = state; 75 spin_unlock_irqrestore(&qhp->lock, flag); 76 } 77 78 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 79 { 80 81 contigfree(sq->queue, sq->memsize, M_DEVBUF); 82 } 83 84 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 85 { 86 87 dealloc_host_sq(rdev, sq); 88 } 89 90 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 91 { 92 sq->queue = contigmalloc(sq->memsize, M_DEVBUF, M_NOWAIT, 0ul, ~0ul, 93 4096, 0); 94 95 if (sq->queue) 96 sq->dma_addr = vtophys(sq->queue); 97 else 98 return -ENOMEM; 99 sq->phys_addr = vtophys(sq->queue); 100 pci_unmap_addr_set(sq, mapping, sq->dma_addr); 101 CTR4(KTR_IW_CXGBE, "%s sq %p dma_addr %p phys_addr %p", __func__, 102 sq->queue, sq->dma_addr, sq->phys_addr); 103 return 0; 104 } 105 106 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 107 struct c4iw_dev_ucontext *uctx) 108 { 109 /* 110 * uP clears EQ contexts when the connection exits rdma mode, 111 * so no need to post a RESET WR for these EQs. 112 */ 113 contigfree(wq->rq.queue, wq->rq.memsize, M_DEVBUF); 114 dealloc_sq(rdev, &wq->sq); 115 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 116 kfree(wq->rq.sw_rq); 117 kfree(wq->sq.sw_sq); 118 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 119 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 120 return 0; 121 } 122 123 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 124 struct t4_cq *rcq, struct t4_cq *scq, 125 struct c4iw_dev_ucontext *uctx) 126 { 127 struct adapter *sc = rdev->adap; 128 int user = (uctx != &rdev->uctx); 129 struct fw_ri_res_wr *res_wr; 130 struct fw_ri_res *res; 131 int wr_len; 132 struct c4iw_wr_wait wr_wait; 133 int ret; 134 int eqsize; 135 struct wrqe *wr; 136 const int spg_ndesc = sc->params.sge.spg_len / EQ_ESIZE; 137 138 wq->sq.qid = c4iw_get_qpid(rdev, uctx); 139 if (!wq->sq.qid) 140 return -ENOMEM; 141 142 wq->rq.qid = c4iw_get_qpid(rdev, uctx); 143 if (!wq->rq.qid) 144 goto err1; 145 146 if (!user) { 147 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq, 148 GFP_KERNEL); 149 if (!wq->sq.sw_sq) 150 goto err2; 151 152 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq, 153 GFP_KERNEL); 154 if (!wq->rq.sw_rq) 155 goto err3; 156 } 157 158 /* RQT must be a power of 2. */ 159 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size); 160 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size); 161 if (!wq->rq.rqt_hwaddr) 162 goto err4; 163 164 if (alloc_host_sq(rdev, &wq->sq)) 165 goto err5; 166 167 memset(wq->sq.queue, 0, wq->sq.memsize); 168 pci_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr); 169 170 wq->rq.queue = contigmalloc(wq->rq.memsize, 171 M_DEVBUF, M_NOWAIT, 0ul, ~0ul, 4096, 0); 172 if (wq->rq.queue) 173 wq->rq.dma_addr = vtophys(wq->rq.queue); 174 else 175 goto err6; 176 CTR5(KTR_IW_CXGBE, 177 "%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx", __func__, 178 wq->sq.queue, (unsigned long long)vtophys(wq->sq.queue), 179 wq->rq.queue, (unsigned long long)vtophys(wq->rq.queue)); 180 memset(wq->rq.queue, 0, wq->rq.memsize); 181 pci_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr); 182 183 wq->db = (void *)((unsigned long)rman_get_virtual(sc->regs_res) + 184 sc->sge_kdoorbell_reg); 185 wq->gts = (void *)((unsigned long)rman_get_virtual(rdev->adap->regs_res) 186 + sc->sge_gts_reg); 187 if (user) { 188 wq->sq.udb = (u64)((char*)rman_get_virtual(rdev->adap->udbs_res) + 189 (wq->sq.qid << rdev->qpshift)); 190 wq->sq.udb &= PAGE_MASK; 191 wq->rq.udb = (u64)((char*)rman_get_virtual(rdev->adap->udbs_res) + 192 (wq->rq.qid << rdev->qpshift)); 193 wq->rq.udb &= PAGE_MASK; 194 } 195 wq->rdev = rdev; 196 wq->rq.msn = 1; 197 198 /* build fw_ri_res_wr */ 199 wr_len = sizeof *res_wr + 2 * sizeof *res; 200 201 wr = alloc_wrqe(wr_len, &sc->sge.mgmtq); 202 if (wr == NULL) 203 return (0); 204 res_wr = wrtod(wr); 205 206 memset(res_wr, 0, wr_len); 207 res_wr->op_nres = cpu_to_be32( 208 V_FW_WR_OP(FW_RI_RES_WR) | 209 V_FW_RI_RES_WR_NRES(2) | 210 F_FW_WR_COMPL); 211 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); 212 res_wr->cookie = (unsigned long) &wr_wait; 213 res = res_wr->res; 214 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ; 215 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 216 217 /* eqsize is the number of 64B entries plus the status page size. */ 218 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + spg_ndesc; 219 220 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 221 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ 222 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */ 223 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */ 224 V_FW_RI_RES_WR_IQID(scq->cqid)); 225 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 226 V_FW_RI_RES_WR_DCAEN(0) | 227 V_FW_RI_RES_WR_DCACPU(0) | 228 V_FW_RI_RES_WR_FBMIN(2) | 229 V_FW_RI_RES_WR_FBMAX(2) | 230 V_FW_RI_RES_WR_CIDXFTHRESHO(0) | 231 V_FW_RI_RES_WR_CIDXFTHRESH(0) | 232 V_FW_RI_RES_WR_EQSIZE(eqsize)); 233 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid); 234 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr); 235 res++; 236 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ; 237 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 238 239 /* eqsize is the number of 64B entries plus the status page size. */ 240 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + spg_ndesc; 241 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 242 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ 243 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */ 244 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */ 245 V_FW_RI_RES_WR_IQID(rcq->cqid)); 246 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 247 V_FW_RI_RES_WR_DCAEN(0) | 248 V_FW_RI_RES_WR_DCACPU(0) | 249 V_FW_RI_RES_WR_FBMIN(2) | 250 V_FW_RI_RES_WR_FBMAX(2) | 251 V_FW_RI_RES_WR_CIDXFTHRESHO(0) | 252 V_FW_RI_RES_WR_CIDXFTHRESH(0) | 253 V_FW_RI_RES_WR_EQSIZE(eqsize)); 254 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid); 255 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr); 256 257 c4iw_init_wr_wait(&wr_wait); 258 259 t4_wrq_tx(sc, wr); 260 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__); 261 if (ret) 262 goto err7; 263 264 CTR6(KTR_IW_CXGBE, 265 "%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx", 266 __func__, wq->sq.qid, wq->rq.qid, wq->db, 267 (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb); 268 269 return 0; 270 err7: 271 contigfree(wq->rq.queue, wq->rq.memsize, M_DEVBUF); 272 err6: 273 dealloc_sq(rdev, &wq->sq); 274 err5: 275 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 276 err4: 277 kfree(wq->rq.sw_rq); 278 err3: 279 kfree(wq->sq.sw_sq); 280 err2: 281 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 282 err1: 283 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 284 return -ENOMEM; 285 } 286 287 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp, 288 struct ib_send_wr *wr, int max, u32 *plenp) 289 { 290 u8 *dstp, *srcp; 291 u32 plen = 0; 292 int i; 293 int rem, len; 294 295 dstp = (u8 *)immdp->data; 296 for (i = 0; i < wr->num_sge; i++) { 297 if ((plen + wr->sg_list[i].length) > max) 298 return -EMSGSIZE; 299 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr; 300 plen += wr->sg_list[i].length; 301 rem = wr->sg_list[i].length; 302 while (rem) { 303 if (dstp == (u8 *)&sq->queue[sq->size]) 304 dstp = (u8 *)sq->queue; 305 if (rem <= (u8 *)&sq->queue[sq->size] - dstp) 306 len = rem; 307 else 308 len = (u8 *)&sq->queue[sq->size] - dstp; 309 memcpy(dstp, srcp, len); 310 dstp += len; 311 srcp += len; 312 rem -= len; 313 } 314 } 315 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp); 316 if (len) 317 memset(dstp, 0, len); 318 immdp->op = FW_RI_DATA_IMMD; 319 immdp->r1 = 0; 320 immdp->r2 = 0; 321 immdp->immdlen = cpu_to_be32(plen); 322 *plenp = plen; 323 return 0; 324 } 325 326 static int build_isgl(__be64 *queue_start, __be64 *queue_end, 327 struct fw_ri_isgl *isglp, struct ib_sge *sg_list, 328 int num_sge, u32 *plenp) 329 330 { 331 int i; 332 u32 plen = 0; 333 __be64 *flitp = (__be64 *)isglp->sge; 334 335 for (i = 0; i < num_sge; i++) { 336 if ((plen + sg_list[i].length) < plen) 337 return -EMSGSIZE; 338 plen += sg_list[i].length; 339 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) | 340 sg_list[i].length); 341 if (++flitp == queue_end) 342 flitp = queue_start; 343 *flitp = cpu_to_be64(sg_list[i].addr); 344 if (++flitp == queue_end) 345 flitp = queue_start; 346 } 347 *flitp = (__force __be64)0; 348 isglp->op = FW_RI_DATA_ISGL; 349 isglp->r1 = 0; 350 isglp->nsge = cpu_to_be16(num_sge); 351 isglp->r2 = 0; 352 if (plenp) 353 *plenp = plen; 354 return 0; 355 } 356 357 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe, 358 struct ib_send_wr *wr, u8 *len16) 359 { 360 u32 plen; 361 int size; 362 int ret; 363 364 if (wr->num_sge > T4_MAX_SEND_SGE) 365 return -EINVAL; 366 switch (wr->opcode) { 367 case IB_WR_SEND: 368 if (wr->send_flags & IB_SEND_SOLICITED) 369 wqe->send.sendop_pkd = cpu_to_be32( 370 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE)); 371 else 372 wqe->send.sendop_pkd = cpu_to_be32( 373 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND)); 374 wqe->send.stag_inv = 0; 375 break; 376 case IB_WR_SEND_WITH_INV: 377 if (wr->send_flags & IB_SEND_SOLICITED) 378 wqe->send.sendop_pkd = cpu_to_be32( 379 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV)); 380 else 381 wqe->send.sendop_pkd = cpu_to_be32( 382 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV)); 383 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 384 break; 385 386 default: 387 return -EINVAL; 388 } 389 390 plen = 0; 391 if (wr->num_sge) { 392 if (wr->send_flags & IB_SEND_INLINE) { 393 ret = build_immd(sq, wqe->send.u.immd_src, wr, 394 T4_MAX_SEND_INLINE, &plen); 395 if (ret) 396 return ret; 397 size = sizeof wqe->send + sizeof(struct fw_ri_immd) + 398 plen; 399 } else { 400 ret = build_isgl((__be64 *)sq->queue, 401 (__be64 *)&sq->queue[sq->size], 402 wqe->send.u.isgl_src, 403 wr->sg_list, wr->num_sge, &plen); 404 if (ret) 405 return ret; 406 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) + 407 wr->num_sge * sizeof(struct fw_ri_sge); 408 } 409 } else { 410 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD; 411 wqe->send.u.immd_src[0].r1 = 0; 412 wqe->send.u.immd_src[0].r2 = 0; 413 wqe->send.u.immd_src[0].immdlen = 0; 414 size = sizeof wqe->send + sizeof(struct fw_ri_immd); 415 plen = 0; 416 } 417 *len16 = DIV_ROUND_UP(size, 16); 418 wqe->send.plen = cpu_to_be32(plen); 419 return 0; 420 } 421 422 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe, 423 struct ib_send_wr *wr, u8 *len16) 424 { 425 u32 plen; 426 int size; 427 int ret; 428 429 if (wr->num_sge > T4_MAX_SEND_SGE) 430 return -EINVAL; 431 wqe->write.r2 = 0; 432 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey); 433 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr); 434 if (wr->num_sge) { 435 if (wr->send_flags & IB_SEND_INLINE) { 436 ret = build_immd(sq, wqe->write.u.immd_src, wr, 437 T4_MAX_WRITE_INLINE, &plen); 438 if (ret) 439 return ret; 440 size = sizeof wqe->write + sizeof(struct fw_ri_immd) + 441 plen; 442 } else { 443 ret = build_isgl((__be64 *)sq->queue, 444 (__be64 *)&sq->queue[sq->size], 445 wqe->write.u.isgl_src, 446 wr->sg_list, wr->num_sge, &plen); 447 if (ret) 448 return ret; 449 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) + 450 wr->num_sge * sizeof(struct fw_ri_sge); 451 } 452 } else { 453 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD; 454 wqe->write.u.immd_src[0].r1 = 0; 455 wqe->write.u.immd_src[0].r2 = 0; 456 wqe->write.u.immd_src[0].immdlen = 0; 457 size = sizeof wqe->write + sizeof(struct fw_ri_immd); 458 plen = 0; 459 } 460 *len16 = DIV_ROUND_UP(size, 16); 461 wqe->write.plen = cpu_to_be32(plen); 462 return 0; 463 } 464 465 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16) 466 { 467 if (wr->num_sge > 1) 468 return -EINVAL; 469 if (wr->num_sge) { 470 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey); 471 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr 472 >> 32)); 473 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr); 474 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey); 475 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length); 476 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr 477 >> 32)); 478 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr)); 479 } else { 480 wqe->read.stag_src = cpu_to_be32(2); 481 wqe->read.to_src_hi = 0; 482 wqe->read.to_src_lo = 0; 483 wqe->read.stag_sink = cpu_to_be32(2); 484 wqe->read.plen = 0; 485 wqe->read.to_sink_hi = 0; 486 wqe->read.to_sink_lo = 0; 487 } 488 wqe->read.r2 = 0; 489 wqe->read.r5 = 0; 490 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16); 491 return 0; 492 } 493 494 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe, 495 struct ib_recv_wr *wr, u8 *len16) 496 { 497 int ret; 498 499 ret = build_isgl((__be64 *)qhp->wq.rq.queue, 500 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size], 501 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL); 502 if (ret) 503 return ret; 504 *len16 = DIV_ROUND_UP(sizeof wqe->recv + 505 wr->num_sge * sizeof(struct fw_ri_sge), 16); 506 return 0; 507 } 508 509 static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe, 510 struct ib_send_wr *wr, u8 *len16) 511 { 512 513 struct fw_ri_immd *imdp; 514 __be64 *p; 515 int i; 516 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32); 517 int rem; 518 519 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH) 520 return -EINVAL; 521 522 wqe->fr.qpbinde_to_dcacpu = 0; 523 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12; 524 wqe->fr.addr_type = FW_RI_VA_BASED_TO; 525 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags); 526 wqe->fr.len_hi = 0; 527 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length); 528 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey); 529 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32); 530 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start & 531 0xffffffff); 532 WARN_ON(pbllen > T4_MAX_FR_IMMD); 533 imdp = (struct fw_ri_immd *)(&wqe->fr + 1); 534 imdp->op = FW_RI_DATA_IMMD; 535 imdp->r1 = 0; 536 imdp->r2 = 0; 537 imdp->immdlen = cpu_to_be32(pbllen); 538 p = (__be64 *)(imdp + 1); 539 rem = pbllen; 540 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) { 541 *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]); 542 rem -= sizeof *p; 543 if (++p == (__be64 *)&sq->queue[sq->size]) 544 p = (__be64 *)sq->queue; 545 } 546 BUG_ON(rem < 0); 547 while (rem) { 548 *p = 0; 549 rem -= sizeof *p; 550 if (++p == (__be64 *)&sq->queue[sq->size]) 551 p = (__be64 *)sq->queue; 552 } 553 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen, 16); 554 return 0; 555 } 556 557 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr, 558 u8 *len16) 559 { 560 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 561 wqe->inv.r2 = 0; 562 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16); 563 return 0; 564 } 565 566 void c4iw_qp_add_ref(struct ib_qp *qp) 567 { 568 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, qp); 569 atomic_inc(&(to_c4iw_qp(qp)->refcnt)); 570 } 571 572 void c4iw_qp_rem_ref(struct ib_qp *qp) 573 { 574 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, qp); 575 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt))) 576 wake_up(&(to_c4iw_qp(qp)->wait)); 577 } 578 579 static void complete_sq_drain_wr(struct c4iw_qp *qhp, struct ib_send_wr *wr) 580 { 581 struct t4_cqe cqe = {}; 582 struct c4iw_cq *schp; 583 unsigned long flag; 584 struct t4_cq *cq; 585 586 schp = to_c4iw_cq(qhp->ibqp.send_cq); 587 cq = &schp->cq; 588 589 PDBG("%s drain sq id %u\n", __func__, qhp->wq.sq.qid); 590 cqe.u.drain_cookie = wr->wr_id; 591 cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) | 592 V_CQE_OPCODE(C4IW_DRAIN_OPCODE) | 593 V_CQE_TYPE(1) | 594 V_CQE_SWCQE(1) | 595 V_CQE_QPID(qhp->wq.sq.qid)); 596 597 spin_lock_irqsave(&schp->lock, flag); 598 cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen)); 599 cq->sw_queue[cq->sw_pidx] = cqe; 600 t4_swcq_produce(cq); 601 spin_unlock_irqrestore(&schp->lock, flag); 602 603 spin_lock_irqsave(&schp->comp_handler_lock, flag); 604 (*schp->ibcq.comp_handler)(&schp->ibcq, 605 schp->ibcq.cq_context); 606 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 607 } 608 609 static void complete_rq_drain_wr(struct c4iw_qp *qhp, struct ib_recv_wr *wr) 610 { 611 struct t4_cqe cqe = {}; 612 struct c4iw_cq *rchp; 613 unsigned long flag; 614 struct t4_cq *cq; 615 616 rchp = to_c4iw_cq(qhp->ibqp.recv_cq); 617 cq = &rchp->cq; 618 619 PDBG("%s drain rq id %u\n", __func__, qhp->wq.sq.qid); 620 cqe.u.drain_cookie = wr->wr_id; 621 cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) | 622 V_CQE_OPCODE(C4IW_DRAIN_OPCODE) | 623 V_CQE_TYPE(0) | 624 V_CQE_SWCQE(1) | 625 V_CQE_QPID(qhp->wq.sq.qid)); 626 627 spin_lock_irqsave(&rchp->lock, flag); 628 cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen)); 629 cq->sw_queue[cq->sw_pidx] = cqe; 630 t4_swcq_produce(cq); 631 spin_unlock_irqrestore(&rchp->lock, flag); 632 633 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 634 (*rchp->ibcq.comp_handler)(&rchp->ibcq, 635 rchp->ibcq.cq_context); 636 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 637 } 638 639 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 640 struct ib_send_wr **bad_wr) 641 { 642 int err = 0; 643 u8 len16 = 0; 644 enum fw_wr_opcodes fw_opcode = 0; 645 enum fw_ri_wr_flags fw_flags; 646 struct c4iw_qp *qhp; 647 union t4_wr *wqe; 648 u32 num_wrs; 649 struct t4_swsqe *swsqe; 650 unsigned long flag; 651 u16 idx = 0; 652 653 qhp = to_c4iw_qp(ibqp); 654 spin_lock_irqsave(&qhp->lock, flag); 655 if (t4_wq_in_error(&qhp->wq)) { 656 spin_unlock_irqrestore(&qhp->lock, flag); 657 complete_sq_drain_wr(qhp, wr); 658 return err; 659 } 660 num_wrs = t4_sq_avail(&qhp->wq); 661 if (num_wrs == 0) { 662 spin_unlock_irqrestore(&qhp->lock, flag); 663 return -ENOMEM; 664 } 665 while (wr) { 666 if (num_wrs == 0) { 667 err = -ENOMEM; 668 *bad_wr = wr; 669 break; 670 } 671 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue + 672 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE); 673 674 fw_flags = 0; 675 if (wr->send_flags & IB_SEND_SOLICITED) 676 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG; 677 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all) 678 fw_flags |= FW_RI_COMPLETION_FLAG; 679 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx]; 680 switch (wr->opcode) { 681 case IB_WR_SEND_WITH_INV: 682 case IB_WR_SEND: 683 if (wr->send_flags & IB_SEND_FENCE) 684 fw_flags |= FW_RI_READ_FENCE_FLAG; 685 fw_opcode = FW_RI_SEND_WR; 686 if (wr->opcode == IB_WR_SEND) 687 swsqe->opcode = FW_RI_SEND; 688 else 689 swsqe->opcode = FW_RI_SEND_WITH_INV; 690 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16); 691 break; 692 case IB_WR_RDMA_WRITE: 693 fw_opcode = FW_RI_RDMA_WRITE_WR; 694 swsqe->opcode = FW_RI_RDMA_WRITE; 695 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16); 696 break; 697 case IB_WR_RDMA_READ: 698 case IB_WR_RDMA_READ_WITH_INV: 699 fw_opcode = FW_RI_RDMA_READ_WR; 700 swsqe->opcode = FW_RI_READ_REQ; 701 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) 702 fw_flags = FW_RI_RDMA_READ_INVALIDATE; 703 else 704 fw_flags = 0; 705 err = build_rdma_read(wqe, wr, &len16); 706 if (err) 707 break; 708 swsqe->read_len = wr->sg_list[0].length; 709 if (!qhp->wq.sq.oldest_read) 710 qhp->wq.sq.oldest_read = swsqe; 711 break; 712 case IB_WR_FAST_REG_MR: 713 fw_opcode = FW_RI_FR_NSMR_WR; 714 swsqe->opcode = FW_RI_FAST_REGISTER; 715 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16); 716 break; 717 case IB_WR_LOCAL_INV: 718 if (wr->send_flags & IB_SEND_FENCE) 719 fw_flags |= FW_RI_LOCAL_FENCE_FLAG; 720 fw_opcode = FW_RI_INV_LSTAG_WR; 721 swsqe->opcode = FW_RI_LOCAL_INV; 722 err = build_inv_stag(wqe, wr, &len16); 723 break; 724 default: 725 CTR2(KTR_IW_CXGBE, "%s post of type =%d TBD!", __func__, 726 wr->opcode); 727 err = -EINVAL; 728 } 729 if (err) { 730 *bad_wr = wr; 731 break; 732 } 733 swsqe->idx = qhp->wq.sq.pidx; 734 swsqe->complete = 0; 735 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) || 736 qhp->sq_sig_all; 737 swsqe->wr_id = wr->wr_id; 738 739 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16); 740 741 CTR5(KTR_IW_CXGBE, 742 "%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u", 743 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx, 744 swsqe->opcode, swsqe->read_len); 745 wr = wr->next; 746 num_wrs--; 747 t4_sq_produce(&qhp->wq, len16); 748 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 749 } 750 751 t4_ring_sq_db(&qhp->wq, idx); 752 spin_unlock_irqrestore(&qhp->lock, flag); 753 return err; 754 } 755 756 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 757 struct ib_recv_wr **bad_wr) 758 { 759 int err = 0; 760 struct c4iw_qp *qhp; 761 union t4_recv_wr *wqe; 762 u32 num_wrs; 763 u8 len16 = 0; 764 unsigned long flag; 765 u16 idx = 0; 766 767 qhp = to_c4iw_qp(ibqp); 768 spin_lock_irqsave(&qhp->lock, flag); 769 if (t4_wq_in_error(&qhp->wq)) { 770 spin_unlock_irqrestore(&qhp->lock, flag); 771 complete_rq_drain_wr(qhp, wr); 772 return err; 773 } 774 num_wrs = t4_rq_avail(&qhp->wq); 775 if (num_wrs == 0) { 776 spin_unlock_irqrestore(&qhp->lock, flag); 777 return -ENOMEM; 778 } 779 while (wr) { 780 if (wr->num_sge > T4_MAX_RECV_SGE) { 781 err = -EINVAL; 782 *bad_wr = wr; 783 break; 784 } 785 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue + 786 qhp->wq.rq.wq_pidx * 787 T4_EQ_ENTRY_SIZE); 788 if (num_wrs) 789 err = build_rdma_recv(qhp, wqe, wr, &len16); 790 else 791 err = -ENOMEM; 792 if (err) { 793 *bad_wr = wr; 794 break; 795 } 796 797 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id; 798 799 wqe->recv.opcode = FW_RI_RECV_WR; 800 wqe->recv.r1 = 0; 801 wqe->recv.wrid = qhp->wq.rq.pidx; 802 wqe->recv.r2[0] = 0; 803 wqe->recv.r2[1] = 0; 804 wqe->recv.r2[2] = 0; 805 wqe->recv.len16 = len16; 806 CTR3(KTR_IW_CXGBE, "%s cookie 0x%llx pidx %u", __func__, 807 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx); 808 t4_rq_produce(&qhp->wq, len16); 809 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 810 wr = wr->next; 811 num_wrs--; 812 } 813 814 t4_ring_rq_db(&qhp->wq, idx); 815 spin_unlock_irqrestore(&qhp->lock, flag); 816 return err; 817 } 818 819 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind) 820 { 821 return -ENOSYS; 822 } 823 824 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type, 825 u8 *ecode) 826 { 827 int status; 828 int tagged; 829 int opcode; 830 int rqtype; 831 int send_inv; 832 833 if (!err_cqe) { 834 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 835 *ecode = 0; 836 return; 837 } 838 839 status = CQE_STATUS(err_cqe); 840 opcode = CQE_OPCODE(err_cqe); 841 rqtype = RQ_TYPE(err_cqe); 842 send_inv = (opcode == FW_RI_SEND_WITH_INV) || 843 (opcode == FW_RI_SEND_WITH_SE_INV); 844 tagged = (opcode == FW_RI_RDMA_WRITE) || 845 (rqtype && (opcode == FW_RI_READ_RESP)); 846 847 switch (status) { 848 case T4_ERR_STAG: 849 if (send_inv) { 850 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 851 *ecode = RDMAP_CANT_INV_STAG; 852 } else { 853 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 854 *ecode = RDMAP_INV_STAG; 855 } 856 break; 857 case T4_ERR_PDID: 858 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 859 if ((opcode == FW_RI_SEND_WITH_INV) || 860 (opcode == FW_RI_SEND_WITH_SE_INV)) 861 *ecode = RDMAP_CANT_INV_STAG; 862 else 863 *ecode = RDMAP_STAG_NOT_ASSOC; 864 break; 865 case T4_ERR_QPID: 866 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 867 *ecode = RDMAP_STAG_NOT_ASSOC; 868 break; 869 case T4_ERR_ACCESS: 870 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 871 *ecode = RDMAP_ACC_VIOL; 872 break; 873 case T4_ERR_WRAP: 874 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 875 *ecode = RDMAP_TO_WRAP; 876 break; 877 case T4_ERR_BOUND: 878 if (tagged) { 879 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 880 *ecode = DDPT_BASE_BOUNDS; 881 } else { 882 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 883 *ecode = RDMAP_BASE_BOUNDS; 884 } 885 break; 886 case T4_ERR_INVALIDATE_SHARED_MR: 887 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND: 888 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 889 *ecode = RDMAP_CANT_INV_STAG; 890 break; 891 case T4_ERR_ECC: 892 case T4_ERR_ECC_PSTAG: 893 case T4_ERR_INTERNAL_ERR: 894 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA; 895 *ecode = 0; 896 break; 897 case T4_ERR_OUT_OF_RQE: 898 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 899 *ecode = DDPU_INV_MSN_NOBUF; 900 break; 901 case T4_ERR_PBL_ADDR_BOUND: 902 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 903 *ecode = DDPT_BASE_BOUNDS; 904 break; 905 case T4_ERR_CRC: 906 *layer_type = LAYER_MPA|DDP_LLP; 907 *ecode = MPA_CRC_ERR; 908 break; 909 case T4_ERR_MARKER: 910 *layer_type = LAYER_MPA|DDP_LLP; 911 *ecode = MPA_MARKER_ERR; 912 break; 913 case T4_ERR_PDU_LEN_ERR: 914 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 915 *ecode = DDPU_MSG_TOOBIG; 916 break; 917 case T4_ERR_DDP_VERSION: 918 if (tagged) { 919 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 920 *ecode = DDPT_INV_VERS; 921 } else { 922 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 923 *ecode = DDPU_INV_VERS; 924 } 925 break; 926 case T4_ERR_RDMA_VERSION: 927 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 928 *ecode = RDMAP_INV_VERS; 929 break; 930 case T4_ERR_OPCODE: 931 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 932 *ecode = RDMAP_INV_OPCODE; 933 break; 934 case T4_ERR_DDP_QUEUE_NUM: 935 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 936 *ecode = DDPU_INV_QN; 937 break; 938 case T4_ERR_MSN: 939 case T4_ERR_MSN_GAP: 940 case T4_ERR_MSN_RANGE: 941 case T4_ERR_IRD_OVERFLOW: 942 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 943 *ecode = DDPU_INV_MSN_RANGE; 944 break; 945 case T4_ERR_TBIT: 946 *layer_type = LAYER_DDP|DDP_LOCAL_CATA; 947 *ecode = 0; 948 break; 949 case T4_ERR_MO: 950 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 951 *ecode = DDPU_INV_MO; 952 break; 953 default: 954 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 955 *ecode = 0; 956 break; 957 } 958 } 959 960 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe, 961 gfp_t gfp) 962 { 963 int ret; 964 struct fw_ri_wr *wqe; 965 struct terminate_message *term; 966 struct wrqe *wr; 967 struct socket *so = qhp->ep->com.so; 968 struct inpcb *inp = sotoinpcb(so); 969 struct tcpcb *tp = intotcpcb(inp); 970 struct toepcb *toep = tp->t_toe; 971 972 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp, 973 qhp->wq.sq.qid, qhp->ep->hwtid); 974 975 wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq); 976 if (wr == NULL) 977 return; 978 wqe = wrtod(wr); 979 980 memset(wqe, 0, sizeof *wqe); 981 wqe->op_compl = cpu_to_be32(V_FW_WR_OP(FW_RI_WR)); 982 wqe->flowid_len16 = cpu_to_be32( 983 V_FW_WR_FLOWID(qhp->ep->hwtid) | 984 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 985 986 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE; 987 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term); 988 term = (struct terminate_message *)wqe->u.terminate.termmsg; 989 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) { 990 term->layer_etype = qhp->attr.layer_etype; 991 term->ecode = qhp->attr.ecode; 992 } else 993 build_term_codes(err_cqe, &term->layer_etype, &term->ecode); 994 ret = creds(toep, inp, sizeof(*wqe)); 995 if (ret) { 996 free_wrqe(wr); 997 return; 998 } 999 t4_wrq_tx(qhp->rhp->rdev.adap, wr); 1000 } 1001 1002 /* Assumes qhp lock is held. */ 1003 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp, 1004 struct c4iw_cq *schp) 1005 { 1006 int count; 1007 int flushed; 1008 unsigned long flag; 1009 1010 CTR4(KTR_IW_CXGBE, "%s qhp %p rchp %p schp %p", __func__, qhp, rchp, 1011 schp); 1012 1013 /* locking hierarchy: cq lock first, then qp lock. */ 1014 spin_lock_irqsave(&rchp->lock, flag); 1015 spin_lock(&qhp->lock); 1016 c4iw_flush_hw_cq(&rchp->cq); 1017 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count); 1018 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count); 1019 spin_unlock(&qhp->lock); 1020 spin_unlock_irqrestore(&rchp->lock, flag); 1021 if (flushed && rchp->ibcq.comp_handler) { 1022 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1023 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); 1024 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1025 } 1026 1027 /* locking hierarchy: cq lock first, then qp lock. */ 1028 spin_lock_irqsave(&schp->lock, flag); 1029 spin_lock(&qhp->lock); 1030 c4iw_flush_hw_cq(&schp->cq); 1031 c4iw_count_scqes(&schp->cq, &qhp->wq, &count); 1032 flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count); 1033 spin_unlock(&qhp->lock); 1034 spin_unlock_irqrestore(&schp->lock, flag); 1035 if (flushed && schp->ibcq.comp_handler) { 1036 spin_lock_irqsave(&schp->comp_handler_lock, flag); 1037 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context); 1038 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 1039 } 1040 } 1041 1042 static void flush_qp(struct c4iw_qp *qhp) 1043 { 1044 struct c4iw_cq *rchp, *schp; 1045 unsigned long flag; 1046 1047 rchp = get_chp(qhp->rhp, qhp->attr.rcq); 1048 schp = get_chp(qhp->rhp, qhp->attr.scq); 1049 1050 if (qhp->ibqp.uobject) { 1051 t4_set_wq_in_error(&qhp->wq); 1052 t4_set_cq_in_error(&rchp->cq); 1053 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1054 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); 1055 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1056 if (schp != rchp) { 1057 t4_set_cq_in_error(&schp->cq); 1058 spin_lock_irqsave(&schp->comp_handler_lock, flag); 1059 (*schp->ibcq.comp_handler)(&schp->ibcq, 1060 schp->ibcq.cq_context); 1061 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 1062 } 1063 return; 1064 } 1065 __flush_qp(qhp, rchp, schp); 1066 } 1067 1068 static int 1069 rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp, struct c4iw_ep *ep) 1070 { 1071 struct c4iw_rdev *rdev = &rhp->rdev; 1072 struct adapter *sc = rdev->adap; 1073 struct fw_ri_wr *wqe; 1074 int ret; 1075 struct wrqe *wr; 1076 struct socket *so = ep->com.so; 1077 struct inpcb *inp = sotoinpcb(so); 1078 struct tcpcb *tp = intotcpcb(inp); 1079 struct toepcb *toep = tp->t_toe; 1080 1081 KASSERT(rhp == qhp->rhp && ep == qhp->ep, ("%s: EDOOFUS", __func__)); 1082 1083 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp, 1084 qhp->wq.sq.qid, ep->hwtid); 1085 1086 wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq); 1087 if (wr == NULL) 1088 return (0); 1089 wqe = wrtod(wr); 1090 1091 memset(wqe, 0, sizeof *wqe); 1092 1093 wqe->op_compl = cpu_to_be32(V_FW_WR_OP(FW_RI_WR) | F_FW_WR_COMPL); 1094 wqe->flowid_len16 = cpu_to_be32(V_FW_WR_FLOWID(ep->hwtid) | 1095 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 1096 wqe->cookie = (unsigned long) &ep->com.wr_wait; 1097 wqe->u.fini.type = FW_RI_TYPE_FINI; 1098 1099 c4iw_init_wr_wait(&ep->com.wr_wait); 1100 1101 ret = creds(toep, inp, sizeof(*wqe)); 1102 if (ret) { 1103 free_wrqe(wr); 1104 return ret; 1105 } 1106 t4_wrq_tx(sc, wr); 1107 1108 ret = c4iw_wait_for_reply(rdev, &ep->com.wr_wait, ep->hwtid, 1109 qhp->wq.sq.qid, __func__); 1110 return ret; 1111 } 1112 1113 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init) 1114 { 1115 CTR2(KTR_IW_CXGBE, "%s p2p_type = %d", __func__, p2p_type); 1116 memset(&init->u, 0, sizeof init->u); 1117 switch (p2p_type) { 1118 case FW_RI_INIT_P2PTYPE_RDMA_WRITE: 1119 init->u.write.opcode = FW_RI_RDMA_WRITE_WR; 1120 init->u.write.stag_sink = cpu_to_be32(1); 1121 init->u.write.to_sink = cpu_to_be64(1); 1122 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD; 1123 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write + 1124 sizeof(struct fw_ri_immd), 1125 16); 1126 break; 1127 case FW_RI_INIT_P2PTYPE_READ_REQ: 1128 init->u.write.opcode = FW_RI_RDMA_READ_WR; 1129 init->u.read.stag_src = cpu_to_be32(1); 1130 init->u.read.to_src_lo = cpu_to_be32(1); 1131 init->u.read.stag_sink = cpu_to_be32(1); 1132 init->u.read.to_sink_lo = cpu_to_be32(1); 1133 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16); 1134 break; 1135 } 1136 } 1137 1138 static int 1139 creds(struct toepcb *toep, struct inpcb *inp, size_t wrsize) 1140 { 1141 struct ofld_tx_sdesc *txsd; 1142 1143 CTR3(KTR_IW_CXGBE, "%s:creB %p %u", __func__, toep , wrsize); 1144 INP_WLOCK(inp); 1145 if ((inp->inp_flags & (INP_DROPPED | INP_TIMEWAIT)) != 0) { 1146 INP_WUNLOCK(inp); 1147 return (EINVAL); 1148 } 1149 txsd = &toep->txsd[toep->txsd_pidx]; 1150 txsd->tx_credits = howmany(wrsize, 16); 1151 txsd->plen = 0; 1152 KASSERT(toep->tx_credits >= txsd->tx_credits && toep->txsd_avail > 0, 1153 ("%s: not enough credits (%d)", __func__, toep->tx_credits)); 1154 toep->tx_credits -= txsd->tx_credits; 1155 if (__predict_false(++toep->txsd_pidx == toep->txsd_total)) 1156 toep->txsd_pidx = 0; 1157 toep->txsd_avail--; 1158 INP_WUNLOCK(inp); 1159 CTR5(KTR_IW_CXGBE, "%s:creE %p %u %u %u", __func__, toep , 1160 txsd->tx_credits, toep->tx_credits, toep->txsd_pidx); 1161 return (0); 1162 } 1163 1164 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp) 1165 { 1166 struct fw_ri_wr *wqe; 1167 int ret; 1168 struct wrqe *wr; 1169 struct c4iw_ep *ep = qhp->ep; 1170 struct c4iw_rdev *rdev = &qhp->rhp->rdev; 1171 struct adapter *sc = rdev->adap; 1172 struct socket *so = ep->com.so; 1173 struct inpcb *inp = sotoinpcb(so); 1174 struct tcpcb *tp = intotcpcb(inp); 1175 struct toepcb *toep = tp->t_toe; 1176 1177 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp, 1178 qhp->wq.sq.qid, ep->hwtid); 1179 1180 wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq); 1181 if (wr == NULL) 1182 return (0); 1183 wqe = wrtod(wr); 1184 1185 memset(wqe, 0, sizeof *wqe); 1186 1187 wqe->op_compl = cpu_to_be32( 1188 V_FW_WR_OP(FW_RI_WR) | 1189 F_FW_WR_COMPL); 1190 wqe->flowid_len16 = cpu_to_be32(V_FW_WR_FLOWID(ep->hwtid) | 1191 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 1192 1193 wqe->cookie = (unsigned long) &ep->com.wr_wait; 1194 1195 wqe->u.init.type = FW_RI_TYPE_INIT; 1196 wqe->u.init.mpareqbit_p2ptype = 1197 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) | 1198 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type); 1199 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE; 1200 if (qhp->attr.mpa_attr.recv_marker_enabled) 1201 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE; 1202 if (qhp->attr.mpa_attr.xmit_marker_enabled) 1203 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE; 1204 if (qhp->attr.mpa_attr.crc_enabled) 1205 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE; 1206 1207 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE | 1208 FW_RI_QP_RDMA_WRITE_ENABLE | 1209 FW_RI_QP_BIND_ENABLE; 1210 if (!qhp->ibqp.uobject) 1211 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE | 1212 FW_RI_QP_STAG0_ENABLE; 1213 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq)); 1214 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd); 1215 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid); 1216 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid); 1217 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid); 1218 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq); 1219 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq); 1220 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord); 1221 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird); 1222 wqe->u.init.iss = cpu_to_be32(ep->snd_seq); 1223 wqe->u.init.irs = cpu_to_be32(ep->rcv_seq); 1224 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size); 1225 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr - 1226 sc->vres.rq.start); 1227 if (qhp->attr.mpa_attr.initiator) 1228 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init); 1229 1230 c4iw_init_wr_wait(&ep->com.wr_wait); 1231 1232 ret = creds(toep, inp, sizeof(*wqe)); 1233 if (ret) { 1234 free_wrqe(wr); 1235 return ret; 1236 } 1237 t4_wrq_tx(sc, wr); 1238 1239 ret = c4iw_wait_for_reply(rdev, &ep->com.wr_wait, ep->hwtid, 1240 qhp->wq.sq.qid, __func__); 1241 1242 toep->ulp_mode = ULP_MODE_RDMA; 1243 1244 return ret; 1245 } 1246 1247 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp, 1248 enum c4iw_qp_attr_mask mask, 1249 struct c4iw_qp_attributes *attrs, 1250 int internal) 1251 { 1252 int ret = 0; 1253 struct c4iw_qp_attributes newattr = qhp->attr; 1254 int disconnect = 0; 1255 int terminate = 0; 1256 int abort = 0; 1257 int free = 0; 1258 struct c4iw_ep *ep = NULL; 1259 1260 CTR5(KTR_IW_CXGBE, "%s qhp %p sqid 0x%x rqid 0x%x ep %p", __func__, qhp, 1261 qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep); 1262 CTR3(KTR_IW_CXGBE, "%s state %d -> %d", __func__, qhp->attr.state, 1263 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1); 1264 1265 mutex_lock(&qhp->mutex); 1266 1267 /* Process attr changes if in IDLE */ 1268 if (mask & C4IW_QP_ATTR_VALID_MODIFY) { 1269 if (qhp->attr.state != C4IW_QP_STATE_IDLE) { 1270 ret = -EIO; 1271 goto out; 1272 } 1273 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ) 1274 newattr.enable_rdma_read = attrs->enable_rdma_read; 1275 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE) 1276 newattr.enable_rdma_write = attrs->enable_rdma_write; 1277 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND) 1278 newattr.enable_bind = attrs->enable_bind; 1279 if (mask & C4IW_QP_ATTR_MAX_ORD) { 1280 if (attrs->max_ord > c4iw_max_read_depth) { 1281 ret = -EINVAL; 1282 goto out; 1283 } 1284 newattr.max_ord = attrs->max_ord; 1285 } 1286 if (mask & C4IW_QP_ATTR_MAX_IRD) { 1287 if (attrs->max_ird > c4iw_max_read_depth) { 1288 ret = -EINVAL; 1289 goto out; 1290 } 1291 newattr.max_ird = attrs->max_ird; 1292 } 1293 qhp->attr = newattr; 1294 } 1295 1296 if (!(mask & C4IW_QP_ATTR_NEXT_STATE)) 1297 goto out; 1298 if (qhp->attr.state == attrs->next_state) 1299 goto out; 1300 1301 switch (qhp->attr.state) { 1302 case C4IW_QP_STATE_IDLE: 1303 switch (attrs->next_state) { 1304 case C4IW_QP_STATE_RTS: 1305 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) { 1306 ret = -EINVAL; 1307 goto out; 1308 } 1309 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) { 1310 ret = -EINVAL; 1311 goto out; 1312 } 1313 qhp->attr.mpa_attr = attrs->mpa_attr; 1314 qhp->attr.llp_stream_handle = attrs->llp_stream_handle; 1315 qhp->ep = qhp->attr.llp_stream_handle; 1316 set_state(qhp, C4IW_QP_STATE_RTS); 1317 1318 /* 1319 * Ref the endpoint here and deref when we 1320 * disassociate the endpoint from the QP. This 1321 * happens in CLOSING->IDLE transition or *->ERROR 1322 * transition. 1323 */ 1324 c4iw_get_ep(&qhp->ep->com); 1325 ret = rdma_init(rhp, qhp); 1326 if (ret) 1327 goto err; 1328 break; 1329 case C4IW_QP_STATE_ERROR: 1330 set_state(qhp, C4IW_QP_STATE_ERROR); 1331 flush_qp(qhp); 1332 break; 1333 default: 1334 ret = -EINVAL; 1335 goto out; 1336 } 1337 break; 1338 case C4IW_QP_STATE_RTS: 1339 switch (attrs->next_state) { 1340 case C4IW_QP_STATE_CLOSING: 1341 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2); 1342 set_state(qhp, C4IW_QP_STATE_CLOSING); 1343 ep = qhp->ep; 1344 if (!internal) { 1345 abort = 0; 1346 disconnect = 1; 1347 c4iw_get_ep(&qhp->ep->com); 1348 } 1349 if (qhp->ibqp.uobject) 1350 t4_set_wq_in_error(&qhp->wq); 1351 ret = rdma_fini(rhp, qhp, ep); 1352 if (ret) 1353 goto err; 1354 break; 1355 case C4IW_QP_STATE_TERMINATE: 1356 set_state(qhp, C4IW_QP_STATE_TERMINATE); 1357 qhp->attr.layer_etype = attrs->layer_etype; 1358 qhp->attr.ecode = attrs->ecode; 1359 if (qhp->ibqp.uobject) 1360 t4_set_wq_in_error(&qhp->wq); 1361 ep = qhp->ep; 1362 if (!internal) 1363 terminate = 1; 1364 disconnect = 1; 1365 c4iw_get_ep(&qhp->ep->com); 1366 break; 1367 case C4IW_QP_STATE_ERROR: 1368 set_state(qhp, C4IW_QP_STATE_ERROR); 1369 if (qhp->ibqp.uobject) 1370 t4_set_wq_in_error(&qhp->wq); 1371 if (!internal) { 1372 abort = 1; 1373 disconnect = 1; 1374 ep = qhp->ep; 1375 c4iw_get_ep(&qhp->ep->com); 1376 } 1377 goto err; 1378 break; 1379 default: 1380 ret = -EINVAL; 1381 goto out; 1382 } 1383 break; 1384 case C4IW_QP_STATE_CLOSING: 1385 1386 /* 1387 * Allow kernel users to move to ERROR for qp draining. 1388 */ 1389 if (!internal && (qhp->ibqp.uobject || attrs->next_state != 1390 C4IW_QP_STATE_ERROR)) { 1391 ret = -EINVAL; 1392 goto out; 1393 } 1394 switch (attrs->next_state) { 1395 case C4IW_QP_STATE_IDLE: 1396 flush_qp(qhp); 1397 set_state(qhp, C4IW_QP_STATE_IDLE); 1398 qhp->attr.llp_stream_handle = NULL; 1399 c4iw_put_ep(&qhp->ep->com); 1400 qhp->ep = NULL; 1401 wake_up(&qhp->wait); 1402 break; 1403 case C4IW_QP_STATE_ERROR: 1404 goto err; 1405 default: 1406 ret = -EINVAL; 1407 goto err; 1408 } 1409 break; 1410 case C4IW_QP_STATE_ERROR: 1411 if (attrs->next_state != C4IW_QP_STATE_IDLE) { 1412 ret = -EINVAL; 1413 goto out; 1414 } 1415 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) { 1416 ret = -EINVAL; 1417 goto out; 1418 } 1419 set_state(qhp, C4IW_QP_STATE_IDLE); 1420 break; 1421 case C4IW_QP_STATE_TERMINATE: 1422 if (!internal) { 1423 ret = -EINVAL; 1424 goto out; 1425 } 1426 goto err; 1427 break; 1428 default: 1429 printf("%s in a bad state %d\n", 1430 __func__, qhp->attr.state); 1431 ret = -EINVAL; 1432 goto err; 1433 break; 1434 } 1435 goto out; 1436 err: 1437 CTR3(KTR_IW_CXGBE, "%s disassociating ep %p qpid 0x%x", __func__, 1438 qhp->ep, qhp->wq.sq.qid); 1439 1440 /* disassociate the LLP connection */ 1441 qhp->attr.llp_stream_handle = NULL; 1442 if (!ep) 1443 ep = qhp->ep; 1444 qhp->ep = NULL; 1445 set_state(qhp, C4IW_QP_STATE_ERROR); 1446 free = 1; 1447 abort = 1; 1448 BUG_ON(!ep); 1449 flush_qp(qhp); 1450 wake_up(&qhp->wait); 1451 out: 1452 mutex_unlock(&qhp->mutex); 1453 1454 if (terminate) 1455 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL); 1456 1457 /* 1458 * If disconnect is 1, then we need to initiate a disconnect 1459 * on the EP. This can be a normal close (RTS->CLOSING) or 1460 * an abnormal close (RTS/CLOSING->ERROR). 1461 */ 1462 if (disconnect) { 1463 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC : 1464 GFP_KERNEL); 1465 c4iw_put_ep(&ep->com); 1466 } 1467 1468 /* 1469 * If free is 1, then we've disassociated the EP from the QP 1470 * and we need to dereference the EP. 1471 */ 1472 if (free) 1473 c4iw_put_ep(&ep->com); 1474 CTR2(KTR_IW_CXGBE, "%s exit state %d", __func__, qhp->attr.state); 1475 return ret; 1476 } 1477 1478 int c4iw_destroy_qp(struct ib_qp *ib_qp) 1479 { 1480 struct c4iw_dev *rhp; 1481 struct c4iw_qp *qhp; 1482 struct c4iw_qp_attributes attrs; 1483 struct c4iw_ucontext *ucontext; 1484 1485 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, ib_qp); 1486 qhp = to_c4iw_qp(ib_qp); 1487 rhp = qhp->rhp; 1488 1489 attrs.next_state = C4IW_QP_STATE_ERROR; 1490 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE) 1491 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1); 1492 else 1493 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0); 1494 wait_event(qhp->wait, !qhp->ep); 1495 1496 spin_lock_irq(&rhp->lock); 1497 remove_handle_nolock(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1498 spin_unlock_irq(&rhp->lock); 1499 atomic_dec(&qhp->refcnt); 1500 wait_event(qhp->wait, !atomic_read(&qhp->refcnt)); 1501 1502 ucontext = ib_qp->uobject ? 1503 to_c4iw_ucontext(ib_qp->uobject->context) : NULL; 1504 destroy_qp(&rhp->rdev, &qhp->wq, 1505 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1506 1507 CTR3(KTR_IW_CXGBE, "%s ib_qp %p qpid 0x%0x", __func__, ib_qp, 1508 qhp->wq.sq.qid); 1509 kfree(qhp); 1510 return 0; 1511 } 1512 1513 struct ib_qp * 1514 c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs, 1515 struct ib_udata *udata) 1516 { 1517 struct c4iw_dev *rhp; 1518 struct c4iw_qp *qhp; 1519 struct c4iw_pd *php; 1520 struct c4iw_cq *schp; 1521 struct c4iw_cq *rchp; 1522 struct c4iw_create_qp_resp uresp; 1523 int sqsize, rqsize; 1524 struct c4iw_ucontext *ucontext; 1525 int ret, spg_ndesc; 1526 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4; 1527 1528 CTR2(KTR_IW_CXGBE, "%s ib_pd %p", __func__, pd); 1529 1530 if (attrs->qp_type != IB_QPT_RC) 1531 return ERR_PTR(-EINVAL); 1532 1533 php = to_c4iw_pd(pd); 1534 rhp = php->rhp; 1535 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid); 1536 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid); 1537 if (!schp || !rchp) 1538 return ERR_PTR(-EINVAL); 1539 1540 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE) 1541 return ERR_PTR(-EINVAL); 1542 1543 spg_ndesc = rhp->rdev.adap->params.sge.spg_len / EQ_ESIZE; 1544 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16); 1545 if (rqsize > T4_MAX_RQ_SIZE(spg_ndesc)) 1546 return ERR_PTR(-E2BIG); 1547 1548 sqsize = roundup(attrs->cap.max_send_wr + 1, 16); 1549 if (sqsize > T4_MAX_SQ_SIZE(spg_ndesc)) 1550 return ERR_PTR(-E2BIG); 1551 1552 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL; 1553 1554 1555 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL); 1556 if (!qhp) 1557 return ERR_PTR(-ENOMEM); 1558 qhp->wq.sq.size = sqsize; 1559 qhp->wq.sq.memsize = (sqsize + spg_ndesc) * sizeof *qhp->wq.sq.queue + 1560 16 * sizeof(__be64); 1561 qhp->wq.rq.size = rqsize; 1562 qhp->wq.rq.memsize = (rqsize + spg_ndesc) * sizeof *qhp->wq.rq.queue; 1563 1564 if (ucontext) { 1565 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE); 1566 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE); 1567 } 1568 1569 CTR5(KTR_IW_CXGBE, "%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu", 1570 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize); 1571 1572 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq, 1573 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1574 if (ret) 1575 goto err1; 1576 1577 attrs->cap.max_recv_wr = rqsize - 1; 1578 attrs->cap.max_send_wr = sqsize - 1; 1579 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE; 1580 1581 qhp->rhp = rhp; 1582 qhp->attr.pd = php->pdid; 1583 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid; 1584 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid; 1585 qhp->attr.sq_num_entries = attrs->cap.max_send_wr; 1586 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr; 1587 qhp->attr.sq_max_sges = attrs->cap.max_send_sge; 1588 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge; 1589 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge; 1590 qhp->attr.state = C4IW_QP_STATE_IDLE; 1591 qhp->attr.next_state = C4IW_QP_STATE_IDLE; 1592 qhp->attr.enable_rdma_read = 1; 1593 qhp->attr.enable_rdma_write = 1; 1594 qhp->attr.enable_bind = 1; 1595 qhp->attr.max_ord = 1; 1596 qhp->attr.max_ird = 1; 1597 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR; 1598 spin_lock_init(&qhp->lock); 1599 mutex_init(&qhp->mutex); 1600 init_waitqueue_head(&qhp->wait); 1601 atomic_set(&qhp->refcnt, 1); 1602 1603 spin_lock_irq(&rhp->lock); 1604 ret = insert_handle_nolock(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid); 1605 spin_unlock_irq(&rhp->lock); 1606 if (ret) 1607 goto err2; 1608 1609 if (udata) { 1610 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL); 1611 if (!mm1) { 1612 ret = -ENOMEM; 1613 goto err3; 1614 } 1615 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL); 1616 if (!mm2) { 1617 ret = -ENOMEM; 1618 goto err4; 1619 } 1620 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL); 1621 if (!mm3) { 1622 ret = -ENOMEM; 1623 goto err5; 1624 } 1625 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL); 1626 if (!mm4) { 1627 ret = -ENOMEM; 1628 goto err6; 1629 } 1630 uresp.flags = 0; 1631 uresp.qid_mask = rhp->rdev.qpmask; 1632 uresp.sqid = qhp->wq.sq.qid; 1633 uresp.sq_size = qhp->wq.sq.size; 1634 uresp.sq_memsize = qhp->wq.sq.memsize; 1635 uresp.rqid = qhp->wq.rq.qid; 1636 uresp.rq_size = qhp->wq.rq.size; 1637 uresp.rq_memsize = qhp->wq.rq.memsize; 1638 spin_lock(&ucontext->mmap_lock); 1639 uresp.sq_key = ucontext->key; 1640 ucontext->key += PAGE_SIZE; 1641 uresp.rq_key = ucontext->key; 1642 ucontext->key += PAGE_SIZE; 1643 uresp.sq_db_gts_key = ucontext->key; 1644 ucontext->key += PAGE_SIZE; 1645 uresp.rq_db_gts_key = ucontext->key; 1646 ucontext->key += PAGE_SIZE; 1647 spin_unlock(&ucontext->mmap_lock); 1648 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp); 1649 if (ret) 1650 goto err7; 1651 mm1->key = uresp.sq_key; 1652 mm1->addr = qhp->wq.sq.phys_addr; 1653 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize); 1654 CTR4(KTR_IW_CXGBE, "%s mm1 %x, %x, %d", __func__, mm1->key, 1655 mm1->addr, mm1->len); 1656 insert_mmap(ucontext, mm1); 1657 mm2->key = uresp.rq_key; 1658 mm2->addr = vtophys(qhp->wq.rq.queue); 1659 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize); 1660 CTR4(KTR_IW_CXGBE, "%s mm2 %x, %x, %d", __func__, mm2->key, 1661 mm2->addr, mm2->len); 1662 insert_mmap(ucontext, mm2); 1663 mm3->key = uresp.sq_db_gts_key; 1664 mm3->addr = qhp->wq.sq.udb; 1665 mm3->len = PAGE_SIZE; 1666 CTR4(KTR_IW_CXGBE, "%s mm3 %x, %x, %d", __func__, mm3->key, 1667 mm3->addr, mm3->len); 1668 insert_mmap(ucontext, mm3); 1669 mm4->key = uresp.rq_db_gts_key; 1670 mm4->addr = qhp->wq.rq.udb; 1671 mm4->len = PAGE_SIZE; 1672 CTR4(KTR_IW_CXGBE, "%s mm4 %x, %x, %d", __func__, mm4->key, 1673 mm4->addr, mm4->len); 1674 insert_mmap(ucontext, mm4); 1675 } 1676 qhp->ibqp.qp_num = qhp->wq.sq.qid; 1677 init_timer(&(qhp->timer)); 1678 CTR5(KTR_IW_CXGBE, 1679 "%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x", 1680 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries, 1681 qhp->wq.sq.qid); 1682 return &qhp->ibqp; 1683 err7: 1684 kfree(mm4); 1685 err6: 1686 kfree(mm3); 1687 err5: 1688 kfree(mm2); 1689 err4: 1690 kfree(mm1); 1691 err3: 1692 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1693 err2: 1694 destroy_qp(&rhp->rdev, &qhp->wq, 1695 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1696 err1: 1697 kfree(qhp); 1698 return ERR_PTR(ret); 1699 } 1700 1701 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1702 int attr_mask, struct ib_udata *udata) 1703 { 1704 struct c4iw_dev *rhp; 1705 struct c4iw_qp *qhp; 1706 enum c4iw_qp_attr_mask mask = 0; 1707 struct c4iw_qp_attributes attrs; 1708 1709 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, ibqp); 1710 1711 /* iwarp does not support the RTR state */ 1712 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR)) 1713 attr_mask &= ~IB_QP_STATE; 1714 1715 /* Make sure we still have something left to do */ 1716 if (!attr_mask) 1717 return 0; 1718 1719 memset(&attrs, 0, sizeof attrs); 1720 qhp = to_c4iw_qp(ibqp); 1721 rhp = qhp->rhp; 1722 1723 attrs.next_state = c4iw_convert_state(attr->qp_state); 1724 attrs.enable_rdma_read = (attr->qp_access_flags & 1725 IB_ACCESS_REMOTE_READ) ? 1 : 0; 1726 attrs.enable_rdma_write = (attr->qp_access_flags & 1727 IB_ACCESS_REMOTE_WRITE) ? 1 : 0; 1728 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0; 1729 1730 1731 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0; 1732 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ? 1733 (C4IW_QP_ATTR_ENABLE_RDMA_READ | 1734 C4IW_QP_ATTR_ENABLE_RDMA_WRITE | 1735 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0; 1736 1737 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0); 1738 } 1739 1740 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn) 1741 { 1742 CTR3(KTR_IW_CXGBE, "%s ib_dev %p qpn 0x%x", __func__, dev, qpn); 1743 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn); 1744 } 1745 1746 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1747 int attr_mask, struct ib_qp_init_attr *init_attr) 1748 { 1749 struct c4iw_qp *qhp = to_c4iw_qp(ibqp); 1750 1751 memset(attr, 0, sizeof *attr); 1752 memset(init_attr, 0, sizeof *init_attr); 1753 attr->qp_state = to_ib_qp_state(qhp->attr.state); 1754 init_attr->cap.max_send_wr = qhp->attr.sq_num_entries; 1755 init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries; 1756 init_attr->cap.max_send_sge = qhp->attr.sq_max_sges; 1757 init_attr->cap.max_recv_sge = qhp->attr.sq_max_sges; 1758 init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE; 1759 init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0; 1760 return 0; 1761 } 1762 #endif 1763