1 /*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 #include <sys/taskqueue.h> 41 42 #include <machine/bus.h> 43 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <dev/mmc/bridge.h> 48 #include <dev/mmc/mmcreg.h> 49 50 #include <dev/sdhci/sdhci.h> 51 52 #include "mmcbr_if.h" 53 #include "sdhci_if.h" 54 55 #include "opt_mmccam.h" 56 57 #include "bcm2835_dma.h" 58 #include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h> 59 #include "bcm2835_vcbus.h" 60 61 #define BCM2835_DEFAULT_SDHCI_FREQ 50 62 63 #define BCM_SDHCI_BUFFER_SIZE 512 64 #define NUM_DMA_SEGS 2 65 66 #ifdef DEBUG 67 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 68 printf(fmt,##args); } while (0) 69 #else 70 #define dprintf(fmt, args...) 71 #endif 72 73 static int bcm2835_sdhci_hs = 1; 74 static int bcm2835_sdhci_pio_mode = 0; 75 76 static struct ofw_compat_data compat_data[] = { 77 {"broadcom,bcm2835-sdhci", 1}, 78 {"brcm,bcm2835-mmc", 1}, 79 {NULL, 0} 80 }; 81 82 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); 83 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); 84 85 struct bcm_sdhci_softc { 86 device_t sc_dev; 87 struct resource * sc_mem_res; 88 struct resource * sc_irq_res; 89 bus_space_tag_t sc_bst; 90 bus_space_handle_t sc_bsh; 91 void * sc_intrhand; 92 struct mmc_request * sc_req; 93 struct sdhci_slot sc_slot; 94 int sc_dma_ch; 95 bus_dma_tag_t sc_dma_tag; 96 bus_dmamap_t sc_dma_map; 97 vm_paddr_t sc_sdhci_buffer_phys; 98 uint32_t cmd_and_mode; 99 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS]; 100 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS]; 101 int dmamap_seg_count; 102 int dmamap_seg_index; 103 int dmamap_status; 104 }; 105 106 static int bcm_sdhci_probe(device_t); 107 static int bcm_sdhci_attach(device_t); 108 static int bcm_sdhci_detach(device_t); 109 static void bcm_sdhci_intr(void *); 110 111 static int bcm_sdhci_get_ro(device_t, device_t); 112 static void bcm_sdhci_dma_intr(int ch, void *arg); 113 114 static void 115 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 116 { 117 struct bcm_sdhci_softc *sc = arg; 118 int i; 119 120 sc->dmamap_status = err; 121 sc->dmamap_seg_count = nseg; 122 123 /* Note nseg is guaranteed to be zero if err is non-zero. */ 124 for (i = 0; i < nseg; i++) { 125 sc->dmamap_seg_addrs[i] = segs[i].ds_addr; 126 sc->dmamap_seg_sizes[i] = segs[i].ds_len; 127 } 128 } 129 130 static int 131 bcm_sdhci_probe(device_t dev) 132 { 133 134 if (!ofw_bus_status_okay(dev)) 135 return (ENXIO); 136 137 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 138 return (ENXIO); 139 140 device_set_desc(dev, "Broadcom 2708 SDHCI controller"); 141 142 return (BUS_PROBE_DEFAULT); 143 } 144 145 static int 146 bcm_sdhci_attach(device_t dev) 147 { 148 struct bcm_sdhci_softc *sc = device_get_softc(dev); 149 int rid, err; 150 phandle_t node; 151 pcell_t cell; 152 u_int default_freq; 153 154 sc->sc_dev = dev; 155 sc->sc_req = NULL; 156 157 err = bcm2835_mbox_set_power_state(BCM2835_MBOX_POWER_ID_EMMC, 158 TRUE); 159 if (err != 0) { 160 if (bootverbose) 161 device_printf(dev, "Unable to enable the power\n"); 162 return (err); 163 } 164 165 default_freq = 0; 166 err = bcm2835_mbox_get_clock_rate(BCM2835_MBOX_CLOCK_ID_EMMC, 167 &default_freq); 168 if (err == 0) { 169 /* Convert to MHz */ 170 default_freq /= 1000000; 171 } 172 if (default_freq == 0) { 173 node = ofw_bus_get_node(sc->sc_dev); 174 if ((OF_getencprop(node, "clock-frequency", &cell, 175 sizeof(cell))) > 0) 176 default_freq = cell / 1000000; 177 } 178 if (default_freq == 0) 179 default_freq = BCM2835_DEFAULT_SDHCI_FREQ; 180 181 if (bootverbose) 182 device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq); 183 184 rid = 0; 185 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 186 RF_ACTIVE); 187 if (!sc->sc_mem_res) { 188 device_printf(dev, "cannot allocate memory window\n"); 189 err = ENXIO; 190 goto fail; 191 } 192 193 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 194 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 195 196 rid = 0; 197 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 198 RF_ACTIVE); 199 if (!sc->sc_irq_res) { 200 device_printf(dev, "cannot allocate interrupt\n"); 201 err = ENXIO; 202 goto fail; 203 } 204 205 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 206 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) { 207 device_printf(dev, "cannot setup interrupt handler\n"); 208 err = ENXIO; 209 goto fail; 210 } 211 212 if (!bcm2835_sdhci_pio_mode) 213 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; 214 215 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; 216 if (bcm2835_sdhci_hs) 217 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; 218 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); 219 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 220 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 221 | SDHCI_QUIRK_DONT_SET_HISPD_BIT 222 | SDHCI_QUIRK_MISSING_CAPS; 223 224 sdhci_init_slot(dev, &sc->sc_slot, 0); 225 226 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); 227 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 228 goto fail; 229 230 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc); 231 232 /* Allocate bus_dma resources. */ 233 err = bus_dma_tag_create(bus_get_dma_tag(dev), 234 1, 0, BUS_SPACE_MAXADDR_32BIT, 235 BUS_SPACE_MAXADDR, NULL, NULL, 236 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE, 237 BUS_DMA_ALLOCNOW, NULL, NULL, 238 &sc->sc_dma_tag); 239 240 if (err) { 241 device_printf(dev, "failed allocate DMA tag"); 242 goto fail; 243 } 244 245 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); 246 if (err) { 247 device_printf(dev, "bus_dmamap_create failed\n"); 248 goto fail; 249 } 250 251 /* FIXME: Fix along with other BUS_SPACE_PHYSADDR instances */ 252 sc->sc_sdhci_buffer_phys = rman_get_start(sc->sc_mem_res) + 253 SDHCI_BUFFER; 254 255 bus_generic_probe(dev); 256 bus_generic_attach(dev); 257 258 #ifdef MMCCAM 259 sdhci_cam_start_slot(&sc->sc_slot); 260 #else 261 sdhci_start_slot(&sc->sc_slot); 262 #endif 263 264 return (0); 265 266 fail: 267 if (sc->sc_intrhand) 268 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 269 if (sc->sc_irq_res) 270 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 271 if (sc->sc_mem_res) 272 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 273 274 return (err); 275 } 276 277 static int 278 bcm_sdhci_detach(device_t dev) 279 { 280 281 return (EBUSY); 282 } 283 284 static void 285 bcm_sdhci_intr(void *arg) 286 { 287 struct bcm_sdhci_softc *sc = arg; 288 289 sdhci_generic_intr(&sc->sc_slot); 290 } 291 292 static int 293 bcm_sdhci_get_ro(device_t bus, device_t child) 294 { 295 296 return (0); 297 } 298 299 static inline uint32_t 300 RD4(struct bcm_sdhci_softc *sc, bus_size_t off) 301 { 302 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 303 return val; 304 } 305 306 static inline void 307 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) 308 { 309 310 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); 311 /* 312 * The Arasan HC has a bug where it may lose the content of 313 * consecutive writes to registers that are within two SD-card 314 * clock cycles of each other (a clock domain crossing problem). 315 */ 316 if (sc->sc_slot.clock > 0) 317 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1); 318 } 319 320 static uint8_t 321 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 322 { 323 struct bcm_sdhci_softc *sc = device_get_softc(dev); 324 uint32_t val = RD4(sc, off & ~3); 325 326 return ((val >> (off & 3)*8) & 0xff); 327 } 328 329 static uint16_t 330 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 331 { 332 struct bcm_sdhci_softc *sc = device_get_softc(dev); 333 uint32_t val = RD4(sc, off & ~3); 334 335 /* 336 * Standard 32-bit handling of command and transfer mode. 337 */ 338 if (off == SDHCI_TRANSFER_MODE) { 339 return (sc->cmd_and_mode >> 16); 340 } else if (off == SDHCI_COMMAND_FLAGS) { 341 return (sc->cmd_and_mode & 0x0000ffff); 342 } 343 return ((val >> (off & 3)*8) & 0xffff); 344 } 345 346 static uint32_t 347 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 348 { 349 struct bcm_sdhci_softc *sc = device_get_softc(dev); 350 351 return RD4(sc, off); 352 } 353 354 static void 355 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 356 uint32_t *data, bus_size_t count) 357 { 358 struct bcm_sdhci_softc *sc = device_get_softc(dev); 359 360 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 361 } 362 363 static void 364 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 365 { 366 struct bcm_sdhci_softc *sc = device_get_softc(dev); 367 uint32_t val32 = RD4(sc, off & ~3); 368 val32 &= ~(0xff << (off & 3)*8); 369 val32 |= (val << (off & 3)*8); 370 WR4(sc, off & ~3, val32); 371 } 372 373 static void 374 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 375 { 376 struct bcm_sdhci_softc *sc = device_get_softc(dev); 377 uint32_t val32; 378 if (off == SDHCI_COMMAND_FLAGS) 379 val32 = sc->cmd_and_mode; 380 else 381 val32 = RD4(sc, off & ~3); 382 val32 &= ~(0xffff << (off & 3)*8); 383 val32 |= (val << (off & 3)*8); 384 if (off == SDHCI_TRANSFER_MODE) 385 sc->cmd_and_mode = val32; 386 else { 387 WR4(sc, off & ~3, val32); 388 if (off == SDHCI_COMMAND_FLAGS) 389 sc->cmd_and_mode = val32; 390 } 391 } 392 393 static void 394 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 395 { 396 struct bcm_sdhci_softc *sc = device_get_softc(dev); 397 WR4(sc, off, val); 398 } 399 400 static void 401 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 402 uint32_t *data, bus_size_t count) 403 { 404 struct bcm_sdhci_softc *sc = device_get_softc(dev); 405 406 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 407 } 408 409 static void 410 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc) 411 { 412 struct sdhci_slot *slot; 413 vm_paddr_t pdst, psrc; 414 int err, idx, len, sync_op; 415 416 slot = &sc->sc_slot; 417 idx = sc->dmamap_seg_index++; 418 len = sc->dmamap_seg_sizes[idx]; 419 slot->offset += len; 420 421 if (slot->curcmd->data->flags & MMC_DATA_READ) { 422 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 423 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 424 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 425 BCM_DMA_INC_ADDR, 426 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 427 psrc = sc->sc_sdhci_buffer_phys; 428 pdst = sc->dmamap_seg_addrs[idx]; 429 sync_op = BUS_DMASYNC_PREREAD; 430 } else { 431 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 432 BCM_DMA_INC_ADDR, 433 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 434 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 435 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 436 psrc = sc->dmamap_seg_addrs[idx]; 437 pdst = sc->sc_sdhci_buffer_phys; 438 sync_op = BUS_DMASYNC_PREWRITE; 439 } 440 441 /* 442 * When starting a new DMA operation do the busdma sync operation, and 443 * disable SDCHI data interrrupts because we'll be driven by DMA 444 * interrupts (or SDHCI error interrupts) until the IO is done. 445 */ 446 if (idx == 0) { 447 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 448 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | 449 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); 450 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE, 451 slot->intmask); 452 } 453 454 /* 455 * Start the DMA transfer. Only programming errors (like failing to 456 * allocate a channel) cause a non-zero return from bcm_dma_start(). 457 */ 458 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len); 459 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start")); 460 } 461 462 static void 463 bcm_sdhci_dma_intr(int ch, void *arg) 464 { 465 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; 466 struct sdhci_slot *slot = &sc->sc_slot; 467 uint32_t reg, mask; 468 int left, sync_op; 469 470 mtx_lock(&slot->mtx); 471 472 /* 473 * If there are more segments for the current dma, start the next one. 474 * Otherwise unload the dma map and decide what to do next based on the 475 * status of the sdhci controller and whether there's more data left. 476 */ 477 if (sc->dmamap_seg_index < sc->dmamap_seg_count) { 478 bcm_sdhci_start_dma_seg(sc); 479 mtx_unlock(&slot->mtx); 480 return; 481 } 482 483 if (slot->curcmd->data->flags & MMC_DATA_READ) { 484 sync_op = BUS_DMASYNC_POSTREAD; 485 mask = SDHCI_INT_DATA_AVAIL; 486 } else { 487 sync_op = BUS_DMASYNC_POSTWRITE; 488 mask = SDHCI_INT_SPACE_AVAIL; 489 } 490 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 491 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); 492 493 sc->dmamap_seg_count = 0; 494 sc->dmamap_seg_index = 0; 495 496 left = min(BCM_SDHCI_BUFFER_SIZE, 497 slot->curcmd->data->len - slot->offset); 498 499 /* DATA END? */ 500 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); 501 502 if (reg & SDHCI_INT_DATA_END) { 503 /* ACK for all outstanding interrupts */ 504 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); 505 506 /* enable INT */ 507 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL 508 | SDHCI_INT_DATA_END; 509 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 510 slot->intmask); 511 512 /* finish this data */ 513 sdhci_finish_data(slot); 514 } 515 else { 516 /* already available? */ 517 if (reg & mask) { 518 519 /* ACK for DATA_AVAIL or SPACE_AVAIL */ 520 bcm_sdhci_write_4(slot->bus, slot, 521 SDHCI_INT_STATUS, mask); 522 523 /* continue next DMA transfer */ 524 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 525 (uint8_t *)slot->curcmd->data->data + 526 slot->offset, left, bcm_sdhci_dmacb, sc, 527 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) { 528 slot->curcmd->error = MMC_ERR_NO_MEMORY; 529 sdhci_finish_data(slot); 530 } else { 531 bcm_sdhci_start_dma_seg(sc); 532 } 533 } else { 534 /* wait for next data by INT */ 535 536 /* enable INT */ 537 slot->intmask |= SDHCI_INT_DATA_AVAIL | 538 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; 539 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 540 slot->intmask); 541 } 542 } 543 544 mtx_unlock(&slot->mtx); 545 } 546 547 static void 548 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot) 549 { 550 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 551 size_t left; 552 553 if (sc->dmamap_seg_count != 0) { 554 device_printf(sc->sc_dev, "DMA in use\n"); 555 return; 556 } 557 558 left = min(BCM_SDHCI_BUFFER_SIZE, 559 slot->curcmd->data->len - slot->offset); 560 561 KASSERT((left & 3) == 0, 562 ("%s: len = %zu, not word-aligned", __func__, left)); 563 564 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 565 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 566 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 567 sc->dmamap_status != 0) { 568 slot->curcmd->error = MMC_ERR_NO_MEMORY; 569 return; 570 } 571 572 /* DMA start */ 573 bcm_sdhci_start_dma_seg(sc); 574 } 575 576 static void 577 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot) 578 { 579 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 580 size_t left; 581 582 if (sc->dmamap_seg_count != 0) { 583 device_printf(sc->sc_dev, "DMA in use\n"); 584 return; 585 } 586 587 left = min(BCM_SDHCI_BUFFER_SIZE, 588 slot->curcmd->data->len - slot->offset); 589 590 KASSERT((left & 3) == 0, 591 ("%s: len = %zu, not word-aligned", __func__, left)); 592 593 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 594 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 595 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 596 sc->dmamap_status != 0) { 597 slot->curcmd->error = MMC_ERR_NO_MEMORY; 598 return; 599 } 600 601 /* DMA start */ 602 bcm_sdhci_start_dma_seg(sc); 603 } 604 605 static int 606 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) 607 { 608 size_t left; 609 610 /* 611 * Do not use DMA for transfers less than block size or with a length 612 * that is not a multiple of four. 613 */ 614 left = min(BCM_DMA_BLOCK_SIZE, 615 slot->curcmd->data->len - slot->offset); 616 if (left < BCM_DMA_BLOCK_SIZE) 617 return (0); 618 if (left & 0x03) 619 return (0); 620 621 return (1); 622 } 623 624 static void 625 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, 626 uint32_t *intmask) 627 { 628 629 /* DMA transfer FIFO 1KB */ 630 if (slot->curcmd->data->flags & MMC_DATA_READ) 631 bcm_sdhci_read_dma(dev, slot); 632 else 633 bcm_sdhci_write_dma(dev, slot); 634 } 635 636 static void 637 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) 638 { 639 640 sdhci_finish_data(slot); 641 } 642 643 static device_method_t bcm_sdhci_methods[] = { 644 /* Device interface */ 645 DEVMETHOD(device_probe, bcm_sdhci_probe), 646 DEVMETHOD(device_attach, bcm_sdhci_attach), 647 DEVMETHOD(device_detach, bcm_sdhci_detach), 648 649 /* Bus interface */ 650 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 651 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 652 653 /* MMC bridge interface */ 654 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 655 DEVMETHOD(mmcbr_request, sdhci_generic_request), 656 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), 657 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 658 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 659 660 /* Platform transfer methods */ 661 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), 662 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), 663 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), 664 /* SDHCI registers accessors */ 665 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), 666 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), 667 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), 668 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), 669 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), 670 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), 671 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), 672 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), 673 674 DEVMETHOD_END 675 }; 676 677 static devclass_t bcm_sdhci_devclass; 678 679 static driver_t bcm_sdhci_driver = { 680 "sdhci_bcm", 681 bcm_sdhci_methods, 682 sizeof(struct bcm_sdhci_softc), 683 }; 684 685 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 686 NULL, NULL); 687 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1); 688 MMC_DECLARE_BRIDGE(sdhci_bcm); 689