1 /*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 3 * Copyright (c) 2012-2015 Luiz Otavio O Souza <loos@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_platform.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/gpio.h> 37 #include <sys/interrupt.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/proc.h> 43 #include <sys/rman.h> 44 #include <sys/sysctl.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr.h> 48 49 #include <dev/gpio/gpiobusvar.h> 50 #include <dev/ofw/ofw_bus.h> 51 52 #include <arm/broadcom/bcm2835/bcm2835_gpio.h> 53 54 #include "gpio_if.h" 55 56 #include "pic_if.h" 57 58 #ifdef DEBUG 59 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 60 printf(fmt,##args); } while (0) 61 #else 62 #define dprintf(fmt, args...) 63 #endif 64 65 #define BCM_GPIO_IRQS 4 66 #define BCM_GPIO_PINS 54 67 #define BCM_GPIO_PINS_PER_BANK 32 68 69 #define BCM_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 70 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | GPIO_INTR_LEVEL_LOW | \ 71 GPIO_INTR_LEVEL_HIGH | GPIO_INTR_EDGE_RISING | \ 72 GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH) 73 74 static struct resource_spec bcm_gpio_res_spec[] = { 75 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 76 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* bank 0 interrupt */ 77 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* bank 1 interrupt */ 78 { -1, 0, 0 } 79 }; 80 81 struct bcm_gpio_sysctl { 82 struct bcm_gpio_softc *sc; 83 uint32_t pin; 84 }; 85 86 struct bcm_gpio_irqsrc { 87 struct intr_irqsrc bgi_isrc; 88 uint32_t bgi_irq; 89 uint32_t bgi_mode; 90 uint32_t bgi_mask; 91 }; 92 93 struct bcm_gpio_softc { 94 device_t sc_dev; 95 device_t sc_busdev; 96 struct mtx sc_mtx; 97 struct resource * sc_res[BCM_GPIO_IRQS + 1]; 98 bus_space_tag_t sc_bst; 99 bus_space_handle_t sc_bsh; 100 void * sc_intrhand[BCM_GPIO_IRQS]; 101 int sc_gpio_npins; 102 int sc_ro_npins; 103 int sc_ro_pins[BCM_GPIO_PINS]; 104 struct gpio_pin sc_gpio_pins[BCM_GPIO_PINS]; 105 struct bcm_gpio_sysctl sc_sysctl[BCM_GPIO_PINS]; 106 struct bcm_gpio_irqsrc sc_isrcs[BCM_GPIO_PINS]; 107 }; 108 109 enum bcm_gpio_pud { 110 BCM_GPIO_NONE, 111 BCM_GPIO_PULLDOWN, 112 BCM_GPIO_PULLUP, 113 }; 114 115 #define BCM_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 116 #define BCM_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 117 #define BCM_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 118 #define BCM_GPIO_WRITE(_sc, _off, _val) \ 119 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val) 120 #define BCM_GPIO_READ(_sc, _off) \ 121 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off) 122 #define BCM_GPIO_CLEAR_BITS(_sc, _off, _bits) \ 123 BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) & ~(_bits)) 124 #define BCM_GPIO_SET_BITS(_sc, _off, _bits) \ 125 BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) | _bits) 126 #define BCM_GPIO_BANK(a) (a / BCM_GPIO_PINS_PER_BANK) 127 #define BCM_GPIO_MASK(a) (1U << (a % BCM_GPIO_PINS_PER_BANK)) 128 129 #define BCM_GPIO_GPFSEL(_bank) (0x00 + _bank * 4) /* Function Select */ 130 #define BCM_GPIO_GPSET(_bank) (0x1c + _bank * 4) /* Pin Out Set */ 131 #define BCM_GPIO_GPCLR(_bank) (0x28 + _bank * 4) /* Pin Out Clear */ 132 #define BCM_GPIO_GPLEV(_bank) (0x34 + _bank * 4) /* Pin Level */ 133 #define BCM_GPIO_GPEDS(_bank) (0x40 + _bank * 4) /* Event Status */ 134 #define BCM_GPIO_GPREN(_bank) (0x4c + _bank * 4) /* Rising Edge irq */ 135 #define BCM_GPIO_GPFEN(_bank) (0x58 + _bank * 4) /* Falling Edge irq */ 136 #define BCM_GPIO_GPHEN(_bank) (0x64 + _bank * 4) /* High Level irq */ 137 #define BCM_GPIO_GPLEN(_bank) (0x70 + _bank * 4) /* Low Level irq */ 138 #define BCM_GPIO_GPAREN(_bank) (0x7c + _bank * 4) /* Async Rising Edge */ 139 #define BCM_GPIO_GPAFEN(_bank) (0x88 + _bank * 4) /* Async Falling Egde */ 140 #define BCM_GPIO_GPPUD(_bank) (0x94) /* Pin Pull up/down */ 141 #define BCM_GPIO_GPPUDCLK(_bank) (0x98 + _bank * 4) /* Pin Pull up clock */ 142 143 static struct ofw_compat_data compat_data[] = { 144 {"broadcom,bcm2835-gpio", 1}, 145 {"brcm,bcm2835-gpio", 1}, 146 {NULL, 0} 147 }; 148 149 static struct bcm_gpio_softc *bcm_gpio_sc = NULL; 150 151 static int bcm_gpio_intr_bank0(void *arg); 152 static int bcm_gpio_intr_bank1(void *arg); 153 static int bcm_gpio_pic_attach(struct bcm_gpio_softc *sc); 154 static int bcm_gpio_pic_detach(struct bcm_gpio_softc *sc); 155 156 static int 157 bcm_gpio_pin_is_ro(struct bcm_gpio_softc *sc, int pin) 158 { 159 int i; 160 161 for (i = 0; i < sc->sc_ro_npins; i++) 162 if (pin == sc->sc_ro_pins[i]) 163 return (1); 164 return (0); 165 } 166 167 static uint32_t 168 bcm_gpio_get_function(struct bcm_gpio_softc *sc, uint32_t pin) 169 { 170 uint32_t bank, func, offset; 171 172 /* Five banks, 10 pins per bank, 3 bits per pin. */ 173 bank = pin / 10; 174 offset = (pin - bank * 10) * 3; 175 176 BCM_GPIO_LOCK(sc); 177 func = (BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank)) >> offset) & 7; 178 BCM_GPIO_UNLOCK(sc); 179 180 return (func); 181 } 182 183 static void 184 bcm_gpio_func_str(uint32_t nfunc, char *buf, int bufsize) 185 { 186 187 switch (nfunc) { 188 case BCM_GPIO_INPUT: 189 strncpy(buf, "input", bufsize); 190 break; 191 case BCM_GPIO_OUTPUT: 192 strncpy(buf, "output", bufsize); 193 break; 194 case BCM_GPIO_ALT0: 195 strncpy(buf, "alt0", bufsize); 196 break; 197 case BCM_GPIO_ALT1: 198 strncpy(buf, "alt1", bufsize); 199 break; 200 case BCM_GPIO_ALT2: 201 strncpy(buf, "alt2", bufsize); 202 break; 203 case BCM_GPIO_ALT3: 204 strncpy(buf, "alt3", bufsize); 205 break; 206 case BCM_GPIO_ALT4: 207 strncpy(buf, "alt4", bufsize); 208 break; 209 case BCM_GPIO_ALT5: 210 strncpy(buf, "alt5", bufsize); 211 break; 212 default: 213 strncpy(buf, "invalid", bufsize); 214 } 215 } 216 217 static int 218 bcm_gpio_str_func(char *func, uint32_t *nfunc) 219 { 220 221 if (strcasecmp(func, "input") == 0) 222 *nfunc = BCM_GPIO_INPUT; 223 else if (strcasecmp(func, "output") == 0) 224 *nfunc = BCM_GPIO_OUTPUT; 225 else if (strcasecmp(func, "alt0") == 0) 226 *nfunc = BCM_GPIO_ALT0; 227 else if (strcasecmp(func, "alt1") == 0) 228 *nfunc = BCM_GPIO_ALT1; 229 else if (strcasecmp(func, "alt2") == 0) 230 *nfunc = BCM_GPIO_ALT2; 231 else if (strcasecmp(func, "alt3") == 0) 232 *nfunc = BCM_GPIO_ALT3; 233 else if (strcasecmp(func, "alt4") == 0) 234 *nfunc = BCM_GPIO_ALT4; 235 else if (strcasecmp(func, "alt5") == 0) 236 *nfunc = BCM_GPIO_ALT5; 237 else 238 return (-1); 239 240 return (0); 241 } 242 243 static uint32_t 244 bcm_gpio_func_flag(uint32_t nfunc) 245 { 246 247 switch (nfunc) { 248 case BCM_GPIO_INPUT: 249 return (GPIO_PIN_INPUT); 250 case BCM_GPIO_OUTPUT: 251 return (GPIO_PIN_OUTPUT); 252 } 253 return (0); 254 } 255 256 static void 257 bcm_gpio_set_function(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t f) 258 { 259 uint32_t bank, data, offset; 260 261 /* Must be called with lock held. */ 262 BCM_GPIO_LOCK_ASSERT(sc); 263 264 /* Five banks, 10 pins per bank, 3 bits per pin. */ 265 bank = pin / 10; 266 offset = (pin - bank * 10) * 3; 267 268 data = BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank)); 269 data &= ~(7 << offset); 270 data |= (f << offset); 271 BCM_GPIO_WRITE(sc, BCM_GPIO_GPFSEL(bank), data); 272 } 273 274 static void 275 bcm_gpio_set_pud(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t state) 276 { 277 uint32_t bank; 278 279 /* Must be called with lock held. */ 280 BCM_GPIO_LOCK_ASSERT(sc); 281 282 bank = BCM_GPIO_BANK(pin); 283 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUD(0), state); 284 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUDCLK(bank), BCM_GPIO_MASK(pin)); 285 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUD(0), 0); 286 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUDCLK(bank), 0); 287 } 288 289 void 290 bcm_gpio_set_alternate(device_t dev, uint32_t pin, uint32_t nfunc) 291 { 292 struct bcm_gpio_softc *sc; 293 int i; 294 295 sc = device_get_softc(dev); 296 BCM_GPIO_LOCK(sc); 297 298 /* Disable pull-up or pull-down on pin. */ 299 bcm_gpio_set_pud(sc, pin, BCM_GPIO_NONE); 300 301 /* And now set the pin function. */ 302 bcm_gpio_set_function(sc, pin, nfunc); 303 304 /* Update the pin flags. */ 305 for (i = 0; i < sc->sc_gpio_npins; i++) { 306 if (sc->sc_gpio_pins[i].gp_pin == pin) 307 break; 308 } 309 if (i < sc->sc_gpio_npins) 310 sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(nfunc); 311 312 BCM_GPIO_UNLOCK(sc); 313 } 314 315 static void 316 bcm_gpio_pin_configure(struct bcm_gpio_softc *sc, struct gpio_pin *pin, 317 unsigned int flags) 318 { 319 320 BCM_GPIO_LOCK(sc); 321 322 /* 323 * Manage input/output. 324 */ 325 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { 326 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT); 327 if (flags & GPIO_PIN_OUTPUT) { 328 pin->gp_flags |= GPIO_PIN_OUTPUT; 329 bcm_gpio_set_function(sc, pin->gp_pin, 330 BCM_GPIO_OUTPUT); 331 } else { 332 pin->gp_flags |= GPIO_PIN_INPUT; 333 bcm_gpio_set_function(sc, pin->gp_pin, 334 BCM_GPIO_INPUT); 335 } 336 } 337 338 /* Manage Pull-up/pull-down. */ 339 pin->gp_flags &= ~(GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN); 340 if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) { 341 if (flags & GPIO_PIN_PULLUP) { 342 pin->gp_flags |= GPIO_PIN_PULLUP; 343 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLUP); 344 } else { 345 pin->gp_flags |= GPIO_PIN_PULLDOWN; 346 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLDOWN); 347 } 348 } else 349 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_NONE); 350 351 BCM_GPIO_UNLOCK(sc); 352 } 353 354 static device_t 355 bcm_gpio_get_bus(device_t dev) 356 { 357 struct bcm_gpio_softc *sc; 358 359 sc = device_get_softc(dev); 360 361 return (sc->sc_busdev); 362 } 363 364 static int 365 bcm_gpio_pin_max(device_t dev, int *maxpin) 366 { 367 368 *maxpin = BCM_GPIO_PINS - 1; 369 return (0); 370 } 371 372 static int 373 bcm_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 374 { 375 struct bcm_gpio_softc *sc = device_get_softc(dev); 376 int i; 377 378 for (i = 0; i < sc->sc_gpio_npins; i++) { 379 if (sc->sc_gpio_pins[i].gp_pin == pin) 380 break; 381 } 382 383 if (i >= sc->sc_gpio_npins) 384 return (EINVAL); 385 386 BCM_GPIO_LOCK(sc); 387 *caps = sc->sc_gpio_pins[i].gp_caps; 388 BCM_GPIO_UNLOCK(sc); 389 390 return (0); 391 } 392 393 static int 394 bcm_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 395 { 396 struct bcm_gpio_softc *sc = device_get_softc(dev); 397 int i; 398 399 for (i = 0; i < sc->sc_gpio_npins; i++) { 400 if (sc->sc_gpio_pins[i].gp_pin == pin) 401 break; 402 } 403 404 if (i >= sc->sc_gpio_npins) 405 return (EINVAL); 406 407 BCM_GPIO_LOCK(sc); 408 *flags = sc->sc_gpio_pins[i].gp_flags; 409 BCM_GPIO_UNLOCK(sc); 410 411 return (0); 412 } 413 414 static int 415 bcm_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 416 { 417 struct bcm_gpio_softc *sc = device_get_softc(dev); 418 int i; 419 420 for (i = 0; i < sc->sc_gpio_npins; i++) { 421 if (sc->sc_gpio_pins[i].gp_pin == pin) 422 break; 423 } 424 425 if (i >= sc->sc_gpio_npins) 426 return (EINVAL); 427 428 BCM_GPIO_LOCK(sc); 429 memcpy(name, sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME); 430 BCM_GPIO_UNLOCK(sc); 431 432 return (0); 433 } 434 435 static int 436 bcm_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 437 { 438 struct bcm_gpio_softc *sc = device_get_softc(dev); 439 int i; 440 441 for (i = 0; i < sc->sc_gpio_npins; i++) { 442 if (sc->sc_gpio_pins[i].gp_pin == pin) 443 break; 444 } 445 446 if (i >= sc->sc_gpio_npins) 447 return (EINVAL); 448 449 /* We never touch on read-only/reserved pins. */ 450 if (bcm_gpio_pin_is_ro(sc, pin)) 451 return (EINVAL); 452 453 bcm_gpio_pin_configure(sc, &sc->sc_gpio_pins[i], flags); 454 455 return (0); 456 } 457 458 static int 459 bcm_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 460 { 461 struct bcm_gpio_softc *sc = device_get_softc(dev); 462 uint32_t bank, reg; 463 int i; 464 465 for (i = 0; i < sc->sc_gpio_npins; i++) { 466 if (sc->sc_gpio_pins[i].gp_pin == pin) 467 break; 468 } 469 if (i >= sc->sc_gpio_npins) 470 return (EINVAL); 471 /* We never write to read-only/reserved pins. */ 472 if (bcm_gpio_pin_is_ro(sc, pin)) 473 return (EINVAL); 474 BCM_GPIO_LOCK(sc); 475 bank = BCM_GPIO_BANK(pin); 476 if (value) 477 reg = BCM_GPIO_GPSET(bank); 478 else 479 reg = BCM_GPIO_GPCLR(bank); 480 BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin)); 481 BCM_GPIO_UNLOCK(sc); 482 483 return (0); 484 } 485 486 static int 487 bcm_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 488 { 489 struct bcm_gpio_softc *sc = device_get_softc(dev); 490 uint32_t bank, reg_data; 491 int i; 492 493 for (i = 0; i < sc->sc_gpio_npins; i++) { 494 if (sc->sc_gpio_pins[i].gp_pin == pin) 495 break; 496 } 497 if (i >= sc->sc_gpio_npins) 498 return (EINVAL); 499 bank = BCM_GPIO_BANK(pin); 500 BCM_GPIO_LOCK(sc); 501 reg_data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank)); 502 BCM_GPIO_UNLOCK(sc); 503 *val = (reg_data & BCM_GPIO_MASK(pin)) ? 1 : 0; 504 505 return (0); 506 } 507 508 static int 509 bcm_gpio_pin_toggle(device_t dev, uint32_t pin) 510 { 511 struct bcm_gpio_softc *sc = device_get_softc(dev); 512 uint32_t bank, data, reg; 513 int i; 514 515 for (i = 0; i < sc->sc_gpio_npins; i++) { 516 if (sc->sc_gpio_pins[i].gp_pin == pin) 517 break; 518 } 519 if (i >= sc->sc_gpio_npins) 520 return (EINVAL); 521 /* We never write to read-only/reserved pins. */ 522 if (bcm_gpio_pin_is_ro(sc, pin)) 523 return (EINVAL); 524 BCM_GPIO_LOCK(sc); 525 bank = BCM_GPIO_BANK(pin); 526 data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank)); 527 if (data & BCM_GPIO_MASK(pin)) 528 reg = BCM_GPIO_GPCLR(bank); 529 else 530 reg = BCM_GPIO_GPSET(bank); 531 BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin)); 532 BCM_GPIO_UNLOCK(sc); 533 534 return (0); 535 } 536 537 static int 538 bcm_gpio_func_proc(SYSCTL_HANDLER_ARGS) 539 { 540 char buf[16]; 541 struct bcm_gpio_softc *sc; 542 struct bcm_gpio_sysctl *sc_sysctl; 543 uint32_t nfunc; 544 int error; 545 546 sc_sysctl = arg1; 547 sc = sc_sysctl->sc; 548 549 /* Get the current pin function. */ 550 nfunc = bcm_gpio_get_function(sc, sc_sysctl->pin); 551 bcm_gpio_func_str(nfunc, buf, sizeof(buf)); 552 553 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 554 if (error != 0 || req->newptr == NULL) 555 return (error); 556 /* Ignore changes on read-only pins. */ 557 if (bcm_gpio_pin_is_ro(sc, sc_sysctl->pin)) 558 return (0); 559 /* Parse the user supplied string and check for a valid pin function. */ 560 if (bcm_gpio_str_func(buf, &nfunc) != 0) 561 return (EINVAL); 562 563 /* Update the pin alternate function. */ 564 bcm_gpio_set_alternate(sc->sc_dev, sc_sysctl->pin, nfunc); 565 566 return (0); 567 } 568 569 static void 570 bcm_gpio_sysctl_init(struct bcm_gpio_softc *sc) 571 { 572 char pinbuf[3]; 573 struct bcm_gpio_sysctl *sc_sysctl; 574 struct sysctl_ctx_list *ctx; 575 struct sysctl_oid *tree_node, *pin_node, *pinN_node; 576 struct sysctl_oid_list *tree, *pin_tree, *pinN_tree; 577 int i; 578 579 /* 580 * Add per-pin sysctl tree/handlers. 581 */ 582 ctx = device_get_sysctl_ctx(sc->sc_dev); 583 tree_node = device_get_sysctl_tree(sc->sc_dev); 584 tree = SYSCTL_CHILDREN(tree_node); 585 pin_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "pin", 586 CTLFLAG_RD, NULL, "GPIO Pins"); 587 pin_tree = SYSCTL_CHILDREN(pin_node); 588 589 for (i = 0; i < sc->sc_gpio_npins; i++) { 590 591 snprintf(pinbuf, sizeof(pinbuf), "%d", i); 592 pinN_node = SYSCTL_ADD_NODE(ctx, pin_tree, OID_AUTO, pinbuf, 593 CTLFLAG_RD, NULL, "GPIO Pin"); 594 pinN_tree = SYSCTL_CHILDREN(pinN_node); 595 596 sc->sc_sysctl[i].sc = sc; 597 sc_sysctl = &sc->sc_sysctl[i]; 598 sc_sysctl->sc = sc; 599 sc_sysctl->pin = sc->sc_gpio_pins[i].gp_pin; 600 SYSCTL_ADD_PROC(ctx, pinN_tree, OID_AUTO, "function", 601 CTLFLAG_RW | CTLTYPE_STRING, sc_sysctl, 602 sizeof(struct bcm_gpio_sysctl), bcm_gpio_func_proc, 603 "A", "Pin Function"); 604 } 605 } 606 607 static int 608 bcm_gpio_get_ro_pins(struct bcm_gpio_softc *sc, phandle_t node, 609 const char *propname, const char *label) 610 { 611 int i, need_comma, npins, range_start, range_stop; 612 pcell_t *pins; 613 614 /* Get the property data. */ 615 npins = OF_getencprop_alloc(node, propname, sizeof(*pins), 616 (void **)&pins); 617 if (npins < 0) 618 return (-1); 619 if (npins == 0) { 620 OF_prop_free(pins); 621 return (0); 622 } 623 for (i = 0; i < npins; i++) 624 sc->sc_ro_pins[i + sc->sc_ro_npins] = pins[i]; 625 sc->sc_ro_npins += npins; 626 need_comma = 0; 627 device_printf(sc->sc_dev, "%s pins: ", label); 628 range_start = range_stop = pins[0]; 629 for (i = 1; i < npins; i++) { 630 if (pins[i] != range_stop + 1) { 631 if (need_comma) 632 printf(","); 633 if (range_start != range_stop) 634 printf("%d-%d", range_start, range_stop); 635 else 636 printf("%d", range_start); 637 range_start = range_stop = pins[i]; 638 need_comma = 1; 639 } else 640 range_stop++; 641 } 642 if (need_comma) 643 printf(","); 644 if (range_start != range_stop) 645 printf("%d-%d.\n", range_start, range_stop); 646 else 647 printf("%d.\n", range_start); 648 OF_prop_free(pins); 649 650 return (0); 651 } 652 653 static int 654 bcm_gpio_get_reserved_pins(struct bcm_gpio_softc *sc) 655 { 656 char *name; 657 phandle_t gpio, node, reserved; 658 ssize_t len; 659 660 /* Get read-only pins if they're provided */ 661 gpio = ofw_bus_get_node(sc->sc_dev); 662 if (bcm_gpio_get_ro_pins(sc, gpio, "broadcom,read-only", 663 "read-only") != 0) 664 return (0); 665 /* Traverse the GPIO subnodes to find the reserved pins node. */ 666 reserved = 0; 667 node = OF_child(gpio); 668 while ((node != 0) && (reserved == 0)) { 669 len = OF_getprop_alloc(node, "name", 1, (void **)&name); 670 if (len == -1) 671 return (-1); 672 if (strcmp(name, "reserved") == 0) 673 reserved = node; 674 OF_prop_free(name); 675 node = OF_peer(node); 676 } 677 if (reserved == 0) 678 return (-1); 679 /* Get the reserved pins. */ 680 if (bcm_gpio_get_ro_pins(sc, reserved, "broadcom,pins", 681 "reserved") != 0) 682 return (-1); 683 684 return (0); 685 } 686 687 static int 688 bcm_gpio_probe(device_t dev) 689 { 690 691 if (!ofw_bus_status_okay(dev)) 692 return (ENXIO); 693 694 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 695 return (ENXIO); 696 697 device_set_desc(dev, "BCM2708/2835 GPIO controller"); 698 return (BUS_PROBE_DEFAULT); 699 } 700 701 static int 702 bcm_gpio_intr_attach(device_t dev) 703 { 704 struct bcm_gpio_softc *sc; 705 706 /* 707 * Only first two interrupt lines are used. Third line is 708 * mirrored second line and forth line is common for all banks. 709 */ 710 sc = device_get_softc(dev); 711 if (sc->sc_res[1] == NULL || sc->sc_res[2] == NULL) 712 return (-1); 713 714 if (bcm_gpio_pic_attach(sc) != 0) { 715 device_printf(dev, "unable to attach PIC\n"); 716 return (-1); 717 } 718 if (bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_MISC | INTR_MPSAFE, 719 bcm_gpio_intr_bank0, NULL, sc, &sc->sc_intrhand[0]) != 0) 720 return (-1); 721 if (bus_setup_intr(dev, sc->sc_res[2], INTR_TYPE_MISC | INTR_MPSAFE, 722 bcm_gpio_intr_bank1, NULL, sc, &sc->sc_intrhand[1]) != 0) 723 return (-1); 724 725 return (0); 726 } 727 728 static void 729 bcm_gpio_intr_detach(device_t dev) 730 { 731 struct bcm_gpio_softc *sc; 732 733 sc = device_get_softc(dev); 734 if (sc->sc_intrhand[0] != NULL) 735 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_intrhand[0]); 736 if (sc->sc_intrhand[1] != NULL) 737 bus_teardown_intr(dev, sc->sc_res[2], sc->sc_intrhand[1]); 738 739 bcm_gpio_pic_detach(sc); 740 } 741 742 static int 743 bcm_gpio_attach(device_t dev) 744 { 745 int i, j; 746 phandle_t gpio; 747 struct bcm_gpio_softc *sc; 748 uint32_t func; 749 750 if (bcm_gpio_sc != NULL) 751 return (ENXIO); 752 753 bcm_gpio_sc = sc = device_get_softc(dev); 754 sc->sc_dev = dev; 755 mtx_init(&sc->sc_mtx, "bcm gpio", "gpio", MTX_SPIN); 756 if (bus_alloc_resources(dev, bcm_gpio_res_spec, sc->sc_res) != 0) { 757 device_printf(dev, "cannot allocate resources\n"); 758 goto fail; 759 } 760 sc->sc_bst = rman_get_bustag(sc->sc_res[0]); 761 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]); 762 /* Setup the GPIO interrupt handler. */ 763 if (bcm_gpio_intr_attach(dev)) { 764 device_printf(dev, "unable to setup the gpio irq handler\n"); 765 goto fail; 766 } 767 /* Find our node. */ 768 gpio = ofw_bus_get_node(sc->sc_dev); 769 if (!OF_hasprop(gpio, "gpio-controller")) 770 /* Node is not a GPIO controller. */ 771 goto fail; 772 /* 773 * Find the read-only pins. These are pins we never touch or bad 774 * things could happen. 775 */ 776 if (bcm_gpio_get_reserved_pins(sc) == -1) 777 goto fail; 778 /* Initialize the software controlled pins. */ 779 for (i = 0, j = 0; j < BCM_GPIO_PINS; j++) { 780 snprintf(sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME, 781 "pin %d", j); 782 func = bcm_gpio_get_function(sc, j); 783 sc->sc_gpio_pins[i].gp_pin = j; 784 sc->sc_gpio_pins[i].gp_caps = BCM_GPIO_DEFAULT_CAPS; 785 sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(func); 786 i++; 787 } 788 sc->sc_gpio_npins = i; 789 bcm_gpio_sysctl_init(sc); 790 sc->sc_busdev = gpiobus_attach_bus(dev); 791 if (sc->sc_busdev == NULL) 792 goto fail; 793 794 return (0); 795 796 fail: 797 bcm_gpio_intr_detach(dev); 798 bus_release_resources(dev, bcm_gpio_res_spec, sc->sc_res); 799 mtx_destroy(&sc->sc_mtx); 800 801 return (ENXIO); 802 } 803 804 static int 805 bcm_gpio_detach(device_t dev) 806 { 807 808 return (EBUSY); 809 } 810 811 static inline void 812 bcm_gpio_modify(struct bcm_gpio_softc *sc, uint32_t reg, uint32_t mask, 813 bool set_bits) 814 { 815 816 if (set_bits) 817 BCM_GPIO_SET_BITS(sc, reg, mask); 818 else 819 BCM_GPIO_CLEAR_BITS(sc, reg, mask); 820 } 821 822 static inline void 823 bcm_gpio_isrc_eoi(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 824 { 825 uint32_t bank; 826 827 /* Write 1 to clear. */ 828 bank = BCM_GPIO_BANK(bgi->bgi_irq); 829 BCM_GPIO_WRITE(sc, BCM_GPIO_GPEDS(bank), bgi->bgi_mask); 830 } 831 832 static inline bool 833 bcm_gpio_isrc_is_level(struct bcm_gpio_irqsrc *bgi) 834 { 835 836 return (bgi->bgi_mode == GPIO_INTR_LEVEL_LOW || 837 bgi->bgi_mode == GPIO_INTR_LEVEL_HIGH); 838 } 839 840 static inline void 841 bcm_gpio_isrc_mask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 842 { 843 uint32_t bank; 844 845 bank = BCM_GPIO_BANK(bgi->bgi_irq); 846 BCM_GPIO_LOCK(sc); 847 switch (bgi->bgi_mode) { 848 case GPIO_INTR_LEVEL_LOW: 849 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask); 850 break; 851 case GPIO_INTR_LEVEL_HIGH: 852 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask); 853 break; 854 case GPIO_INTR_EDGE_RISING: 855 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 856 break; 857 case GPIO_INTR_EDGE_FALLING: 858 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 859 break; 860 case GPIO_INTR_EDGE_BOTH: 861 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 862 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 863 break; 864 } 865 BCM_GPIO_UNLOCK(sc); 866 } 867 868 static inline void 869 bcm_gpio_isrc_unmask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi) 870 { 871 uint32_t bank; 872 873 bank = BCM_GPIO_BANK(bgi->bgi_irq); 874 BCM_GPIO_LOCK(sc); 875 switch (bgi->bgi_mode) { 876 case GPIO_INTR_LEVEL_LOW: 877 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask); 878 break; 879 case GPIO_INTR_LEVEL_HIGH: 880 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask); 881 break; 882 case GPIO_INTR_EDGE_RISING: 883 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 884 break; 885 case GPIO_INTR_EDGE_FALLING: 886 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 887 break; 888 case GPIO_INTR_EDGE_BOTH: 889 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask); 890 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask); 891 break; 892 } 893 BCM_GPIO_UNLOCK(sc); 894 } 895 896 static int 897 bcm_gpio_intr_internal(struct bcm_gpio_softc *sc, uint32_t bank) 898 { 899 u_int irq; 900 struct bcm_gpio_irqsrc *bgi; 901 uint32_t reg; 902 903 /* Do not care of spurious interrupt on GPIO. */ 904 reg = BCM_GPIO_READ(sc, BCM_GPIO_GPEDS(bank)); 905 while (reg != 0) { 906 irq = BCM_GPIO_PINS_PER_BANK * bank + ffs(reg) - 1; 907 bgi = sc->sc_isrcs + irq; 908 if (!bcm_gpio_isrc_is_level(bgi)) 909 bcm_gpio_isrc_eoi(sc, bgi); 910 if (intr_isrc_dispatch(&bgi->bgi_isrc, 911 curthread->td_intr_frame) != 0) { 912 bcm_gpio_isrc_mask(sc, bgi); 913 if (bcm_gpio_isrc_is_level(bgi)) 914 bcm_gpio_isrc_eoi(sc, bgi); 915 device_printf(sc->sc_dev, "Stray irq %u disabled\n", 916 irq); 917 } 918 reg &= ~bgi->bgi_mask; 919 } 920 return (FILTER_HANDLED); 921 } 922 923 static int 924 bcm_gpio_intr_bank0(void *arg) 925 { 926 927 return (bcm_gpio_intr_internal(arg, 0)); 928 } 929 930 static int 931 bcm_gpio_intr_bank1(void *arg) 932 { 933 934 return (bcm_gpio_intr_internal(arg, 1)); 935 } 936 937 static int 938 bcm_gpio_pic_attach(struct bcm_gpio_softc *sc) 939 { 940 int error; 941 uint32_t irq; 942 const char *name; 943 944 name = device_get_nameunit(sc->sc_dev); 945 for (irq = 0; irq < BCM_GPIO_PINS; irq++) { 946 sc->sc_isrcs[irq].bgi_irq = irq; 947 sc->sc_isrcs[irq].bgi_mask = BCM_GPIO_MASK(irq); 948 sc->sc_isrcs[irq].bgi_mode = GPIO_INTR_CONFORM; 949 950 error = intr_isrc_register(&sc->sc_isrcs[irq].bgi_isrc, 951 sc->sc_dev, 0, "%s,%u", name, irq); 952 if (error != 0) 953 return (error); /* XXX deregister ISRCs */ 954 } 955 if (intr_pic_register(sc->sc_dev, 956 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))) == NULL) 957 return (ENXIO); 958 959 return (0); 960 } 961 962 static int 963 bcm_gpio_pic_detach(struct bcm_gpio_softc *sc) 964 { 965 966 /* 967 * There has not been established any procedure yet 968 * how to detach PIC from living system correctly. 969 */ 970 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__); 971 return (EBUSY); 972 } 973 974 static void 975 bcm_gpio_pic_config_intr(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi, 976 uint32_t mode) 977 { 978 uint32_t bank; 979 980 bank = BCM_GPIO_BANK(bgi->bgi_irq); 981 BCM_GPIO_LOCK(sc); 982 bcm_gpio_modify(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask, 983 mode == GPIO_INTR_EDGE_RISING || mode == GPIO_INTR_EDGE_BOTH); 984 bcm_gpio_modify(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask, 985 mode == GPIO_INTR_EDGE_FALLING || mode == GPIO_INTR_EDGE_BOTH); 986 bcm_gpio_modify(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask, 987 mode == GPIO_INTR_LEVEL_HIGH); 988 bcm_gpio_modify(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask, 989 mode == GPIO_INTR_LEVEL_LOW); 990 bgi->bgi_mode = mode; 991 BCM_GPIO_UNLOCK(sc); 992 } 993 994 static void 995 bcm_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 996 { 997 struct bcm_gpio_softc *sc = device_get_softc(dev); 998 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 999 1000 bcm_gpio_isrc_mask(sc, bgi); 1001 } 1002 1003 static void 1004 bcm_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 1005 { 1006 struct bcm_gpio_softc *sc = device_get_softc(dev); 1007 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1008 1009 arm_irq_memory_barrier(bgi->bgi_irq); 1010 bcm_gpio_isrc_unmask(sc, bgi); 1011 } 1012 1013 static int 1014 bcm_gpio_pic_map_fdt(struct bcm_gpio_softc *sc, struct intr_map_data_fdt *daf, 1015 u_int *irqp, uint32_t *modep) 1016 { 1017 u_int irq; 1018 uint32_t mode, bank; 1019 1020 /* 1021 * The first cell is the interrupt number. 1022 * The second cell is used to specify flags: 1023 * bits[3:0] trigger type and level flags: 1024 * 1 = low-to-high edge triggered. 1025 * 2 = high-to-low edge triggered. 1026 * 4 = active high level-sensitive. 1027 * 8 = active low level-sensitive. 1028 */ 1029 if (daf->ncells != 2) 1030 return (EINVAL); 1031 1032 irq = daf->cells[0]; 1033 if (irq >= BCM_GPIO_PINS || bcm_gpio_pin_is_ro(sc, irq)) 1034 return (EINVAL); 1035 1036 /* Only reasonable modes are supported. */ 1037 bank = BCM_GPIO_BANK(irq); 1038 if (daf->cells[1] == 1) 1039 mode = GPIO_INTR_EDGE_RISING; 1040 else if (daf->cells[1] == 2) 1041 mode = GPIO_INTR_EDGE_FALLING; 1042 else if (daf->cells[1] == 3) 1043 mode = GPIO_INTR_EDGE_BOTH; 1044 else if (daf->cells[1] == 4) 1045 mode = GPIO_INTR_LEVEL_HIGH; 1046 else if (daf->cells[1] == 8) 1047 mode = GPIO_INTR_LEVEL_LOW; 1048 else 1049 return (EINVAL); 1050 1051 *irqp = irq; 1052 if (modep != NULL) 1053 *modep = mode; 1054 return (0); 1055 } 1056 1057 static int 1058 bcm_gpio_pic_map_gpio(struct bcm_gpio_softc *sc, struct intr_map_data_gpio *dag, 1059 u_int *irqp, uint32_t *modep) 1060 { 1061 u_int irq; 1062 uint32_t mode; 1063 1064 irq = dag->gpio_pin_num; 1065 if (irq >= BCM_GPIO_PINS || bcm_gpio_pin_is_ro(sc, irq)) 1066 return (EINVAL); 1067 1068 mode = dag->gpio_intr_mode; 1069 if (mode != GPIO_INTR_LEVEL_LOW && mode != GPIO_INTR_LEVEL_HIGH && 1070 mode != GPIO_INTR_EDGE_RISING && mode != GPIO_INTR_EDGE_FALLING && 1071 mode != GPIO_INTR_EDGE_BOTH) 1072 return (EINVAL); 1073 1074 *irqp = irq; 1075 if (modep != NULL) 1076 *modep = mode; 1077 return (0); 1078 } 1079 1080 static int 1081 bcm_gpio_pic_map(struct bcm_gpio_softc *sc, struct intr_map_data *data, 1082 u_int *irqp, uint32_t *modep) 1083 { 1084 1085 switch (data->type) { 1086 case INTR_MAP_DATA_FDT: 1087 return (bcm_gpio_pic_map_fdt(sc, 1088 (struct intr_map_data_fdt *)data, irqp, modep)); 1089 case INTR_MAP_DATA_GPIO: 1090 return (bcm_gpio_pic_map_gpio(sc, 1091 (struct intr_map_data_gpio *)data, irqp, modep)); 1092 default: 1093 return (ENOTSUP); 1094 } 1095 } 1096 1097 static int 1098 bcm_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 1099 struct intr_irqsrc **isrcp) 1100 { 1101 int error; 1102 u_int irq; 1103 struct bcm_gpio_softc *sc = device_get_softc(dev); 1104 1105 error = bcm_gpio_pic_map(sc, data, &irq, NULL); 1106 if (error == 0) 1107 *isrcp = &sc->sc_isrcs[irq].bgi_isrc; 1108 return (error); 1109 } 1110 1111 static void 1112 bcm_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 1113 { 1114 struct bcm_gpio_softc *sc = device_get_softc(dev); 1115 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1116 1117 if (bcm_gpio_isrc_is_level(bgi)) 1118 bcm_gpio_isrc_eoi(sc, bgi); 1119 } 1120 1121 static void 1122 bcm_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 1123 { 1124 1125 bcm_gpio_pic_enable_intr(dev, isrc); 1126 } 1127 1128 static void 1129 bcm_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 1130 { 1131 struct bcm_gpio_softc *sc = device_get_softc(dev); 1132 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1133 1134 bcm_gpio_isrc_mask(sc, bgi); 1135 if (bcm_gpio_isrc_is_level(bgi)) 1136 bcm_gpio_isrc_eoi(sc, bgi); 1137 } 1138 1139 static int 1140 bcm_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 1141 struct resource *res, struct intr_map_data *data) 1142 { 1143 u_int irq; 1144 uint32_t mode; 1145 struct bcm_gpio_softc *sc; 1146 struct bcm_gpio_irqsrc *bgi; 1147 1148 if (data == NULL) 1149 return (ENOTSUP); 1150 1151 sc = device_get_softc(dev); 1152 bgi = (struct bcm_gpio_irqsrc *)isrc; 1153 1154 /* Get and check config for an interrupt. */ 1155 if (bcm_gpio_pic_map(sc, data, &irq, &mode) != 0 || bgi->bgi_irq != irq) 1156 return (EINVAL); 1157 1158 /* 1159 * If this is a setup for another handler, 1160 * only check that its configuration match. 1161 */ 1162 if (isrc->isrc_handlers != 0) 1163 return (bgi->bgi_mode == mode ? 0 : EINVAL); 1164 1165 bcm_gpio_pic_config_intr(sc, bgi, mode); 1166 return (0); 1167 } 1168 1169 static int 1170 bcm_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 1171 struct resource *res, struct intr_map_data *data) 1172 { 1173 struct bcm_gpio_softc *sc = device_get_softc(dev); 1174 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc; 1175 1176 if (isrc->isrc_handlers == 0) 1177 bcm_gpio_pic_config_intr(sc, bgi, GPIO_INTR_CONFORM); 1178 return (0); 1179 } 1180 1181 static phandle_t 1182 bcm_gpio_get_node(device_t bus, device_t dev) 1183 { 1184 1185 /* We only have one child, the GPIO bus, which needs our own node. */ 1186 return (ofw_bus_get_node(bus)); 1187 } 1188 1189 static device_method_t bcm_gpio_methods[] = { 1190 /* Device interface */ 1191 DEVMETHOD(device_probe, bcm_gpio_probe), 1192 DEVMETHOD(device_attach, bcm_gpio_attach), 1193 DEVMETHOD(device_detach, bcm_gpio_detach), 1194 1195 /* GPIO protocol */ 1196 DEVMETHOD(gpio_get_bus, bcm_gpio_get_bus), 1197 DEVMETHOD(gpio_pin_max, bcm_gpio_pin_max), 1198 DEVMETHOD(gpio_pin_getname, bcm_gpio_pin_getname), 1199 DEVMETHOD(gpio_pin_getflags, bcm_gpio_pin_getflags), 1200 DEVMETHOD(gpio_pin_getcaps, bcm_gpio_pin_getcaps), 1201 DEVMETHOD(gpio_pin_setflags, bcm_gpio_pin_setflags), 1202 DEVMETHOD(gpio_pin_get, bcm_gpio_pin_get), 1203 DEVMETHOD(gpio_pin_set, bcm_gpio_pin_set), 1204 DEVMETHOD(gpio_pin_toggle, bcm_gpio_pin_toggle), 1205 1206 /* Interrupt controller interface */ 1207 DEVMETHOD(pic_disable_intr, bcm_gpio_pic_disable_intr), 1208 DEVMETHOD(pic_enable_intr, bcm_gpio_pic_enable_intr), 1209 DEVMETHOD(pic_map_intr, bcm_gpio_pic_map_intr), 1210 DEVMETHOD(pic_post_filter, bcm_gpio_pic_post_filter), 1211 DEVMETHOD(pic_post_ithread, bcm_gpio_pic_post_ithread), 1212 DEVMETHOD(pic_pre_ithread, bcm_gpio_pic_pre_ithread), 1213 DEVMETHOD(pic_setup_intr, bcm_gpio_pic_setup_intr), 1214 DEVMETHOD(pic_teardown_intr, bcm_gpio_pic_teardown_intr), 1215 1216 /* ofw_bus interface */ 1217 DEVMETHOD(ofw_bus_get_node, bcm_gpio_get_node), 1218 1219 DEVMETHOD_END 1220 }; 1221 1222 static devclass_t bcm_gpio_devclass; 1223 1224 static driver_t bcm_gpio_driver = { 1225 "gpio", 1226 bcm_gpio_methods, 1227 sizeof(struct bcm_gpio_softc), 1228 }; 1229 1230 DRIVER_MODULE(bcm_gpio, simplebus, bcm_gpio_driver, bcm_gpio_devclass, 0, 0); 1231