1.\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara@gmail.com> 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" $FreeBSD$ 26.\" 27.Dd March 22, 2013 28.Dt PMC.HASWELL 3 29.Os 30.Sh NAME 31.Nm pmc.haswell 32.Nd measurement events for 33.Tn Intel 34.Tn Haswsell 35family CPUs 36.Sh LIBRARY 37.Lb libpmc 38.Sh SYNOPSIS 39.In pmc.h 40.Sh DESCRIPTION 41.Tn Intel 42.Tn "Haswell" 43CPUs contain PMCs conforming to version 2 of the 44.Tn Intel 45performance measurement architecture. 46These CPUs may contain up to two classes of PMCs: 47.Bl -tag -width "Li PMC_CLASS_IAP" 48.It Li PMC_CLASS_IAF 49Fixed-function counters that count only one hardware event per counter. 50.It Li PMC_CLASS_IAP 51Programmable counters that may be configured to count one of a defined 52set of hardware events. 53.El 54.Pp 55The number of PMCs available in each class and their widths need to be 56determined at run time by calling 57.Xr pmc_cpuinfo 3 . 58.Pp 59Intel Haswell PMCs are documented in 60.Rs 61.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 62.%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C" 63.%N "Order Number: 325462-045US" 64.%D January 2013 65.%Q "Intel Corporation" 66.Re 67.Ss HASWELL FIXED FUNCTION PMCS 68These PMCs and their supported events are documented in 69.Xr pmc.iaf 3 . 70.Ss HASWELL PROGRAMMABLE PMCS 71The programmable PMCs support the following capabilities: 72.Bl -column "PMC_CAP_INTERRUPT" "Support" 73.It Em Capability Ta Em Support 74.It PMC_CAP_CASCADE Ta \&No 75.It PMC_CAP_EDGE Ta Yes 76.It PMC_CAP_INTERRUPT Ta Yes 77.It PMC_CAP_INVERT Ta Yes 78.It PMC_CAP_READ Ta Yes 79.It PMC_CAP_PRECISE Ta \&No 80.It PMC_CAP_SYSTEM Ta Yes 81.It PMC_CAP_TAGGING Ta \&No 82.It PMC_CAP_THRESHOLD Ta Yes 83.It PMC_CAP_USER Ta Yes 84.It PMC_CAP_WRITE Ta Yes 85.El 86.Ss Event Qualifiers 87Event specifiers for these PMCs support the following common 88qualifiers: 89.Bl -tag -width indent 90.It Li rsp= Ns Ar value 91Configure the Off-core Response bits. 92.Bl -tag -width indent 93.It Li DMND_DATA_RD 94Counts the number of demand and DCU prefetch data reads of full 95and partial cachelines as well as demand data page table entry 96cacheline reads. Does not count L2 data read prefetches or 97instruction fetches. 98.It Li REQ_DMND_RFO 99Counts the number of demand and DCU prefetch reads for ownership (RFO) 100requests generated by a write to data cacheline. Does not count L2 RFO 101prefetches. 102.It Li REQ_DMND_IFETCH 103Counts the number of demand and DCU prefetch instruction cacheline reads. 104Does not count L2 code read prefetches. 105.It Li REQ_WB 106Counts the number of writeback (modified to exclusive) transactions. 107.It Li REQ_PF_DATA_RD 108Counts the number of data cacheline reads generated by L2 prefetchers. 109.It Li REQ_PF_RFO 110Counts the number of RFO requests generated by L2 prefetchers. 111.It Li REQ_PF_IFETCH 112Counts the number of code reads generated by L2 prefetchers. 113.It Li REQ_PF_LLC_DATA_RD 114L2 prefetcher to L3 for loads. 115.It Li REQ_PF_LLC_RFO 116RFO requests generated by L2 prefetcher 117.It Li REQ_PF_LLC_IFETCH 118L2 prefetcher to L3 for instruction fetches. 119.It Li REQ_BUS_LOCKS 120Bus lock and split lock requests. 121.It Li REQ_STRM_ST 122Streaming store requests. 123.It Li REQ_OTHER 124Any other request that crosses IDI, including I/O. 125.It Li RES_ANY 126Catch all value for any response types. 127.It Li RES_SUPPLIER_NO_SUPP 128No Supplier Information available. 129.It Li RES_SUPPLIER_LLC_HITM 130M-state initial lookup stat in L3. 131.It Li RES_SUPPLIER_LLC_HITE 132E-state. 133.It Li RES_SUPPLIER_LLC_HITS 134S-state. 135.It Li RES_SUPPLIER_LLC_HITF 136F-state. 137.It Li RES_SUPPLIER_LOCAL 138Local DRAM Controller. 139.It Li RES_SNOOP_SNP_NONE 140No details on snoop-related information. 141.It Li RES_SNOOP_SNP_NO_NEEDED 142No snoop was needed to satisfy the request. 143.It Li RES_SNOOP_SNP_MISS 144A snoop was needed and it missed all snooped caches: 145-For LLC Hit, ReslHitl was returned by all cores 146-For LLC Miss, Rspl was returned by all sockets and data was returned from 147DRAM. 148.It Li RES_SNOOP_HIT_NO_FWD 149A snoop was needed and it hits in at least one snooped cache. Hit denotes a 150cache-line was valid before snoop effect. This includes: 151-Snoop Hit w/ Invalidation (LLC Hit, RFO) 152-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) 153-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) 154In the LLC Miss case, data is returned from DRAM. 155.It Li RES_SNOOP_HIT_FWD 156A snoop was needed and data was forwarded from a remote socket. 157This includes: 158-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). 159.It Li RES_SNOOP_HITM 160A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a 161cache-line was in modified state before effect as a results of snoop. This 162includes: 163-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) 164-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) 165-Snoop MtoS (LLC Hit, IFetch/Data_RD). 166.It Li RES_NON_DRAM 167Target was non-DRAM system address. This includes MMIO transactions. 168.El 169.It Li cmask= Ns Ar value 170Configure the PMC to increment only if the number of configured 171events measured in a cycle is greater than or equal to 172.Ar value . 173.It Li edge 174Configure the PMC to count the number of de-asserted to asserted 175transitions of the conditions expressed by the other qualifiers. 176If specified, the counter will increment only once whenever a 177condition becomes true, irrespective of the number of clocks during 178which the condition remains true. 179.It Li inv 180Invert the sense of comparison when the 181.Dq Li cmask 182qualifier is present, making the counter increment when the number of 183events per cycle is less than the value specified by the 184.Dq Li cmask 185qualifier. 186.It Li os 187Configure the PMC to count events happening at processor privilege 188level 0. 189.It Li usr 190Configure the PMC to count events occurring at privilege levels 1, 2 191or 3. 192.El 193.Pp 194If neither of the 195.Dq Li os 196or 197.Dq Li usr 198qualifiers are specified, the default is to enable both. 199.Ss Event Specifiers (Programmable PMCs) 200Haswell programmable PMCs support the following events: 201.Bl -tag -width indent 202.It Li LD_BLOCKS.STORE_FORWARD 203.Pq Event 03H , Umask 02H 204Loads blocked by overlapping with store buffer that 205cannot be forwarded. 206.It Li MISALIGN_MEM_REF.LOADS 207.Pq Event 05H , Umask 01H 208Speculative cache-line split load uops dispatched to 209L1D. 210.It Li MISALIGN_MEM_REF.STORES 211.Pq Event 05H , Umask 02H 212Speculative cache-line split Store-address uops 213dispatched to L1D. 214.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS 215.Pq Event 07H , Umask 01H 216False dependencies in MOB due to partial compare 217on address. 218.It Li DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK 219.Pq Event 08H , Umask 01H 220Misses in all TLB levels that cause a page walk of any 221page size. 222.It Li DTLB_LOAD_MISSES.WALK_COMPLETED_4K 223.Pq Event 08H , Umask 02H 224Completed page walks due to demand load misses 225that caused 4K page walks in any TLB levels. 226.It Li DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K 227.Pq Event 08H , Umask 02H 228Completed page walks due to demand load misses 229that caused 2M/4M page walks in any TLB levels. 230.It Li DTLB_LOAD_MISSES.WALK_COMPLETED 231.Pq Event 08H , Umask 0EH 232Completed page walks in any TLB of any page size 233due to demand load misses 234.It Li DTLB_LOAD_MISSES.WALK_DURATION 235.Pq Event 08H , Umask 10H 236Cycle PMH is busy with a walk. 237.It Li DTLB_LOAD_MISSES.STLB_HIT_4K 238.Pq Event 08H , Umask 20H 239Load misses that missed DTLB but hit STLB (4K). 240.It Li DTLB_LOAD_MISSES.STLB_HIT_2M 241.Pq Event 08H , Umask 40H 242Load misses that missed DTLB but hit STLB (2M). 243.It Li DTLB_LOAD_MISSES.STLB_HIT 244.Pq Event 08H , Umask 60H 245Number of cache load STLB hits. No page walk. 246.It Li DTLB_LOAD_MISSES.PDE_CACHE_MISS 247.Pq Event 08H , Umask 80H 248DTLB demand load misses with low part of linear-to- 249physical address translation missed 250.It Li INT_MISC.RECOVERY_CYCLES 251.Pq Event 0DH , Umask 03H 252Cycles waiting to recover after Machine Clears 253except JEClear. Set Cmask= 1. 254.It Li UOPS_ISSUED.ANY 255.Pq Event 0EH , Umask 01H 256ncrements each cycle the # of Uops issued by the 257RAT to RS. 258Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles 259of this core. 260.It Li UOPS_ISSUED.FLAGS_MERGE 261.Pq Event 0EH , Umask 10H 262Number of flags-merge uops allocated. Such uops 263adds delay. 264.It Li UOPS_ISSUED.SLOW_LEA 265.Pq Event 0EH , Umask 20H 266Number of slow LEA or similar uops allocated. Such 267uop has 3 sources (e.g. 2 sources + immediate) 268regardless if as a result of LEA instruction or not. 269.It Li UOPS_ISSUED.SiNGLE_MUL 270.Pq Event 0EH , Umask 40H 271Number of multiply packed/scalar single precision 272uops allocated. 273.It Li L2_RQSTS.DEMAND_DATA_RD_MISS 274.Pq Event 24H , Umask 21H 275Demand Data Read requests that missed L2, no 276rejects. 277.It Li L2_RQSTS.DEMAND_DATA_RD_HIT 278.Pq Event 24H , Umask 41H 279Demand Data Read requests that hit L2 cache. 280.It Li L2_RQSTS.ALL_DEMAND_DATA_RD 281.Pq Event 24H , Umask E1H 282Counts any demand and L1 HW prefetch data load 283requests to L2. 284.It Li L2_RQSTS.RFO_HIT 285.Pq Event 24H , Umask 42H 286Counts the number of store RFO requests that hit 287the L2 cache. 288.It Li L2_RQSTS.RFO_MISS 289.Pq Event 24H , Umask 22H 290Counts the number of store RFO requests that miss 291the L2 cache. 292.It Li L2_RQSTS.ALL_RFO 293.Pq Event 24H , Umask E2H 294Counts all L2 store RFO requests. 295.It Li L2_RQSTS.CODE_RD_HIT 296.Pq Event 24H , Umask 44H 297Number of instruction fetches that hit the L2 cache. 298.It Li L2_RQSTS.CODE_RD_MISS 299.Pq Event 24H , Umask 24H 300Number of instruction fetches that missed the L2 301cache. 302.It Li L2_RQSTS.ALL_DEMAND_MISS 303.Pq Event 24H , Umask 27H 304Demand requests that miss L2 cache. 305.It Li L2_RQSTS.ALL_DEMAND_REFERENCES 306.Pq Event 24H , Umask E7H 307Demand requests to L2 cache. 308.It Li L2_RQSTS.ALL_CODE_RD 309.Pq Event 24H , Umask E4H 310Counts all L2 code requests. 311.It Li L2_RQSTS.L2_PF_HIT 312.Pq Event 24H , Umask 50H 313Counts all L2 HW prefetcher requests that hit L2. 314.It Li L2_RQSTS.L2_PF_MISS 315.Pq Event 24H , Umask 30H 316Counts all L2 HW prefetcher requests that missed 317L2. 318.It Li L2_RQSTS.ALL_PF 319.Pq Event 24H , Umask F8H 320Counts all L2 HW prefetcher requests. 321.It Li L2_RQSTS.MISS 322.Pq Event 24H , Umask 3FH 323All requests that missed L2. 324.It Li L2_RQSTS.REFERENCES 325.Pq Event 24H , Umask FFH 326All requests to L2 cache. 327.It Li L2_DEMAND_RQSTS.WB_HIT 328.Pq Event 27H , Umask 50H 329Not rejected writebacks that hit L2 cache 330.It Li LONGEST_LAT_CACHE.REFERENCE 331.Pq Event 2EH , Umask 4FH 332This event counts requests originating from the core 333that reference a cache line in the last level cache. 334.It Li LONGEST_LAT_CACHE.MISS 335.Pq Event 2EH , Umask 41H 336This event counts each cache miss condition for 337references to the last level cache. 338.It Li CPU_CLK_UNHALTED.THREAD_P 339.Pq Event 3CH , Umask 00H 340Counts the number of thread cycles while the thread 341is not in a halt state. The thread enters the halt state 342when it is running the HLT instruction. The core 343frequency may change from time to time due to 344power or thermal throttling. 345.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK 346.Pq Event 3CH , Umask 01H 347Increments at the frequency of XCLK (100 MHz) 348when not halted. 349.It Li L1D_PEND_MISS.PENDING 350.Pq Event 48H , Umask 01H 351Increments the number of outstanding L1D misses 352every cycle. Set Cmaks = 1 and Edge =1 to count 353occurrences. 354.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK 355.Pq Event 49H , Umask 01H 356Miss in all TLB levels causes an page walk of any 357page size (4K/2M/4M/1G). 358.It Li DTLB_STORE_MISSES.WALK_COMPLETED_4K 359.Pq Event 49H , Umask 02H 360Completed page walks due to store misses in one or 361more TLB levels of 4K page structure. 362.It Li DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M 363.Pq Event 49H , Umask 04H 364Completed page walks due to store misses in one or 365more TLB levels of 2M/4M page structure. 366.It Li DTLB_STORE_MISSES.WALK_COMPLETED 367.Pq Event 49H , Umask 0EH 368Completed page walks due to store miss in any TLB 369levels of any page size (4K/2M/4M/1G). 370.It Li DTLB_STORE_MISSES.WALK_DURATION 371.Pq Event 49H , Umask 10H 372Cycles PMH is busy with this walk. 373.It Li DTLB_STORE_MISSES.STLB_HIT_4K 374.Pq Event 49H , Umask 20H 375Store misses that missed DTLB but hit STLB (4K). 376.It Li DTLB_STORE_MISSES.STLB_HIT_2M 377.Pq Event 49H , Umask 40H 378Store misses that missed DTLB but hit STLB (2M). 379.It Li DTLB_STORE_MISSES.STLB_HIT 380.Pq Event 49H , Umask 60H 381Store operations that miss the first TLB level but hit 382the second and do not cause page walks. 383.It Li DTLB_STORE_MISSES.PDE_CACHE_MISS 384.Pq Event 49H , Umask 80H 385DTLB store misses with low part of linear-to-physical 386address translation missed. 387.It Li LOAD_HIT_PRE.SW_PF 388.Pq Event 4CH , Umask 01H 389Non-SW-prefetch load dispatches that hit fill buffer 390allocated for S/W prefetch. 391.It Li LOAD_HIT_PRE.HW_PF 392.Pq Event 4CH , Umask 02H 393Non-SW-prefetch load dispatches that hit fill buffer 394allocated for H/W prefetch. 395.It Li L1D.REPLACEMENT 396.Pq Event 51H , Umask 01H 397Counts the number of lines brought into the L1 data 398cache. 399.It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED 400.Pq Event 58H , Umask 04H 401Number of integer Move Elimination candidate uops 402that were not eliminated. 403.It Li MOVE_ELIMINATION.SMID_NOT_ELIMINATED 404.Pq Event 58H , Umask 08H 405Number of SIMD Move Elimination candidate uops 406that were not eliminated. 407.It Li MOVE_ELIMINATION.INT_ELIMINATED 408.Pq Event 58H , Umask 01H 409Unhalted core cycles when the thread is in ring 0. 410.It Li MOVE_ELIMINATION.SMID_ELIMINATED 411.Pq Event 58H , Umask 02H 412Number of SIMD Move Elimination candidate uops 413that were eliminated. 414.It Li CPL_CYCLES.RING0 415.Pq Event 5CH , Umask 02H 416Unhalted core cycles when the thread is in ring 0. 417.It Li CPL_CYCLES.RING123 418.Pq Event 5CH , Umask 01H 419Unhalted core cycles when the thread is not in ring 0. 420.It Li RS_EVENTS.EMPTY_CYCLES 421.Pq Event 5EH , Umask 01H 422Cycles the RS is empty for the thread. 423.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD 424.Pq Event 60H , Umask 01H 425Offcore outstanding Demand Data Read transactions 426in SQ to uncore. Set Cmask=1 to count cycles. 427.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD 428.Pq Event 60H , Umask 02H 429Offcore outstanding Demand code Read transactions 430in SQ to uncore. Set Cmask=1 to count cycles. 431.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO 432.Pq Event 60H , Umask 04H 433Offcore outstanding RFO store transactions in SQ to 434uncore. Set Cmask=1 to count cycles. 435.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD 436.Pq Event 60H , Umask 08H 437Offcore outstanding cacheable data read 438transactions in SQ to uncore. Set Cmask=1 to count 439cycles. 440.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION 441.Pq Event 63H , Umask 01H 442Cycles in which the L1D and L2 are locked, due to a 443UC lock or split lock. 444.It Li LOCK_CYCLES.CACHE_LOCK_DURATION 445.Pq Event 63H , Umask 02H 446Cycles in which the L1D is locked. 447.It Li IDQ.EMPTY 448.Pq Event 79H , Umask 02H 449Counts cycles the IDQ is empty. 450.It Li IDQ.MITE_UOPS 451.Pq Event 79H , Umask 04H 452Increment each cycle # of uops delivered to IDQ from 453MITE path. 454Set Cmask = 1 to count cycles. 455.It Li IDQ.DSB_UOPS 456.Pq Event 79H , Umask 08H 457Increment each cycle. # of uops delivered to IDQ 458from DSB path. 459Set Cmask = 1 to count cycles. 460.It Li IDQ.MS_DSB_UOPS 461.Pq Event 79H , Umask 10H 462Increment each cycle # of uops delivered to IDQ 463when MS_busy by DSB. Set Cmask = 1 to count 464cycles. Add Edge=1 to count # of delivery. 465.It Li IDQ.MS_MITE_UOPS 466.Pq Event 79H , Umask 20H 467ncrement each cycle # of uops delivered to IDQ 468when MS_busy by MITE. Set Cmask = 1 to count 469cycles. 470.It Li IDQ.MS_UOPS 471.Pq Event 79H , Umask 30H 472Increment each cycle # of uops delivered to IDQ from 473MS by either DSB or MITE. Set Cmask = 1 to count 474cycles. 475.It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS 476.Pq Event 79H , Umask 18H 477Counts cycles DSB is delivered at least one uops. Set 478Cmask = 1. 479.It Li IDQ.ALL_DSB_CYCLES_4_UOPS 480.Pq Event 79H , Umask 18H 481Counts cycles DSB is delivered four uops. Set Cmask 482=4. 483.It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS 484.Pq Event 79H , Umask 24H 485Counts cycles MITE is delivered at least one uops. Set 486Cmask = 1. 487.It Li IDQ.ALL_MITE_CYCLES_4_UOPS 488.Pq Event 79H , Umask 24H 489Counts cycles MITE is delivered four uops. Set Cmask 490=4. 491.It Li IDQ.MITE_ALL_UOPS 492.Pq Event 79H , Umask 3CH 493# of uops delivered to IDQ from any path. 494.It Li ICACHE.MISSES 495.Pq Event 80H , Umask 02H 496Number of Instruction Cache, Streaming Buffer and 497Victim Cache Misses. Includes UC accesses. 498.It Li ITLB_MISSES.MISS_CAUSES_A_WALK 499.Pq Event 85H , Umask 01H 500Misses in ITLB that causes a page walk of any page 501size. 502.It Li ITLB_MISSES.WALK_COMPLETED_4K 503.Pq Event 85H , Umask 02H 504Completed page walks due to misses in ITLB 4K page 505entries. 506.It Li TLB_MISSES.WALK_COMPLETED_2M_4M 507.Pq Event 85H , Umask 04H 508Completed page walks due to misses in ITLB 2M/4M 509page entries. 510.It Li ITLB_MISSES.WALK_COMPLETED 511.Pq Event 85H , Umask 0EH 512Completed page walks in ITLB of any page size. 513.It Li ITLB_MISSES.WALK_DURATION 514.Pq Event 85H , Umask 10H 515Cycle PMH is busy with a walk. 516.It Li ITLB_MISSES.STLB_HIT_4K 517.Pq Event 85H , Umask 20H 518ITLB misses that hit STLB (4K). 519.It Li ITLB_MISSES.STLB_HIT_2M 520.Pq Event 85H , Umask 40H 521ITLB misses that hit STLB (2K). 522.It Li ITLB_MISSES.STLB_HIT 523.Pq Event 85H , Umask 60H 524TLB misses that hit STLB. No page walk. 525.It Li ILD_STALL.LCP 526.Pq Event 87H , Umask 01H 527Stalls caused by changing prefix length of the 528instruction. 529.It Li ILD_STALL.IQ_FULL 530.Pq Event 87H , Umask 04H 531Stall cycles due to IQ is full. 532.It Li BR_INST_EXEC.NONTAKEN_COND 533.Pq Event 88H , Umask 41H 534Count conditional near branch instructions that were executed (but not 535necessarily retired) and not taken. 536.It Li BR_INST_EXEC.TAKEN_COND 537.Pq Event 88H , Umask 81H 538Count conditional near branch instructions that were executed (but not 539necessarily retired) and taken. 540.It Li BR_INST_EXEC.DIRECT_JMP 541.Pq Event 88H , Umask 82H 542Count all unconditional near branch instructions excluding calls and 543indirect branches. 544.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET 545.Pq Event 88H , Umask 84H 546Count executed indirect near branch instructions that are not calls nor 547returns. 548.It Li BR_INST_EXEC.RETURN_NEAR 549.Pq Event 88H , Umask 88H 550Count indirect near branches that have a return mnemonic. 551.It Li BR_INST_EXEC.DIRECT_NEAR_CALL 552.Pq Event 88H , Umask 90H 553Count unconditional near call branch instructions, excluding non call 554branch, executed. 555.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL 556.Pq Event 88H , Umask A0H 557Count indirect near calls, including both register and memory indirect, 558executed. 559.It Li BR_INST_EXEC.ALL_BRANCHES 560.Pq Event 88H , Umask FFH 561Counts all near executed branches (not necessarily retired). 562.It Li BR_MISP_EXEC.NONTAKEN_COND 563.Pq Event 89H , Umask 41H 564Count conditional near branch instructions mispredicted as nontaken. 565.It Li BR_MISP_EXEC.TAKEN_COND 566.Pq Event 89H , Umask 81H 567Count conditional near branch instructions mispredicted as taken. 568.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET 569.Pq Event 89H , Umask 84H 570Count mispredicted indirect near branch instructions that are not calls 571nor returns. 572.It Li BR_MISP_EXEC.RETURN_NEAR 573.Pq Event 89H , Umask 88H 574Count mispredicted indirect near branches that have a return mnemonic. 575.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL 576.Pq Event 89H , Umask 90H 577Count mispredicted unconditional near call branch instructions, excluding 578non call branch, executed. 579.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL 580.Pq Event 89H , Umask A0H 581Count mispredicted indirect near calls, including both register and memory 582indirect, executed. 583.It Li BR_MISP_EXEC.ALL_BRANCHES 584.Pq Event 89H , Umask FFH 585Counts all mispredicted near executed branches (not necessarily retired). 586.It Li IDQ_UOPS_NOT_DELIVERED.CORE 587.Pq Event 9CH , Umask 01H 588Count number of non-delivered uops to RAT per 589thread. 590.It Li UOPS_EXECUTED_PORT.PORT_0 591.Pq Event A1H , Umask 01H 592Cycles which a Uop is dispatched on port 0 in this 593thread. 594.It Li UOPS_EXECUTED_PORT.PORT_1 595.Pq Event A1H , Umask 02H 596Cycles which a Uop is dispatched on port 1 in this 597thread. 598.It Li UOPS_EXECUTED_PORT.PORT_2 599.Pq Event A1H , Umask 04H 600Cycles which a Uop is dispatched on port 2 in this 601thread. 602.It Li UOPS_EXECUTED_PORT.PORT_3 603.Pq Event A1H , Umask 08H 604Cycles which a Uop is dispatched on port 3 in this 605thread. 606.It Li UOPS_EXECUTED_PORT.PORT_4 607.Pq Event A1H , Umask 10H 608Cycles which a Uop is dispatched on port 4 in this 609thread. 610.It Li UOPS_EXECUTED_PORT.PORT_5 611.Pq Event A1H , Umask 20H 612Cycles which a Uop is dispatched on port 5 in this 613thread. 614.It Li UOPS_EXECUTED_PORT.PORT_6 615.Pq Event A1H , Umask 40H 616Cycles which a Uop is dispatched on port 6 in this 617thread. 618.It Li UOPS_EXECUTED_PORT.PORT_7 619.Pq Event A1H , Umask 80H 620Cycles which a Uop is dispatched on port 7 in this 621thread. 622.It Li RESOURCE_STALLS.ANY 623.Pq Event A2H , Umask 01H 624Cycles Allocation is stalled due to Resource Related 625reason. 626.It Li RESOURCE_STALLS.RS 627.Pq Event A2H , Umask 04H 628Cycles stalled due to no eligible RS entry available. 629.It Li RESOURCE_STALLS.SB 630.Pq Event A2H , Umask 08H 631Cycles stalled due to no store buffers available (not 632including draining form sync). 633.It Li RESOURCE_STALLS.ROB 634.Pq Event A2H , Umask 10H 635Cycles stalled due to re-order buffer full. 636.It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING 637.Pq Event A3H , Umask 01H 638Cycles with pending L2 miss loads. Set Cmask=2 to 639count cycle. 640.It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING 641.Pq Event A3H , Umask 02H 642Cycles with pending memory loads. Set Cmask=2 to 643count cycle. 644.It Li CYCLE_ACTIVITY.STALLS_L2_PENDING 645.Pq Event A3H , Umask 05H 646Number of loads missed L2. 647.It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING 648.Pq Event A3H , Umask 08H 649Cycles with pending L1 cache miss loads. Set 650Cmask=8 to count cycle. 651.It Li ITLB.ITLB_FLUSH 652.Pq Event AEH , Umask 01H 653Counts the number of ITLB flushes, includes 6544k/2M/4M pages. 655.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD 656.Pq Event B0H , Umask 01H 657Demand data read requests sent to uncore. 658.It Li OFFCORE_REQUESTS.DEMAND_CODE_RD 659.Pq Event B0H , Umask 02H 660Demand code read requests sent to uncore. 661.It Li OFFCORE_REQUESTS.DEMAND_RFO 662.Pq Event B0H , Umask 04H 663Demand RFO read requests sent to uncore, including 664regular RFOs, locks, ItoM. 665.It Li OFFCORE_REQUESTS.ALL_DATA_RD 666.Pq Event B0H , Umask 08H 667Data read requests sent to uncore (demand and 668prefetch). 669.It Li UOPS_EXECUTED.CORE 670.Pq Event B1H , Umask 02H 671Counts total number of uops to be executed per-core 672each cycle. 673.It Li OFF_CORE_RESPONSE_0 674.Pq Event B7H , Umask 01H 675Requires MSR 01A6H 676.It Li OFF_CORE_RESPONSE_1 677.Pq Event BBH , Umask 01H 678Requires MSR 01A7H 679.It Li PAGE_WALKER_LOADS.DTLB_L1 680.Pq Event BCH , Umask 11H 681Number of DTLB page walker loads that hit in the 682L1+FB. 683.It Li PAGE_WALKER_LOADS.ITLB_L1 684.Pq Event BCH , Umask 21H 685Number of ITLB page walker loads that hit in the 686L1+FB. 687.It Li PAGE_WALKER_LOADS.DTLB_L2 688.Pq Event BCH , Umask 12H 689Number of DTLB page walker loads that hit in the L2. 690.It Li PAGE_WALKER_LOADS.ITLB_L2 691.Pq Event BCH , Umask 22H 692Number of ITLB page walker loads that hit in the L2. 693.It Li PAGE_WALKER_LOADS.DTLB_L3 694.Pq Event BCH , Umask 14H 695Number of DTLB page walker loads that hit in the L3. 696.It Li PAGE_WALKER_LOADS.ITLB_L3 697.Pq Event BCH , Umask 24H 698Number of ITLB page walker loads that hit in the L3. 699.It Li PAGE_WALKER_LOADS.DTLB_MEMORY 700.Pq Event BCH , Umask 18H 701Number of DTLB page walker loads from memory. 702.It Li PAGE_WALKER_LOADS.ITLB_MEMORY 703.Pq Event BCH , Umask 28H 704Number of ITLB page walker loads from memory. 705.It Li TLB_FLUSH.DTLB_THREAD 706.Pq Event BDH , Umask 01H 707DTLB flush attempts of the thread-specific entries. 708.It Li TLB_FLUSH.STLB_ANY 709.Pq Event BDH , Umask 20H 710Count number of STLB flush attempts. 711.It Li INST_RETIRED.ANY_P 712.Pq Event C0H , Umask 00H 713Number of instructions at retirement. 714.It Li INST_RETIRED.ALL 715.Pq Event C0H , Umask 01H 716Precise instruction retired event with HW to reduce 717effect of PEBS shadow in IP distribution. 718.It Li OTHER_ASSISTS.AVX_TO_SSE 719.Pq Event C1H , Umask 08H 720Number of transitions from AVX-256 to legacy SSE 721when penalty applicable. 722.It Li OTHER_ASSISTS.SSE_TO_AVX 723.Pq Event C1H , Umask 10H 724Number of transitions from SSE to AVX-256 when 725penalty applicable. 726.It Li OTHER_ASSISTS.ANY_WB_ASSIST 727.Pq Event C1H , Umask 40H 728Number of microcode assists invoked by HW upon 729uop writeback. 730.It Li UOPS_RETIRED.ALL 731.Pq Event C2H , Umask 01H 732Counts the number of micro-ops retired, Use 733cmask=1 and invert to count active cycles or stalled 734cycles. 735.It Li UOPS_RETIRED.RETIRE_SLOTS 736.Pq Event C2H , Umask 02H 737Counts the number of retirement slots used each 738cycle. 739.It Li MACHINE_CLEARS.MEMORY_ORDERING 740.Pq Event C3H , Umask 02H 741Counts the number of machine clears due to memory 742order conflicts. 743.It Li MACHINE_CLEARS.SMC 744.Pq Event C3H , Umask 04H 745Number of self-modifying-code machine clears 746detected. 747.It Li MACHINE_CLEARS.MASKMOV 748.Pq Event C3H , Umask 20H 749Counts the number of executed AVX masked load 750operations that refer to an illegal address range with 751the mask bits set to 0. 752.It Li BR_INST_RETIRED.ALL_BRANCHES 753.Pq Event C4H , Umask 00H 754Branch instructions at retirement. 755.It Li BR_INST_RETIRED.CONDITIONAL 756.Pq Event C4H , Umask 01H 757Counts the number of conditional branch instructions Supports PEBS 758retired. 759.It Li BR_INST_RETIRED.NEAR_CALL 760.Pq Event C4H , Umask 02H 761Direct and indirect near call instructions retired. 762.It Li BR_INST_RETIRED.ALL_BRANCHES 763.Pq Event C4H , Umask 04H 764Counts the number of branch instructions retired. 765.It Li BR_INST_RETIRED.NEAR_RETURN 766.Pq Event C4H , Umask 08H 767Counts the number of near return instructions 768retired. 769.It Li BR_INST_RETIRED.NOT_TAKEN 770.Pq Event C4H , Umask 10H 771Counts the number of not taken branch instructions 772retired. 773 It Li BR_INST_RETIRED.NEAR_TAKEN 774.Pq Event C4H , Umask 20H 775Number of near taken branches retired. 776.It Li BR_INST_RETIRED.FAR_BRANCH 777.Pq Event C4H , Umask 40H 778Number of far branches retired. 779.It Li BR_MISP_RETIRED.ALL_BRANCHES 780.Pq Event C5H , Umask 00H 781Mispredicted branch instructions at retirement 782.It Li BR_MISP_RETIRED.CONDITIONAL 783.Pq Event C5H , Umask 01H 784Mispredicted conditional branch instructions retired. 785.It Li BR_MISP_RETIRED.CONDITIONAL 786.Pq Event C5H , Umask 04H 787Mispredicted macro branch instructions retired. 788.It Li FP_ASSIST.X87_OUTPUT 789.Pq Event CAH , Umask 02H 790Number of X87 FP assists due to Output values. 791.It Li FP_ASSIST.X87_INPUT 792.Pq Event CAH , Umask 04H 793Number of X87 FP assists due to input values. 794.It Li FP_ASSIST.SIMD_OUTPUT 795.Pq Event CAH , Umask 08H 796Number of SIMD FP assists due to Output values. 797.It Li FP_ASSIST.SIMD_INPUT 798.Pq Event CAH , Umask 10H 799Number of SIMD FP assists due to input values. 800.It Li FP_ASSIST.ANY 801.Pq Event CAH , Umask 1EH 802Cycles with any input/output SSE* or FP assists. 803.It Li ROB_MISC_EVENTS.LBR_INSERTS 804.Pq Event CCH , Umask 20H 805Count cases of saving new LBR records by hardware. 806.It Li MEM_TRANS_RETIRED.LOAD_LATENCY 807.Pq Event CDH , Umask 01H 808Randomly sampled loads whose latency is above a 809user defined threshold. A small fraction of the overall 810loads are sampled due to randomization. 811.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS 812.Pq Event D0H , Umask 11H 813Count retired load uops that missed the STLB. 814.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES 815.Pq Event D0H , Umask 12H 816Count retired store uops that missed the STLB. 817.It Li MEM_UOPS_RETIRED.SPLIT_LOADS 818.Pq Event D0H , Umask 41H 819Count retired load uops that were split across a cache line. 820.It Li MEM_UOPS_RETIRED.SPLIT_STORES 821.Pq Event D0H , Umask 42H 822Count retired store uops that were split across a cache line. 823.It Li MEM_UOPS_RETIRED.ALL_LOADS 824.Pq Event D0H , Umask 81H 825Count all retired load uops. 826.It Li MEM_UOPS_RETIRED.ALL_STORES 827.Pq Event D0H , Umask 82H 828Count all retired store uops. 829.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT 830.Pq Event D1H , Umask 01H 831Retired load uops with L1 cache hits as data sources. 832.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT 833.Pq Event D1H , Umask 02H 834Retired load uops with L2 cache hits as data sources. 835.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT 836.Pq Event D1H , Umask 04H 837Retired load uops with LLC cache hits as data 838sources. 839.It Li MEM_LOAD_UOPS_RETIRED.L2_MISS 840.Pq Event D1H , Umask 10H 841Retired load uops missed L2. Unknown data source 842excluded. 843.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB 844.Pq Event D1H , Umask 40H 845Retired load uops which data sources were load uops 846missed L1 but hit FB due to preceding miss to the 847same cache line with data not ready. 848.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS 849.Pq Event D2H , Umask 01H 850Retired load uops which data sources were LLC hit 851and cross-core snoop missed in on-pkg core cache. 852.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT 853.Pq Event D2H , Umask 02H 854Retired load uops which data sources were LLC and 855cross-core snoop hits in on-pkg core cache. 856.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM 857.Pq Event D2H , Umask 04H 858Retired load uops which data sources were HitM 859responses from shared LLC. 860.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE 861.Pq Event D2H , Umask 08H 862Retired load uops which data sources were hits in 863LLC without snoops required. 864.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM 865.Pq Event D3H , Umask 01H 866Retired load uops which data sources missed LLC but 867serviced from local dram. 868.It Li BACLEARS.ANY 869.Pq Event E6H , Umask 1FH 870Number of front end re-steers due to BPU 871misprediction. 872.It Li L2_TRANS.DEMAND_DATA_RD 873.Pq Event F0H , Umask 01H 874Demand Data Read requests that access L2 cache. 875.It Li L2_TRANS.RFO 876.Pq Event F0H , Umask 02H 877RFO requests that access L2 cache. 878.It Li L2_TRANS.CODE_RD 879.Pq Event F0H , Umask 04H 880L2 cache accesses when fetching instructions. 881.It Li L2_TRANS.ALL_PF 882.Pq Event F0H , Umask 08H 883Any MLC or LLC HW prefetch accessing L2, including 884rejects. 885.It Li L2_TRANS.L1D_WB 886.Pq Event F0H , Umask 10H 887L1D writebacks that access L2 cache. 888.It Li L2_TRANS.L2_FILL 889.Pq Event F0H , Umask 20H 890L2 fill requests that access L2 cache. 891.It Li L2_TRANS.L2_WB 892.Pq Event F0H , Umask 40H 893L2 writebacks that access L2 cache. 894.It Li L2_TRANS.ALL_REQUESTS 895.Pq Event F0H , Umask 80H 896Transactions accessing L2 pipe. 897.It Li L2_LINES_IN.I 898.Pq Event F1H , Umask 01H 899L2 cache lines in I state filling L2. 900.It Li L2_LINES_IN.S 901.Pq Event F1H , Umask 02H 902L2 cache lines in S state filling L2. 903.It Li L2_LINES_IN.E 904.Pq Event F1H , Umask 04H 905L2 cache lines in E state filling L2. 906.It Li L2_LINES_IN.ALL 907.Pq Event F1H , Umask 07H 908L2 cache lines filling L2. 909.It Li L2_LINES_OUT.DEMAND_CLEAN 910.Pq Event F2H , Umask 05H 911Clean L2 cache lines evicted by demand. 912.It Li L2_LINES_OUT.DEMAND_DIRTY 913.Pq Event F2H , Umask 06H 914Dirty L2 cache lines evicted by demand. 915.El 916.Sh SEE ALSO 917.Xr pmc 3 , 918.Xr pmc.atom 3 , 919.Xr pmc.core 3 , 920.Xr pmc.corei7 3 , 921.Xr pmc.corei7uc 3 , 922.Xr pmc.haswelluc 3 , 923.Xr pmc.iaf 3 , 924.Xr pmc.ivybridge 3 , 925.Xr pmc.ivybridgexeon 3 , 926.Xr pmc.k7 3 , 927.Xr pmc.k8 3 , 928.Xr pmc.p4 3 , 929.Xr pmc.p5 3 , 930.Xr pmc.p6 3 , 931.Xr pmc.sandybridge 3 , 932.Xr pmc.sandybridgeuc 3 , 933.Xr pmc.sandybridgexeon 3 , 934.Xr pmc.soft 3 , 935.Xr pmc.tsc 3 , 936.Xr pmc.ucf 3 , 937.Xr pmc.westmere 3 , 938.Xr pmc.westmereuc 3 , 939.Xr pmc_cpuinfo 3 , 940.Xr pmclog 3 , 941.Xr hwpmc 4 942.Sh HISTORY 943The 944.Nm pmc 945library first appeared in 946.Fx 6.0 . 947.Sh AUTHORS 948.An -nosplit 949The 950.Lb libpmc 951library was written by 952.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 953The support for the Haswell 954microarchitecture was written by 955.An Hiren Panchasara Aq Mt hiren.panchasara@gmail.com . 956