1b173cc4 | 12-Aug-2024 |
Sunil V L <sunilvl@ventanamicro.com> |
ACPI: RISC-V: Implement function to add implicit dependencies
RISC-V interrupt controllers for wired interrupts are platform devices and hence their driver will be probed late. Also, APLIC which is
ACPI: RISC-V: Implement function to add implicit dependencies
RISC-V interrupt controllers for wired interrupts are platform devices and hence their driver will be probed late. Also, APLIC which is one such interrupt controller can not be probed early since it needs MSI services. This needs a probing order between the interrupt controller driver and the device drivers.
_DEP is typically used to indicate such dependencies. However, the dependency may be already available like GSI mapping. Hence, instead of an explicit _DEP, architecture can find the implicit dependencies and add to the dependency list.
For RISC-V, add the dependencies for below use cases.
1) For devices which has IRQ resource, find out the interrupt controller using GSI number map and add the dependency.
2) For PCI host bridges: a) If _PRT indicate PCI link devices, add dependency on the link device. b) If _PRT indicates GSI, find out the interrupt controller using GSI number map and add the dependency.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> Link: https://patch.msgid.link/20240812005929.113499-13-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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e77b8dc0 | 12-Aug-2024 |
Sunil V L <sunilvl@ventanamicro.com> |
ACPI: RISC-V: Initialize GSI mapping structures
RISC-V has PLIC and APLIC in MADT as well as namespace devices. Initialize the list of those structures using MADT and namespace devices to create map
ACPI: RISC-V: Initialize GSI mapping structures
RISC-V has PLIC and APLIC in MADT as well as namespace devices. Initialize the list of those structures using MADT and namespace devices to create mapping between the ACPI handle and the GSI ranges. This will be used later to add dependencies.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> Link: https://patch.msgid.link/20240812005929.113499-12-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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f8bba143 | 12-Aug-2024 |
Sunil V L <sunilvl@ventanamicro.com> |
ACPI: RISC-V: Implement function to reorder irqchip probe entries
On RISC-V platforms, the RINTC structures should be probed before any other interrupt controller structures and IMSIC before APLIC.
ACPI: RISC-V: Implement function to reorder irqchip probe entries
On RISC-V platforms, the RINTC structures should be probed before any other interrupt controller structures and IMSIC before APLIC. This order is established by using MADT sub table types which are ordered in the incremental order from the RINTC. So, add the architecture function for RISC-V to reorder the interrupt controller probing as per the hierarchy like below.
ACPI_MADT_TYPE_RINTC = 24, ACPI_MADT_TYPE_IMSIC = 25, ACPI_MADT_TYPE_APLIC = 26, ACPI_MADT_TYPE_PLIC = 27
This means processing all RINTC structures (in the order of appearance in MADT), followed by IMSIC strucutre and then all APLIC/PLIC structures.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> Link: https://patch.msgid.link/20240812005929.113499-11-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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30f3ffbe | 08-Feb-2024 |
Sunil V L <sunilvl@ventanamicro.com> |
ACPI: RISC-V: Add CPPC driver
Add cpufreq driver based on ACPI CPPC for RISC-V. The driver uses either SBI CPPC interfaces or the CSRs to access the CPPC registers as defined by the RISC-V FFH spec.
ACPI: RISC-V: Add CPPC driver
Add cpufreq driver based on ACPI CPPC for RISC-V. The driver uses either SBI CPPC interfaces or the CSRs to access the CPPC registers as defined by the RISC-V FFH spec.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Acked-by: Rafael J. Wysocki <rafael@kernel.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Link: https://lore.kernel.org/r/20240208034414.22579-2-sunilvl@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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9ca87564 | 18-Oct-2023 |
Sunil V L <sunilvl@ventanamicro.com> |
RISC-V: ACPI: RHCT: Add function to get CBO block sizes
Cache Block Operation (CBO) related block size in ACPI is provided by RHCT. Add support to read the CMO node in RHCT to get this information.
RISC-V: ACPI: RHCT: Add function to get CBO block sizes
Cache Block Operation (CBO) related block size in ACPI is provided by RHCT. Add support to read the CMO node in RHCT to get this information.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20231018124007.1306159-4-sunilvl@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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