perf arch events: Fix duplicate RISC-V SBI firmware event nameCurrently, the RISC-V firmware JSON file has duplicate event name"FW_SFENCE_VMA_RECEIVED". According to the RISC-V SBI PMU extension[1
perf arch events: Fix duplicate RISC-V SBI firmware event nameCurrently, the RISC-V firmware JSON file has duplicate event name"FW_SFENCE_VMA_RECEIVED". According to the RISC-V SBI PMU extension[1],the event name should be "FW_SFENCE_VMA_ASID_SENT".Before this patch:$ perf listfirmware: fw_access_load [Load access trap event. Unit: cpu] fw_access_store [Store access trap event. Unit: cpu].... fw_set_timer [Set timer event. Unit: cpu] fw_sfence_vma_asid_received [Received SFENCE.VMA with ASID request from other HART event. Unit: cpu] fw_sfence_vma_received [Sent SFENCE.VMA with ASID request to other HART event. Unit: cpu]After this patch:$ perf listfirmware: fw_access_load [Load access trap event. Unit: cpu] fw_access_store [Store access trap event. Unit: cpu]..... fw_set_timer [Set timer event. Unit: cpu] fw_sfence_vma_asid_received [Received SFENCE.VMA with ASID request from other HART event. Unit: cpu] fw_sfence_vma_asid_sent [Sent SFENCE.VMA with ASID request to other HART event. Unit: cpu] fw_sfence_vma_received [Received SFENCE.VMA request from other HART event. Unit: cpu]Link: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/src/ext-pmu.adoc#event-firmware-events-type-15 [1]Fixes: 8f0dcb4e7364 ("perf arch events: riscv sbi firmware std event files")Fixes: c4f769d4093d ("perf vendor events riscv: add Sifive U74 JSON file")Fixes: acbf6de674ef ("perf vendor events riscv: Add StarFive Dubhe-80 JSON file")Fixes: 7340c6df49df ("perf vendor events riscv: add T-HEAD C9xx JSON file")Fixes: f5102e31c209 ("riscv: andes: Support specifying symbolic firmware and hardware raw event")Signed-off-by: Eric Lin <eric.lin@sifive.com>Reviewed-by: Samuel Holland <samuel.holland@sifive.com>Reviewed-by: Nikita Shubin <n.shubin@yadro.com>Reviewed-by: Inochi Amaoto <inochiama@outlook.com>Reviewed-by: Andrew Jones <ajones@ventanamicro.com>Reviewed-by: Atish Patra <atishp@rivosinc.com>Link: https://lore.kernel.org/r/20240719115018.27356-1-eric.lin@sifive.comSigned-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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perf vendor events riscv: add T-HEAD C9xx JSON fileAdd JSON file of T-HEAD C9xx series events.The event idx (raw value) is summary as following:event id range | support cpu 0x01 - 0x2a |
perf vendor events riscv: add T-HEAD C9xx JSON fileAdd JSON file of T-HEAD C9xx series events.The event idx (raw value) is summary as following:event id range | support cpu 0x01 - 0x2a | c906,c910,c920The event ids are based on the public document of T-HEAD and cover thec900 series.These events are the max that c900 series support. Since T-HEAD letmanufacturers decide whether events are usable, the final support of theperf events is determined by the pmu node of the soc dtb.Signed-off-by: Inochi Amaoto <inochiama@outlook.com>Tested-by: Guo Ren <guoren@kernel.org>Acked-by: Palmer Dabbelt <palmer@rivosinc.com>Cc: Adrian Hunter <adrian.hunter@intel.com>Cc: Albert Ou <aou@eecs.berkeley.edu>Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>Cc: Chen Wang <unicorn_wang@outlook.com>Cc: Ian Rogers <irogers@google.com>Cc: Ingo Molnar <mingo@redhat.com>Cc: Jiri Olsa <jolsa@kernel.org>Cc: Jisheng Zhang <jszhang@kernel.org>Cc: Mark Rutland <mark.rutland@arm.com>Cc: Namhyung Kim <namhyung@kernel.org>Cc: Paul Walmsley <paul.walmsley@sifive.com>Cc: Peter Zijlstra <peterz@infradead.org>Cc: Wei Fu <wefu@redhat.com>Cc: linux-riscv@lists.infradead.orgLink: https://lore.kernel.org/r/IA1PR20MB495325FCF603BAA841E29281BBBAA@IA1PR20MB4953.namprd20.prod.outlook.comSigned-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>